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Logic Circuit

The document is a workbook focused on digital electronics, specifically combinational logic circuits, including various problems and solutions related to logic gates, decoders, multiplexers, and adders. It presents multiple-choice questions aimed at engineering students preparing for exams like IES, GATE, and PSUs. The content includes practical applications and theoretical concepts essential for understanding digital logic design.

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rampratap
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24 views2 pages

Logic Circuit

The document is a workbook focused on digital electronics, specifically combinational logic circuits, including various problems and solutions related to logic gates, decoders, multiplexers, and adders. It presents multiple-choice questions aimed at engineering students preparing for exams like IES, GATE, and PSUs. The content includes practical applications and theoretical concepts essential for understanding digital logic design.

Uploaded by

rampratap
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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(IES|GATE | PSUs 13

ENGINEERS ZONE Digital Electronics (Workbook)


Zone of Excellence for Enginoers

COMBINATIONAL
|2
1. Assume that only X and Y logic inputs are
available, and their complements x and y
are not available. What is the minimum
LOGIC CIRCUITS
4. The logic circuit shown in fig, irnplements

3-t0-8
Decoder D,
number of 2-input NAND gates required to A D,
implement X Y? D,PL
B
(a) 2
(b) 3 CL D,
D
(c) 4
(d) 5
(a) D(AOC+AC)
2. F(X, X,, X,)=?
(b) D(BC+AC)
3-to-8
Decoder (c) pBC+ AB)
D (d) D(BoC +A B)
5. For the logic circuit shown in fig. the output
Y is

1
(a) [(1, 2, 4, 5,7)
(b) (1,2, 4, 5, 7)
EN
(c) (0,3, 6) A
MUX
(d) None of abOve B
C
3. fS, =?

3-to-8 D
Decoder D, (a) AB
D
D, (b) AOB
D;
(c) A BOC
D,
(d) A BÐC
(a) x,X, Xy 6.
The number of 4-line-to- l6 line decorder
required to make an 8-line-to-256-line
(b) x, x, > x, decorder is
(c) 1
(a) 16
(d) 0
Munirka Market, New Delhi-110067
Regd. office: 65/C, Prateek Market. Near Canara Bank, Website: www.qhengineerszone.com
Contact No: 011-26194869, 9873000903, 9873664427, 8860182273;
DigitalElectronlcs (Workbook)
ESIGATE| PSU
ENGINEERS
14

(c) Thrce bit ring, counter


(b) 17
(d) Threce bit Johnson counter
(c) 32
12. Minimum number of 2-input NAND)
(d) 64 required to implement the
7. It is required to construct a
gn -to - 1
multiplexer by using 2-to-l multiplexers only. F=(}+Y)(Z +W) is funit.
needed?
How many of 2-to-1multiplexers are (a) 3
(a) n
(b) 4
(b) 22n
(c) 5
(d) 6
(c) 21 13. Which one of the following is equivale.
AND-OR realization?
(d) 2 -1
(a) NAND-NOR realization
8 A 4-bit full-adder can be implemented with
half-adders and OR gates (b) NOR-NOR realization
la) 8 half-adders, 4-0R gates (c) NOR-NAND realization
(b) 8 half-adders, 3-0R gates (d) NAND-NAND realization
(c) 7 half-adders, 4-OR gates 14. For the given multiplexer, Yis equal to
(d) 7 half-adders, 3-0R gates
D
9. The output of the gated network shown in
the given figure is
1 8:1|
MUX OY

$s,S

(a) (AB)(CD) (EF) (a) ACD+ + AD


(b) ABC +AC +
(b) AB + CD + EF
(c) ACD +
(c) AB + CD + EF (d) ACD ABD + AD
(d) (A+ B) (C+ D)(E +F) 15. A 3 line to 8 line decorder, with active lou
10. The digital multiplexer is basically a outputs, is used to implement a 3-vanabie
combinational logic circuit to perform the Boolean function as shown in the figure
operation
(a) AND-AND
A,
(b) OR-OR A,
(c) AND-OR XA, 5
(d) OR-AND
11. Which one of the following will give the sum function
of full-adder as output? The simplifier form of Boolean
ofSum
(a) Three bit magnitude comparator F(A, B,C) implementedin Product
(b) Three bit parity checker form will be

Regd. office: 65/C, Prateek Market, Near Canara Bank, Munirka Market, New.qhengineerszone.com
Delhi-110007
Contact No: 011-26194869, 9873000903, 9873664427, 8860182273; Website: www.

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