SEMICONDUCTOR TECHNICAL DATA





High–Performance Silicon–Gate CMOS



The MC54/74HCT161A and HCT163A are identical in pinout to the LS161A

and LS163A. These devices may be used as level converters for interfacing
TTL or NMOS outputs to high speed CMOS inputs.
J SUFFIX
The HCT161A and HCT163A are programmable 4–bit binary counters with CERAMIC PACKAGE
asynchronous and synchronous reset, respectively. 16 CASE 620–10
1

• Output Drive Capability: 10 LSTTL Loads

• TTL, NMOS Compatible Input Levels N SUFFIX
• Outputs Directly Interface to CMOS, NMOS, and TTL 16 PLASTIC PACKAGE
CASE 648–08
• Operating Voltage Range: 4.5 to 5.5 V 1
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices D SUFFIX
• In Compliance with the Requirements Defined by JEDEC Standard 16 SOIC PACKAGE
No. 7A 1 CASE 751B–05

• Chip Complexity: 200 FETs or 50 Equivalent Gates

ORDERING INFORMATION
MC54HCXXXAJ Ceramic
LOGIC DIAGRAM
MC74HCXXXAN Plastic
MC74HCXXXAD SOIC
3 14
P0 Q0
Preset 4 13
P1 Q1
Data BCD or Binary Device Count Mode Reset Mode
5 12 Outputs
Inputs P2 Q2
6 11 HCT161A Binary Asynchronous
P3 Q3 HCT163A Binary Synchronous

2 15 Ripple
Clock
Carry Out
Pinout: 16–Lead Package (Top View)
1 Enable
Reset
Pin 16 = VCC VCC RCO* Q0 Q1 Q2 Q3 T Load
9
Load Pin 8 = GND 16 15 14 13 12 11 10 9
7
Count Enable P
Enables 10
Enable T

FUNCTION TABLE
Inputs
Output
Clock Reset* Load Enable P Enable T Q 1 2 3 4 5 6 7 8
Reset Clock P0 P1 P2 P3 Enable GND
L X X X Reset
P
H L X X Load Preset Data * RCO = Ripple Carry Out
H H H H Count
H H L X No Count
H H X L No Count
H = High Level; L = Low Level; X = Don’t Care
* = HCT163A only. HCT161A is an “Asynchronous–Reset” device.

10/95

 Motorola, Inc. 1995 1 REV 2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC54/74HCT161A MC54/74HCT163A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Value Unit This device contains protection

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
due to high static voltages or electric
Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V fields. However, precautions must

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
be taken to avoid applications of any

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
voltage higher than maximum rated
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins ± 50 mA v
range GND (Vin or Vout) VCC. v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic or Ceramic DIP† 750 mW

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tied to an appropriate logic voltage
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _C
Tstg Storage Temperature Range – 65 to + 150 Unused outputs must be left open.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Plastic DIP or SOIC Package 260
Ceramic DIP 300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SOIC Package: – 7 mW/_C from 65_ to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns

DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)

VCC Guaranteed Limit
Symbol Parameter Test Conditions V – 55 to 25_C ≤ 85°C ≤ 125°C Unit
VIH Minimum High–Level Input Vout = 0.1 V or VCC = –1.0V 4.5 2.0 2.0 2.0 V
Voltage v
|Iout| 20 µA 5.5 2.0 2.0 2.0

v
VIL Maximum Low–Level Input Vout = 0.1 V 4.5 0.80 0.80 0.80 V
Voltage |Iout| 20 µA 5.5 0.80 0.80 0.80
VOH Minimum High–Level Output Vin = VIH or VIL 4.5 4.4 4.4 4.4 V
Voltage v
|Iout| 20 µA 5.5 5.4 5.4 5.4
Vin = VIH or VIL
v
|Iout| 4.0 mA 4.5 3.98 3.84 3.70 V

VOL Maximum Low–Level Output Vin = VIH or VIL 4.5 0.10 0.10 0.10
Voltage v
|Iout| 20 µA 5.5 0.10 0.10 0.10 V
Vin = VIH or VIL
v
|Iout| 4.0 mA 4.5 0.26 0.33 0.40 V

Iin Maximum Input Leakage Current Vin = VCC or GND 5.5 ± 0.10 ± 1.00 ± 1.00 µA
ICC Maximum Quiescent Supply Vin = VCC or GND 5.5 4 40 160 µA
Current (Per Package) Iout – 0 µA

Vin = 2.4V,
ICC Additional Quiescent Supply Any One Input ≥–55°C 25 to +125°C
Current VIN = VCC or GND 2.9 2.4
Other Inputs Iout – 0 µA 5.5 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

MOTOROLA 2 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HCT161A MC54/74HCT163A

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±10%: CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit
Symbol Parameter Fig – 55 to 25_C ≤85°C ≤125°C Unit
fmax Maximum Clock Frequency (50% Duty Cycle)* 1,7 30 24 20 MHz
tPLH Maximum Propagation Delay Clock to Q 1,7 20 23 28 ns
tPHL 1,7 25 30 32 ns
tPHL Maximum Propagation Delay Reset to Q (HCT161A Only) 2,7 25 29 33 ns
tPLH Maximum Propagation Delay Enable T to Ripple Carry Out 3,7 16 18 20 ns
tPHL 3,7 21 24 28 ns
tPLH Maximum Propagation Delay Clock to Ripple Carry Out 1,7 22 25 28 ns
tPHL 1,7 28 33 35 ns
tPHL Maximum Propagation Delay Reset to Ripple Carry Out 2,7 24 28 32 ns
(HCT161A Only)
tTLH, Maximum Output Transition Time, Any Output 2,7 15 19 22 ns
tTHL
Cin Maximum Input Capacitance 1,7 10 10 10 pF

* Applies to noncascaded/nonsynchronous clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out
propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the fmax in the table above is applicable. See
Applications information in this data sheet.
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Gate)* 60 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (VCC = 5.0 V ±10%: CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit
– 55 to
Symbol Parameter Fig. 25_C ≤85°C ≤125°C Unit
tsu Minimum Setup Time, Preset Data Inputs to Clock 5 12 18 20 ns
Minimum Setup Time, Load to Clock 5 12 18 20 ns
Minimum Setup Time, Reset to Clock (HCT163A Only) 4 12 18 20 ns
Minimum Setup Time, Enable T or Enable P to Clock 6 12 18 20 ns
th Minimum Hold Time, Clock to Preset Data Inputs 5 3 3 3 ns
Minimum Hold Time, Clock to Load 5 3 3 3 ns
Minimum Hold Time, Clock to Reset (HCT163A Only) 4 3 3 3 ns
Minimum Hold Time, Clock to En T or En P 6 3 3 3 ns
trec Minimum Recovery Time, Reset Inactive to Clock (HCT161A Only) 2 12 17 23 ns
Minimum Recovery Time, Load Inactive to Clock 2 12 17 23 ns
tw Minimum Pulse Width, Clock 1 12 15 18 ns
Minimum Pulse Width, Reset (HCT161A Only) 1 12 15 18 ns
tr, tf Maximum Input Rise and Fall Times 500 500 500 ns

High–Speed CMOS Logic Data 3 MOTOROLA

DL129 — Rev 6
MC54/74HCT161A MC54/74HCT163A

FUNCTION DESCRIPTION

The HCT161A/163A are programmable 4–bit synchronous CONTROL FUNCTIONS

counters that feature parallel Load, synchronous or asynchro-
nous Reset, a Carry Output for cascading and count–enable Resetting
controls. A low level on the Reset pin (pin 1) resets the internal flip–
The HCT161A and HCT163A are binary counters with flops and sets the outputs (Q0 through Q3) to a low level. The
asynchronous Reset and synchronous Reset, respectively. HCT161A resets asynchronously, and the HCT163A resets
with the rising edge of the Clock input (synchronous reset).

INPUTS Loading
With the rising edge of the Clock, a low level on Load (pin
Clock (Pin 2) 9) loads the data from the Preset Data input pins (P0, P1, P2,
The internal flip–flops toggle and the output count ad- P3) into the internal flip–flops and onto the output pins, Q0
vances with the rising edge of the Clock input. In addition, con- through Q3. The count function is disabled as long as Load is
trol functions, such as resetting and loading occur with the low.
rising edge of the Clock input. In addition, control functions, Count Enable/Disable
such as resetting (HCT163A) and loading occur with the rising
These devices have two count–enable control pins: Enable
edge of the Clock Input.
P (Pin 7) and Enable T (Pin 10). The devices count when these
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6) two pins and the Load pin are high. The logic equation is:
These are the data inputs for programmable counting. Data Count Enable = Enable P • Enable T • Load
on these pins may be synchronously loaded into the internal The count is either enabled or disabled by the control inputs
flip–flops and appear at the counter outputs. P0 (Pin 3) is the according to Table 1. In general, Enable P is a count–enable
least–significant bit and P3 (Pin 6) is the most–significant bit. control: Enable T is both a count–enable and a Ripple–Carry
Output control.
OUTPUTS
Table 1. Count Enable/Disable
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
These are the counter outputs. Q0 (Pin 14) is the least–sig- Control Inputs Result at Outputs
nificant bit and Q3 (Pin 11) is the most–significant bit. Load Enable Enable Q0–Q3 Ripple Carry Out
P T
Ripple Carry Out (Pin 15)
When the counter is in its maximum state 1111, this output H H H Count High when Q0–Q3
goes high, providing an external look–ahead carry pulse that L H H No Count are maximum*
may be used to enable successive cascaded counters. Ripple
Carry Out remains high only during the maximum count state. X L H No Count High when Q0–Q3
The logic equation for this output is: are maximum*

Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3 X X L No Count L

Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.

OUTPUT STATE DIAGRAM

0 1 2 3 4

15 5

14 6

13 7

12 11 10 9 8

Binary Counters

MOTOROLA 4 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HCT161A MC54/74HCT163A

SWITCHING WAVEFORMS

tr tf tw
3.0V 3.0V
90%
Clock 1.3V Reset 1.3V
10% GND GND
tw tPHL
1/fMAX
tPLH tPHL Any 1.3V
Output
Any 90%
Output 1.3V trec
10% 3.0V
tTLH tTHL Clock 1.3V
GND

Figure 1. Figure 2.

tr tf
3.0V 3.0V
90%
Enable T 1.3V Reset 1.3V
10% GND GND
tPLH tPHL
tsu th
90% 3.0V
Ripple
Carry Out 1.3V Clock 1.3V
10% GND
tTLH tTHL

Figure 3. Figure 4. HCT163A Only

3.0V
Inputs P0,
P1, P2, P3 1.3V
GND Valid
Enable T 3.0V
tsu th or 1.3V
3.0V Enable P GND
Load 1.3V
tsu th
GND 3.0V
th
tsu trec Clock 1.3V
3.0V
GND
Clock 1.3V
GND
Figure 5. Figure 6.

TEST
POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 7. Test Circuit

High–Speed CMOS Logic Data 5 MOTOROLA

DL129 — Rev 6
MC54/74HCT161A MC54/74HCT163A

14
T0 Q0
R Q0
C
C
Load
3 Load Q0
P0 P0

13
T1 Q1
R Q1
C
C
Load
4 Load Q1
P1 P1

12
T2 Q2
R Q2
C
C
Load
5 Load Q2
P2 P2

11
T3 Q3
R Q3
C
C
Load
6 Load
P3 P3

15 Ripple
Carry Out

7
Enable P

10
Enable T

The flip–flops shown in the circuit diagrams are Toggle–

1
Reset R Enable flip–flops. A Toggle–Enable flip–flop is a combina-
tion of a D flip–flop and a T flip–flop. When loading data
9 from Preset inputs P0, P1, P2 and P3, the Load signal is
Load Load
used to disable the Toggle input (Tn) of the flip–flop. The
Load logic level at the Pn input is then clocked to the Q output of
2 the flip–flop on the next rising edge of the clock.
Clock C
A logic zero on the Reset device input forces the internal
C
clock (C) high and resets the Q output of the flip–flop low.

Figure 8. 4–Bit Binary Counter with Asynchronous Reset (MC54/74HCT161A)

MOTOROLA 6 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HCT161A MC54/74HCT163A

Reset (HCT161A) (Asynchronous)

Reset (HCT163A) (Synchronous)

Load

P0

Preset P1
Data
Inputs
P2

P3

Clock (HCT161A)

Clock (HCT163A)

Enable P
Count
Enables
Enable T

Q0

Q1
Outputs
Q2

Q3

Ripple Carry Out

12 13 14 15 0 1 2
Count Inhibit

Reset Load

Figure 9. Timing Diagram

High–Speed CMOS Logic Data 7 MOTOROLA

DL129 — Rev 6
MC54/74HCT161A MC54/74HCT163A

14
T0 Q0
R Q0
C
C
Load
3 Load Q0
P0 P0

13
T1 Q1
R Q1
C
C
Load
4 Load Q1
P1 P1

12
T2 Q2
R Q2
C
C
Load
5 Load Q2
P2 P2

11
T3 Q3
R Q3
C
C
Load
6 Load
P3 P3

15 Ripple
Carry Out

7
Enable P

10
Enable T

The flip–flops shown in the circuit diagrams are Toggle–

1
Reset R Enable flip–flops. A Toggle–Enable flip–flop is a combina-
tion of a D flip–flop and a T flip–flop. When loading data
9 from Preset inputs P0, P1, P2 and P3, the Load signal is
Load Load
used to disable the Toggle input (Tn) of the flip–flop. The
Load logic level at the Pn input is then clocked to the Q output of
2 the flip–flop on the next rising edge of the clock.
Clock C
A logic zero on the Reset device input forces the internal
C
clock (C) high and resets the Q output of the flip–flop low.

Figure 10. 4–Bit Binary Counter with Synchronous Reset (MC54/74HCT163A)

MOTOROLA 8 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HCT161A MC54/74HCT163A

TYPICAL APPLICATIONS CASCADING

Load

Inputs Inputs Inputs

Load Q0 Q1 Q2 Q3 Load Q0 Q1 Q2 Q3 Load Q0 Q1 Q2 Q3

H=Count
L=Disable Enable P Enable P Enable P
Ripple Ripple Ripple To More
H=Count
Enable T Carry Enable T Carry Enable T Carry Significant
L=Disable
Out Out Out Stages
Clock Clock Clock
Reset Q0 Q1 Q2 Q3 Reset Q0 Q1 Q2 Q3 Reset Q0 Q1 Q2 Q3

Reset

Outputs Outputs Outputs

Clock

NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will
depend on number of stages. This limitation is due to set–up times between Enable (port) and clock.

Figure 11. N–Bit Synchronous Counters

Inputs Inputs Inputs

Load
Enable P
Enable T

Load Q0 Q1 Q2 Q3 Load Q0 Q1 Q2 Q3 Load Q0 Q1 Q2 Q3

Enable P Enable P Enable P

Ripple Ripple Ripple To More
Enable T Carry Enable T Carry Enable T Carry Significant
Out Out Out Stages
Clock Clock Clock Clock
Reset Q0 Q1 Q2 Q3 Reset Q0 Q1 Q2 Q3 Reset Q0 Q1 Q2 Q3

Reset

Outputs Outputs Outputs

Figure 12. Nibble Ripple Counter

High–Speed CMOS Logic Data 9 MOTOROLA

DL129 — Rev 6
MC54/74HCT161A MC54/74HCT163A

TYPICAL APPLICATIONS VARYING THE MODULUS

HCT163A HCT163A

Other Q0 Other Q0
Inputs Optional Buffer Inputs Optional Buffer
Q1 for Noise Rejection Q1 for Noise Rejection

Q2 Output Q2 Output

Q3 Q3
Reset Reset

Figure 13. Modulo–5 Counter Figure 14. Modulo–11 Counter

The HCT163A facilitates designing counters of any modulus with minimal external logic. The output is glitch–
free due to the synchronous Reset.

MOTOROLA 10 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HCT161A MC54/74HCT163A

OUTLINE DIMENSIONS

J SUFFIX
–A CERAMIC PACKAGE
– CASE 620–10
NOTES:
16 9 ISSUE V 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
–B 2. CONTROLLING DIMENSION: INCH.
– 3. DIMENSION L TO CENTER OF LEAD WHEN
1 8 FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
C L THE LEAD ENTERS THE CERAMIC BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
–T B 0.240 0.295 6.10 7.49
–
SEATING N K C — 0.200 — 5.08
PLANE D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
E M G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
F G J 16 PL K 0.125 0.170 3.18 4.31
D 16 PL 0.25 (0.010) M T B S L 0.300 BSC 7.62 BSC
M 0° 15° 0° 15°
0.25 (0.010) M T A S N 0.020 0.040 0.51 1.01

N SUFFIX
–A PLASTIC PACKAGE NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
– CASE 648–08 Y14.5M, 1982.
ISSUE R 2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
F DIM MIN MAX MIN MAX
C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.070 1.02 1.77
–T PLANE G 0.100 BSC 2.54 BSC
– H 0.050 BSC 1.27 BSC
K M J
H J 0.008 0.015 0.21 0.38
G K 0.110 0.130 2.80 3.30
D 16 PL L 0.295 0.305 7.50 7.74
M 0° 10° 0° 10°
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

D SUFFIX
PLASTIC SOIC PACKAGE
–A CASE 751B–05
– ISSUE J NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B MOLD PROTRUSION.
P 8 PL 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
–
1 8 0.25 (0.010) M B M PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
G MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45° B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
–T
–
SEATING M J J 0.19 0.25 0.008 0.009
PLANE K 0.10 0.25 0.004 0.009
D 16 PL M 0° 7° 0° 7°
0.25 (0.010) M T B S A S P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

High–Speed CMOS Logic Data 11 MOTOROLA

DL129 — Rev 6
MC54/74HCT161A MC54/74HCT163A

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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*MC54/74HCT161A/D*
◊ CODELINE MC54/74HCT161A/D
MOTOROLA 12 High–Speed CMOS Logic Data
DL129 — Rev 6