TX31D203VM0EAB
TX31D203VM0EAB
5th ,2021
TX31D203VM0EAB
Contents
No. ITEM SHEET No. PAGE
1 COVER 7B64PS 2701-TX31D203VM0EAB-2 1-1/1
2 RECORD OF REVISION 7B64PS 2702-TX31D203VM0EAB-2 2-1/1
3 GENERAL DATA 7B64PS 2703-TX31D203VM0EAB-2 3-1/1
4 ABSOLUTE MAXIMUM RATINGS 7B64PS 2704-TX31D203VM0EAB-2 4-1/1
5 ELECTRICAL CHARACTERISTICS 7B64PS 2705-TX31D203VM0EAB-2 5-1/1
6 OPTICAL CHARACTERISTICS 7B64PS 2706-TX31D203VM0EAB-2 6-1/2~2/2
7 BLOCK DIAGRAM 7B64PS 2707-TX31D203VM0EAB-2 7-1/1
8 RELIABILITY TESTS 7B64PS 2708-TX31D203VM0EAB-2 8-1/1
9 LCD INTERFACE 7B64PS 2709-TX31D203VM0EAB-2 9-1/15~15/15
10 OUTLINE DIMENSIONS 7B64PS 2710-TX31D203VM0EAB-2 10-1/2~2/2
11 APPEARANCE STANDARD 7B64PS 2711-TX31D203VM0EAB-2 11-1/3~3/3
12 PRECAUTIONS 7B64PS 2712-TX31D203VM0EAB-2 12-1/2~2/2
13 DESIGNATION OF LOT MARK 7B64PS 2713-TX31D203VM0EAB-2 13-1/1
ACCEPTED BY : PROPOSED BY :
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KAOHSIUNG OPTO-ELECTRONICS INC. NO. 7B64PS 2701-TX31D203VM0EAB-2 PAGE 1-1/1
2. RECORD OF REVISION
DATE SHEET No. SUMMARY
Feb.5,’21 7B64PS2710 – 10.2 REAR VIEW
TX31D203VM0EAB-2 Revised : the rear view of outline dimensions
Page 10-2/2
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KAOHSIUNG OPTO-ELECTRONICS INC. NO. 7B64PS 2702-TX31D203VM0EAB-2 PAGE 2-1/1
3. GENERAL DATA
3.1 DISPLAY FEATURES
This module is a 12.3” HD of 8:3 format amorphous silicon TFT. The pixel format is vertical stripe and
sub pixels are arranged as R(red), G(green), B(blue) sequentially. This display is RoHS compliant, and
COG (chip on glass) technology and LED backlight are applied on this display
Weight 600 g
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KAOHSIUNG OPTO-ELECTRONICS INC. NO. 7B64PS 2703-TX31D203VM0EAB-2 PAGE 3-1/1
4. ABSOLUTE MAXIMUM RATINGS
Item Symbol Min. Max. Unit Remarks
Supply Voltage VDD -0.3 4.0 V -
Input Voltage of Logic VI -0.3 VDD +0.3 V Note 1
Operating Temperature Top -40 85 C Note 2
Storage Temperature Tst -40 90 C Note 2
Backlight Input Voltage VLED 6 21 V -
Backlight Voltage for PWM VPWM -0.3 6 V -
Backlight Voltage for EN VEN -0.3 6 V -
Note 1: The rating is defined for the signal voltages of the interface such as CLK and pixel data pairs.
Note 2: The maximum rating is defined as above based on the chamber temperature, which might be
different from ambient temperature after assembling the panel into the application. Moreover,
some temperature-related phenomenon as below needed to be noticed:
- Background color, contrast and response time would be different in temperatures other than
25 C .
- Operating under high temperature will shorten LED lifetime.
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KAOHSIUNG OPTO-ELECTRONICS INC. NO. 7B64PS 2704-TX31D203VM0EAB-2 PAGE 4-1/1
5. ELECTRICAL CHARACTERISTICS
5.1 OPERATING CONDITIONS Ta = 25 C, VSS = 0V
Standard Value
Item Symbol Condition Unit Remarks
Min. Typ. Max.
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KAOHSIUNG OPTO-ELECTRONICS INC. NO. 7B64PS 2705-TX31D203VM0EAB-2 PAGE 5-1/2
5.2 BACKLIGHT CHARACTERISTICS
Ta = 25 C
Item Symbol Condition Min. Typ. Max. Unit Remarks
LED Input Voltage VLED ILED=1000mA 11.5 12 12.5 V Note 1
LED Forward Current 100% duty - 1000 -
ILED mA Note 2
(DIM Control) 5% duty - 70 -
High 2.5 3.3 5
V
PWM Signal Voltage - Low - - 0.9 -
Range 5 - 100 %
EN Voltage VEN - 2.5 3.3 5.0 V -
LED Lifetime - ILED=1000mA - 50K - hrs Note 3
Note 2: Dimming function can be obtained by applying PWM signal from the display interface CN2. The
recommended PWM signal is 1K ~ 10KHz with 3.3 V amplitude.
Note 3: The estimated lifetime is specified as the time to reduce 50% brightness by applying 1000mA at
25 C .
12V
ILED
VEN
CN2 Pin 8
LED
Driver
VPWM
CN2 Pin 9
Fig 5.1
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KAOHSIUNG OPTO-ELECTRONICS INC. NO. 7B64PS 2705-TX31D203VM0EAB-2 PAGE 5-2/2
6. OPTICAL CHARACTERISTICS
The optical characteristics are measured based on the conditions as below:
- Supplying the signals and voltages defined in the section of electrical characteristics.
- The backlight unit needs to be turned on for 30 minutes.
- The ambient temperature is 25 C .
- In the dark room less than 100 lx, the equipment has been set for the measurements as shown in Fig
6.1.
Ta = 25 C , f Frame = 60 Hz, VDD = 3.3V
Item Symbol Condition Min. Typ. Max. Unit Remarks
2
Brightness of White - 800 1000 - cd/m Note 1
= 0 , = 0 ,
Brightness Uniformity - 75 - - % Note 2
ILED= 1000mA
Contrast Ratio CR 800 1300 - - Note 3
Response Time - = 0 , = 0
- - 25 ms -
NTSC Ratio - = 0 , = 0
- 70 - % -
x = 0 , CR 10
- 85 -
x = 180 , CR 10
- 85 -
Viewing Angle Degree Note 5
y = 90 , CR 10
- 85 -
y = 270, CR 10 - 85 -
X 0.59 0.64 0.69
Red
Y 0.25 0.30 0.35
X 0.28 0.33 0.38
Green
Color Y 0.57 0.62 0.67
= 0 , = 0 - Note 6
Chromaticity X 0.09 0.14 0.19
Blue
Y 0.02 0.07 0.12
X 0.26 0.31 0.36
White
Y 0.28 0.33 0.38
Note 1: The brightness is measured from the panel center point, P5 in Fig. 6.2, for the typical value.
Note 2: The brightness uniformity is calculated by the equation as below:
Min. Brightness
Brightness uniformity = 100%
Max. Brightness
which is based on the brightness values of the 9 points in active area measured by BM-5 as
shown in Fig. 6.2. 1X 2X 2X 1X
6 6 6 6
1Y
6
P1 P2 P3
Photo Detector: BM-5 or equivalent
2Y
6
Field: 1
P4 P5 P6 Y
Distance: 500 mm 2Y
6
P7 P8 P9
LCD panel 1Y
6
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KAOHSIUNG OPTO-ELECTRONICS INC. NO. 7B64PS 2706-TX31D203VM0EAB-2 PAGE 6-1/2
Note 3: The Contrast Ratio is measured from the center point of the panel, P5, and defined as the
following equation:
Brightness of White
CR =
Brightness of Black
Note 4: The definition of response time is shown in Fig. 6.3. The rising time is the period from 10%
brightness to 90% brightness when the data is from black to white. Oppositely, Falling time is
the period from 90% brightness rising to 10% brightness.
Falling time
100 % Tr Rising time Tf
90
Brightness
10
0
0
Fig 6.3
Note 5: The definition of viewing angle is shown in Fig. 6.4. Angle is used to represent viewing
directions, for instance, = 270 means 6 o’clock, and = 0 means 3 o’clock. Moreover, angle
is used to represent viewing angles from axis Z toward plane XY.
The display is super wide viewing angle version; 85° viewing angle can be obtained from each
viewing direction.
z
= Viewing angle
= 90
y
12 o'clock
(x, y ,0)
x =0
x'
= 180 3 o'clock
9 o'clock
y' = 270
6 o'clock
z'
Fig 6.4
Note 6: The color chromaticity is measured from the center point of the panel, P5, as shown in Fig. 6.2.
Display-check
Signals
Timing
CS,SCK,SDIO Controller
VDD
Gate Driver
12.3 inch HD LCD panel
CN1
DC/DC
Circuit
PWRON
Source Driver
Dim(PWM)
VLED LED
CN2
LED Backlight
EN Driver Circuit
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KAOHSIUNG OPTO-ELECTRONICS INC. NO. 7B64PS 2707-TX31D203VM0EAB-2 PAGE 7-1/1
8. RELIABILITY TESTS
Test Item Condition
1) Operating
High Temperature 500 hrs
1) 2) 85 C
1) Operating
Low Temperature 500 hrs
1) 2) -40 C
1) Storage
High Temperature 500 hrs
2) 90 C
1) Storage
Low Temperature 500 hrs
2) -40 C
1) Operating
Heat Cycle 2) –35 C ~85 C 500 hrs
3) 3hrs~1hr~3hrs
1) Non-Operating
2) -35 C 85 C
Thermal Shock 500 hrs
3) 0.5 hr 0.5 hr
1) Operating
High Temperature & 500 hrs
2) 40 C & 85%RH
Humidity (Note 3)
3) Without condensation
1) Non-Operating
2) 10~200 Hz
Vibration 1 hr for each direction
3) 5G
4) X, Y, and Z directions
1) Non-Operating
2) 10 ms
Mechanical Shock Once for each direction
3) 80G
4) X, Y and Z directions
1) Operating
1) Glass: 9 points
2) Tip:150 pF,330
ESD 2) Metal frame: 8 points
3) Air discharge for glass: 12KV
(Note4)
4) Contact discharge for metal frame: 15KV
Note 1: Display functionalities are inspected under the conditions defined in the specification after the
reliability tests.
Note 2: The display is not guaranteed for use in corrosive gas environments.
Note 3: Under the condition of high temperature & humidity, if the temperature is higher than 40 C , the
humidity needs to be reduced as Fig. 8.1 shown.
Relative Humidity RH (%)
90
80
70
60
50
40
30
20
10
0
20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
Temperature Ta ( C)
Fig. 8.1
Note 4: All pins of LCD interface (CN1) have been tested by 100V contact discharge of ESD under
non-operating condition.
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KAOHSIUNG OPTO-ELECTRONICS INC. NO. 7B64PS 2708-TX31D203VM0EAB-2 PAGE 8-1/1
9. LCD INTERFACE
9.1 INTERFACE PIN CONNECTIONS
The display interface connector is FH41 made by Hirose and pin assignment of LCD interface CN1 is
as below.
Pin No. Symbol Function I/O/P Remarks
1 NC Not connected - Connected to Pin #50 on PWB
2 CS Serial interface chip select I
3 SCK Serial interface clock I
4 SDIO Serial interface data I/O
5 NC Innter test pin O
6 PWRON Power ON/OFF I
7 GND GND (0V) P
8 GND GND (0V) P
9 GND GND (0V) P
10 GND GND (0V) P
11 NC Not connected -
12 VDD +3.3V P
13 VDD +3.3V P
14 VDD +3.3V P
15 VDD +3.3V P
16 NC Not connected -
17 GND GND (0V) P
18 GND GND (0V) P
19 NC Not connected -
20 GND GND (0V) P
21 RO0- LVDS data (-), Channel 0-odd I
22 RO0+ LVDS data (+), Channel 0-odd I
23 GND GND (0V) P
24 RO1- LVDS data (-), Channel 1-odd I
25 RO1+ LVDS data (+), Channel 1-odd I
26 GND GND (0V) P
27 RO2- LVDS data (-), Channel 2-odd I
28 RO2+ LVDS data (+), Channel 2-odd I
29 GND GND (0V) P
30 CLKO- LVDS clock (-), Odd I
31 CLKO+ LVDS clock (+), Odd I
32 GND GND (0V) P
33 RO3- LVDS data (-), Channel 3-odd I
34 RO3+ LVDS data (+), Channel 3-odd I
35 GND GND (0V) P
36 RE0- LVDS data (-), Channel 0-Even I
37 RE0+ LVDS data (+), Channel 0-Even I
38 GND GND (0V) P
39 RE1- LVDS data (-), Channel 1-Even I
40 RE1+ LVDS data (+), Channel 1-Even I
Note 1: I: input pin, I/O: input / output pin, P: power pin, O: output pin
RO* : 1st , 3rd …Pixel, RE*: 2nd, 4th,… Pixel
Note 2: It outputs Display_check signal to check the condition of LCD. The TCON monitors the rising
edge of the cascade-out of the Gate driver IC. If the TCON is not able to check the rising edge
into the Check_window, the Display_check signal is set to Low.
The interface CN2 is SM10B-SRSS-TB(LF)(SN) made by JST and pin assignment is as below:
Connector Name Pin No. Symbol Function
1 VLED(+) Power Supply for LED
2 VLED(+) Power Supply for LED
3 VLED(+) Power Supply for LED
4 NC No Connected
5 VLED(-) GND
SM10B-SRSS-TB(LF)(SN)
6 VLED(-) GND
7 VLED(-) GND
8 VEN Backlight On/Off
9 NC No Connected
10 VPWM Brightness dimming
Note 1: Normal brightness: 100% PWM duty; Brightness control: 5% to 100% PWM duty.
<Write Access>
<Read Access>
0 0 0 0 0 0 - Fixed value.
Display Enable
E0h 0 0 0 0 0 0 0 1 01 DISPON_CMD 00h: Disable(black screen)
01h, Enable
SCANNING DIRECTION
F
Input data
tHSCS tPWSCS
VIH VIH
VIL VIL
tSCK tPWLSC tPWHSC
tSSD
tOSSD tOHSD
The serial interface uses the three pins: SCK, SDIO and CS.
SDIO data is sampled at the rising edge of SCK when CS is high level. Data unit of one access is three
bytes. The data unit consists of Start byte and Address byte and Data byte.
The start byte has parity bit and access mode bit. Relationship of access mode setting and the
operation are shown in the table below.
Parity check is odd parity. In Write mode, the parity check is performed on the sum of Start byte and
Address byte and Data byte. In Read mode, the parity check is performed on the sum of Start byte and
Address byte. Burst access is not support. One access is complete, CS should be set to low level once.
tV 748
tVPOS 25
tVPW tVA 720 tVFP 3(Fix)
VSYNC
HSYNC
DE
tH 1288
tHPOS 268 tHA 960 tHFP 60
tHPW
HSYNC
tCLK
DE
CLK
V DD 0.8VDD
t1 0.8VDD 0.8VDD t7
0.2VDD 0.2VDD
t3 t8
STEP-B1(*1)
STEP-A1~A3
Refresh sequence
SPI
(STEP-C1~C4)
(SCK, CS, t5 t6
t9 t10
t11
Note 1:
a) When power supply is OFF (VDD=0V), logic input must be kept at either VSS level or high
impedance
b) The rising speed of power supply (VDD=+3.3V) should be less than 2V/100µs.
c) When the PWRON signal is 0V, VDD must be 0V. (However t1 and t7 except)
d) LVDS signal level of the invalid period may be within the absolute maximum rating.
Note 2: STEP-B1 send after STEP-A3
Note 3: In order to avoid high Inrush current, VLED rising time need to set more than 0.5ms.
(Normal operation)
STEP-B1
(Display on)
Write 01h to DISPON_CMD(E0h)
(Refresh sequence)
STEP-C1
Write the specified data.
address:05h~0Fh,
2Bh~46h,
48h~49h
STEP-C2
Write the deigital gamma data.
Address:10h~2Ah
Power Off
RO0-/+ OG1[2] OR1[7] OR1[6] OR1[5] OR1[4] OR1[3] OR1[2] OG2[2] OR2[7] OR2[6] OR2[5] OR2[4] OR2[3] OR2[2] OG3[2] OR3[7] OR3[6]
RO1-/+ OB1[3] OB1[2] OG1[7] OG1[6] OG1[5] OG1[4] OG1[3] OB2[3] OB2[2] OG2[7] OG2[6] OG2[5] OG2[4] OG2[3] OB3[3] OB3[2] OG3[7]
RO2-/+ DE VSYNC HSYNC OB1[7] OB1[6] OB1[5] OB1[4] DE VSYNC HSYNC OB2[7] OB2[6] OB2[5] OB2[4] DE VSYNC HSYNC
NO.
SHEET
1st pixel data
CLKE-/+
RE0-/+ EG1[2] ER1[7] ER1[6] ER1[5] ER1[4] ER1[3] ER1[2] EG2[2] ER2[7] ER2[6] ER2[5] ER2[4] ER2[3] ER2[2] EG3[2] ER3[7] ER3[6]
RE1-/+ EB1[3] EB1[2] EG1[7] EG1[6] EG1[5] EG1[4] EG1[3] EB2[3] EB2[2] EG2[7] EG2[6] EG2[5] EG2[4] EG2[3] EB3[3] EB3[2] EG3[7]
RE2-/+ DE VSYNC HSYNC EB1[7] EB1[6] EB1[5] EB1[4] DE VSYNC HSYNC EB2[7] EB2[6] EB2[5] EB2[4] DE VSYNC HSYNC
RE3-/+ - EB1[1] EB1[0] EG1[1] EG1[0] ER1[1] ER1[0] - EB2[1] EB2[0] EG2[1] EG2[0] ER2[1] ER2[0] - EB3[1] EB3[0]
7B64PS 2709-TX31D203VM0EAB-2
2nd pixel data
PAGE
9-14/15
9.8 DATA INPUT for DISPLAY COLOR
Relationship between input data and display color
Fig. 11.1
Metal frame
A zone
B zone
Fig. 11.2
a+b
Average diameter =
b
2
Fig
Fig.11.5
11.5
4 1 2 3 T 1 2 3 4 5 6
Serial number
T: Made in Taiwan
Week
Month
Year
Fig.
Fig 13.1
13.1
2) The tables as below are showing what the first 4 digits of lot mark are shorted for.
3) Except letters I and O, revision number will be shown on lot mark and following letters A to Z.
4) The location of the lot mark is on the back of the display shown in Fig. 13.2.
Label example:
TX31D203VM0EAB REV:A
4123T (5D) 123456
Fig. 13.2