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Power dissipation in CMOS : Introduction

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2 jj 2/22/2019
Power dissipation in CMOS : Introduction

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3 jj 2/22/2019
Power dissipation in CMOS

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4 jj 2/22/2019
Power dissipation in CMOS

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5 jj 2/22/2019
Power dissipation in CMOS

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6 jj 2/22/2019
Power dissipation in CMOS

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7 jj 2/22/2019
 CMOS Inverter
• Inverter structure, which consists of an enhancement-type

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nMOS transistor and an enhancement-type pMOS transistor,
operating in complementary mode

• The circuit topology is complementary push-pull in the sense

that for high input, the nMOS transistor drives (pulls down) the
output node while the pMOS transistor acts as the load, and for
low input the pMOS transistor drives (pulls up) the output node
while the nMOS transistor acts as the load

• Both devices contribute equally to the circuit operation

characteristics.

8 jj 2/22/2019
9jj
CMOS Inverter

2/22/2019

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 CMOS Inverter:

•Input voltage is connected to the gate terminals of both

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the nMOS and the pMOS transistors.

•The substrate of the nMOS transistor is connected to the

ground, while the substrate of the pMOS transistor
is connected to the power supply voltage, VDD, in
order to reverse-bias the source and drain
junctions.

•Since VSB = 0 for both devices, there will be no

substrate-bias effect for either device.
10 jj 2/22/2019
 The Static CMOS Inverter

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• Simple switch model of the MOS transistor

• A switch with an infinite off resistance (for |VGS| < |VT|),

and a finite on-resistance (for |VGS| > |VT|)

11 jj 2/22/2019
 CMOS Inverter: Voltage-transfer characteristics

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12 jj 2/22/2019
 CMOS Inverter: Voltage-transfer characteristics

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 Region R1: 0 < Vin < Vthn, NMOS transistor is off, PMOS
device operates in the linear region.

 Region R2: Vthn< Vin< VDD - |Vthp|

and Vin + |Vthp| < Vout ≤ VDD,
NMOS transistor in saturation, and PMOS transistor
still in the linear region.

 Region R3: Vthn<Vin<VDD - |Vthp|

and Vin - Vthn ≤ Vout ≤ Vin + |Vthp|,
both the transistors are in saturation.
13 jj 2/22/2019
 CMOS Inverter: Voltage-transfer characteristics

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 Region R4: Vthn < Vin< VDD – |Vthp| and
Vout < Vin- Vthn, NMOS transistor
is in the linear region and PMOS remains in saturation.

 Region R5: VDD – |Vthp| < Vin < VDD,

PMOS transistor in cut-off, NMOS in the linear region.

14 jj 2/22/2019
 Sources of power dissipation in CMOS
 There are two types of power dissipation in CMOS circuits:

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dynamic and static.
 Dynamic power dissipation is caused by switching
activities of the circuits.
 A higher operating frequency leads to more frequent switching
activities in the circuits and results in increased power
dissipation.
 Static power dissipation is related to the logical states of the
circuits rather than switching activities.
 In CMOS logic, leakage current is the only source of static power
dissipation.

15 jj 2/22/2019
 Sources of power dissipation in CMOS
 The most significant source of dynamic power dissipation in

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CMOS circuits is the charging and discharging of capacitance.
 Sometimes, capacitors are intentionally fabricated to achieve certain
non-digital operations such as charge sharing and signal delay
 However, most digital CMOS circuits do not require capacitors for
their intended operations.
 The capacitance forms due to parasitic effects of
interconnection wires and transistors
 Such parasitic capacitance cannot be avoided and it has a significant
impact on the power dissipation of the circuits
 The estimation and analysis of parasitic capacitance is a crucial subject
matter not only for signal delay, but also for power.

16 jj 2/22/2019
 Charging and Discharging Capacitance
 Figure 1.1 depicts the equivalent

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circuit of charging and discharging
output capacitance of a CMOS logic
gate
 A switch that flips up and down to
model the charging and discharging
cycles
 Referring to the figure, V is an ideal
constant voltage source and Rc (Rd )
is the resistance of the charging
(discharging) circuitry, either
intentional or parasitic
17 jj 2/22/2019
 Charging and Discharging Capacitance
 According to the laws of physics, the voltage v c(t) and the

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current i (t) of a capacitance C L at time t are given by

18 jj 2/22/2019
 Charging and Discharging Capacitance

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19 jj 2/22/2019
 Charging and Discharging Capacitance

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20 jj 2/22/2019
 Charging and Discharging Capacitance
 Generality and applicability of the P = C L V2 f equation

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 During charging, C L V2 energy is drawn from the energy source,
half of which is dissipated in the charging resistance Rc and the
other half is stored in the capacitor.
 During discharge, the energy stored in the capacitor is dissipated
as heat in the discharging resistor Rd.
 Assumptions are made in our derivation:
1. The capacitance C L is constant.
2. The voltage V is constant.
3. The capacitor is fully charged and discharged, i.e., Vc(to) = 0,
Vc (t1) = V, Vc(t2) = 0

21 jj 2/22/2019
 Charging and Discharging Capacitance
 The result is independent of the charging and discharging circuitry

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Rc , Rd ;
 The length of charging and discharging cycle to, t1, t2 ;
 The voltage or current waveform v c(t), ic(t), etc.
 Rc & Rd can be nonlinear, time varying resistance (such as a
transistor)
 Derivation is still valid as long as the three assumptions are
satisfied.
 For most CMOS circuits operating at medium to high frequency,
this is the prevailing mode of power dissipation.

22 jj 2/22/2019
 Charging and Discharging Capacitance
 Total power summed over each capacitance Ci in a circuit

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23 jj 2/22/2019
 Charging and Discharging Capacitance

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24 jj 2/22/2019
 Charging and Discharging Capacitance

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25 jj 2/22/2019
 Short-circuit Current in CMOS Circuit
 Another component of power dissipation caused by signal switching

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called short-circuit power.
 Short-circuit Current of an Inverter

26 jj 2/22/2019
 Short-circuit Current in CMOS Circuit
 Figure 1.2 shows a simple CMOS inverter operating at Vdd with the

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transistor threshold voltages of Vtn and Vtp
 When the input signal level is above Vtn the N-transistor is turned
on.
 When the signal level is below Vtp the P-transistor is turned on.
 When the input signal Vi switches, there is a short duration in which
the input level is between V tn and Vtp and both transistors are
turned on.
 This causes a short-circuit current from Vdd to ground and
dissipates power.
 The electrical energy drawn from the source is dissipated as heat in
the P and N -transistors.

27 jj 2/22/2019
 Short-circuit Current in CMOS Circuit
 From the first order analysis of the MOS transistor model, the time

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variation of the short-circuit current during signal
transition is shown in Figure 1.3.

28 jj 2/22/2019
 Short-circuit Current in CMOS Circuit
 The current is zero when the input signal is below Vtn

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or above Vtp.
 The current increases as Vi rises beyond Vtn and decreases
as it approaches Vtp.
 Since the supply voltage is constant, the integration of
the current over time multiplies by the supply
voltage is the energy dissipated during the input
transition period.

29 jj 2/22/2019
 Short-circuit Current in CMOS Circuit
 The shape of the short-circuit current curve is dependent on several

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factors:
1. The duration and slope of the input signal
2. The I-V curves of the P and N transistors, which depend
on their sizes, process technology, temperature, etc.
3. The output loading capacitance of the inverter.

30 jj 2/22/2019
 Short-circuit Current in CMOS Circuit

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31 jj 2/22/2019
 Short-circuit Current in CMOS Circuit

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32 jj 2/22/2019
 Short-circuit Current in CMOS Circuit

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33 jj 2/22/2019
 Short-circuit Current in CMOS Circuit

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34 jj 2/22/2019
 Short-circuit Current in CMOS Circuit
 where ß is the size of the transistors and is the duration of

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the input signal.
 This equation is useful in showing the relationship of each parameter to
the short-circuit energy or power dissipation but is seldom used to
compute the actual value.
 In real circuits, the actual energy dissipation is a complex function of the
factors listed above.
 Furthermore, the equation assumes that the output loading capacitance
of the CMOS inverter is zero which is not true in real circuits.

36 jj 2/22/2019
 Short-circuit Current in CMOS Circuit
 Despite the difficulties in expressing the short-circuit current and energy, they can
be computed quite accurately using circuit simulators such as SPICE.

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 To obtain the short-circuit current when the inverter input changes from
low to high, - measure the source-drain current of the N-transistor.
 If the input changes from high to low, - measure current through the P-
transistor.
 As a rule of thumb, short circuit power dissipation is generally 10-60% of the
total power dissipation of a CMOS gate.
 In a cell-based design in which all basic circuit elements are pre-designed, the
short-circuit power dissipation can be characterized much like
timing delay
 For a full-custom design style in which cells are not characterized,
transistor-level simulation can be used to measure the power dissipation with
reasonable accuracy and speed

37 jj 2/22/2019
 Short-circuit Current Variation with Output Load
 Short-circuit current exhibits some characteristic with

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respect to the output loading capacitance and the input
signal slope of a CMOS inverter.
 These characteristics have some implications on the analysis and
optimization of the power efficiency for CMOS circuits.
 Duration of short-circuit current depends on the transition
period of the input signal.
 The short-circuit current depend on the output loading capacitance

38 jj 2/22/2019
 Short-circuit Current Variation with Output Load
 Consider the case when the input voltage is falling and the output
voltage is rising.

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 Based on the on-off properties of the transistors, the short-circuit
current is non-zero only when the input level is between V tn
and Vtp.
 When the inverter input is at 0.5 Vdd , its output voltage is
somewhere between zero and 0.5 Vdd assuming a symmetrical
transfer curve.
 If the output capacitance is large, the output voltage barely
rises above zero and the voltage across the source and drain of the N
transistor is only slightly above zero.
 The low source-drain potential difference results in small
short-circuit current.

39 jj 2/22/2019
 Short-circuit Current Variation with Output Load
 Conversely, if the output capacitance is small, the output

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voltage rises faster and the source-drain voltage is much
higher, causing a larger short-circuit current.
 To see the effects of output capacitance on short-circuit current, --
several SPICE simulations with different capacitance values while
keeping all conditions (signal slope, temperature, etc.) constant.
 The short-circuit currents are plotted in Figure 1.4.*

40 jj 2/22/2019
 Short-circuit Current Variation with Output Load

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41 jj 2/22/2019
 Short-circuit Current Variation with Output Load
 short-circuit current envelope is the largest when the output

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capacitance is the smallest.
 As the output capacitance increases, the current envelope becomes
smaller and eventually approaches zero.
 However, the duration of the short circuit current is
independent of the output capacitance because it depends
on the input signal slope only.
 The short-circuit current is non-zero only when the input voltage is
between Vtn and Vtp.
 Thus if all conditions are kept identical, increasing the output
loading capacitance has the effect of reducing the short-
circuit energy per transition.

42 jj 2/22/2019
 Short-circuit Current Variation with Output Load
 From the above observation, one might question

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whether increasing the output loading capacitance can
reduce power dissipation of the circuit because of smaller
shortcircuit current; or is there an optimum output
loading value that optimizes the total power dissipation of
a CMOS gate?
 The answer is negative as shown by Figure 1.5.
 In this experiment, we again keep all conditions identical and vary
only the output capacitance.
 This time, we measure the total current, i.e., the sum of short-
circuit current and the capacitance charging or
discharging current.

43 jj 2/22/2019
 Short-circuit Current Variation with Output Load

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44 jj 2/22/2019
 Short-circuit Current Variation with Output Load
 The results show that when the output capacitance is

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increased, the total current always increases in peak as
well as duration.

 This means that increasing the output capacitance decreases

the short-circuit power dissipation but the sum of
capacitive and short-circuit power increases.

 Therefore, capacitance is always the enemy of power efficiency and a

low power digital design should always strive to reduce
loading capacitance.

45 jj 2/22/2019
 Short-circuit Current Variation with Output Load
 A major contribution of capacitance is the input capacitance of the

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signal receiving gate.
 The size of the receiving gate is constrained by its speed
requirement.
 Driving a signal faster than necessary results in wasted power.
 Thus for low power design, a good design practice is to
choose the minimum gate size that meets the speed
constraint to minimize capacitance.
 This agrees with the minimum area design goal and presents no
conflicting requirements in the area-power trade-off.

46 jj 2/22/2019
 Short-circuit Current Variation with Output Load
 To understand the effects of increasing output capacitance on short-

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circuit current , capacitor current and total current
 width (the duration in which the current is non-zero), peak and the
integration of the current envelope over time, which corresponds to
the energy dissipated per transition.
 The observations are summarized in the following table:

47 jj 2/22/2019
 Short-circuit Current Variation with Input Signal Slope

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48 jj 2/22/2019
 Short-circuit Current Variation with Input Signal Slope
 As the input signal slope deteriorates (longer signal transition time),

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the short-circuit current peak and duration increase.
 For the total current, i.e., short-circuit plus capacitance current, the
width increases but the peak decreases.
 Integration of the total current over time (energy) is increasing.
 The capacitive charging/discharging energy remains identical
because the capacitance is kept constant
 The observations are summarized in Table 1.2

49 jj 2/22/2019
 Short-circuit Current Variation with Input Signal Slope
 To improve power efficiency of a CMOS circuit, we should use

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the fastest input signal slope for all signals.

 while the sharp signal slope reduces power dissipation of the signal
receiving gate, the transistor sizes of the signal driving gate
have to be increased to sustain the steep slope.

 A larger driver gate means more power consumption due

to increased input capacitance and short-circuit current

 Thus, enforcing sharp signal slopes presents conflicting effects on

the power dissipation of the signal driver and receiver gates
50 jj 2/22/2019
 Glitch Power Dissipation

 Glitches are temporary changes in the value of the output –

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unnecessary transitions
 They are caused due to the skew in the input signals to a gate
 Glitch power dissipation accounts for 15% – 20 % of the global
power
 Basic contributes of hazards to power dissipation are
 Hazard generation
 Hazard propagation

51 jj 2/22/2019
 Glitch Power Dissipation

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 P = 1/2 .CL.Vdd . (Vdd – Vmin) ;
Vmin : min voltage swing at the output
 Glitch power dissipation is dependent on
 Output load
 Input pattern
 Input slope

52 jj 2/22/2019
 Glitch Power Dissipation

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 Hazard generation can be reduced by gate sizing and path balancing
techniques
 Hazard propagation can be reduced by using less number of
inverters which tend to amplify and propagate glitches

53 jj 2/22/2019
 CMOS Leakage Current

 In circuits that use MOS transistors, there are two major sources of

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leakage current:

1. reverse biased PN-junction current

2. subthreshold channel conduction current.

54 jj 2/22/2019
 CMOS Leakage Current - Reverse Biased PN-junction
 Leakage current occurs when the source or drain of an N-

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transistor (P-transistor) is at Vdd (Gnd).
 PN-junctions are formed at the source or drain of transistors
because of a parasitic effect of the bulk CMOS device
structure
 Figure 1.7, the junction current at the source or drain of the
transistor is picked up through the bulk or well contact.

55 jj 2/22/2019
 CMOS Leakage Current - Reverse Biased PN-junction
 The magnitude of the current depends on the temperature,

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process, bias voltage and the area of the PN-junction.
 Analysis of the semiconductor physics shows that the reverse biased
PN-junction current is

56 jj 2/22/2019
 CMOS Leakage Current - Reverse Biased PN-junction

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57 jj 2/22/2019
 CMOS Leakage Current - Reverse Biased PN-junction

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 To summarize, the reverse biased PN-junction current is
largely independent of operating voltage
 but depends on the fabrication process, junction area and
temperature.

 Generally, the leakage current is not a problem for most chips and
there is very little one can do to reduce this current in a large scale
digital design.

58 jj 2/22/2019
 CMOS Leakage Current - Subthreshold Channel Leakage
 The second source of leakage current is the subthreshold

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leakage through a MOS device channel.
 Even though a transistor is logically turned off, there is a
non-zero leakage current through the channel at the
microscopic level, as illustrated in Figure 1.8.

59 jj 2/22/2019
 CMOS Leakage Current - Subthreshold Channel Leakage
 This current is known as the subthreshold leakage because it occurs

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when the gate voltage is below its threshold voltage.
 Other than the device dimension and fabrication process,
the magnitude of the subthreshold conduction current Isub further
depends on: gate voltage VgS, drain voltage V ds and
temperature.
 Subthreshold conduction current Isub depends on:
1 device dimension
2 fabrication process
3 gate voltage VgS
4 drain voltage V ds
5 temperature.
60 jj 2/22/2019
 CMOS Leakage Current - Subthreshold Channel Leakage
 The dependency on V ds is insignificant when it is much

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larger the thermal voltage.
 In CMOS circuits, V ds ~ Vdd when subthreshold current occurs
and thus, the current essentially depends on Vgs, device dimension
and operating temperature.

61 jj 2/22/2019
 CMOS Leakage Current - Subthreshold Channel Leakage

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62 jj 2/22/2019
 CMOS Leakage Current - Subthreshold Channel Leakage

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63 jj 2/22/2019
64
jj
 To summarize

2/22/2019

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 Power and Energy

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 Power is drawn from a voltage source attached to the VDD
pin(s) of a chip.

 Instantaneous Power: P(t )  iDD (t )VDD

T T

 Energy: E   P(t )dt   iDD (t )VDD dt

0 0
T
E 1
 Average Power: Pavg    iDD (t )VDD dt
T T 0

Slide 65 jj 2/22/2019
 Dynamic Power

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 A signal transition can be classified into two categories
 a functional transition and
 a glitch

Slide 66 jj 2/22/2019
 Dynamic Power (Switching Power)

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 Dynamic power is required to charge and discharge load
capacitances when transistors switch.

 One cycle involves a rising and falling output.

 On rising output, charge Q = CVDD is required
 On falling output, charge is dumped to GND
VDD
 This repeats Tfsw times
iDD(t)
over an interval of T
C
fsw

Slide 67 jj 2/22/2019
 Dynamic Power Cont.

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T
1
Pdynamic   iDD (t )VDD dt
T 0
T
VDD

T 0 iDD (t )dt

VDD
 TfswCVDD  VDD
T iDD(t)
 CVDD 2 f sw
C
fsw

Slide 68 jj 2/22/2019
 Activity Factor

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 Suppose the system clock frequency = f
 Let fsw = af, where a = activity factor
 If the signal is a clock, a = 1
 If the signal switches once per cycle, a = ½
 Dynamic gates:
 Switch either 0 or 2 times per cycle, a = ½
 Static gates:
 Depends on design, but typically a = 0.1

 Dynamic power:
Pdynamic  aCVDD f 2

69 jj 2/22/2019
 Dynamic Power Reduction

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P
 switching  a CV 2
DD f

 Try to minimize:
 Activity factor
 Capacitance
 Supply voltage
 Frequency

70 jj
 Short Circuit Power Dissipation

 Short circuit current occurs during signal transitions when both the

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NMOS and PMOS are ON and there is a direct path between Vdd and
GND
 Also called crowbar current
 Accounts for more than 20% of total power dissipation
 As clock frequency increases transitions increase consequently short
circuit power dissipation increases
 Can be reduced :
 faster input and slower output
 Vdd <= Vtn + |Vtp|
 So both NMOS and PMOS are not on at the same time

71 jj 2/22/2019
 Glitch Power Dissipation

 Glitches are temporary changes in the value of the output –

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unnecessary transitions
 They are caused due to the skew in the input signals to a gate
 Glitch power dissipation accounts for 15% – 20 % of the global
power
 Basic contributes of hazards to power dissipation are
 Hazard generation
 Hazard propagation

 Hazard generation can be reduced by gate sizing and path balancing

techniques
 Hazard propagation can be reduced by using less number of
inverters which tend to amplify and propagate glitches
72 jj 2/22/2019
 Glitch Power Dissipation

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 P = 1/2 .CL.Vdd . (Vdd – Vmin) ;
Vmin : min voltage swing at the output
 Glitch power dissipation is dependent on
 Output load
 Input pattern
 Input slope

73 jj 2/22/2019
 Static Power

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 Static power is consumed even when chip is quiescent.
 Ratioed circuits burn power in fight between ON transistors
 Leakage draws power from nominally OFF devices

74 jj 2/22/2019
 Static Power Consumption
Vd d

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Istat
Vo ut

CL
Vin =5V

Pstat = P(In=1) .Vdd . Istat

• Dominates over dynamic consumption

Wasted energy …
• Not a function of switching frequency
Should be avoided in almost all cases
75 jj 2/22/2019
 Static Power Dissipation
 Power dissipation occurring when device is in standby mode
 As technology scales this becomes significant

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 Leakage power dissipation
 Components:
 Reverse biased p-n junction
 Sub threshold leakage

76 jj 2/22/2019
 Power Dissipation Sources

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 Ptotal = Pdynamic + Pstatic
 Dynamic power: Pdynamic = Pswitching + Pshortcircuit + Pglitching
 Switching load capacitances
 Short-circuit current
 Glitching current
 Static power: Pstatic = (Isub + Ijunct)VDD
 Subthreshold leakage
 Junction leakage

78 jj 2/22/2019
 Low Power Design

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 Reduce dynamic power
 a: clock gating, sleep mode
 C: small transistors (esp. on clock), short wires
 VDD: lowest suitable voltage
 f: lowest suitable frequency
 Reduce static power
 Selectively use ratioed circuits
 Selectively use low Vt devices
 Leakage reduction:
stacked devices, body bias, low temperature

79
jj 2/22/2019
 Conclusion
 Power dissipation is unavoidable especially as technology scales down

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 Techniques must be devised to reduce power dissipation
 Techniques must be devised to accurately estimate the power
dissipation
 Estimation and modeling of the sources of power dissipation for
simulation purposes

80 jj 2/22/2019