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AT24C16B

This document describes an AT24C16B serial EEPROM chip with the following key specifications: 1. It has 16K bits of serial EEPROM organized into 2048 words of 8 bits each. 2. It operates at low voltages between 1.8V and 3.6V. 3. It uses a two-wire serial interface for communication and has various small packaging options like PDIP, SOIC, and SOT23. 4. It has high endurance of 1 million write cycles and data retention of 100 years.

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lucio perez
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0% found this document useful (0 votes)
72 views20 pages

AT24C16B

This document describes an AT24C16B serial EEPROM chip with the following key specifications: 1. It has 16K bits of serial EEPROM organized into 2048 words of 8 bits each. 2. It operates at low voltages between 1.8V and 3.6V. 3. It uses a two-wire serial interface for communication and has various small packaging options like PDIP, SOIC, and SOT23. 4. It has high endurance of 1 million write cycles and data retention of 100 years.

Uploaded by

lucio perez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Features

• Low-voltage and Standard-voltage Operation


– 1.8 (VCC = 1.8V to 3.6V)
• Internally Organized 2048 x 8 (16K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (3.6V, 2.7V, 2.5V), 400 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 16-byte Page (16K) Write Modes


Partial Page Writes Allowed
Self-timed Write Cycle (5 ms max)
Two-wire
• High-reliability
– Endurance: 1 Million Write Cycles
Serial EEPROM
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra 16K (2048 x 8)
Thin Mini-MAP (MLP 2x3), 5-lead SOT23,
8-lead TSSOP and 8-ball dBGA2 Packages
• Lead-free/Halogen-free
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers

AT24C16B
Description
The AT24C16B provides 16384 bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as 2048 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low-power Preliminary
and low-voltage operation are essential. The AT24C16B is available in space-saving
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead
SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire
serial interface. In addition, the AT24C16B is available in 1.8V (1.8V to 3.6V) version.

Table 1. Pin Configuration


8-lead Ultra Thin
Pin Name Function
Mini-MAP (MLP 2x3) 8-ball dBGA2
A0 - A2 No Connect VCC 8 1 A0 VCC 8 1 A0
SDA Serial Data WP 7 2 A1 WP 7 2 A1
SCL 6 3 A2 SCL 6 3 A2
SCL Serial Clock Input SDA 5 4 GND SDA 5 4 GND

WP Write Protect Bottom View Bottom View

NC No Connect 8-lead TSSOP 8-lead SOIC


A0 1 8 VCC A0 1 8 VCC
GND Ground
A1 2 7 WP A1 2 7 WP
VCC Power Supply A2 3 6 SCL A2 3 6 SCL
GND 4 5 SDA GND 4 5 SDA

5-lead SOT23 8-lead PDIP


SCL 1 5 WP A0 1 8 VCC
A1 2 7 WP
GND 2
A2 3 6 SCL
SDA 3 4 VCC GND 4 5 SDA

5175A–SEEPR–09/06

1
Absolute Maximum Ratings
Operating Temperature..................................–55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature .....................................–65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .................................... –1.0V to +5.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage ............................................ 4.3V conditions for extended periods may affect device
reliability.
DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

2 AT24C16B Preliminary
5175A–SEEPR–09/06
AT24C16B Preliminary

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open-
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The AT24C16B does not use the device
address pins, which limits the number of devices on a single bus to one. The A0, A1, A2
are no connects and can be connected to ground.
WRITE PROTECT (WP): The AT24C16B has a write protect pin that provides hardware
data protection. The write protect pin allows normal read/write operations when con-
nected to ground (GND). When the write protect pin is connected to V CC , the write
protection feature is enabled and operates as shown in Table 2.

Table 2. Write Protect


Part of the Array Protected

WP Pin
Status 24C16B

At VCC Full (16K) Array

At GND Normal Read/Write Operations

Memory Organization AT24C16B, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes
each, the 16K requires an 11-bit data word address for random word addressing.

3
5175A–SEEPR–09/06
Table 3. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (SCL) 6 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.

Table 4. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +3.6V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 3.6 V
ICC1 Supply Current VCC = 3.6V READ at 400 kHz 1.0 2.0 mA
ICC2 Supply Current VCC = 3.6V WRITE at 400 kHz 2.0 3.0 mA

Standby Current VCC = 1.8V 1.0 µA


ISB1 VIN = VCC or VSS
(1.8V option) VCC = 3.6V 3.0
ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA
Output Leakage
ILO VOUT = VCC or VSS 0.05 3.0 µA
Current
VIL Input Low Level(1) −0.6 VCC x 0.3 V
(1)
VIH Input High Level VCC x 0.7 VCC + 0.5 V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
Notes: 1. VIL min and VIH max are reference only and are not tested.

4 AT24C16B Preliminary
5175A–SEEPR–09/06
AT24C16B Preliminary

Table 5. AC Characteristics (Industrial Temperature)


Applicable over recommended operating range from TAI = −40°C to +85°C, VCC = +1.8V to +3.6V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt 2.5-volt 3.6-volt
Symbol Parameter Min Max Min Max Min Max Units
fSCL Clock Frequency, SCL 400 1000 1000 kHz
tLOW Clock Pulse Width Low 1.3 0.4 0.4 µs
tHIGH Clock Pulse Width High 0.6 0.4 0.4 µs
tAA Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 0.05 0.55 µs
Time the bus must be free before a
tBUF 1.3 0.5 0.5 µs
new transmission can start(1)
tHD.STA Start Hold Time 0.6 0.25 0.25 µs
tSU.STA Start Set-up Time 0.6 0.25 0.25 µs
tHD.DAT Data In Hold Time 0 0 0 µs
tSU.DAT Data In Set-up Time 100 100 100 ns
(1)
tR Inputs Rise Time 0.3 0.3 0.3 µs
(1)
tF Inputs Fall Time 300 100 100 ns
tSU.STO Stop Set-up Time 0.6 0.25 0.25 µs
tDH Data Out Hold Time 50 50 50 ns
tWR Write Cycle Time 5 5 5 ms
Write
Endurance(1) 25°C, Page Mode, 3.3V 1,000,000
Cycles
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 3.6V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 VCC

5
5175A–SEEPR–09/06
Device CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on
Operation page 7). Data changes during SCL high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C16B features a low-power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.

6 AT24C16B Preliminary
5175A–SEEPR–09/06
AT24C16B Preliminary

Bus Timing
Figure 2. SCL: Serial Clock, SDA: Serial Data I/O®

Write Cycle Timing


Figure 3. SCL: Serial Clock, SDA: Serial Data I/O

SCL

SDA 8th BIT ACK

WORDn
(1)
twr
STOP START
CONDITION CONDITION

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

Figure 4. Data Validity

7
5175A–SEEPR–09/06
Figure 5. Start and Stop Definition

Figure 6. Output Acknowledge

8 AT24C16B Preliminary
5175A–SEEPR–09/06
AT24C16B Preliminary

Device The 16K EEPROM device requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure 7).
Addressing
The device address word consists of a mandatory one, zero sequence for the first four most
significant bits as shown. This is common to all the EEPROM devices.
The next 3 bits used for memory page addressing and are the most significant bits of the data
word address which follows.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the chip will return to a standby state.

Write BYTE WRITE: A write operation requires an 8-bit data word address following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
Operations respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit
data word, the EEPROM will output a zero and the addressing device, such as a microcontrol-
ler, must terminate the write sequence with a stop condition. At this time the EEPROM enters
an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during
this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on
page 11).
PAGE WRITE: The 16K EEPROM is capable of an 16-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to fifteen data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (see Figure 9 on page 11).
The data word address lower three bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than sixteen data words
are transmitted to the EEPROM, the data word address will “roll over” and previous data will
be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero allowing the read or write sequence to continue.

Read Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
Operations current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll
over” during read is from the last byte of the last memory page to the first byte of the first page.
The address “roll over” during write is from the last byte of the current page to the first byte of
the same page.

9
5175A–SEEPR–09/06
Once the device address with the read/write select bit set to one is clocked in and acknowl-
edged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condi-
tion (see Figure 10 on page 11).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a fol-
lowing stop condition (see Figure 11 on page 12).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will “roll over” and the sequential read will con-
tinue. The sequential read operation is terminated when the microcontroller does not respond
with a zero but does generate a following stop condition (see Figure 12 on page 12).

10 AT24C16B Preliminary
5175A–SEEPR–09/06
AT24C16B Preliminary

Figure 7. Device Address

16 P2 P1 P0
MSB

Figure 8. Byte Write

Figure 9. Page Write

Figure 10. Current Address Read

11
5175A–SEEPR–09/06
Figure 11. Random Read

Figure 12. Sequential Read

12 AT24C16B Preliminary
5175A–SEEPR–09/06
AT24C16B Preliminary

AT24C16B Ordering Information


Ordering Codes Voltage Package Operating Range
AT24C16B-PU (Bulk Form Only) 1.8 8P3
AT24C16BN-SH-B(1) (NiPdAu Lead Finish) 1.8 8S1
AT24C16BN-SH-T(2) (NiPdAu Lead Finish) 1.8 8S1 Lead-Free
AT24C16B-TH-B(1) (NiPdAu Lead Finish) 1.8 8A2 Halogen-Free
AT24C16B-TH-T(2) (NiPdAu Lead Finish) 1.8 8A2 Industrial Temperature
AT24C16BY6-YH-T(2) (NiPdAu Lead Finish) 1.8 8Y6 (-40°C to 85°C)
AT24C16BTSU-T(2) 1.8 5TS1
AT24C16BU3-UU-T(2) 1.8 8U3-1
Industrial Temperature
AT24C16B-W-11(3) 1.8 Die Sales
(-40°C to 85°C)
Notes: 1. “-B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini MAP, SOT23, dBGA2 = 5K per reel.
3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon
request. Please contact Serial EEPROM Marketing.

Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y6 8-lead, 2.0 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)
5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)
8U3-1 8-ball, die Ball Grid Away Package (dBGA2)
Options
–1.8 Low-voltage (1.8V to 3.6V)

13
5175A–SEEPR–09/06
Packaging Information

8P3 – PDIP

1
E

E1

Top View c
eA

End View

COMMON DIMENSIONS
D (Unit of Measure = inches)
e
D1 SYMBOL MIN NOM MAX NOTE
A2 A
A – – 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
b2 L D1 0.005 – – 3
b3 E 0.300 0.310 0.325 4
4 PLCS b E1 0.240 0.250 0.280 3
e 0.100 BSC
Side View
eA 0.300 BSC 4
L 0.115 0.130 0.150 2

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8P3, 8-lead, 0.300" Wide Body, Plastic Dual
8P3 B
R San Jose, CA 95131 In-line Package (PDIP)

14 AT24C16B Preliminary
5175A–SEEPR–09/06
AT24C16B Preliminary

8S1 – JEDEC SOIC

E E1

N L


Top View
End View
e B
COMMON DIMENSIONS
A
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE


A1 A 1.35 – 1.75
A1 0.10 – 0.25
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
D
E1 3.81 – 3.99
E 5.79 – 6.20
Side View e 1.27 BSC
L 0.40 – 1.27
∅ 0˚ – 8˚

Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

10/7/03
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Colorado Springs, CO 80906 8S1 B
R
Small Outline (JEDEC SOIC)

15
5175A–SEEPR–09/06
8A2 – TSSOP

3 2 1

Pin 1 indicator
this corner

E1 E

L1

N
L
Top View End View
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A D 2.90 3.00 3.10 2, 5


b E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20

e A2 A2 0.80 1.00 1.05


b 0.19 – 0.30 4
D
e 0.65 BSC
Side View L 0.45 0.60 0.75
L1 1.00 REF

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8A2, 8-lead, 4.4 mm Body, Plastic
8A2 B
R San Jose, CA 95131 Thin Shrink Small Outline Package (TSSOP)

16 AT24C16B Preliminary
5175A–SEEPR–09/06
AT24C16B Preliminary

8Y6 - Mini Map

A D2 b
(8X)

Pin 1
Index
Area

E2
E

Pin 1 ID

L (8X)

D
e (6X)
A2 A1
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE


D 2.00 BSC
E 3.00 BSC
D2 1.40 1.50 1.60
E2 - - 1.40
A - - 0.60
A1 0.0 0.02 0.05
A2 - - 0.55
A3 0.20 REF
L 0.20 0.30 0.40
e 0.50 BSC
b 0.20 0.25 0.30 2

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
8/26/05
TITLE DRAWING NO. REV.
2325 Orchard Parkway
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, 8Y6 C
R San Jose, CA 95131 Dual No Lead Package (DFN), (MLP 2x3)

17
5175A–SEEPR–09/06
5TS1 – SOT23
e1

5 4 C

E1 E C
L

L1

1 2 3
Top View End View

A2 A

Seating
Plane A1
e

D
Side View COMMON DIMENSIONS
(Unit of Measure = mm)

NOTES: 1. This drawing is for general information only. Refer to JEDEC Drawing SYMBOL MIN NOM MAX NOTE
MO-193, Variation AB, for additional information. A – – 1.10
2. Dimension D does not include mold flash, protrusions, or gate burrs.
Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per end. A1 0.00 – 0.10
Dimension E1 does not include interlead flash or protrusion. Interlead A2 0.70 0.90 1.00
flash or protrusion shall not exceed 0.15 mm per side.
3. The package top may be smaller than the package bottom. Dimensions c 0.08 – 0.20 4
D and E1 are determined at the outermost extremes of the plastic body D 2.90 BSC 2, 3
exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom of the plastic body. E 2.80 BSC 2, 3
4. These dimensions apply to the flat section of the lead between 0.08 mm E1 1.60 BSC 2, 3
and 0.15 mm from the lead tip.
5. Dimension "b" does not include Dambar protrusion. Allowable Dambar L1 0.60 REF
protrusion shall be 0.08 mm total in excess of the "b" dimension at e 0.95 BSC
maximum material condition. The Dambar cannot be located on the lower
radius of the foot. Minimum space between protrusion and an adjacent lead e1 1.90 BSC
shall not be less than 0.07 mm. b 0.30 – 0.50 4, 5

6/25/03
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink
R Colorado Springs, CO 80906 Small Outline Package (SHRINK SOT) PO5TS1 A

18 AT24C16B Preliminary
5175A–SEEPR–09/06
AT24C16B Preliminary

8U3-1 – dBGA2

D
1. b

A1
PIN 1 BALL PAD CORNER
A2
Top View
A

PIN 1 BALL PAD CORNER Side View


1 2 3 4
(d1)

8 7 6 5
e
COMMON DIMENSIONS
(Unit of Measure = mm)
(e1)
SYMBOL MIN NOM MAX NOTE
Bottom View A 0.71 0.81 0.91
8 SOLDER BALLS
A1 0.10 0.15 0.20
A2 0.40 0.45 0.50
b 0.20 0.25 0.30
D 1.50 BSC
1. Dimension “b” is measured at the maximum solder ball diameter.
E 2.00 BSC
This drawing is for general information only. e 0.50 BSC
e1 0.25 REF
d 1.00 BSC
d1 0.25 REF

6/24/03
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
R Colorado Springs, CO 80906 Small Die Ball Grid Array Package (dBGA2) PO8U3-1 A

19
5175A–SEEPR–09/06
Atmel Corporation Atmel Operations
2325 Orchard Parkway Memory RF/Automotive
San Jose, CA 95131, USA 2325 Orchard Parkway Theresienstrasse 2
Tel: 1(408) 441-0311 San Jose, CA 95131, USA Postfach 3535
Fax: 1(408) 487-2600 Tel: 1(408) 441-0311 74025 Heilbronn, Germany
Fax: 1(408) 436-4314 Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Regional Headquarters Microcontrollers
Europe 2325 Orchard Parkway 1150 East Cheyenne Mtn. Blvd.
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