Features

• Low-voltage and Standard-voltage Operation

– 2.7 (VCC = 2.7 to 5.5V)
– 1.8 (VCC = 1.8 to 5.5V)
• Low-power Devices (ISB = 6 µA at 5.5V) Available
• Internally Organized 8192 x 8
• 2-Wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 400 kHz Clock Rate 2-Wire
• Write Protect Pin for Hardware Data Protection
• 32-Byte Page Write Mode (Partial Page Writes Allowed) Serial EEPROM
• Self-Timed Write Cycle (5 ms max)
• High Reliability
64K (8192 x 8)
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Lead-free/Halogen-free Devices Available AT24C64B
• 8-lead JEDEC SOIC and 8-lead TSSOP Packages
• Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers

Description
The AT24C64B provides 65,536 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 8192 words of 8 bits each. The device’s
cascadable feature allows up to 8 devices to share a common 2-wire bus. The device
is optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT24C64B is available in space saving
8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a 2-wire serial
interface. In addition, the entire family is available in 2.7V (2.7 to 5.5V) and 1.8V (1.8
to 5.5V) versions.

Pin Configurations 8-lead SOIC 2-Wire, 32K

Pin Name Function
A0 1 8 VCC Serial E2PROM
A0 - A2 Address Inputs A1 2 7 WP
A2 3 6 SCL
SDA Serial Data
GND 4 5 SDA
SCL Serial Clock Input
WP Write Protect

8-lead TSSOP

A0 1 8 VCC
A1 2 7 WP
A2 3 6 SCL
GND 4 5 SDA

3350E–SEEPR–9/07
Absolute Maximum Ratings*
Operating Temperature...................................... -55 to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ......................................... -65 to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground ....................................... -1.0 to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage .......................................... 6.25V conditions for extended periods may affect
device reliability.
DC Output Current........................................................ 5.0 mA

1. Block Diagram
VCC
GND
WP
SCL START
STOP
SDA LOGIC SERIAL
EN
CONTROL H.V. PUMP/TIMING
LOGIC
LOAD

DEVICE COMP DATA RECOVERY

ADDRESS
COMPARATOR LOAD INC
A2
A1 R/W X DEC
DATA WORD EEPROM
A0 ADDR/COUNTER

Y DEC SERIAL MUX

DIN DOUT/ACK
LOGIC
DOUT

2. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain
driven and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are
hard wired or left not connected for hardware compatibility with other AT24CXX devices. When
the pins are hardwired, as many as eight 64K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device Addressing section). If the pins are
left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive cou-

2 AT24C64B
3350E–SEEPR–9/07
 AT24C64B

pling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel recommends connecting
the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write
operations. When WP is connected high to VCC, all write operations to the upper quandrant (16K
bits) of memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to
GND if the capacitive coupling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel
recommends connecting the pin to GND.

3. Memory Organization
AT24C64B, 64K SERIAL EEPROM: The 64K is internally organized as 256 pages of 32 bytes
each. Random word addressing requires a 13 bit data word address.

Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics
Applicable over recommended operating range from: TAI = -40 to +85°C, VCC = +1.8 to +5.5V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V READ at 400 kHz 0.4 1.0 mA
ICC2 Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA
Standby Current
ISB1 VCC = 1.8V VIN = VCC or VSS 1.0 μA
(1.8V option)
Standby Current
ISB2 VCC = 2.7V VIN = VCC or VSS 2.0 μA
(2.7V option)
Standby Current
ISB3 VCC = 4.5 - 5.5V VIN = VCC or VSS 6.0 μA
(5V option)
Input Leakage
ILI VIN = VCC or VSS 0.10 3.0 μA
Current
Output Leakage
ILO VOUT = VCC or VSS 0.05 3.0 μA
Current
VIL Input Low Level(1) -0.6 VCC x 0.3 V
(1)
VIH Input High Level VCC x 0.7 VCC + 0.5 V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
Note: 1. VIL min and VIH max are reference only and are not tested.

3
3350E–SEEPR–9/07
4. AC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
AT24C64B
1.8V – 3.6V 5.0V
Symbol Parameter Min Max Min Max Units
fSCL Clock Frequency, SCL 400 400 kHz
tLOW Clock Pulse Width Low 1.3 1.2 µs
tHIGH Clock Pulse Width High 0.6 0.6 µs
(1)
tI Noise Suppression Time 100 50 ns
tAA Clock Low to Data Out Valid 0.2 0.9 0.1 0.9 µs
(2)
tBUF Time the bus must be free before a new transmission can start 1.3 1.2 µs
tHD.STA Start Hold Time 0.6 0.6 µs
tSU.STA Start Set-up Time 0.6 0.6 µs
tHD.DAT Data In Hold Time 0 0 µs
tSU.DAT Data In Set-up Time 100 100 ns
(2)
tR Inputs Rise Time 0.3 0.3 µs
tF Inputs Fall Time(2) 300 300 ns
tSU.STO Stop Set-up Time 0.6 0.6 µs
tDH Data Out Hold Time 200 50 ns
tWR Write Cycle Time 5 5 ms
(1
Endurance Write
) 5.0V, 25°C, Page Mode 1M 1M
Cycles

Notes: 1. This parameter is characterized and is not 100% tested (TA = 25°C)
2. This parameter is characterized and is not 100% tested.

4 AT24C64B
3350E–SEEPR–9/07
 AT24C64B

5. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (refer to Data Valid-
ity timing diagram). Data changes during SCL high periods will indicate a start or stop condition
as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (refer to
Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C64B features a low power standby mode which is enabled: a)
upon power-up and b) after the receipt of the Stop bit and the completion of any internal
operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part
can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create
a start condition as SDA is high.

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3350E–SEEPR–9/07
6. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
tHIGH
tF tR

tLOW tLOW
SCL

tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO

SDA IN

tAA tDH tBUF

SDA OUT

7. Write Cycle Timing

SCL: Serial Clock, SDA: Serial Data I/O

SCL

SDA 8th BIT ACK

WORDn
(1)
twr

STOP START
CONDITION CONDITION
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

6 AT24C64B
3350E–SEEPR–9/07
 AT24C64B

8. Data Validity

SDA

SCL

DATA STABLE DATA STABLE

DATA
CHANGE

9. Start and Stop Definition

SDA

SCL

START STOP

10. Output Acknowledge

SCL 1 8 9

DATA IN

DATA OUT

START ACKNOWLEDGE

7
3350E–SEEPR–9/07
11. Device Addressing
The 64K EEPROM requires an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see Figure 13-1 on page 11). The device address word
consists of a mandatory one, zero sequence for the first four most significant bits as shown. This
is common to all 2-wire EEPROM devices.
The 64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the
same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1,
and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins
are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is ini-
tiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to standby state.
NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small
noise spikes from activating the device. A low-VCC detector (5-volt option) resets the device to
prevent data corruption in a noisy environment.
DATA SECURITY: The AT24C64B has a hardware data protection scheme that allows the user
to write protect the upper quadrant (16K bits) of memory when the WP pin is at VCC.

12. Write Operations

BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addressing device, such as a microcontroller,
must terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this
write cycle and the EEPROM will not respond until the write is complete (see Figure 13-2 on
page 11).
PAGE WRITE: The 64K EEPROM is capable of 32-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 31 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (see Figure 13-3 on page 11).
The data word address lower 5 bits are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row
location. When the word address, internally generated, reaches the page boundary, the follow-
ing byte is placed at the beginning of the same page. If more than 32 data words are transmitted
to the EEPROM, the data word address will “roll over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a zero, allowing the read or write sequence to continue.

8 AT24C64B
3350E–SEEPR–9/07
 AT24C64B

13. Read Operations

Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll over”
during read is from the last byte of the last memory page, to the first byte of the first page. The
address “roll over” during write is from the last byte of the current page to the first byte of the
same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged
by the EEPROM, the current address data word is serially clocked out. The microcontroller does
not respond with an input zero but does generate a following stop condition (see Figure 13-4 on
page 12).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition. The
microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a follow-
ing stop condition (see Figure 13-5 on page 12).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory address
limit is reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a zero
but does generate a following stop condition (see Figure 13-6 on page 12).

Figure 13-1. Device Address

9
3350E–SEEPR–9/07
Figure 13-2. Byte Write

Figure 13-3. Page Write

Note: 1. * = DON’T CARE bits

Figure 13-4. Current Address Read

10 AT24C64B
3350E–SEEPR–9/07
 AT24C64B

Figure 13-5. Random Read

Note: 1. * = DON’T CARE bits

Figure 13-6. Sequential Read

11
3350E–SEEPR–9/07
AT24C64B Ordering Information(1)
Ordering Code Package Operation Range
(2)
AT24C64BN-10SU-2.7 8S1
Lead-free/Halogen-free
AT24C64BN-10SU-1.8(2) 8S1
Industrial Temperature
AT24C64B-10TU-2.7(2) 8A2
(-40°C to 85°C)
AT24C64B-10TU-1.8(2) 8A2
Industrial Temperature
AT24C64B-W1.8-11(3) Die Sale
(-40°C to 85°C)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
2. “U” designates Green Package & RoHS compliant.
3. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial Marketing.

Package Type
8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 4.4 mm Body, Plastic, Thin Shrink Small Outline Package (TSSOP)
Options
-2.7 Low Voltage (2.7V to 5.5V)
-1.8 Low Voltage (1.8V to 5.5V)

12 AT24C64B
3350E–SEEPR–9/07
 AT24C64B

14. Packaging Information

8S1 – JEDEC SOIC

E E1

N L

Ø
TOP VIEW
END VIEW
e b
A COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1
A 1.35 – 1.75
A1 0.10 – 0.25
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
D
E1 3.81 – 3.99
E 5.79 – 6.20
SIDE VIEW e 1.27 BSC
L 0.40 – 1.27
θ 0˚ – 8˚

Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

3/17/05
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Colorado Springs, CO 80906 Small Outline (JEDEC SOIC) 8S1 C
R

13
3350E–SEEPR–9/07
8A2 – TSSOP

3 2 1

Pin 1 indicator
this corner

E1 E

L1

N
L
Top View End View
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A D 2.90 3.00 3.10 2, 5

b E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20

e A2 A2 0.80 1.00 1.05

b 0.19 – 0.30 4
D
e 0.65 BSC
Side View L 0.45 0.60 0.75
L1 1.00 REF

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8A2, 8-lead, 4.4 mm Body, Plastic
8A2 B
R San Jose, CA 95131 Thin Shrink Small Outline Package (TSSOP)

14 AT24C64B
3350E–SEEPR–9/07
 AT24C64B

Revision History

Doc. Rev. Date Comments

3350E 9/2007 Updated to new template; implemented revision history.

15
3350E–SEEPR–9/07
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3350E–SEEPR–9/07