What is the Antenna Effect?

The term Antenna Effect might not give you the right intuition about the actual
effect it may lead you to think about electromagnetic radiation or transmitter-
receiver concepts but here the case is different. So It has another popular name
which is called “Plasma Induced Gate Oxide Damage” which provides the right
intuition about the effect. As this name itself indicates that this is an effect caused
by the Gate Oxide Damage due to the Plasma Etching process during the
fabrication process of VLSI chips.

Although the antenna effect occurs during the fabrication stage of the chip
especially at the time of plasma etching but the prevention mechanism should be
set in the physical design stage. The fabrication laboratory provides the antenna
rule file which must be checked and designed should be cleaned as per the
antenna rule during the physical signoff stage.

In fabrication flow first FEOL (Front End Of Line) is fabricated which involves the
fabrication of all MOS transistors. Once the FEOL fabrication is done BEOL (Back
End Of Line) fabrication starts which involves the fabrication of metal
interconnects. Antenna effect comes into the picture while BEOL fabrication.

In IC manufacturing process Plasma etching process is used to fabricate the metal

interconnects. Plasma etching is a dry and anisotropic etching process, used for
selective etching. Plasma contains high energetic ions and radicals which get
collected by the metal interconnects while the etching process of metals. Figure-1
shows the structure of MOS and collection of plasma by the interconnect.

Figure-1: MOS structure and plasma etching

The amount of charge accumulation depends on the surface area of interconnect.

These collected ions increase the potential of the interconnect and if the
interconnect is connected to the poly gate, ultimately the potential of the gate will
increase. Due to this increased potential of the gate, a drainage path may be
formed through the gate oxide to substrate to balance this extra accumulated
charge on the gate. If the amount of charge accumulation is high, this drainage
path through the gate oxide may either breakdown the gate oxide which leads to
permanent damage of MOSFET or may create charge trapping in the gate oxide
which further leads to many side effects like early gate oxide breakdown, mobility
degradation and threshold voltage shift.

Gate oxide damage occurs basically due to plasma etching of interconnects

connected to the gate, that’s why this effect is also called “Plasma Induced Gate
Oxide Damage” or “Antenna Effect”. The metal interconnect which collects the
plasma (ions) and is connected to the gate is basically termed as the antenna.
Here it is important to know the fabrication process of interconnects which is
explained in the next section.
Interconnects Fabrication Process

Over the polysilicon, a layer of dielectric is deposited and then cuts are made for
the contact. Over the contact, Metal-1 is deposited and patterned and etched the
extra metal and filled the whole region by the dielectric. Now before fabricating
the metal-2, cuts are made in dielectrics for Via-1 and filled with Via-1 then over
the via-1 Metal-2 is deposited. Again in the same way Metal 2 is etched and filled
with dielectrics. This process is repeated as many times as the number of metal
layers is there. At the end of all the metals processed, A PSG encapsulation is done
as shown in the figure.

There are basically three steps are performed to process any metal layer after the
corresponding via/contact is fabricated.

Deposition

Etching

CMP

In the first step metal is deposited, In the second step the unwanted area of metal
is etched away and in the third step, CMP (Chemical Mechanical Policing) is done.
Antenna Violation Solutions:
Metal Jumpers: Break signal lines and use jumpers to route them to the top metal layers.
The lengthy wire connecting the gate and route to the higher metal layer is broken
when a jumper is inserted. As a result, it grows shorter and less capable of charging. If
an antenna violation occurs on a metal layer, use upper metal layers as a metal jumper
because all of the lower levels have previously been produced.
Diode Insertion: Connecting reverse biased diodes near the gate input when a net is
violated gives a discharge channel to the substrate, saving the transistor’s gate. The
addition of a diode increases the area as well as the capacitance, resulting in a delay
increase.
Antenna Violation: Antenna Violation occurs when the antenna ratio exceeds a value specified in
a Process Design Kit (PDK). The antenna ratio is the ratio of the gate area to the gate oxide area.
The amount of charge collection is determined by the area/size of the conductor (gate area).

Plasma Etching
Here the plasma etching process will be explained in brief just to
understand the process. Plasma etching involves a high-speed
stream of plasma of an appropriate gas mixture being shot at the
sample. The plasma source is known as etch species are either
charged ions or neutral atoms or radicals. During the etching
process, plasma generates volatile etch products from the
chemical reaction between the target material and the reactive
species generated by the plasma. A basic setup of plasma etching
has shown in the figure below.
 Figure-3: Plasma etching setups

Figure-4: Plasma etching process in semiconductor fabrication

Both top and bottom electrodes are equal in size and parallel to each other.
Bottom electrode holds the wafer and it is grounded. Due to the application of RF
voltage and high pressure (P = 100mT to 1T) a plasma is set up between the two
electrodes. High energetic electrons react with gas molecules and give various
reactive species, neutral species and ions. Neutral species provide chemical
etching and ions provide physical etching and a combination of reactive species
and ions provides Ion Enhanced Etching.
Plasma Etching
Here the plasma etching process will be explained in brief just to
understand the process. Plasma etching involves a high-speed
stream of plasma of an appropriate gas mixture being shot at the
sample. The plasma source is known as etch species are either
charged ions or neutral atoms or radicals. During the etching
process, plasma generates volatile etch products from the
chemical reaction between the target material and the reactive
species generated by the plasma. A basic setup of plasma etching
has shown in the figure below.

Figure-3: Plasma etching setups

 Figure-4: Plasma etching process in semiconductor fabrication

Both top and bottom electrodes are equal in size and parallel to each other.
Bottom electrode holds the wafer and it is grounded. Due to the application of RF
voltage and high pressure (P = 100mT to 1T) a plasma is set up between the two
electrodes. High energetic electrons react with gas molecules and give various
reactive species, neutral species and ions. Neutral species provide chemical
etching and ions provide physical etching and a combination of reactive species
and ions provides Ion Enhanced Etching.

Antenna Effect Preventions Techniques

Insert Jumper
To prevent the antenna effect from destroying your circuit you need to reduce the
floating metal/gate area ratio or give the charge a safe way to dissipate to the
ground before it can build up and cause damage. To reduce the floating metal/gate
area ratio, the layout designer must change the routing and go for the higher metal.
Long metal can be taken to a higher metal routing layer. This is known as metal
jumping. This metal jumping is usually done near the gate.

This metal jumping will break the long interconnect and hence the charge collected
on the long interconnect will not discharge through gate oxide because the higher
metal layer is not yet fabricated. Why do we go for the highest metal jumper
because lower metal is already fabricated during the fabrication process, so the
overall area will remain the same, so do we need to go for the higher metal
jumper? Jumpers can be used to effectively control antenna issues, but complicate
the routing by adding lots of extra vias and small pieces of wire into the layout.
Diode InsertionThe diode helps dissipate charges accumulated on metal. The
diode should be placed as near as possible to the gate of the device on the low
level of metal. Connecting a diode to the gate electrode provides a discharging
path for the static charge present on the metal layer. The diode should always
be connected in reverse bias, with the cathode connected to the gate electrode
and the anode connected to ground potential, so that in normal operation
diode act as a reverse bias, and during fabrication, it will act as a restore.

Diodes are a very effective way of preventing antenna effect damage, but the
disadvantage of inserting diodes into a circuit is that they add extra capacitance,
which affects circuit performance, and they increase area.

Reduce the via-area

Large via area also results in process antenna violation. Large multiple via also
may cause the Antenna effect. While conversion of multi-cut vias to double-cut via
or double-cut vias to single-cut via reducing the cut area. This may impose serious
reliability issues such as electromigration.

The whole CMOS fabrication process is

divided into :
i. FEOL or Front End of Line :
In First End of Line we develop transistor
level layout design on the wafer. The
individual components like
transistors , capacitors, resistors, etc. are
fabricated in the semiconductor. FEOL
consist of chemical mechanical polishing
a.k.a Polarization and Cleaning of the
wafer. Shallow Trench Isolation (STI) or
LOCOS (tech node > 0.25 μm) comes
under FEOL. FEOL also include well
formation , gate module formation, Source
and Drain module formation.
ii. MEOL or Mid End of Line :
In Middle End of Line or MEOL we do the
transistor level interconnect. MEOL consist
of semiconductor wafer processing steps
that create local electrical connections
among source/drain/gate of transistors.
Most important part of MEOL is gate
contact formation. Most important part of
MEOL is gate contact formation. It occurs
after Front-End-Of-Line (i.e
transistors/design-capacitor/design-resistor
formation) process are complete. Before
Back-End-Of-Line metal/via/isolation-
dielectric formation processes.
iii. BEOL or Back End of Line :
In Back End of Line we do the PnR level
Interconnect through Metalization/Vias
including Dielectric Separators among
Various Metal layers.
Antenna Effect Phenomenon :
Let's understand what is antenna effect
phenomenon. Now-a-days chemical etching
has been completely replaced by hot
plasma-etching.Plasma related
process are used for CMOS flow for
etching and deposition. The gaseous
plasma contains charged particles
inside. This charge gets transferred to the
under-construction floating metals routes
which may be connected way below up to
the gate areas of MOSFET. At the same
time such metals may not be connected to
any diffusion areas in the FEOL Zone.
Such metal wires act as “antennas” charge
receptors that pick up electrical charge from
the plasma gas. Charge accumulation on
the metal strip is proportional to its length.

Antenna Ratio :
The magnitude of the accumulated charge
depends on the ratio of the floating
conducting region area to the gate area.
This is called the Antenna Ratio and
quoted in Design Rule Manual.
The above equation shows the relationship
between the antenna ratio and the current
densities. A higher antenna ratio means a
larger Vg and, thus more damage.
Antenna Issue Mitigation :
There are a few ways to to eliminate the
antenna effect.
1. Jumper Insertion :
This is creating a metal bridge (a.k.a
jumper) near gate of MOS device so
that while fabrication. This jumper should
take gate connections directly up to the top
level metal
through stacked vias. Consequently the
gate will not see any antenna due to the
break-up of a long metal piece into stacked
metal/via layers. The drawback is the use of
stacked vias can lead to routing congestion,
and hence also to an increase in die
area. Stacked metal/vias may/may-not lead
to EM/IR reliability issues.
2. Gate Protection Diode:
Here we connect each gate to reverse
biased p-n diodes.
Using diode provides a discharge path
directly to the substrate by contact to
a diffusion area. If possible, these diodes
are connected to gate with Metal1 so that
prevention starts right with Metal1
fabrication. During normal operation this
reverse biased diode will not effect
functionality.
However the plasma-induced charge is
discharged through the diodes, leaving gate
unaffected. Drawback is usage of antenna
diodes increase die area by 4-6%.
3. Embedded Protection Diode:
Add protection diodes on every input port
for every standard cell. These diodes are
embedded and fixed. Hence consume
unnecessary area.
4. Diode Insertion After PnR:
Fixing only the wire with the antenna
violation which will not waste
routing resources. During wafer
manufacturing, all the inserted diodes are
floating (or ground). One diode can be used
to protect all input ports that are connected
to the same
output ports.

Effect of charge accumulation in isolated nodes of an integrated circuit during its processing
is known as Antenna effect. This effect is also known as Plasma Induced Damage. The
discharging of accumulated charges, which is done through the thin gate oxide of the
transistor, it might cause damage to the transistors and degrade its performance. During the
fabrication process, we need to etch out the unwanted oxide layer from the wafer, which can
be done using plasma etching. Plasma contains high energetic ions and radicals for etching
that get collected by interconnect. The amount of charge accumulation depends on the
surface area of interconnects. These collected ions increase the potential of interconnects
and if the interconnect is connected to gate, a drainage path could be formed through the
 gate oxide to balance out the charge collection depending upon the amount of charge
collected by interconnects. The drainage path could either breakdown the gate oxide, which
may lead to permanent damage of the device. During the plasma etching of interconnect,
positive ions and neutral species from the plasma get strikes at interconnector these are
collected by the interconnects, so if the area of the interconnect connected to the gates is
large enough then the potential of the interconnect or poly silicon maybe large enough that
it could breakdown the gate oxide.

2. Etching:

Etching refers to the removal of material from the wafer surface. There are two main types
of etching:
 Wet etching: Wafers are immersed in an etchant solution (mixture of chemicals). A
chemical reaction occurs between the wafer surface and the etchants that helps in material
removal.
 Dry etching: In this, plasma or etchant gasses remove unwanted material. This reaction
that take place which can be done by utilizing high kinetic energy of particle beam or
chemical reaction.
3. Plasma Etching:

In this process, chemical etchant is introduced in the gas phase. For etching silicon oxide,
CF4 (tetrafluoromethane) is used. In a chamber, there are two electrodes; one is holding a
wafer and a very high electric field created between these two electrodes. The chamber is
first evacuated before introducing the gas. Radio frequency electrodes are then used to
generate the plasma that ionizes the gas. This ionized gas attacks the oxide layer and
remove the layer.

When high energetic ions beam are bombarded on the target that dislodge portion of the
material from the exposed surface.

Plasma etching is an anisotropic or highly uniform and fair directionality.

 fig 1.
4. Flow of finding antenna violations: Inputs and Outputs.

fig 2.
 Antenna rules: Foundry provides the antenna rule file, which must be followed during the
layout design. In the antenna rules most common rule is Antenna Ratio same as shown in
fig2. Antenna ratio is the ratio of metal area connected to the gate to the total area of gate.

Antenna area/gate area < Maximum Antenna Ratio

 Antenna Violations: Long metal lines and Vias introduce antenna violations. The antenna
rule specifies the maximum tolerance for the ratio of a metal line area to the area of
connected gates. VLSI process starts from the substrate, device layer and then metal
layers. The Etch process builds up the electrical charges on metal layers. These charges
cause a high voltage spike, which may damage the gates connected to the metals. Gate
area is the multiplication of channel length and channel width. Antenna problem is due to
 Bottom area and parameter of the metal line. Via and contact also contributes to the
antenna violations. There are three kinds of antenna violations in the design:
o Metal area antenna rule: The maximum limit to the ratio of the metal line area to the
connected gates area.
o Perimeter antenna rule: The maximum limit to the ratio of the metal line perimeter
connected gates area.
o Via or contact area: The maximum limit to the ratio of the via or contact area to the
connected gates area.

Violations to the above antenna rules in every metal layer have to be fixed before the chip
tape out. Fig 3 shows the layout of one piece of metal connected to a poly gate. The poly
gate with L and W for gate length and gate width and gate area is W*L. The perimeter
antenna ratio for figure is defined as follows:

R=(P*T)/(W*L)

In fig 3, P is the sum of the periphery length for the metal as shown in figure. T is the
thickness of the metal. W and L are the gate width and gate length. The perimeter antenna
rule specifies the upper limit for R. If we increase the W or L for gate or decrease P for
metal line, the ratio R is reduced. Each metal layer may have various upper limit to R based
on the process specifications.

fig3.
 5. Antenna Preventions:

Techniques to fix the antenna violations as follows:

 Routing on Higher Metal Layer: Long metal can be taken to higher metal routing layer.
This is known as metal jumping. This metal jumping is usually done near to the load. This
metal jumping will break the long interconnect and hence the charge collected on the long
interconnect will not discharge through gate oxide because the higher metal layer is not yet
fabricated. This solution may increase the routing congestion on higher metal layer
(see fig4.)
 Reduce the via-area: Large via area also results in process antenna violation. Converting
multi-cut vias to double-cut via or double-cut vias to single-cut via reducing the cut area.
This may impose serious reliability issues such as electro migration.
 Diode Insertion: Diode helps dissipate charges accumulated on metal. Diode should be
placed as near as possible to the gate of device on low level of metal. Connecting a diode to
the gate electrode which provides a discharging path for the static charge present on the
metal layer. Diode should always be connected in reverse bias, with cathode connected to
gate electrode and anode connected to ground potential.

fig 4.
6. Application:
Chip is on 16 nm technology which is being operated at 1GHZ and its size is 7900.0
x 3244.0

We faced Some Antenna violations while working on it.

 Via Area: Violation due to via area which was routed on higher metal let’s say on M8 and
M9 and its net respectively. It was sorted by changing the routing from higher metal routing
 layer M8 and M9 to lower Metal routing layer let’s say M6 and M7. As shown in fig5 and fig6
via area is reduced.
 Metal Area: Violation due to long Metal routing layer let’s say it is on M8, which was
resolved by breaking this layer and connected by inserting jumper near to the load. It can
also be resolved by inserting diode (Reversed Biased) near to the load.
Antenna Ratio :
The magnitude of the accumulated charge
depends on the ratio of the floating
conducting region area to the gate area.
This is called the Antenna Ratio and
quoted in Design Rule Manual.
The above equation shows the relationship
between the antenna ratio and the current
densities. A higher antenna ratio means a
larger Vg and, thus more damage.
Antenna Issue Mitigation :
There are a few ways to to eliminate the
antenna effect.
1. Jumper Insertion :
This is creating a metal bridge (a.k.a
jumper) near gate of MOS device so
that while fabrication. This jumper should
take gate connections directly up to the top
level metal
through stacked vias. Consequently the
gate will not see any antenna due to the
break-up of a long metal piece into stacked
metal/via layers. The drawback is the use of
stacked vias can lead to routing congestion,
and hence also to an increase in die
area. Stacked metal/vias may/may-not lead
to EM/IR reliability issues.
2. Gate Protection Diode:
Here we connect each gate to reverse
biased p-n diodes.
Using diode provides a discharge path
directly to the substrate by contact to
a diffusion area. If possible, these diodes
are connected to gate with Metal1 so that
prevention starts right with Metal1
fabrication. During normal operation this
reverse biased diode will not effect
functionality.
However the plasma-induced charge is
discharged through the diodes, leaving gate
unaffected. Drawback is usage of antenna
diodes increase die area by 4-6%.
3. Embedded Protection Diode:
 Add protection diodes on every input port
for every standard cell. These diodes are
embedded and fixed. Hence consume
unnecessary area.
4. Diode Insertion After PnR:
Fixing only the wire with the antenna
violation which will not waste
routing resources. During wafer
manufacturing, all the inserted diodes are
floating (or ground). One diode can be used
to protect all input ports that are connected
to the same
output ports.

Antenna Effect
•Antenna effect occurs due to the charge
that builds up on metal during
fabrication.
•Antenna violation is caused when the
antenna ratio
 (Exposed gate area/gate oxide area)
exceeds the value mentioned in the
PDK.
•Ions will get collected on the exposed
wafer during polysilicon/Metal etching.
The remaining portion of the metal/PolySi,
which is not getting etched act as an
antenna to collect the ions injected during
this Plasma processing
 •Antenna effect occurs during the dry
etching(Reactive Ion Etching) step of
fabrication process. This process is
conducted in side a chamber , the wafer
will be grounded during the process as
shown in Fig1.
 

•This accumulated charges

causes a potential, which when
becomes large causes gate
oxide damage, Vth shift etc
making the chip useless.
•Solutions
-Can be avoided by using metal
jumpers.
-Can be avoided by using NAC (Net
Area Check) diode.
 - Can be avoided by using dummy
transistor which will increase the
gate oxide area.

• •Using Jumpers:
A shot jumper of higher metal is
placed near the transistor that
causes the antenna violation.
Suppose Antenna violation is
occurring in Nth metal and we are
using N-1 th metal jumper, then
this will again cause violation as N-
1th metal will be already fabricated
 when nth metal is fabricated, so
we must use N+1th metal as
jumper.

*Jumpers introduce extra vias and

therefore degrade both
manufacturing yield and timing
performance.

• •NAC diode
Any diffusion connected to net causes
the ions collected during antenna
violation to reach the substrate as
 reverse leakage current before the
occurrence of gate oxide damage. So
we purposefully add a NAC(Net Area
Check) diode near (as near as
possible allowed in the PDK) the
transistor causing violation.
Make sure that the diode is reverse
biased during normal operation of the
circuit.
Fig 4
* NAC diode are only applicable for M1
and above not for poly(use jumpers),
since diodes are made of diffusion,
which will be formed in the wafer
after polysilicon deposition step. So
during poly etching there won’t be any
diode for protection.

 •Dummy transistor
- Connect a dummy transistor in
such a way that its Gate is connected
to the antenna net causing violation
and Source, Drain & Bulk connected
to GND. This will increase the gate
oxide area thereby reducing Antenna
ratio.
- Dummy transistors can also be
connected as -diode with S & D
connected to the Antenna net and
Gate & bulk connected to the bulk
potential.
Fig 5
