BSIM-SOI 4.6.0 Technical Manual
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Shashank BanchhorBSIM-SOI 4.6.0 Technical Manual
Uploaded by
Shashank BanchhorBSIMSOIv4.6.
0 MOSFET MODEL
Users’ Manual
BSIM GROUP
May 2017
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley, CA 94720
Copyright 2017
The Regents of the University of California
All Rights Reserved
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley
B4SOI Developers:
Tapas Dutta
Chetan Kumar Dabhi
Shivendra Singh Parihar
Chetan Gupta
Harshit Agrawal
Prof. Yogesh Singh Chauhan
Previous BSIMSOI/BSIMPD Developers:
Mr. Hui Wan
Dr. Xuemei Xi
Dr. Samuel Fung
Dr. Dennis Sinitsky
Dr. Stephen Tang
Dr. Pin Su
Dr. Weidong Liu
Dr. Robert Tu
Prof. Mansun Chan
Prof. Ping K. Ko
Prof. Chenming Hu
Dr. Wenwei Yang
Dr. Chung-Hsun Lin
Dr. Tanvir Hasan Morshed
Dr. Darsen Lu
Dr. Angada B. Sachid
Dr. Navid Paydavosi
Prof. Ali Niknejad
Prof. Chenming Hu
BSIMSOIv4.x web site with BSIM source code and documents:
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley
http://bsim.berkeley.edu/models/bsimsoi
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley
Acknowledgement:
The development of BSIMSOIv4.6.0 benefited from the input of many BSIMSOI users,
especially the Compact Model Coalition (CMC) member companies. The developers would
like to thank Joe Saurabh Sirohi and Richard Williams at IBM, Joddy Wang, Jane Xi, and
Weidong Liu at Synopsys, Geoffrey Coram at ADI, Jushan Xie and Yunpeng Pei at
Cadence, Jung-Suk Goo at GLOBALFOUNDRIES, Thomas Miller and Samuel Mertens
at Agilent Technologies, Ahmed Ramadan at Mentor Graphics and James Ma at ProPlus
Design Solutions for their valuable assistance in identifying the desirable modifications
and testing of the new model.
The BSIM project is partially supported by SRC and CMC.
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley
Chapter 1: Introduction 1
Chapter 2: MOS I-V Model 4
2.1. Floating Body Operation and Effective Body Potential 5
2.2. Threshold Voltage in the High Vbs Regime 5
2.2.1. Linear Extrapolation for the Square-Root Expression 5
2.2.2. Width Dependence of the Body Effect 6
2.3. Bulk Charge Effect in the High Vbs Regime 6
2.4. Asymmetric and Bias-Dependent Source/Drain Resistance Model 7
2.5. Single Drain Current Equation 8
Chapter 3: Body Currents Model 10
3.1. Diode and Parasitic BJT Currents 10
3.2. New Impact Ionization Current Equation 13
3.3. Gate Induced Source/Drain Leakage Current 14
3.4. Oxide Tunneling Current 16
3.5. Gate-to-Channel Current (Igc0) and Gate-to-S/D (Igs and Igd) 17
3.5.1 Partition of Igc 18
3.6. Body Contact Current 19
3.6. Body Contact Parasitics 19
Chapter 4: MOS C-V Model 21
4.1. Charge Conservation 23
4.2. Intrinsic Charges 24
4.3. Source/Drain Junction Charges 26
4.4. Extrinsic Capacitances 27
4.5. Body Contact Parasitics 29
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley
4.6 Finite Thickness Formulation 31
Chapter 5: Temperature Dependence and Self-Heating 34
5.1. Temperature Dependence 34
5.2. Self-Heating Implementation 35
Chapter 6: BSIMSOI –A Unified Model for PD and FD SOI MOSFETs 37
6.1. BSIMSOI Framework and Built-In Potential Lowering Model 37
6.2. Verification 41
6.3. Model Selector SOIMOD 43
Chapter 7: BSIMSOI RF Model 46
7.1 Gate Electrode and Intrinsic-Input Resistance (IIR) Model 46
7.2 Body Resistance Network 48
Chapter 8 BSIMSOI Noise Model 49
8.1 Flicker noise models 49
8.2 Thermal noise models 51
8.3 Other improvement on noise model 54
Chapter 9 Stress Effect Model 55
9.1 Mobility Related Equations 55
9.2 Vth-related Equations 57
9.3 Multiple Finger Device 58
Chapter 10 New Material Model 59
10.1 Non-Silicon Channel 59
10.2 Non-SiO2 Gate insulator 60
10.3 Non-Poly Silicon Gate Material 60
Appendix A: Model Instance Syntax 62
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley
A.2. About Optional Nodes 64
A.3. Notes on Debugging 66
Appendix B: Model Parameter List 69
B.1. BSIMSOI Model Control Parameters 69
B.2. Process Parameters 70
B.3. DC Parameters 71
B.4. Gate-to-body tunneling parameters 80
B.5. AC and Capacitance Parameters 81
B.6. Temperature Parameters 83
B.7. BSIMSOI Built-In Potential Lowering (Vbi) Model Parameters 85
B.8. BSIMSOI RF Model Parameters 86
B.9. BSIMSOI Noise Model Parameters 87
B.10. BSIMSOI Stress Model Parameters 87
B.11. Model Parameter Notes 89
Appendix C: Equation List 91
C1: Equation List for BSIMSOI Built-In Potential Lowering Calculation 91
C2: Equation List for BSIMPD IV 94
Appendix D: Parameter Extraction 115
D.1. Extraction Strategy 115
D.2. Suggested I-V Measurement 115
Appendix E: Model Parameter Binning 117
E.1. DC Parameters 118
E.2. AC and Capacitance Parameters 122
References 123
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley
Chapter 1: Introduction
Chapter 1: Introduction
BSIMSOI is an international standard model for SOI (Silicon-On-Insulator) circuit design
[20, 21]. This model is formulated on top of the BSIM3 framework [1]. It shares the same basic
equations with the bulk model so that the physical nature and smoothness of BSIM3v3 are
retained. Most parameters related to general MOSFET operation (non-SOI specific) are directly
imported from BSIM3v3 to ensure parameter compatibility.
BSIMPD [18] is the Partial-Depletion (PD) mode of BSIMSOI. Many enhanced features are
included in BSIMPD through the joint effort of the BSIM Team at UC Berkeley and IBM
Semiconductor Research and Development Center (SRDC) at East Fishkill. In particular, the
model has been tested extensively within IBM on its state-of-the-art high speed SOI technology.
BSIMPD, a derivative of BSIM3SOIv1.3 [2], has the following features and enhancements:
Real floating body simulation in both I-V and C-V. The body potential is determined by
the balance of all the body current components.
An improved parasitic bipolar current model. This includes enhancements in the various
diode leakage components, second order effects (high-level injection and Early effect),
diffusion charge equation, and temperature dependence of the diode junction capacitance.
An improved impact-ionization current model. The contribution from BJT current is also
modeled by the parameter Fbjtii.
A gate-to-body tunneling current model, which is important to thin-oxide SOI
technologies.
Enhancements in the threshold voltage and bulk charge formulation of the high positive
body bias regime.
Instance parameters (Pdbcp, Psbcp, Agbcp, Aebcp, Nbc) are provided to model the
parasitics of devices with various body-contact and isolation structures [17].
An external body node (the 6th node) and other improvements are introduced to facilitate
the modeling of distributed body-resistance [17].
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Chapter 1: Introduction
Self heating. An external temperature node (the 7th node) is supported to facilitate the
simulation of thermal coupling among neighboring devices.
A unique SOI low frequency noise model, including a new excess noise resulting from
the floating body effect [3].
Width dependence of the body effect is modeled by parameters (K1, K1w1, K1w2).
Improved history dependence of the body charges with two new parameters, (Fbody,
DLCB).
An instance parameter Vbsusr is provided for users to set the transient initial condition of
the body potential.
The new charge-thickness capacitance model introduced in BSIM3v3.2 [4], capMod=3,
is included.
In BSIMSOIv4.0, based on BSIMSOIv3.2 [26] and BSIMv4.5.0 bulk model [27], we
included the following features:
1. A scalable stress effect model for process induced stress effect, device performance becoming
thus a function of the active area geometry and the location of the device in the active area;
2. Asymmetric current/capacitance model S/D diode and asymmetric S/D resistance;
3. Improved GIDL model with BSIM4 GIDL compatibility;
4. Noise model Improvements:
1) Improved width/length dependence of flicker noise
2) SPICE2 thermal noise model is introduced as TNOIMOD=2 with parameter NTNOI that
adjusts the magnitude of the noise density
3) Body contact resistance induced thermal noise
4) Thermal noise induced by the body resistance network
5) Shot noises induced by Ibs and Ibd separated
5. A two resistance body resistance network introduced for RF simulation;
6. Threshold voltage model enhancement:
1) Long channel DIBL effect model added
2) Channel-length dependence of body effect improved
7. Drain induced threshold shift (DITS) model introduced in output conductance;
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Chapter 1: Introduction
8. Improved model accuracy in moderate inversion region with BSIM4 compatible Vgsteff;
9. Multi-finger device with instance parameter NF;
10. A new instance parameter AGBCPD to improve gate current for body contact;
11. A new instance parameter DELVTO representing threshold voltage variation;
12. FRBODY is both instance/model parameter.
In BSIMSOIv4.1, the following features are added:
1. A new material model (mtrlMod);
2. Asymmetric GIDL/GISL model and new GIDL/GISL model (gidlMod);
3. A new impact-ionization current model;
4. An improved Coulombic scattering model for high k/metal gate;
5. An improved body-contact model to characterize the opposite-type gate;
6. A new ∆Vbi model to simplify the parameter extraction;
7. A new VgsteffCV model for C-V, which is similar to Vgsteff in I-V;
8. A new gate current component in body contact region;
9. An improved DITS model with more flexibility and better fit.
BSIMSOIv4.2 up to v4.5 benefits from an extensive review of the code by the CMC
members. A significant number of code implement issues/ errors are resolved and fixed in these
versions through close interaction with many user companies. The voltage, temperature and
charge derivatives are reviewed and improved as well. We believe users will greatly benefit from
the improvements introduced in the latest version. In BSIMSOIv4.4 two new features were
added (Vb check in SOIMOD=2 and fringe capacitance model enhancement), compared to
BSIMSOIv4.3.1. The correlated thermal noise model along with many other improvements is
introduced in version 4.5.0.
Note that BSIMSOIv4.6.0 model might not be backward compatible with its previous versions
(BSIMSOIv4.4.0 or below).
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Chapter 2: MOS I-V Model
Chapter 2: MOS I-V Model
A typical PD SOI MOSFET structure is shown in Fig. 2.1. The device is formed on a thin
SOI film of thickness Tsi on top of a layer of buried oxide with thickness Tbox. In the floating
body configuration, there are four external biases which are gate voltage (Vg), drain voltage (Vd),
source voltage (Vs) and substrate bias (Ve). The body potential (Vb) is iterated in circuit
simulation. If a body contact is applied, there will be one more external bias, the body contact
voltage (Vp).
EXTERNAL BODY BIAS
Vp
Vg
Vs Vd
GATE
Tox
SOURCE DRAIN
Tsi
Vb BODY
Tbox
SUBSTRATE
Ve
Fig. 2.1 Schematic of a typical PD SOI MOSFET.
Since the backgate (Ve) effect is decoupled by the neutral body, PD SOI MOSFETs have
similar characteristics as bulk devices. Hence most PD SOI models reported [5, 6] were
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Chapter 2: MOS I-V Model
developed by adding some SOI specific effects onto a bulk model. These effects include parasitic
bipolar current, self-heating and body contact resistance.
BSIMPD is formulated on top of the BSIM3v3 framework. In this way, a lot of physical
effects which are common in bulk and SOI devices can be shared. These effects are reverse short
channel effect, poly depletion, velocity saturation, DIBL in subthreshold and output resistance,
short channel effect, mobility degradation, narrow width effect and source/drain series resistance
[1, 4].
2.1. Floating Body Operation and Effective Body Potential
In BSIMPD, the floating body voltage is iterated by the SPICE engine. The result of iteration
is determined by the body currents [7, 18]. In the case of DC, body currents include diode
current, impact ionization, gate-induced drain leakage (GIDL), oxide tunneling and body contact
current. For AC or transient simulations, the displacement currents originated from the capacitive
coupling are also contributive.
To ensure a good model behavior during simulations, the iterated body potential Vbs is
bounded by the following smoothing function
T1 Vbsc 0.5Vbs Vbsc Vbs Vbsc 2 4Vbsc , Vbsc 5V (2.1)
Vbsh s1 0.5s1 T1 s1 T1 2 4T1 , s1 1.5V (2.2)
Here the body potential Vbsh is equal to the Vbs bounded between (Vbsc, s1), and is used in the
threshold voltage and bulk charge calculation. To validate the popular square root expression
s Vbsh in the MOSFET model, Vbsh is further limited to 0.95s to give the following effective
body potential
Vbseff s 0 0.5 s 0 Vbsh s 0 Vbsh 2 4Vbsh , s 0 0.95 s (2.3)
2.2. Threshold Voltage in the High Vbs Regime
2.2.1. Linear Extrapolation for the Square-Root Expression
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Chapter 2: MOS I-V Model
Using the Vbseff which is clamped to the surface potential s, the square-root dependence
s Vbseff of the threshold voltage is ensured to behave properly during simulations [20].
However the real body potential may be larger than the surface potential in state-of-the-art PD
SOI technologies. To accurately count the body effect in such a high body bias regime, we
extend the square-root expression by
sqrtPhisExt s Vbseff sVbsh Vbseff s
1
, 2 s s 0 (2.4)
where a linear extrapolation is employed for Vbsh 0.95 s . Notice that sqrtPhisExt s Vbseff
for Vbsh 0.95 s .
2.2.2. Width Dependence of the Body Effect
In BSIMPD, the body effect coefficient K1 is replaced by
K
K1eff K1 1 ' 1w1
W K1 w 2 (2.5)
eff
to model the width dependence of the body effect. Notice that K1eff approaches K1 asymptotically
as the effective channel width W’eff increases. While the body effect coefficient will be
determined by the parameters (K1w1, K1w2 ) when W’eff becomes small so that the contribution
from the channel-stop doping should be taken into account.
The complete equation of the threshold voltage Vth can be found in the Appendix C.
2.3. Bulk Charge Effect in the High Vbs Regime
The bulk charge factor in BSIMSOI4.0 is given as
2
K1ox 1 LPEB / Leff A0 Leff Leff B0 (2.6)
Abulk 1 1 A V
L 2 T X gs gsteff
Leff 2 Tsi X dep Weff' B1
2 (s Ketas)
Vbsh eff
si dep
1 Keta Vbsh
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Chapter 2: MOS I-V Model
to accommodate the model behavior in the high body bias regime, which is important in PD SOI.
The parameter Ketas acts like an effective increment of the surface potential, which can be used
to adjust the Abulk rollup with the body potential Vbsh. While the other parameter Keta is used to
tune the rate of rollup with Vbsh. By using this new expression, the non-physical drain current
roll-off due to the dramatic Abulk rollup at high body bias can be avoided [20].
2.4. Asymmetric and Bias-Dependent Source/Drain Resistance Model
The total parasitic resistance at the source/drain terminal consists of two parts: (a) Bias
independent and (b) Bias dependent. BSIMSOIv4.6 offers three different options to model
parasitic resistance with variations on the way the bias dependent and bias independent parts of
the parasitic resistance are handled . These options can be exercised by the switch RDSMOD
as described below:
(a)RDSMOD=0: Bias dependent part of parasitic resistance is internal to the model, while bias
independent part is external to the model. Additional nodes are created. This is same as BSIM3
model.
(b)RDSMOD=1: Both bias dependent and bias independent parts of parasitic resistances
are external to the model. This option allows the source extension resistance Rs(V ) and the drain
extension resistance Rd(V ) to be external and asymmetric (i.e. Rs(V ) and Rd(V ) can be
connected between the external and internal source and drain nodes, respectively; furthermore,
Rs(V ) does not have to be equal to Rd(V )). This feature makes accurate RF CMOS simulation
possible.
(c)RDSMOD=2: Both bias dependent and bias independent parts of parasitic resistances
are internal to the model. This option assumes symmetric source/drain resistances. No additional
nodes are created in this option.
The expressions for source/drain series resistances are as follows:
• rdsMod = 0 (Bias Independent External Series Resistance, Bias Dependent Internal
Resistance)
(√ √ )
( )
( )
Rs = Rs,geo, Rd = Rd,geo
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Chapter 2: MOS I-V Model
• rdsMod = 1 (External Rd(V) and Rs(V))
* +
( )
( )
( )
* +
( )
( )
( )
k BT N gate
Where, V fbsd ln 20 for NGATE larger than 0, otherwise, V fbsd 0 .
q 10
• rdsMod = 2 (Bias Dependent Internal Resistance, Rds(V))
(√ √ )
( )
( )
Where, The resistance Rs,geo and Rd,geo are simply calculated as the sheet resistance (RSH) times
the number of squares (NRS, NRD):
Rs,geo = NRS*RSH
Rd,geo = NRD*RSH
2.5. Single Drain Current Equation
After improving the Vth and Abulk behavior in the high body bias regime, we can describe the
MOSFET drain current by the same equation as BSIM3v3. The effective drain voltage Vdseff and
effective gate overdrive voltage Vgsteff (i.e., effective Vgse – Vth in Appendix C-5) introduced in
BSIM3v3 [1] are employed to link subthreshold, linear and saturation operation regions into a
single expression as
I ds 0 Vds Vdseff
I ds ,MOSFET (1 )
Rds I dso VA
1
Vdseff
Weff
eff Cox
Leff
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Chapter 2: MOS I-V Model
Vdseff
Vgsteff 1 Abulk Vdseff
Idso
2 Vgsteff
2vt
(2.7)
Vdseff
1
Esat Leff
Where, Vdseff is the effective source-drain bias (Appendix C-8), Rds is the source/drain series
resistance, eff is the mobility ( Users are suggested to check the details in Chap. 10 and
Appendix C), Esat is the critical electrical field at which the carrier velocity becomes saturated
and VA accounts for channel length modulation (CLM) and DIBL as in BSIM3v3. The substrate
current body effect (SCBE) [8, 9] on VA is not included because it has been taken into account
explicitly by the real floating body simulation determined by the body currents, which will be
detailed in the next chapter.
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Chapter 3: Body Currents Model
Chapter 3: Body Currents Model
Body currents determine the body potential and therefore the drain current through the body
effect. Beside the impact ionization current considered in BSIM3v3, diode (bipolar) current,
GIDL, oxide tunneling and body contact current are all included in the BSIMPD model [Fig. 3.1]
to give an accurate body-potential prediction in the floating body simulation [18].
3.1. Diode and Parasitic BJT Currents
In this section we describe various current components originated from Body-to-Source/Drain
(B-S/D) injection, recombination in the B-S/D junction depletion region, Source/Drain-to-Body
(S/D-B) injection, recombination current in the neutral body, and diode tunneling current.
Igb
Iii Idiode
Fig. 3.1 Various current components inside the body.
The backward injection current in the B-S/D diode can be expressed as
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Chapter 3: Body Currents Model
Vbs
I bs1 Wdios Tsi j difs exp 1
ndiodesVt
(3.1)
Vbd
I bd 1 Wdiod Tsi j difd exp 1
n dioded Vt
Here ndiodes , jdifs ,Wdios , ndioded , jdifd ,Wdiod are the non-ideality factor, the saturation current, the
effective B-S diode width and the B-D diode width, respectively.
The carrier recombination and trap-assisted tunneling current in the space-charge region is
modeled by
Vbs Vsb Vrec0 s
I bs 2 Wdios Tsi j recs exp exp
0.026n
0.026n
recfs recrs Vrec0 s V sb
(3.2)
Vbd Vdb Vrec0 d
I bd 2 Wdiod Tsi j recd exp exp
0.026n
0.026n
recfd recrd Vrec0 d Vdb
Here nrecfs , nrecrs , jrecs , nrecfd , nrecrd , jrecd are non-ideality factors for forward bias and reverse bias,
the saturation current, respectively. Note that the parameters Vrec0 s , Vrec0 d are provided to model
the current roll-off in the high reverse bias regime.
The reverse bias tunneling current, which may be significant in junctions with high doping
concentration, can be expressed as
Vsb Vtun 0 s
I bs 4 Wdios Tsi jtuns 1 exp
0.026ntuns Vtun 0 s Vsb
(3.3)
Vdb Vtun 0 d
I bd 4 Wdiod Tsi jtund 1 exp
0.026n tund Vtun 0 d V db
where jtuns , jtund are the saturation currents. The parameters ntuns , ntund and Vtun 0 s , Vtun 0 d are
provided to better fit the data.
The recombination current in the neutral body can be described by
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Chapter 3: Body Currents Model
Vbs
I bs 3 1 bjt I ens exp
1
1
ndiodesVt E hlis 1
Vbd
I bd 3 1 bjt I end exp
1
1
n diodedVt E hlid 1
N bjt
1 1
Weff' Tsi jbjts Lbjt 0
I ens
L L
eff n
N bjt
1 1
W Tsi jbjtd Lbjt 0
'
I end eff L
eff Ln
Vbs
E hlis Ahlis _ eff exp 1
ndiodesVt
Vbd
E hlid Ahlid _ eff exp 1
n diodedVt
Leff
2
bjt exp 0.5 (3.4)
Ln
Here bjt is the bipolar transport factor, whose value depends on the ratio of the effective
channel length Leff and the minority carrier diffusion length Ln . jbjts and jbjtd are the saturation
currents, while the parameters Lbjt 0 and N bjt are provided to better fit the forward injection
characteristics. Notice that E hlis and E hlid , determined by the parameter Ahlis and Ahlid , stand for
the high level injection effect in the B-S/D diode, respectively.
The parasitic bipolar transistor current is important in transient body discharge, especially in
pass-gate floating body SOI designs [7]. The BJT collector current is modeled as
V V 1
I c bjt I en exp bs exp bd
ndiodesVt ndiodedVt E2 nd
Eely Eely 2 4 Ehli
E2 nd (3.5)
2
Vbs Vbd
Eely 1
VAbjt Aely Leff
Ehli Ehlis Ehlid
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Chapter 3: Body Currents Model
where E 2 nd is composed of the Early effect Eely and the high level injection roll-off E hli . Note
that E2nd Eely as Eely Ehli . While E2nd Ehli as Ehli Eely , in which case the Early
voltage VAbjt Aely Leff is high.
4 4
To sum up, the total B-S current is I bs I bsi , and the total B-D current is I bd I bdi .
i 1 i 1
The total drain current including the BJT component can then be expressed as
I ds,total I ds,MOSFET I c (3.6)
3.2. New Impact Ionization Current Equation
IiiMod = 0
An accurate impact ionization current equation is crucial to the PD SOI model since it may
affect the transistor output characteristics through the body effect [11]. Hence in BSIMPD we
use a more recent expression [22] to formulate the impact ionization current Iii as
Vdiff
I ii 0 ( I ds , MOSFET I ii _ BJT ) exp
V V 2
2 1 diff 0 diff
Here, when IiiMod = 0, Iii_BJT is defined as:
Iii _ BJT Fbjtii Ic
Vdiff Vds Vdsatii
T L
Vdsatii VgsStep Vdsatii 0 1 Tii 1 ii
Tnom Leff
(3.7)
E satii Leff 1 S V
VgsStep Sii 2 ii 0 gst
1 E L 1 S V 1 S V
satii eff ii 1 gsteff iid ds
Here the Fbjtii I c term represents the contribution from the parasitic bipolar current. Notice that
the classical impact ionization current model [12] adopted in BSIM3v3 is actually a special case
of Eqn. (3.6) when 0 , 1 , 2 1,0,0 . However, the dependence of log( I ii I ds ) on the drain
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Chapter 3: Body Currents Model
overdrive voltage Vdiff is quite linear [22] for state-of-the-art SOI technologies due to thermally
assisted impact ionization [23]. In this case, 0 , 1 , 2 0,0,1 .
The extracted saturation drain voltage Vdsatii depends on the gate overdrive voltage Vgst and
Leff . One can first extract the parameters Vdsatii 0 , Lii by the Vdsatii - Leff characteristics at Vgst 0 .
All the other parameters ( E satii , Sii1 , Sii 2 , Sii 0 , Siid ) can then be determined by the plot of Vdsatii
versus Vgs for different Leff . Notice that a linear temperature dependence of Vdsatii 0 with the
parameter Tii is also included.
IiiMod = 1
When IiiMod = 0, the two component currents I ds,MOSFET and Ic have a same bias dependence
for impact ionization rate. This approximation generally won’t cause accuracy problem because
the MOSFET drain current is the major contribution on impact ionization current in the
interested operation regions. While SOI MOSFET device operates in subthreshold to
accumulation regions, parasitic BJT effect starts to dominant nodal drain current at high drain
bias. In order to model Iii better, IiiMod =1 is introduce to treat I ds,MOSFET and Ic separately. It
means that these two components have the different impact ionization rate [30].
Here I ds,MOSFET still uses the old impact ionization model. The BJT contribution is expressed
in Equ (3.8). The temperature dependence is also improved.
CBJTII EBJTII Leff (3.8)
I ii _ BJT I C (Vbci Vbd ) exp ABJTII (Vbci Vbd )( MBJTII 1)
Leff
T
Vbci VBCI 1 TVBCI 1
TNOM
where ABJTII, CBJTII, EBJTII, MBJTII, VBCI and TVBCI are model parameters and explained
in Appendix B.
3.3. Gate Induced Source/Drain Leakage Current
gidlMod = 0
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Chapter 3: Body Currents Model
GISL/GIDL can be important in SOI device because it can affect the body potential in the
low Vgs and high Vds regime.
The formula for GIDL current is:
Vds Vgse EGIDL V fbsd 3 Toxe BGIDL Vdb3
I GIDL AGIDL Wdiod Nf exp
3 Toxe Vds Vgse EGIDL CGIDL Vdb3
(3.9)
Where, AGIDL, BGIDL, CGIDL, and EGIDL are model parameters and explained in Appendix
A. CGIDL accounts for the body-bias dependence of IGIDL and IGISL. Here Vgse accounts for
poly depletion effect.
Following BSIM4, BSIMSOI4.1 also introduces GISL current. In order to model asymmetric
source/drain, GISL model has another set of parameters: AGISL, BGISL, CGISL, and EGISL.
Vds Vgse EGISL V fbsd 3 Toxe BGISL Vsb3
I GISL AGISL Wdios Nf exp
3 Toxe Vds Vgse EGISL CGISL Vsb3
(3.10)
gidlMod = 1
In this new model, the basic idea is to decouple Vds and Vgs dependence by introducing an
extra parameter rgidl. The body bias dependence part is also revised. Here, KGIDL and FGILD
are Vbs dependent parameters.
Vds RGIDL Vgse EGIDL V fbsd (3.11)
I GIDL AGIDL Wdiod Nf
3 Toxe
3 Toxe BGIDL KGIDL
exp exp
Vds Vgse EGIDL
Vds FGIDL
Vds RGISL Vgse EGISL V fbsd
I GISL AGISL Wdios Nf
3 Toxe
3 Toxe BGISL KGISL
exp exp
Vds Vgse EGISL
Vbs FGISL
Here Vfbsd = 0 when mtrlMod = 0.
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Chapter 3: Body Currents Model
3.4. Oxide Tunneling Current
For thin oxide (below 20Å), oxide tunneling is important in the determination of floating-
body potential [20]. In BSIMPD the following equations are used to calculate the tunneling
current density Jgb :
In inversion,
J gb A
V gbVaux Toxref
N tox
exp
B α gb1 β gb1 Vox Tox
Tox2 Toxqm
1 V ox V gb1
Vox φ g
Vaux VEVB ln1 exp
VEVB
q3
A
8h b (3.12)
8 2mox 32
B
b
3hq
b 4.2eV
mox 0.3m0
In accumulation,
J gb A
V gbVaux Toxref
N tox
exp
B α gb2 β gb2 Vox Tox
Tox Toxqm
2
1 Vox Vgb2
V gb V fb
Vaux VECBVt ln 1 exp
VECB
q3
A
8h b (3.13)
8 2mox b3 2
B
3hq
b 3.1eV
mox 0.4m0
Igb is evaluated in IgbMod=1. IgbMod=0 turns it off. Please see Appendix B for model
parameter descriptions.
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Chapter 3: Body Currents Model
In BSIMSOI4.1, the instance parameter Agbcp2 represents the parasitic gate-to-body overlap
area due to the body contact. This parameter applies for the opposite-type gate, which is shown
Fig. 4.4. In order to account the tunneling current in this region, Ig_agbcp2 is introduced as
following:
I g _ agbcp 2 A Aagbcp 2 min(Vgp V fb 2 , 0) Vgp _ eff ToxRatio
exp B Toxqm AIGBCP2 BIGBCP2 Vgp _ eff 1 CIGBCP2 V gp _ eff (3.14)
V V fb 2 2 Vgp V fb 2
2
Vgp _ eff 0.5 gp
0.01
3.5. Gate-to-Channel Current (Igc0) and Gate-to-S/D (Igs and Igd)
Igc0, determined by ECB for NMOS and HVB (Hole tunneling from Valence Band)
for PMOS at Vds=0, is formulated as
Igc0 Weff Leff A ToxRatio Vgse Vaux
exp B TOXE AIGC BIGC Voxdepinv 1 CIGC Voxdepinv (3.15)
where A = 4.97232 A/V2 for NMOS and 3.42537 A/V2 for PMOS, B = 7.45669e11
(g/F-s2)0.5 for NMOS and 1.16645e12 (g/F-s2)0.5 for PMOS, and
Vgse VTH 0 (3.16)
Vaux NIGC vt log 1 exp
NIGC vt
Igs and Igd -- Igs represents the gate tunneling current between the gate and the
source diffusion region, while Igd represents the gate tunneling current between the
gate and the drain diffusion region. Igs and Igd are determined by ECB for NMOS
and HVB for PMOS, respectively.
I gs Weff DLCIG A ToxRatioEdge Vgs Vgs ' (3.17)
exp B TOXE POXEDGE AIGS BIGS Vgs ' 1 CIGS Vgs '
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Chapter 3: Body Currents Model
and
I gd Weff DLCIGD A ToxRatioEdge Vgd Vgd ' (3.18)
exp B TOXE POXEDGE AIGD BIGD Vgd ' 1 CIGD Vgd '
where A = 4.97232 A/V2 for NMOS and 3.42537 A/V2 for PMOS, B = 7.45669e11
(g/F-s2)0.5 for NMOS and 1.16645e12 (g/F-s2)0.5 for PMOS, and
TOXREF
NTOX
1 (3.19)
ToxRatioEdge
TOXE POXEDGE TOXE POXEDGE
2
V V fbsd 1.0e 4 (3.20)
2
Vgs ' gs
V V fbsd 1.0e 4 (3.21)
2
Vgd ' gd
Vfbsd is the flat-band voltage between gate and S/D diffusions calculated as
If NGATE > 0.0
kBT NGATE (3.22)
V fbsd log VFBSDOFF
q NSD
Else Vfbsd = 0.0.
3.5.1 Partition of Igc
To consider the drain bias effect, Igc is split into two components, Igcs and Igcd, that
is Igc = Igcs + Igcd, and
PIGCD Vdseff exp PIGCD Vdseff 1 1.0e 4 (3.23)
Igcs Igc0
PIGCD 2 Vdseff 2 2.0e 4
and
1 PIGCD Vdseff 1 exp PIGCD Vdseff 1.0e 4 (3.24)
Igcd Igc0
PIGCD 2 Vdseff 2 2.0e 4
where Igc0 is Igc at Vds=0.
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Chapter 3: Body Currents Model
If the model parameter PIGCD is not specified, it is given by
B TOXE Vdseff (3.25)
PIGCD 1
Vgsteff 2 Vgsteff
2
Igc is evaluated in IgcMod=1. IgcMod=0 turns it off.
3.6. Body Contact Current
In BSIMPD, a body resistor is connected between the body (B node) and the body contact (P
node) if the transistor has a body-tie. The body resistance is modeled by
'
W eff '
W eff
Rbp
Rbody || R , R Rbsh N rb (3.26)
Leff halo 2 bodyext
Here Rbp and Rbodyext represent the intrinsic and extrinsic body resistance respectively. Rbody is
the intrinsic body sheet resistance, Rhalo accounts for the effect of halo implant, Nrb is the number
of square from the body contact to the device edge and Rbsh is the sheet resistance of the body
contact diffusion.
The body contact current I bp is defined as the current flowing through the body resistor:
Vbp
I bp (3.27)
Rbp Rbodyext
where Vbp is the voltage across the B node and P node. Notice that I bp 0 if the transistor has a
floating body.
3.6. Body Contact Parasitics
The effective channel width may change due to the body contact. Hence the following
equations are used:
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Chapter 3: Body Currents Model
Weff Wdrawn N bc dWbc ( 2 N bc )dW
Weff Wdrawn N bc dWbc ( 2 N bc )dW '
'
(3.28)
Wdiod Weff Pdbcp
'
Wdios Weff Psbcp
'
Here dWbc is the width offset for the body contact isolation edge. N bc is the number of body
contact isolation edge. For example: N bc 0 for floating body devices, N bc 1 for T-gate
structures and N bc 2 for H-gate structures. Pdbcp / Psbcp represents the parasitic perimeter length
for body contact at drain/source side. The body contact parasitics [17] may affect the I-V
significantly for narrow width devices [20].
After introducing all the mechanisms that contribute the body current, we can express the
nodal equation (KCL) for the body node as
Ibs Ibd Ibp Iii I dgidl I sgisl I gb 0 (3.29)
Eqn. (3.18) is important since it determines the body potential through the balance of various
body current components. The I-V characteristics can then be correctly predicted after this
critical body potential can be well anchored.
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Chapter 4: MOS C-V Model
Chapter 4: MOS C-V Model
BSIMPD approaches capacitance modeling by adding SOI-specific capacitive effect to the
C-V model of BSIM3v3. Similar to the I-V case, the body charges belonged to the floating body
node will be our emphasis. The model incorporates features listed below with the SOI-specific
features bold-faced and italicized.
Separate effective channel length and width for IV and CV models.
The CV model is not piece-wise (i.e. divided into inversion, depletion, and
accumulation). Instead, a single equation is used for each nodal charge covering all
regions of operation. This ensures continuity of all derivatives and enhances convergence
properties. Just like in BSIM3v3, the inversion and body capacitances are continuous at
the threshold voltage.
In BSIMSOI4.1, a new model selector vgstcvMod is introduced for the Vgsteff
calculation. When vgstcvMod = 0, it is the old code. Nothing has been changed; even
Qinv/Cgs/Cgd etc., are untouched for the backward compatibility. Thus users are
suggested to choose vgstcvMod =1 or 2. Here, vgstcvMod = 1 fixes the bug in
vgstcvMod = 0 (For more details, please check the BSIMSOI4.1 release note).
vgstcvMod = 2 adopts a new Vgsteff, which is similar to that in IV model. Body effect
and DIBL are automatically incorporated in the capacitance model.
Intrinsic capacitance model has two options. The capMod = 2 option yields capacitance
model based on BSIM3v3 short channel capacitance model. The capMod = 3 option is
the new charge-thickness model from BSIM3v3.2 [4].
Front gate overlap capacitance is comprised of two parts: 1) a bias independent part
which models the effective overlap capacitance between the gate and the heavily doped
source/drain, and 2) a gate bias dependent part between the gate and the LDD region.
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Chapter 4: MOS C-V Model
Bias independent fringing capacitances are added between the gate and source as well as
the gate and drain. A sidewall source/drain to substrate (under the buried oxide) fringing
capacitance is added.
A source/drain-buried oxide-Si substrate parasitic MOS capacitor is added.
Body-to-back-gate coupling is added.
Parasitic gate capacitance model is improved by the new body contact model.
A good intrinsic charge model is important in bulk MOSFETs because intrinsic capacitance
comprises a sizable portion of the overall capacitance, and because a well behaved charge model
is required for robust large circuit simulation convergence. In analog applications there are
devices biased near the threshold voltage. Thus, a good charge model must be well-behaved in
transition regions as well. To ensure proper behavior, both the I-V and C-V model equations
should be developed from an identical set of charge equations so that Cij/Id is well behaved.
A good physical charge model of SOI MOSFETs is even more important than in bulk. This is
because transient behavior of the floating body depends on capacitive currents [18]. Also, due to
the floating body node, convergence issues in PD SOI are more volatile than in bulk, so that
charge smoothness and robustness are important. An example is that a large negative guess of
body potential by SPICE during iterations can force the transistor into depletion, and a smooth
transition between depletion and inversion is required. Therefore the gate/source/drain/backgate
to body capacitive coupling is important in PD SOI.
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Chapter 4: MOS C-V Model
4.1. Charge Conservation
Fig. 4.1 Intrinsic charge components in BSIMPD CV model
To ensure charge conservation, terminal charges instead of terminal voltages are used as state
variables. The terminal charges Qg, Qd, Qs, Qb, and Qe are the charges associated with the gate,
drain, source, body, and substrate respectively. These charges can be expressed in terms of
inversion charge (Qinv), front gate body charge (QBf), source junction charge (Qjs) and drain
junction charge (Qjd). The intrinsic charges are distributed between the nodes as shown in Fig.
4.1. The charge conservation equations are:
QBf Qac0 Qsub0 Qsubs
Qinv Qinv , s Qinv , d
Qg Qinv QBf
Qb QBf Qe Q js Q jd (4.1)
Qs Qinv ,s Q js
Qd Qinv ,d Q jd
Qg Qe Qb Qs Qd 0
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Chapter 4: MOS C-V Model
The front gate body charge (QBf) is composed of the accumulation charge (Qac0) and the bulk
charge ( Q sub0 and Q subs ), which may be divided further into two components: the bulk charge at
Vds=0 (Qsub0), and the bulk charge induced by the drain bias (Qsubs) (similar to Qsub in
BSIM3v3).
All capacitances are derived from the charges to ensure charge conservation. Since there are
5 charge nodes, there are 25 (as compared to 16 in BSIM3v3) components. For each component:
C C
dQi
Cij , where i and j denote transistor nodes. In addition, ij ij 0.
dV j i j
4.2. Intrinsic Charges
BSIMPD uses similar expressions to BSIM3v3 for Q inv and Q Bf . First, the bulk charge
constant AbulkCV is defined as
CLC CLE
AbulkCV Abulk 0 1 (4.2)
Lactive
where Abulk 0 Abulk Vgsteff 0 (4.3)
This is done in order to empirically fit VdsatCV to channel length. Experimentally,
V gsteffCV
VdsatIV VdsatCV VdsatIV L
(4.4)
Abulk
vgstcvMod = 0 or 1
The effective CV Vgst is defined as
Vgs Vth delvt
VgsteffCV nvt ln 1 exp exp (4.5)
nvt nvt
vgstcvMod = 0 and 1 use the same VgsteffCV definition. As mentioned above, the only difference
between vgstcvMod = 0 and 1 is that Mod =1 fixes the bug in the code. Users are suggested to
choose vgstcvMod =1 or 2.
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Chapter 4: MOS C-V Model
vgstcvMod = 2
This new VgsteffCV follows that in IV model. There are two new model parameters MINVCV
and VOFFCV, which are binnable.
m*CV (Vgs _ eff Vth delvt )
nvt ln 1 exp( )
nvt (4.6)
VgsteffCV
2 s (1 m )(Vgs _ eff Vth delvt ) VoffCV
*CV
m*CV nCox exp( )
q si N dep nvt
arctan( MINVCV )
m*CV 0.5
Then we can calculate the CV saturation drain voltage
VdsatCV VgsteffCV / AbulkCV . (4.7)
Define effective CV Vds as
1
VdsCV VdsatCV (VdsatCV Vds (VdsatCV Vds ) 2 4VdsatCV ) (4.8)
2
Then the inversion charge can be expressed as
AbulkCV
2
AbulkCV VdsCV
2
Qinv Wactive LactiveCox VgsteffCV VdsCV (4.9)
2 A
2
12VgsteffCV bulkCV VdsCV
2
where Wactive and Lactive are the effective channel width and length in CV, respectively. The
channel partition can be set by the Xpart parameter. The exact evaluation of source and drain
charges for each partition option is presented in Appendix C.
A parameter VFBeff is used to smooth the transition between accumulation and depletion
regions. The expression for VFBeff is:
V fb Vgb
2
VFBeff V fb 0.5 V fb Vgb 2 (4.10)
where Vgb Vgs Vbseff , V fb Vth s K1eff s Vbseff
.
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Chapter 4: MOS C-V Model
The physical meaning of the function is the following: it is equal to Vgb for Vgb<VFB, and
equal to VFB for Vgb>VFB. Using VFBeff, the accumulation charge can be calculated as
Qac0 FbodyWactive LactiveBCox (VFBeff V fb ) (4.11)
where LactiveB Lactive DLCB . Notice that the parameters Fbody and DLCB are provided to give
a better fit for the SOI-specific history dependence of the body charge [14].
The gate-induced depletion charge and drain-induced depletion charge can be expressed as
K1eff 4(Vgs VFBeff VgsteffCV Vbseff )
2
Qsub0 FbodyWactive LactiveBCox 1 1 (4.12)
2 K
2
1eff
V 2
AbulkCV VdsCV
Q subs FbodyWactive LactiveB K1eff Cox 1 AbulkCV dsCV
12V gsteffCV AbulkCV VdsCV 2
(4.13)
2
respectively.
Finally, the back gate body charge can be modeled by
Qe FbodyWactive LactiveBGCbox Ves V fbb Vbseff (4.14)
where LactiveBG LactiveB 2Lbg . The parameter Lbg is provided to count the difference of LactiveB
and LactiveBG due to the source/drain extension in the front channel.
For capMod=3, the flat band voltage is calculated from the bias-independent threshold
voltage, which is different from capMod=2. For the finite thickness formulation, refer to Section
4.6 and Chapter 7 of BSIM4.6.2 Users’ Manual.
4.3. Source/Drain Junction Charges
Beside the junction depletion capacitance considered in BSIM3v3, the diffusion capacitance,
which is important in the forward body-bias regime [20], is also included in BSIMPD. The
source/drain junction charges Q jswg / Q jdwg can therefore be expressed as
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Chapter 4: MOS C-V Model
Q jswg Qbsdep Qbsdif
(4.15)
Q jdwg Qbddep Qbddif
The depletion charges Qbsdep / Qbddep have similar expressions as in BSIM3v3 [Appendix C].
While the diffusion charges Qbsdif / Qbddif can be modeled by
Weff ' 1
N dif
V
1 1
Qbsdif Tsi J sbjt 1 Ldif 0 Lbj 0 exp bs 1
N seg
Leff Ln ndiosVt Ehlis 1
(4.16)
Weff ' 1
N dif
V
1 1
Qbddif Tsi J dbjt 1 Ldif 0 Lbj 0 exp bd 1
Leff Ln
N seg
ndiodVt Ehlid 1
The parameter represents the transit time of the injected minority carriers in the body. The
parameters Ldif 0 and N dif are provided to better fit the data.
4.4. Extrinsic Capacitances
Expressions for extrinsic (parasitic) capacitances that are common in bulk and SOI
MOSFETs are taken directly from BSIM3v3. They are source/drain-to-gate overlap capacitance
and source/drain-to-gate fringing capacitance. Additional SOI-specific parasitics added are
substrate-to-source sidewall capacitance Cessw, and substrate-to-drain sidewall capacitance Cedsw,
substrate-to-source bottom capacitance (Cesb) and substrate-to-drain bottom capacitance (Cedb)
[Fig. 4.2].
Cessw
Cesb
Fig. 4.2 SOI MOSFET extrinsic charge components. Cessw is the substrate-to-
source sidewall capacitance. Cesb is the substrate-to-source bottom capacitance.
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Chapter 4: MOS C-V Model
In SOI, there is a parasitic source/drain-buried oxide-Si substrate parasitic MOS structure
with a bias dependent capacitance. If Vs,d=0, this MOS structure might be in accumulation.
However, if Vs,d=Vdd, the MOS structure is in depletion with a much smaller capacitance,
because the Si substrate is lightly doped. The bias dependence of this capacitance is similar to
high frequency MOS depletion capacitance as shown in Fig. 4.3. It might be substantial in
devices with large source/drain diffusion areas. BSIMPD models it by piece-wise expressions,
with accurately chosen parameters to achieve smoothness of capacitance and continuity to the
second derivative of charge. The substrate-to-source bottom capacitance (per unit source/drain
area) Cesb is:
Cbox if Vse Vsdfb
2
Vse Vsdfb
box A box
C
1
sd
C Cmin
Vsdth Vsdfb
elseif
Vse Vsdfb Asd Vsdth Vsdfb (4.17)
Cesb 2
Vse Vsdth
Cmin
1
C Cmin V V
1 Asd box
elseif Vse Vsdth
sdth sdfb
Cmin else
Physical parameters Vsdfb (flat-band voltage of the MOS structure) and Vsdth (threshold voltage of
the MOS structure) can be easily extracted from measurement. Cmin should also be extracted
from measurement, and it can account for deep depletion as well. Asd is a smoothing parameter.
The expression for Cedb is similar to Cesb. Fig. 4.3 shows the comparison of the model and
measured Cesb.
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Chapter 4: MOS C-V Model
measured data
model fit
160
Capacitance (fF)
140
120
100
80
-4 -2 0 2 4
Vs/d,e
Fig. 4.3 Bottom source/drain to substrate capacitance for a PD SOI MOSFET.
Finally, the sidewall source/drain to substrate capacitance (per unit source/drain perimeter
length) can be expressed by
T
Cs / d ,esw Csdesw log CfrCoeff 1 si (4.18)
Tbox
which depends on the silicon film thickness Tsi and the buried oxide thickness Tbox . The
parameter C sdesw represents the fringing capacitance per unit length. CfrCoeff has a default value
= 1, and is limited to a value of 2 (introduced in v4.4).
4.5. Body Contact Parasitics
The parasitic capacitive coupling due to the body contact is considered in BSIMPD. The
instance parameter Agbcp represents the parasitic gate-to-body overlap area due to the body
contact, and Aebcp represents the parasitic substrate-to-body overlap area. The effect may be
significant for small area devices [CV part in Appendix C].
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Chapter 4: MOS C-V Model
Note: There are four instance parameters used to calculate parasitic capacitances associated
with body contacts. They are: psbcp, pdbcp, agbcp and aebcp. It is worth pointing out that psbcp
and pdbcp represent additional gate perimeter to the source and drain and must be specified on a
per finger basis, while agbcp and aebcp represent addition gate area and addition area of body
over the box and must be specified on a total transistor basis.
BSIMSOI4.1 also considers the P+ implantation for body contact (as shown in Figure 4.4),
which will induce parasitic P+-poly gate/NMOS.
Fig. 4.4 Parasitic capacitance in opposite-type gate.
In BSIMSOI4.0, the instance parameter Agbcp represents the parasitic gate-to-body overlap
area due to the body contact. This parameter only applies for the same-type gate. For the
opposite-type gate, the charge will be overestimated by Agbcp. Charge model has to be modified
to include the effect of P+/P region in this case.
The higher VFB in the P+/P region lowers the gate charge and the net gate charge is the sum of
N+/P and P+/P regions as shown below. One new instance parameter Agbcp2 is introduced to
account for the opposite-type parasitic capacitance. The final charge could be expressed as
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Chapter 4: MOS C-V Model
following:
Total Charge = WL N / NMOS Agbcp N / NMOS Agbcp 2 P / NMOS (4.19)
Fig. 4.5 The total charge in the opposite-type gate.
Note: In this case, there is a new instant parameters agbcp2, which is similar to agbcp and
specified on a total transistor basis.
4.6 Finite Thickness Formulation
The finite thickness formulation is similar to that in BSIM4.
mtrlMod=0
The charge thickness introduces a capacitance in series with Cox, resulting in an effective
Coxeff. Based on numerical self-consistent solution of Shrődinger, Poisson and Fermi-Dirac
equations, universal and analytical XDC models have been developed. Coxeff can be expressed as:
Coxp Ccen (4.20)
Coxeff
Coxp Ccen
where
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Chapter 4: MOS C-V Model
Ccen si / X DC (4.21)
(i) XDC for accumulation and depletion
The DC charge thickness in the accumulation and depletion regions can be expressed by
1 NDEP
0.25
Vgse Vbseff VFBeff (4.22)
X DC Ldebye exp ACDE 16
3 2 10 TOXP
where Ldebye is Debye length, and XDC is in the unit of cm and (Vgse - Vbseff - VFBeff) / TOXP is in
units of MV/cm. For numerical stability, (4.22) is replaced by (4.23)
X DC X max
1
2
X 0 X 02 4 x X max (4.23)
where
X 0 X max X DC x (4.24)
and Xmax = Ldebye / 3; = 10-3TOXE.
(ii) XDC of inversion charge
The inversion charge layer thickness can be formulated as
ADOS 1.9 109 m (4.25)
X DC 0.7 BDOS
V 4 VTH 0 VFB s
1 gsteff
2TOXP
Here, the density of states parameters ADOS and BDOS are introduced to control the charge
centroid. Their default values are one.
Through the VFB term, equation (4.25) is found to be applicable to N+ or P+ poly-Si gates and
even other future gate materials.
(iii) Body charge thickness in inversion
In inversion region, the body charge thickness effect is modeled by including the deviation of
the surface potential ФS (bias-dependence) from 2 ФB
VgsteffCV (VgsteffCV 2K1ox 2 B (4.26)
s 2 B t ln 1
MOIN K1ox 2 t
The channel charge density is therefore derived as
qinv Coxeff Vgsteff ,CV (4.27)
eff
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Chapter 4: MOS C-V Model
mtrlMod = 1
In this case, TOXP should be iteratively calculated by EOT first:
3.9 (4.28)
TOXP EOT X DC V VDDEOT ,V V 0
EPSRSUB gs ds bs
With the calculated TOXP, XDC could be obtained at different gate voltage, just like
mtrlMod=0.
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Chapter 5: Temperature Dependence and Self-Heating
Chapter 5: Temperature Dependence and Self-Heating
Self-heating in SOI is more important than in bulk since the thermal conductivity of silicon
dioxide is about two orders of magnitude lower than that of silicon [15]. It may degrade the
carrier mobility, increase the junction leakage [20], enhance the impact ionization rate [24], and
therefore affect the output characteristics [16] of floating-body SOI devices.
5.1. Temperature Dependence
The temperature dependence of threshold voltage, mobility, saturation velocity and series
resistance in BSIMSOI is identical to BSIM3v3. However a different temperature dependence of
diode characteristics is adopted in BSIMSOI4.0:
Eg (300 K ) T
jsbjt isbjt exp X bjt 1
ndiodesVt Tnom
Eg (300 K ) T
jdbjt idbjt exp X bjt 1
ndiodedVt Tnom
Eg (300 K ) T
jsdif isdif exp X dif 1
ndiodesVt Tnom
Eg (300 K ) T
jddif iddif exp X dif 1
ndiodedVt Tnom
Eg (300 K ) T
jsrec isrec exp X rec 1
nrecf 0 sVt Tnom
Eg (300 K ) T
jdrec idrec exp X rec 1
nrecf 0 dVt Tnom
T
jstun istun exp X tun 1
Tnom
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Chapter 5: Temperature Dependence and Self-Heating
T
jdtun idtun exp X tun 1 (5.1)
Tnom
T
nrecrs nrecr 0 s 1 ntrecr 1
Tnom
T
nrecrd nrecr 0 d 1 ntrecr 1
Tnom
T
nrecfs nrecf 0 s 1 ntrecf 1
Tnom
T
nrecfd nrecf 0 d 1 ntrecf 1
Tnom
The parameters isbjt , idbjt , isdif , iddif , isrec , idrec , istun , idtun are diode saturation currents at the nominal
temperature Tnom , and the parameters X bjt , X dif , X rec , X tun are provided to model the temperature
dependence. Notice that the non-ideality factors nrecfs , nrecfd , nrecrs , nrecrd are also temperature
dependent.
5.2. Self-Heating Implementation
BSIMPD/BSIMSOI models the self-heating by an auxiliary Rth C th circuit as shown in Fig.
5.1 [18]. The temperature node (T node) will be created in SPICE simulation if the self-heating
selector shMod is ON and the thermal resistance is non-zero. The T node is treated as a voltage
node and is connected to ground through a thermal resistance Rth and a thermal capacitance Cth:
Rth0
Rth , C th C th0 ( Weff
'
Wth0 ) (5.2)
'
Weff Wth0
where R th 0 and C th 0 are normalized thermal resistance and capacitance, respectively. Wth0 is the
minimum width for thermal resistance calculation [19]. Notice that the current source is driving a
current equal to the power dissipated in the device.
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Chapter 5: Temperature Dependence and Self-Heating
P I ds Vds (5.3)
To save computation time, the turn-on surface potential s (Phi) is taken to be a constant
within each timepoint because a lot of parameters (e.g. Xdep) are function of s. Each timepoint
will use a s calculated with the temperature iterated in the previous timepoint. However this
approximation may induce error in DC, transient and AC simulation. Therefore, it is a tradeoff
between accuracy and speed. The error in DC or transient is minimal if the sweeping step or time
step is sufficiently small.
IdVd Rth Cth
Fig. 5.1 Equivalent circuit for self-heating simulation.
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Chapter 6: BSIMSOI - A Unified Model for PD and FD SOI MOSFETs
Chapter 6: BSIMSOI –A Unified Model for PD and
FD SOI MOSFETs
Using BSIMPD as a foundation, we have developed a unified model for both PD and FD SOI
circuit designs based on the concept of body-source built-in potential lowering [20, 25].
6.1. BSIMSOI Framework and Built-In Potential Lowering Model
As described in [20], we construct BSIMSOI based on the concept of body-source built-in
potential lowering, Vbi. There are four modes (soiMod = 0, 1, 2 and 3) in BSIMSOI: BSIMPD
(soiMod = 0) can be used to model the PD SOI device, where the body potential is independent
of Vbi (VBS > Vbi). Therefore the calculation of Vbi is skipped in this mode. On the other
hand, the ideal FD model (soiMod = 2) is for the FD device with body potential equal to Vbi.
Hence the calculation of body current/charge, which is essential to the PD model, is skipped. For
the unified SOI model (soiMod = 1), however, both Vbi and body current/charge are calculated
to capture the floating-body behavior exhibited in FD devices. As shown in Figure 6.1, this
unified model covers both BSIMPD and the ideal FD model. When soiMod = 3, BSIMSOI will
select the operation mode based on Vbs0t (For details, refer Section 6.3)
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Chapter 6: BSIMSOI - A Unified Model for PD and FD SOI MOSFETs
0.7 soiMod=0 (BSIMPD)
soiMod=1 (Unified Model)
soiMod=2 (Ideal FD)
0.6
0.5 Vbi
VBS (V) 0.4
0.3
0.2
0.1 VGS=0.5V
L=0.5m
0.0 TSi=40nm
0.0 0.5 1.0 1.5 2.0
VDS (V)
Fig. 6.1 The body potential in the unified model approaches the VBS solved in BSIMPD for PD
devices, while returns to Vbi for ideal FD devices [20].
This unified model shares the same floating-body module as BSIMPD, with a generalized diode
current model considering the body-source built-in potential lowering effect (IBS exp(-
qVbi/kT)). Therefore, an accurate and efficient Vbi model is crucial. The following
formulation for Vbi is mainly based on the Poisson equation and the physical characterization
for Vbi, as presented in [25].
In order to keep backward compatibility, a new model selector fdMod is introduced. Here,
fdMod = 0 is the old Vbi formulation, while fdMod = 1 is the new one that is easier to fit.
fdMod = 0
For a given surface band bending (source reference), Vbi can be formulated by applying
the Poisson equation in the vertical direction and continuity of normal displacement at the back
interface:
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Chapter 6: BSIMSOI - A Unified Model for PD and FD SOI MOSFETs
Vbi
C Si
C Si C BOX
qN ch
TSi VDIBL e Leff
2 C BOX
VbGS VFBb
2 Si C Si C BOX
(6.1).
Si OX OX
C Si , C BOX , COX
TSi TBOX TOX
The first term of Equation (6.1) represents the frontgate coupling. TSi is the SOI thickness. Nch
accounts for the effective channel doping, which may vary with channel length due to the non-
ch 2 qN
uniform lateral doping effect. Here, 2 TSi is band bending in the body due to depletion
si
charges, which is limited to (Eg-0.1) eV in v4.4. In SOIMOD=2, for any combinations of TSi and
Nch, if this term exceeds this limit, Nch is lowered accordingly. The second term of Equation (6.1)
represents the backgate coupling (VbGS). VFBb is the backgate flatband voltage. Equation (6.1)
shows that the impact of frontgate on Vbi reaches maximum when the buried oxide thickness,
TBOX, approaches infinity.
In Equation (6.1), VDIBL represents the short channel effect on Vbi,
Leff L
VDIBL Dvbd 0 exp Dvbd1 2 exp Dvbd1 eff Vbi 2 B (6.2),
2l l
as addressed in [25]. Here l is the characteristic length for the short-channel-effect calculation.
Dvbd0 and Dvbd1 are model parameters. Similarly, the following equation
Leff
e Leff K1b K2b exp Dk 2b
L
2 exp Dk 2b eff (6.3)
2l l
is used to account for the short channel effect on the backgate coupling, as described in [25].
DK1b, DK2b, K1b (default 1) and K2b (default 0) are model parameters.
fdMod = 1
However, the two length-dependent functions (i.e., Eqr (6.2) and (6.3)) in Vbi model make
the parameter extraction difficult. Thus, BSIMSOI4.1 introduces a new Vbi equation as
following:
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Chapter 6: BSIMSOI - A Unified Model for PD and FD SOI MOSFETs
Csi qN ch (1 Lpe 0 / Leff ) 2 (6.4)
Vbi Tsi Vnonideal
Csi CBOX CDSBS 2 Si
CBOX CDSBS
VbGS VFBb VSCE
Csi CBOX CDSBS Csi CBOX CDSBS
CDSBS is the new model parameter representing the capacitance of drain to the body-source
potential. ∆VSCE is the length dependence of the capacitance coupling from drain. VSCE is the
new model parameter for SCE of ∆Vbi at zero Vds.
Leff Leff
VSCE DVBD0 exp DVBD1 2 exp DVBD1 Vds VSCE
2l l (6.4)
If body contact devices are available, a direct probe of ∆Vbi can be achieved by finding the
onset of the external body bias after the channel current (threshold voltage) of FD device is
modulated.
If body contact devices are not available, the length dependence related parameters of ∆Vbi
will be set to the value of SCE parameters in VT equation.
Dvbd 0 DVT 0 (6.5)
Dvbd1 DVT 1
The surface band bending, , is determined by the frontgate VGS and may be approximated by
ON for VGS VT
(6.6).
VT VGS for VGS VT
COX
ON
COX C Si
1
C BOX
1 1
To improve the simulation convergence, the following single continuous function from
subthreshold to strong inversion is used:
COX V Vgs _ eff VOFF , FD
ON NOFF , FD vt ln 1 exp T , FD
(6.7).
COX CSi CBOX
1 1 1
NOFF , FD vt
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Chapter 6: BSIMSOI - A Unified Model for PD and FD SOI MOSFETs
Here Vgs_eff is the effective gate bias considering the poly-depletion effect. VT,FD is the threshold
voltage at VBS = Vbi(=2B). NOFF,FD (default 1) and VOFF,FD (default 0) are model parameters
introduced to improve the transition between subthreshold and strong inversion. Vt is the thermal
voltage. Notice that the frontgate coupling ratio in the subthreshold regime approaches 1 as TBOX
approaches infinity.
To accurately model Vbi and thus the device output characteristics, the surface band bending
at strong inversion, ON, is not pinned at 2B. Instead, the following equation
Vgsteff .FD Vgsteff , FD 2 K1 2 B
ON 2 B vt ln 1
(6.8)
moin K1 vt 2
is used to account for the surface potential increment with gate bias in the strong inversion
regime [4]. Here moin is a model parameter. K1 is the body effect coefficient. Notice that a
single continuous function,
Vgs _ eff VT ,FD VOFF ,FD
Vgsteff ,FD N OFF ,FDVt ln 1 exp (6.9)
N OFF ,FDVt
has been used to represent the gate overdrive in Equation (6.7).
6.2. Verification
The BSIMPD parameter extraction methodology presented in [20] may still be used under the
unified BSIMSOI framework, provided that the link between PD and FD, Vbi, can be accurately
extracted. As described in [25], a direct probe of Vbi can be achieved by finding the onset of the
external body bias (through a body contact) after which the threshold voltage and hence the
channel current of the FD SOI device is modulated. When the body contact is not available,
nevertheless, model parameters related to Vbi should be extracted based on the subthreshold
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Chapter 6: BSIMSOI - A Unified Model for PD and FD SOI MOSFETs
characteristics of the floating-body device. As shown in Figure 6.2, the reduction of Vbi with
backgate bias is responsible for the transition from the ideal subthreshold swing (~ 60 mV/dec. at
room temperature) to the non-ideal one.
Figure 6.2 clearly shows that the PD/FD transition can be captured by the Vbi approach. In
other words, Vbi is indeed an index of the degree of full depletion, as pointed out in [20, 25]. As
shown in Figure 6.3, larger floating-body effect can be observed for negative backgate bias due
to smaller Vbi. In case the Vbi value is raised by charge sharing as described in [25], it can be
predicted that the short-channel device should exhibit less floating-body effect than the long-
channel one due to larger Vbi, as verified in Figure 6.4.
0.0020
LG=0.5m -4 LG=0.5m
line: model VGS=1.5V
10
VDS=0.05V
VbGS=0V -5
10 o
VbGS=-1.5V
T=27 C
0.0015 -6
10
-7
~67mV/dec.
10
1.2V
ID (A)
ID (A)
-8
0.0010 10 ~102mV/dec.
-9
10 VbGS=4V
-10 2V
0.9V 10
0.0005 0V
-11
10 -2V
0.6V 10
-12 -4V
-13
line: model
0.0000 10
0.0 0.3 0.6 0.9 1.2 1.5 -0.5 0.0 0.5 1.0 1.5
VDS (V) VGS (V)
(Left) Fig. 6.2 The PD/FD transition can be captured by modeling Vbi [20].
(Right) Fig. 6.3 Larger floating-body effect can be seen for the negative backgate bias (source
reference) due to smaller Vbi [20].
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Chapter 6: BSIMSOI - A Unified Model for PD and FD SOI MOSFETs
Fig. 6.4 Less floating-body effect can be seen for the short-channel device due to larger Vbi
[20].
6.3. Model Selector SOIMOD
The model selector, SoiMod, is an instance parameter and a model parameter. SoiMod will
determine the operation of BSIMSOI.
If SoiMod=0 (default), the model equation is identical to BSIMPD equation.
If SoiMod=1 (unified model for PD&FD) or SoiMod=2 (ideal FD), the following equations (FD
module) are added on top of BSIMPD.
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Chapter 6: BSIMSOI - A Unified Model for PD and FD SOI MOSFETs
Vbs 0
C Si
phi
qN ch 1 N LX Leff
TSi Vnonideal V DIBL e
2 C BOX
Ves VFBb
C Si C BOX 2 Si C Si C BOX
Si OX OX
where C Si , C BOX , C OX
TSi TBOX TOX
Leff L
V DIBL Dvbd 0 exp Dvbd1 2 exp Dvbd1 eff Vbi 2 B
2l l
Leff L
e K 1b K 2b exp Dk 2b 2 exp Dk 2b eff
2l
l
C OX Vth ,FD V gs _ eff VOFF ,FD
phi phiON N OFF ,FDVt ln 1 exp
C OX C Si
1
C BOX
1 1
N OFF ,FDVt
V gsteff .FD V gsteff ,FD 2 K 1 2 B
phiON 2 B Vt ln 1
,
MoinFD K 1 Vt
2
V gs _ eff Vth ,FD VOFF ,FD
V gsteff ,FD N OFF ,FDVt ln 1 exp
N OFF ,FDVt
Here Nch is the channel doping concentration. NLX is the lateral non-uniform doping coefficient
to account for the lateral non-uniform doping effect. VFBb is the backgate flatband voltage. Vth,FD
is the threshold voltage at Vbs=Vbs0(phi=2B). vt is thermal voltage. K1 is the body effect
coefficient.
If SoiMod=1, the lower bound of Vbs (SPICE solution) is set to Vbs0. If SoiMod=2, Vbs is pinned
at Vbs0. Notice that there is no body node and body leakage/charge calculation in SoiMod=2.
The zero field body potential that will determine the transistor threshold voltage, Vbsmos, is then
calculated by
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Chapter 6: BSIMSOI - A Unified Model for PD and FD SOI MOSFETs
if Vbs Vbs 0 TOX
Vbs 0 TOX Vbs
CSi 2
Vbsmos Vbs
2qN chTSi
else
Vbsmos Vbs
The subsequent clamping of Vbsmos will use the same equation that utilized in BSIMPD. Please
download the BSIMPD manual at (http://bsim.berkeley.edu/models/bsimsoi).
If SoiMod=3 is specified, BSIMSOI will select the operation mode for the user based on the
estimated value of Vbs0 at phi=2B (bias independent), Vbs0t:
If Vbs0t > Vbs0fd, BSIMSOI will be in the ideal FD mode (SoiMod=2).
If Vbs0t < Vbs0pd, BSIMSOI will be in the BSIMPD mode (SoiMod=0).
Otherwise, BSIMSOI will be operated under SoiMod=1.
Notice that both Vbs0fd and Vbs0pd are model parameters.
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Chapter 7: BSIMSOI RF Model
Chapter 7: BSIMSOI RF Model
BSIMSOI4.1 provides the gate resistance model and body resistance model for devices used in
RF application.
7.1 Gate Electrode and Intrinsic-Input Resistance (IIR) Model
Users have four options for modeling gate electrode resistance (bias independent) and intrinsic-
input resistance (Rii, bias-dependent) by choosing model choice parameter rgateMod.
RgateMod = 0 (zero-resistance):
In this case, no gate resistance is generated.
RgateMod = 1 (constant-resistance):
Rgeltd
In this case, only the electrode gate resistance (bias-independent) is generated by adding an
internal gate node. The electrode gate resistance Rgeltd is given by
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Chapter 7: BSIMSOI RF Model
Weff
RSHG XGW
3 NGCON NSEG
Rgeltd (7.1)
NGCON L drawn XGL
RgateMod = 2 (RII model with variable resistance):
Rgeltd+
Rii
In this case, the gate resistance is the sum of the electrode gate resistance and the intrinsic-input
1 I Weff eff C oxeff k B T
resistance Rii as given by XRCRG1 ds XRCRG2
Rii V qL
dseff eff
(7.2)
An internal gate node will be generated.
RgateMod = 3 (RII model with two nodes):
In this case, the gate electrode resistance is in series with the intrinsic-input resistance Rii
through two internal gate nodes, so that the overlap capacitance current will not pass through the
intrinsic-input resistance.
Rgeltd
Rii
Cgso Cgdo
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Chapter 7: BSIMSOI RF Model
7.2 Body Resistance Network
RbodyMod = 0
In this case, body resistance network turns off. RF data still could be fit for fully depleted SOI
device [28].
RbodyMod =1
A two-resistance body resistance network turns on as shown in the following figure.
Two extra nodes sbNode and dbNode are introduced in this case. The body resistor
RBSB/RBDB are located between sbNode/dbNode and bNode. As in BSIM4, a minimum
conductance, GBMIN, is introduced in parallel with each resistance and therefore to prevent
infinite resistance values, which would otherwise cause poor convergence.
Note that the intrinsic model body reference point in this case is the internal body node bNode,
into which the impact ionization current Iii and the GIDL current IGIDL flow.
R
sb bdb
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Chapter 8: BSIM SOI Noise Model
Chapter 8 BSIMSOI Noise Model
8.1 Flicker noise models
BSIMSOI4.1 provides two flicker noise models. When the model selector fnoiMod is set to
0, a simple flicker noise model which is convenient for hand calculation is invoked. A
unified physical flicker noise model, which is the default model, will be used if fnoiMod=1.
These two modes come from BSIMSOI3.1, but the unified model has many improvements.
For instance, it is now smooth over all bias regions and considers the bulk charge effect.
fnoiMod = 0 (simple model)
The noise density is:
1 AF
Weff KF I dsAF (8.1)
Sid ( f )
eff f
Coxe LBF EF
W 0 FLK
fnoiMOd = 1 (unified model)
The physical mechanism for the flicker noise is trapping/de-trapping related charge
fluctuation in oxide traps, which results in fluctuations of both mobile carrier numbers and
mobility in the channel. The unified flicker noise model captures this physical process.
The noise density in inversion region is given by:
k BTq 2 eff I ds N0 N
Sid ,inv ( f )
1010
NOIA log NOIB N N
NOIC 2
N N l
2
Nl N
0 l 0
Coxe L2eff Abulk f ef 2
k BTI ds2 Lclm NOIA NOIB Nl NOIC Nl2
Weff L2eff f ef 1010 N N
2
l
(8.2)
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Chapter 8: BSIM SOI Noise Model
Where eff is the effective mobility at the given bias condition, and Leff and Weff are the
effective length and width respectively. The parameter N 0 is the charge density at the source
side given by:
CoxVgsteff (8.3)
N0
q
The parameter N l is the charge density at the source side given by:
CoxVgsteff AbulkVdseff (8.4)
Nl 1
q Vgsteff 2vt
N is given by:
k BT (Cox Cd CIT ) (8.5)
N
q2
where CIT is a model parameter from DC IV and C d is the depletion capacitance.
Lclm is the channel length reduction due to channel length modulation and given by:
Vds Vdseff (8.6)
EM
Lclm Litl log Litl
Esat
2VSAT
Esat
eff
In the subthreshold region, the noise density is written as:
NOIA kBT I ds2 (8.5)
Sid , subVt ( f )
Weff Leff f EF N *2 1010
The total flicker noise density is given by
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Chapter 8: BSIM SOI Noise Model
Sid ,inv ( f ) Sid , subvt ( f ) (8.6)
Sid ( f )
Sid ,inv ( f ) Sid , subvt ( f )
8.2 Thermal noise models
There are three channel thermal noise models in BSIMSOI4.0 beta version. One is the charge
based model (default) similar to that used in BSIMSOI3.1. The second is the BSIM4
compatible holistic thermal noise model. The simple SPICE2 thermal noise model is also
provided in BSIMSOI4.1. These three models can be selected through the model selector
tnoiMod.
tnoiMod = 0 (charge based model)
The noise current is given by
4k BT f (8.7)
id2 NTNOI
L2eff
Rds
eff Qinv
where Rds is the source/drain resistance, and the parameter NTNOI is introduced for more
accurate fitting of short-channel devices. Qinv is the inversion channel charge computed from
the capacitance models
tnoiMod = 1 (holistic model)
In this thermal noise model, all the short-channel effects and velocity saturation effect
incorporated in the IV model are automatically included, hence the name “holistic thermal
noise model”. In addition, the amplification of the channel thermal noise through Gm and
G mbs as well as the induced-gate noise with partial correlation to the channel thermal noise
are all captured in the new “noise partition” model.
The noise voltage source partitioned to the source side is given by:
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Chapter 8: BSIM SOI Noise Model
Vdseff f (8.8)
vd2 4kBT tnoi
2
I ds
and the noise current source put in the channel region with gate and body amplification is
given by:
Vdseff f (8.9)
Gds tnoi Gm Gmbs vd2 Gm Gds Gmbs
2
id2 4kBT
2
I ds
where
V 2
(8.10)
tnoi RNOIB 1 TNOIB Leff gsteff
E L
sat eff
V
2
tnoi RNOIA 1 TNOIA Leff gsteff
E L
sat eff
tnoiMod = 2 (SPICE2 model)
8k BT f (8.11)
id2 NTNOI Gm Gmbs Gds
3
The parameter NTNOI is added to give the flexibility to tune the magnitude of noise
density.
tnoiMod = 3
Unlike tnoiMod=1, in this thermal noise model both the gate and the drain noise are
implemented as current noise sources. The drain current noise flows from drain to
source; whereas the induced gate current noise flows from the gate to the source and
drain. The correlation between the two noise sources is independently controllable and
can be tuned using the parameter RNOIC, although the use of default value 0.395 is
recommended when measured data is not available. The relevant formulations of
tnoiMod=3 are given below.
(8.12)
(8.13)
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Chapter 8: BSIM SOI Noise Model
(8.14)
(8.15)
(8.16)
(8.17)
(8.18)
* ( ) +
(8.19)
( )
√ (8.20)
[ ( ) ]
(8.21)
[ ( ) ]
(8.22)
(8.23)
( ) (8.24)
(8.25)
(8.26)
√ ⁄
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Chapter 8: BSIM SOI Noise Model
( ) ( | |) (8.27)
( ) ( ) (8.28)
( ) ( ) (8.29)
I (di, si) ctnoi V (N) sf SCALEN (8.30)
I (gi, si) ddt 0.5C0 SCALEN V (N) (8.31)
I (gi, di) ddt 0.5C0 SCALEN V (N) (8.32)
8.3 Other improvement on noise model
In BSIMSOI4.1, some other improvements on noise model are made as following
1. Body contact resistance induced thermal noise is introduced.
2. Thermal noise induced by the body resistance network is introduced as RBODYMOD=1.
3. Shot noises induced by Ibs and Ibd are equal in BSIMSOI3.2 and BSIMPD. In
BSIMSOI4.0, these two noises are separated.
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Chapter 9: Stress Effect Model
Chapter 9 Stress Effect Model
The mechanical stress effect induced by process causes the performance of MOSFET to be
function of the active area size (OD: oxide definition) and the location of the device in the active
area. The necessity of new models to describe the layout dependence of MOS parameters due to
stress effect becomes very urgent in advance CMOS technologies. Influence of stress on mobility
has been well known since the 0.13um technology. The stress influence on saturation velocity is
also experimentally demonstrated. Stress-induced enhancement or suppression of dopant
diffusion during the processing is reported. Since the doping profile may be changed due to
different STI sizes and stress, the threshold voltage shift and changes of other second-order
effects, such as DIBL and body effect, were shown in process integration.
Experimental analysis shows that there exist at least two different mechanisms within the
influence of stress effect on device characteristics. The first one is mobility related which is
induced by the band structure modification. The second one is Vth related as a result of doping
profile variation. Both of them follow the same 1/LOD trend but reveal different L and W
scaling. A BSIM4 compatible phenomenological stress model based on these findings has been
developed by modifying some parameters. Note that the following equations have no impact on
the iteration time because there are no voltage-controlled components in them.
9.1 Mobility Related Equations
Mobility changes induced by stress effect is modeled by adjusting U 0 and Vsat according to
different W, L and OD shapes. The relative change of mobility is defined as follows:
eff eff eff 0
(9.1)
eff
eff 0 eff 0
So we have
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Chapter 9: Stress Effect Model
eff
1 eff (9.2)
eff 0
Figure (9.1) shows the typical layout of a MOSFET on active layout surrounded by STI
isolation. SA, SB are the distances between isolation edge to Poly from one and the other side,
respectively [27]. 2D simulation shows that stress distribution can be expressed by a simple
function of SA and SB. Figure (9.2) shows the schematic stress distribution in the OD region
[29].
Fig. 9.1 shows the typical layout of a MOSFET [27]
Fig. 9.2 Schematic stress distribution in the OD region [29]
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Chapter 9: Stress Effect Model
Assuming that mobility relative change is proportional to stress distribution. It can be described
as function of SA, SB(LOD effect), L, W, and T dependence.
KU 0
Inv _ sa Inv _ sb (9.3)
eff
Kstress _ u 0
1 1
where Inv _ sa , Inv _ sb ,
SA 0.5 Ldrawn SB 0.5 Ldrawn
LKU 0 WKU 0
1 ( L
drawn XL) (Wdrawn XW WLOD)
LLODKU 0 WLODKU 0
Kstress _ u 0
PKU 0 Temperature
1 TKU 0
WLODKU 0
1
( Ldrawn XL) (Wdrawn XW WLOD) TNOM
LLODKU 0
So that
1 eff ( SA, SB)
eff eff 0 (9.4)
1 eff ( SAref , SBref )
1 KVSAT eff ( SA, SB )
vsattemp vsattemp 0 (9.5)
1 KVSAT eff ( SAref , SBref )
where eff 0 , vsattemp 0 are low field mobility and low field saturation velocity at SAref , SBref .
SAref , SBref are reference distances between OD edge to poly from one and the other side.
9.2 Vth-related Equations
Vth0, K2 and ETA0 are modified to cover the doping profile change in the devices with
different LOD. They use the same 1/LOD formulas as shown in section(13.1.1), but different
equations for W and L scaling:
VTH 0 VTH 0original
KVTH 0
Kstress _ vth0
Inv _ sa Inv _ sb Inv _ saref Inv _ sbref (9.6)
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Chapter 9: Stress Effect Model
Inv _ sa Inv _ sb Inv _ saref Inv _ sbref
STK 2
K 2 K 2original (9.7)
Kstress _ vth0 LODK 2
Inv _ sa Inv _ sb Inv _ saref Inv _ sbref
STETA0
ETA0 ETA0original (9.8)
Kstress _ vth0 LODETA0
1 1
where Inv _ saref , Inv _ sbref
SAref 0.5 Ldrawn SBref 0.5 Ldrawn
LKVTH 0 WKVTH 0
1 ( L
drawn XL) (Wdrawn XW WLOD)WLODKVTH
LLODKVTH
Kstress _ vth0 (9.9)
PKVTH 0
(L
drawn XL) (Wdrawn XW WLOD)WLODKVTH
LLODKVTH
9.3 Multiple Finger Device
For multiple finger devices, as shown the layout in Fig. 9.3, the total LOD effect is the
average of LOD effect to every finger. That is:
1 NF 1 1
Inv _ sa
NF i 0 SA 0.5 Ldrawn i (SD Ldrawn )
NF 1
1 1
Inv _ sb SB 0.5 L
NF i 0 drawn i ( SD Ldrawn )
Fig. 9.3 Layout of multiple-finger MOSFET [27]
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Chapter 10: New Material Model
Chapter 10 New Material Model
In BSIMSOI4.1, a new global selector is introduced to turn on or of the new material models,
which are important for the advanced CMOS technology. When users select mtrlMod = 1, the
new materials (such as high k/metal gate) could be modeled. The default value (mtrlMod = 0)
maintains the backward compatibility.
10.1 Non-Silicon Channel
With the three new parameters, the temperature-dependent band gap and
intrinsic carriers in non-silicon channel are described as follow:
TBGASUB Tnom 2 (10.1)
Eg 0 BG 0SUB
Tnom TBGBSUB
TBGASUB 300.152 (10.2)
Eg (300.15) BG 0SUB
300.15 TBGBSUB
Eg (300.15) Eg 0 (10.3)
3/ 2
Tnom
ni NI 0SUB exp
300.15 2vt
TBGASUB Temp 2 (10.4)
Eg BG0SUB
Temp TBGBSUB
Here, BG0SUB is the band-gap of substrate at T=0K; TBGASUB and TBGBSUB are the first and
second parameters of band-gap change due to temperature, respectively.
When capMod=3, the inversion charge layer thickness (XDC) is also modified as follows:
ADOS 1.9 10 9 (10.5)
X DC 0.7 BDOS
V (VTH 0 VFB s )
1 gsteff
2TOXP
Here, the density of states parameters ADOS and BDOS are introduced to control the charge
centroid.
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Chapter 10: New Material Model
10.2 Non-SiO2 Gate insulator
For Non-SiO2 gate insulator, the equivalent SiO2 thickness (EOT) is a new input parameter,
which is measured at VDDEOT. Given these new parameters (EOT and VDDEOT), the physical
gate oxide thickness TOXP could be calculated as follows:
3.9 (10.6)
TOXP EOT X DC V VDDEOT ,V V 0
EPSRSUB gs ds bs
Here, EPSRSUB is the dielectric constant of substrate relative to vacuum.
10.3 Non-Poly Silicon Gate Material
Two new parameters are introduced to describe the non-poly silicon gate material. One is PHIG,
which is the gate work function. Another is EPSRGATE, the dielectric constant of gate relative to
vacuum. It is worth pointing out that EPSRGATE=0 represents the metal gate and deactivates the
ploy depletion effect.
When the gate dielectric and channel are different materials, the flat band voltage at
Source/Drain is calculated using the following:
Eg 0 Eg 0 NSD (10.7)
V fbsd PHIG ( EASUB B 4SOItype MIN , vt ln
2 2 ni
Here B4SOItype is defined as +1 for nMOS and -1 for pMOS.
This new flat band equation improves the GIDL/GISL models as following:
Vds Vgse EGIDL V fbsd (10.8)
I GIDL AGIDL WeffCJ Nf
EPSRSUB
EOT
3.9
EPSRSUB
EOT 3.9
BGIDL
Vdb3
exp
Vds Vgse EGIDL V fbsd CGIDL Vdb
3
Vds Vgse EGISL V fbsd (10.9)
I GIDS AGISL WeffCJ Nf
EPSRSUB
EOT
3.9
EPSRSUB
EOT 3.9
BGISL
Vdb3
exp
Vds Vgse EGISL V fbsd CGISL Vdb
3
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Chapter 10: New Material Model
Furthermore, for mtrlMod=1 the mobility degradation uses the new expression of the vertical
field in channel as following:
(10.10)
Vgsteff 2Vth 2 B 4SOItype ( PHIG EASUB Eg / 2 0.45) 3.9
Eeff
EOT EPSRSUB
Consequently, when mtrlMod=1, mobMod=1, 2 and 3 are changed, respectively:
mobMod=1
o (10.11)
eff
1 (U a U cVbseff ) Eeff U b Eeff 2
mobMod=2
o (10.12)
eff
Vgsteff U d Vgsteff U d
1 (U a U cVbseff )( ) Ub ( )2
Tox Tox
U d 2 B 4 SOItype ( PHIG EASUB Eg / 2 0.45)
mobMod=3
0 (10.13)
eff
1 [U a Eeff U b Eeff 2 ](1 U cVbseff )
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Appendix A: Model Instance Syntax
Appendix A: Model Instance Syntax
Mname <D node> <G node> <S node> <E node> [P node]
[B node] [T node] <model>
[L=<val>] [W=<val>]
[AD=<val>] [AS=<val>] [PD=<val>] [PS=<val>]
[NRS=<val>] [NRD=<val>] [NRB=<val>]
[OFF][BJTOFF=<val>]
[IC=<val>,<val>,<val>,<val>,<val>]
[RTH0=<val>] [CTH0=<val>]
[DEBUG=<val>]
[DELVTO=<val>]
[SA=<val>][SB=<val>][SD=<val>]
[NF=<val>]
[NBC=<val>] [NSEG=<val>] [PDBCP=<val>] [PSBCP=<val>]
[AGBCP=<val>][AEBCP=<val>][VBSUSR=<val>][TNODEOUT]
[FRBODY=<val>][AGBCPD=<val>][SHMOD=<val>]
Description
<D node> Drain node
<G node> Gate node
<S node> Source node
<E node> Substrate node
[P node] (Optional) external body contact node
[B node] (Optional) internal body node
[T node] (Optional) temperature node
<model> Level 9 BSIM3SOI model name
[L] Channel length
[W] Channel width
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Appendix A: Model Instance Syntax
[AD] Drain diffusion area
[AS] Source diffusion area
[PD] Drain diffusion perimeter length
[PS] Source diffusion perimeter length
[NRS] Number of squares in source series resistance
[NRD] Number of squares in drain series resistance
[NRB] Number of squares in body series resistance
[OFF] Device simulation off
[BJTOFF] Turn off BJT current if equal to 1
[IC] Initial guess in the order of (Vds, Vgs, Vbs, Ves, Vps). (Vps will be
ignored in the case of 4-terminal device)
[RTH0] Thermal resistance per unit width
if not specified, RTH0 is extracted from model card.
if specified, it will override the one in model card.
[CTH0] Thermal capacitance per unit width
if not specified, CTH0 is extracted from model card.
if specified, it will over-ride the one in model card.
[DEBUG] Please see the debugging notes
[DELVTO] Zero bias threshold voltage variation
[SA] Stress effect parameter
[SB] Stress effect parameter
[SD] Stress effect parameter
[NF] Number of fingers
[NBC] Number of body contact isolation edge
[NSEG] Number of segments for channel width partitioning [17]
[PDBCP] Parasitic perimeter length for body contact at drain side
[PSBCP] Parasitic perimeter length for body contact at source side
[AGBCP] Parasitic gate-to-body overlap area for body contact (n+-p)
[AGBCP2] Parasitic gate-to-body overlap area for body contact (p+-p)
For details of AGBCP and AGBCP2, please check Fig.4.4
[AEBCP] Parasitic body-to-substate overlap area for body contact
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Appendix A: Model Instance Syntax
[VBSUSR] Optional initial value of Vbs specified by user for transient analysis
[TNODEOUT] Temperature node flag indicating the usage of T node
[FRBODY] Layout-dependent body resistance coefficient
[AGBCPD] Parasitic gate-to-body overlap area for body contact in DC
[RBDB] Resistance between bNode and dbNode
[RBSB] Resistance between bNode and sbNode
A.2. About Optional Nodes
There are three optional nodes, P, B and T nodes. P and B nodes are used for body contact
devices. Let us consider the case when TNODEOUT is not set. If user specifies four nodes, this
element is a 4-terminal device, i.e., floating body. If user specifies five nodes, the fifth node
represents the external body contact node (P). There is a body resistance between internal body
node and P node. In these two cases, an internal body node is created but it is not accessible in
the circuit deck. If user specifies six nodes, the fifth node represents the P node and the sixth
node represents the internal body node (B). This configuration is useful for distributed body
resistance simulation.
If TNODEOUT flag is set, the last node is interpreted as the temperature node. In this case,
if user specifies five nodes, it is a floating body case. If user specifies six nodes, it is a body-
contacted case. Finally, if user specifies seven nodes, it is a body-contacted case with an
accessible internal body node. The temperature node is useful for thermal coupling simulation.
If the NODECHK flag is set, different warning messages are displayed and unsupported
nodes are grounded according to the following table.
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Appendix A: Model Instance Syntax
Spice-syntax netlist
(node-order determined
$port_connected(NODE) Warning message
terminals)
BSIM-SOI
Nodes
nodes as seen
supplied TNODEOUT SOIMOD
from the TNODEOUT SOIMOD=2
CASE on NODE=P NODE=B NODE=T (instance SHMOD =0,1,3
USER (not Messages Messages
instance parameter) Messages
model)
call
perspective
1 DGSE 4 F F F 0 0 None None None
2 DGSEP 5 T F F 0 0 None None s1
3 DGSEPB 6 T T F 0 0 None None s2
4 DGSEPBT 7 T T T 0 0 None None s2
5 DGSE 4 F F F 1 0 None None None
6 DGSET 5 T F F 1 0 None None None
7 DGSEPT 6 T T F 1 0 None None s1
8 DGSEPBT 7 T T T 1 0 None None s2
9 DGSE 4 F F F 0 1 None None None
10 DGSEP 5 T F F 0 1 None None s1
11 DGSEPB 6 T T F 0 1 None None s2
12 DGSEPBT 7 T T T 0 1 None None s2
13 DGSE 4 F F F 1 1 t1 None None
14 DGSET 5 T F F 1 1 t2 None None
15 DGSEPT 6 T T F 1 1 t3 None None
16 DGSEPBT 7 T T T 1 1 None None s2
List of warning messages:
s1 "Warning: A P node was specified however SOIMOD=2 does not support a P node.
Internally this node is tied to global ground"
s2 "Warning: P and B nodes were specified however SOIMOD=2 does not support P or B
nodes. Internally these nodes are tied to global ground”
t1 "Warning: TNODEOUT=1 requesting an external temperature node but a 5th node for
temperature is not supplied"
t2 ""Warning: A 5th node has been specified with TNODEOUT=1. The 5th node will be
treated as the temperature node T""
t3 "Warning: 5th and 6th nodes were specified when TNODEOUT=1. The 6th node will be
treated as the temperature node T and Internally the 5th node will be tied to global
ground"
Implementation Notes:
1) These new warning messages are toggled on/off by a new model parameter INSTANCECHK
(analogous to PARAMCHK).
2) $port_connected(NODE) only provides information about whether a node is present in the
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Appendix A: Model Instance Syntax
node list of the instance in the netlist. $port_connected does not provide any information about
whether or where NODE is actually connected in the circuit.
3) If more than 4 nodes are specified but the TNODEOUT, SHMOD, and SOIMOD are not set
to use any of the rightmost 5th, 6th, or 7th nodes, these nodes will be ignored and no warning
will be issued.
4) TNODEOUT is an integer instance parameter (default 0).
5) When TNODEOUT=1, the right-most node is always interpreted as the temperature node T.
6) When SOIMOD=0,1,3 the P and B node are treated consistently with the BSIM-SOI self-
heating model.
7) When SOIMOD=2, the P node is grounded, i.e. (V(p) <+ 0) in cases 2,3,4,7,8,10,11,12,15,16.
8) When SOIMOD=2, the B node grounded, i.e. (V(b) <+ 0) in cases 3,4,8,11,12,16.
9) When SHMOD=0 and TNODEOUT=1 there are no self-heating messages because self-
heating is inactive.
10) When SHMOD=1 and TNODEOUT=1 and number of nodes=5, switch SH network to use
the 5th node (case 14).
11) When SHMOD=1 and TNODEOUT=1 and number of nodes=6, switch SH network to use
the 6th node (case 15).
12) When SHMOD=1 and TNODEOUT=1 and number of nodes=7, switch SH network to use
the 7th node (case 16).
A.3. Notes on Debugging
The instance parameter <DEBUG> allows users to turn on debugging information
selectively. Internal parameters (e.g. par) for an instance (e.g. m1) can be plotted by this
command:
plot m1#par
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Appendix A: Model Instance Syntax
By default, <DEBUG> is set to zero and two internal parameters will be available for
plotting:
#body Vb value iterated by SPICE
#temp Device temperature with self-heating mode turned on
If <DEBUG> is set to one or minus one, more internal parameters are available for
plotting. This serves debugging purposes when there is a convergence problem. This can also
help the user to understand the model more. For <DEBUG> set to minus one, there will be
charge calculation even if the user is running DC simulation. Here is the list of internal
parameters:
#Vbs Real Vbs value used by the IV calculation
#Vgsteff Effective gate-overdrive voltage
#Vth Threshold voltage
#Ids MOS drain current
#Ic BJT current
#Ibs Body to source diode current
#Ibd Body to drain diode current
#Iii Impact ionization current
#Igidl GIDL current
#Itun Tunneling current
#Ibp Body contact current
#Gds Output conductance
#Gm Transconductance
#Gmb Drain current derivative wrt Vbs
These parameters are valid only if charge computation is required
#Cbb Body charge derivative wrt Vbs
#Cbd Body charge derivative wrt Vds
#Cbe Body charge derivative wrt Ves
#Cbg Body charge derivative wrt Vgs
#Qbody Total body charge
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Appendix A: Model Instance Syntax
#Qgate Gate charge
#Qac0 Accumulation charge
#Qsub Bulk charge
#Qsub0 Bulk charge at zero drain bias
#Qbf Channel depletion charge
#Qjd Parasitic drain junction charge
#Qjs Parasitic source junction charge
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Appendix B: Model Parameter List
Appendix B: Model Parameter List
All model parameters additional to BSIM3v3/BSIM4 will be shown with bold cases.
B.1. BSIMSOI Model Control Parameters
Symbol Symbol
used in used in Description Unit Default Notes (below
equation SPICE the table)
None level Level 10 for BSIMSOI4.1 - 10 -
SoiMod soiMod SOI model selector (instance) - 0
SoiMod=0: BSIMPD
SoiMod=1: unified model for PD&FD.
SoiMod=2: ideal FD.
SoiMod=3: auto selection by BSIMSOI
Shmod shMod Flag for self-heating - 0
0 - no self-heating,
1 - self-heating
Mobmod mobmod Mobility model selector - 1 -
Capmod capmod Flag for the short channel capacitance model - 2
Noimod noimod Flag for Noise model - 1 -
IgcMod IgcMod Gate-to-channel tunneling current model selector - 0
IgbMod IgbMod Gate-to-body tunneling current model selector - 0
RdsMod rdsMod Bias-dependent source/drain resistance - 0
model selector
RgateMod rgateMod Flag for gate resistance model - 0 -
RbodyMod rbodyMod Flag for body resistance model - 0 -
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Appendix B: Model Parameter List
FnoiMod fnoiMod Flicker noise model selector - 1
TnoiMod TnoiMod Thermal noise model selector - 0
MtrlMod mtrlMod New material model selector - 0
VgstcvMod VgstcvMod VgsteffCV model selector - 0
IiiMod IiiMod Impact ionization current model selector - 0
gidlMod gidlMod New GIDL/GISL model selector - 0
fdMod fdMod New ∆Vbi model selector - 0
B.2. Process Parameters
Symbol Symbol
used in used in Description Unit Default Notes
equation SPICE (below the table)
tsi Tsi Silicon film thickness m 10-7 -
tbox Tbox Buried oxide thickness m 3x10-7 -
tox tox Gate oxide thickness m 1x10-8 -
Toxm toxm Gate oxide thickness used in extraction m tox
Xj Xj S/D junction depth m Tsi -
nch Nch Channel doping concentration 1/cm3 1.7x1017 -
nsub Nsub Substrate doping concentration 1/cm3 6x1016 -
Ngate ngate poly gate doping concentration 1/cm3 0 -
Eot eot Effective SiO2 thickness nm 10
Leffeot leffeot Effective length for extraction of EOT um 1 -
Weffeot weffeot Effective width for extraction of EOT um 10 -
Tempeot tempeot Temperature for extraction of EOT K 300.15 -
Note: Leffeot, Weffeot, Tempeot and Vddeot are the parameters in EOT extraction and used in
Toxp calculation (i.e., Eq. (10.6)).
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Appendix B: Model Parameter List
B.3. DC Parameters
Symbol Symbol
used in used in Description Unit Default Notes (below the
equation SPICE table)
Vth0 vth0 Threshold voltage @Vbs=0 for long and - 0.7 -
wide device
K1 k1 First order body effect coefficient V1/2 0.6 -
K1w1 k1w1 First body effect width dependent m 0 -
parameter
K1w2 k1w2 Second body effect width dependent m 0 -
parameter
K2 k2 Second order body effect coefficient - 0 -
K3 k3 Narrow width coefficient - 0 -
K3b k3b Body effect coefficient of k3 1/V 0 -
Kb1 Kb1 Backgate body charge coefficient - 1 -
W0 w0 Narrow width parameter m 0 -
Lpe0 LPE0/ Lateral non-uniform doping parameter m 1.74e-7 If Lpe0 not given,
lpe0=nlx if nlx given,;
Else take the default
NLX
Lpe0 was called nlx in
BSIMSOI3
Lpeb LPEB Lateral non-uniform doping effect on K1 m 0.0 -
Dvt0 Dvt0 first coefficient of short-channel effect - 2.2 -
on Vth
Dvt1 dvt1 Second coefficient of short-channel - 0.53 -
effect on Vth
Dvt2 dvt2 Body-bias coefficient of short-channel 1/V -0.032 -
effect on Vth
Dvt0w dvt0w first coefficient of narrow width effect - 0 -
on Vth for small channel length
Dvt1w dvt1w Second coefficient of narrow width - 5.3e6 -
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Appendix B: Model Parameter List
effect on Vth for small channel length
Dvt2w dvt2w Body-bias coefficient of narrow width 1/V -0.032 -
effect on Vth for small channel length
0 u0 Mobility at Temp = Tnom cm2/( -
NMOSFET V-sec) 670
PMOSFET 250
Ua ua First-order mobility degradation m/V 2.25e-9 -
coefficient
Ub ub Second-order mobility degradation (m/V) 5.9e-19 -
2
coefficient
Uc uc Body-effect of mobility degradation 1/V -.0465 -
coefficient
Ud ud Coulomb scattering factor of mobility - 0
Ucs ucs Mobility exponent factor in mobMod=4 - 0
Eu eu Mobility exponent factor in mobMod=4 - 0
vsat vsat Saturation velocity at Temp=Tnom m/sec 8e4 -
A0 a0 Bulk charge effect coefficient for - 1.0 -
channel length
Ags ags Gate bias coefficient of Abulk 1/V 0.0 -
B0 b0 Bulk charge effect coefficient for m 0.0 -
channel width
B1 b1 Bulk charge effect width offset m 0.0 -
Keta keta Body-bias coefficient of bulk charge V-1 0 -
effect
Ketas Ketas Surface potential adjustment for bulk V 0 -
charge effect
A1 A1 First non-saturation effect parameter 1/V 0.0 -
A2 A2 Second non-saturation effect parameter 0 1.0 -
Rdsw rdsw Parasitic resistance per unit width - 100 -
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Appendix B: Model Parameter List
mWr
Prwb prwb Body effect coefficient of Rdsw 1/V 0 -
Prwg prwg Gate bias effect coefficient of Rdsw 1/V1/2 0 -
Wr wr Width offset from Weff for Rds - 1 -
calculation
Nfactor nfactor Subthreshold swing factor - 1 -
Wint wint Width offset fitting parameter from I-V m 0.0 -
without bias
Lint lint Length offset fitting parameter from I-V m 0.0 -
without bias
DWg dwg Coefficient of Weff’s gate dependence m/V 0.0
DWb dwb Coefficient of Weff’s substrate body bias m/V1/2 0.0
dependence
DWbc Dwbc Width offset for body contact isolation m 0.0
edge
Voff voff Offset voltage in the subthreshold region V -0.08 -
for large W and L
Eta0 eta0 DIBL coefficient in subthreshold region - 0.08 -
Eta0CV eta0cv DIBL coefficient in subthreshold region - Eta0 -
for CV
Etab etab Body-bias coefficient for the 1/V -0.07 -
subthreshold DIBL effect
EtabCV etabcv Body-bias coefficient for the 1/V Etab -
subthreshold DIBL effect for CV
Dsub dsub DIBL coefficient exponent - 0.56 -
Cit cit Interface trap capacitance F/m2 0.0 -
Cdsc cdsc Drain/Source to channel coupling F/m2 2.4e-4 -
capacitance
Cdscb cdscb Body-bias sensitivty of Cdsc F/m2 0 -
Cdscd cdscd Drain-bias sensitivty of Cdsc F/m2 0 -
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Appendix B: Model Parameter List
Pclm pclm Channel length modulation parameter - 1.3 -
Pdibl1 pdibl1 First output resistance DIBL effect - .39 -
correction parameter
Pdibl2 pdibl2 Second output resistance DIBL effect - 0.086 -
correction parameter
Drout drout L dependence coefficient of the DIBL - 0.56 -
correction parameter in Rout
Pvag pvag Gate dependence of Early voltage - 0.0 -
delta Effective Vds parameter - 0.01 -
0 alpha0 The first parameter of impact ionization m/V 0.0 -
current
Fbjtii fbjtii Fraction of bipolar current affecting the - 0.0 -
impact ionization
0 beta0 First Vds dependent parameter of impact V-1 0 -
ionization current
1 beta1 Second Vds dependent parameter of - 0 -
impact ionization current
2 beta2 Third Vds dependent parameter of impact V 0.1 -
ionization current
Vdsatii0 vdsatii0 Nominal drain saturation voltage at V 0.9 -
threshold for impact ionization current
Tii tii Temperature dependent parameter for - 0 -
impact ionization current
Lii lii Channel length dependent parameter at - 0 -
threshold for impact ionization current
Esatii esatii Saturation channel electric field for V/m 1e7 -
impact ionization current
Sii0 sii0 First Vgs dependent parameter for impact V-1 0.5 -
ionization current
Sii1 sii1 Second Vgs dependent parameter for V-1 0.1 -
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Appendix B: Model Parameter List
impact ionization current
Sii2 sii2 Third Vgs dependent parameter for - 0 -
impact ionization current
Siid siid Vds dependent parameter of drain V-1 0 -
saturation voltage for impact ionization
current
Abjtii abjtii Exponent factor for avalanche current V-1 0
Cbjtii cbjtii Length scaling parameter for II BJT part m 0
Ebjtii ebjtii Impact ionization parameter for BJT part - 0
Mbjtii mbjtii Internal B-C grading coefficient - 0.4
Vbci vbci Internal B-C built-in potential V 0
Agidl Agidl Pre-exponential GIDL constant 1 0.0 -
Bgidl Bgidl GIDL exponential coefficient V/m 2.3e9 -
3
Cgidl Cgidl Parameter for body bias effect on GIDL V 0.5
Egidl Egidl/ Fitting parameter for band bending for V 1.2 If Egidl not
given,
Ngidl GIDL
Egidl=Ngidl if
Ngidl given,;
Else take the
default
Egidl was called
Ngidl in
BSIMSOI3
Agisl Agisl Pre-exponential GISL constant 1 0.0 -
Bgisl Bgisl GISL exponential coefficient V/m 2.3e9 -
Cgisl Cgisl Parameter for body bias effect on GISL V3 0.5
Egisl Egisl Fitting parameter for band bending for V 1.2
GISL
Rgidl rgidl Vgs-dependent parameter for GIDL - 1.0
when gidlMod = 1
Kgidl kgidl Vds-dependent parameter for GIDL V 0.0
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Appendix B: Model Parameter List
when gidlMod = 1
Fgidl fgidl Vds-dependent parameter for GIDL
when gidlMod = 1
Rgisl rgisl Vgs-dependent parameter for GISL - 1.0
when gidlMod = 1
Kgisl kgisl Vbs-dependent parameter for GISL V 0.0
when gidlMod = 1
Fgisl fgisl Vbs-dependent parameter for GISL V 0.0
when gildMod = 1
ndiodes Ndiode Diode non-ideality factor for source - 1.0 -
ndioded Ndioded Diode non-ideality factor for drain - Default -
to its
source
value
nrecf0s Nrecf0 Recombination non-ideality factor at - 2.0 -
forward bias for source
nrecf0d Nrecf0d Recombination non-ideality factor at - Default -
forward bias for drain to its
source
value
nrecr0s Nrecr0 Recombination non-ideality factor at - 10 -
reversed bias for source
nrecr0d Nrecr0d Recombination non-ideality factor at - Default -
reversed bias for drain to its
source
value
isbjt Isbjt BJT injection saturation current A/m2 1e-6 -
Idbjt Idbjt BJT injection saturation current A/m2 1e-6 -
isdif Isdif Body to source/drain injection saturation A/m2 1e-7 -
current
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Appendix B: Model Parameter List
Iddif Iddif Body to source/drain injection saturation A/m2 1e-7 -
current
isrec Isrec Recombination in depletion saturation A/m2 1e-5 -
current
Idrec Idrec Recombination in depletion saturation A/m2 1e-5 -
current
istun Istun Reverse tunneling saturation current A/m2 0.0 -
Idtun Idtun Reverse tunneling saturation current A/m2 0.0 -
Ln Ln Electron/hole diffusion length m 2e-6 -
Vrec0s Vrec0 Voltage dependent parameter for V 0 -
recombination current for source
Vrec0d Vrec0d Voltage dependent parameter for V Default -
recombination current for drain to its
source
value
Vtun0s Vtun0 Voltage dependent parameter for V 0 -
tunneling current for source
Vtun0d Vtun0d Voltage dependent parameter for V Default -
tunneling current for drain to its
source
value
Nbjt Nbjt Power coefficient of channel length - 1 -
dependency for bipolar current
Lbjt0 Lbjt0 Reference channel length for bipolar m 0.20e-6 -
current
Vabjt Vabjt Early voltage for bipolar current V 10 -
Aely Aely Channel length dependency of early V/m 0 -
voltage for bipolar current
Ahlis Ahli High level injection parameter for - 0 -
bipolar current for source
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Appendix B: Model Parameter List
Ahlid Ahlid High level injection parameter for - Default -
bipolar current for drain to its
source
value
Rbody Rbody Intrinsic body contact sheet resistance ohm/s 0.0 -
quare
Rbsh Rbsh Extrinsic body contact sheet resistance ohm/s 0.0 -
quare
Rsh rsh Source drain sheet resistance in ohm per ohm/s 0.0 -
square quare
Rhalo rhalo Body halo sheet resistance ohm/ 1e15 -
m
Rsw Rsw Zero bias lightly-doped source resistance per Ohm(u 50
unit width for RDSMOD=1 m)WR
Rdw Rdw Zero bias lightly-doped drain resistance per Ohm(u 50
WR
unit width for RDSMOD=1 m)
Rswmin Rswmin Lightly-doped source resistance per unit Ohm(u 0
WR
width at high Vgs and zero Vbs for m)
RDSMOD=1
Rdwmin Rdwmin Lightly-doped source resistance per unit Ohm(u 0
WR
width at high Vgs and zero Vbs for m)
RDSMOD=1
Dvtp0 Dvtp0 First parameter for Vth shift due to p m 0.0
ocket
Dvtp1 Dvtp1 Second parameter for Vth shift due to p v-1 0.0
ocket
Dvtp2 Dvtp2 Third parameter for Vth shift due to pocket v-1 0.0
Dvtp3 Dvtp3 Forth parameter for Vth shift due to pocket v-1 0.0
Dvtp4 Dvtp4 Fifth parameter for Vth shift due to pocket v-1 0.0
Pdits Pdits Coefficient for drain-induced Vth shifts v-1 1e-20
Pditsl Pditsl Length dependence of drain-induced Vt m-1 0
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Appendix B: Model Parameter List
h shifts
Pditsd Pditsd Vds dependence of drain-induced Vth shifts v-1 0
Fprout Fprout Effect of pocket implant on rout degradation V/m0.5 0.0
Minv Minv Vgsteff fitting parameter for moderate 0.0
inversion
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 79
Appendix B: Model Parameter List
B.4. Gate-to-body tunneling parameters
B.4. Gate-to-body tunneling parameters
Symbol Symbol used Description Unit Default
used in in SPICE
equation
IgMod igMod Gate current model selector - 0
Toxqm toxqm Oxide thickness for Igb calculation m Tox
Ntox ntox Power term of gate current - 1
Toxref toxref Target oxide thickness m 2.5e-9
g ebg Effective bandgap in gate current V 1.2
calculation
gb1 alphaGB1 First Vox dependent parameter for gate 1/V .35
current in inversion
gb1 betaGB1 Second Vox dependent parameter for 1/V2 .03
gate current in inversion
Vgb1 vgb1 Third Vox dependent parameter for V 300
gate current in inversion
VEVB vevb Vaux parameter for valence band - 0.075
electron tunneling
gb2 alphaGB2 First Vox dependent parameter for gate 1/V .43
current in accumulation
gb2 betaGB2 Second Vox dependent parameter for 1/V2 .05
gate current in accumulation
Vgb2 vgb2 ThirdVox dependent parameter for gate V 17
current in accumulation
VECB vecb Vaux parameter for conduction band - .026
electron tunneling
AIGBCP2 aigbcp2 First Vgp dependent parameter for gate 1/V2 0.043
current in accumulation in AGBCP2
region
BIGBCP2 bigbcp2 Second Vgp dependent parameter for 1/V2 0.0054
gate current in accumulation in
AGBCP2 region
CIGBCP2 cigbcp2 Third Vgp dependent parameter for 1/V2 0.0075
gate current in accumulation in
AGBCP2 region
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 80
Appendix B: Model Parameter List
B.5. AC and Capacitance Parameters
Symbol Symbol
used in used in Description Unit Default Notes (below
equation SPICE the table)
Xpart xpart Charge partitioning rate flag - 0
CGS0 cgso Non LDD region source-gate overlap F/m calcu- nC-1
capacitance per channel length lated
CGD0 cgdo Non LDD region drain-gate overlap F/m calcu- nC-2
capacitance per channel length lated
CGEO cgeo Gate substrate overlap capacitance per unit F/m 0.0 -
channel length
Cjswgs cjswg Source (gate side) sidewall junction -
capacitance per unit width (normalized to F/m2 1e-10
100nm Tsi)
Cjswgd cjswgd Drain (gate side) sidewall junction -
capacitance per unit width (normalized to F/m2 Default
100nm Tsi) to its
source
value
Pbswgs pbswg Source (gate side) sidewall junction V .7 -
capacitance buit in potential
Pbswgd pbswgd Drain (gate side) sidewall junction V Default -
capacitance buit in potential to its
source
value
Mjswgs mjswg Source (gate side) sidewall junction V 0.5 -
capacitance grading coefficient
Mjswgd mjswgd Drain (gate side) sidewall junction V Default -
capacitance grading coefficient to its
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 81
Appendix B: Model Parameter List
source
value
tt tt Diffusion capacitance transit time second 1e-12 -
coefficient
Ndif Ndif Power coefficient of channel length - -1 -
dependency for diffusion capacitance
Ldif0 Ldif0 Channel-length dependency coefficient of - 1 -
diffusion cap.
Vsdfb vsdfb Source/drain bottom diffusion capacitance V calcu- nC-3
flatband voltage lated
Vsdth vsdth Source/drain bottom diffusion capacitance V calcu- nC-4
threshold voltage lated
Csdmin csdmin Source/drain bottom diffusion minimum V calcu- nC-5
capacitance lated
Asd asd Source/drain bottom diffusion smoothing - 0.3 -
parameter
Csdesw csdesw Source/drain sidewall fringing capacitance F/m 0.0 -
per unit length
CGSl cgsl Light doped source-gate region overlap F/m 0.0 -
capacitance
CGDl cgdl Light doped drain-gate region overlap F/m 0.0 -
capacitance
CKAPPA ckappa Coefficient for lightly doped region F/m 0.6 -
overlap capacitance fringing field
capacitance
Cf cf Gate to source/drain fringing field F/m calcu- nC-6
capacitance lated
CLC clc Constant term for the short channel model m 0.1x10-7 -
CLE cle Exponential term for the short channel none 0.0 -
model
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Appendix B: Model Parameter List
DLC dlc Length offset fitting parameter for gate m lint -
charge
DLCB dlcb Length offset fitting parameter for body m 0 -
charge
DLBG dlbg Length offset fitting parameter for m 0.0 -
backgate charge
DWC dwc Width offset fitting parameter from C-V m wint -
DelVt delvt Threshold voltage adjust for C-V V 0.0 -
Fbody fbody Scaling factor for body charge - 1.0 -
acde acde Exponential coefficient for charge m/V 1.0 -
thickness in capMod=3 for accumulation
and depletion regions.
moin moin Coefficient for the gate-bias dependent V1/2 15.0 -
surface potential.
CfrCoeff cfrcoeff Sidewall fringe capacitance coefficient - 1 Max limit = 2
B.6. Temperature Parameters
Symbol Symbol
used in used in Description Unit Default Note
equation SPICE
Tnom tnom Temperature at which parameters are ºC 27 -
expected
te ute Mobility temperature exponent none -1.5 -
Kt1 kt1 Temperature coefficient for threshold V -0.11 -
voltage
Kt11 kt11 Channel length dependence of the V*m 0.0
temperature coefficient for threshold
voltage
Kt2 kt2 Body-bias coefficient of the Vth none 0.022 -
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Appendix B: Model Parameter List
temperature effect
Ua1 ua1 Temperature coefficient for Ua m/V 4.31e-9 -
Ub2 ub1 Temperature coefficient for Ub (m/V)2 -7.61e-18 -
Uc1 uc1 Temperature coefficient for Uc 1/V -.056 nT-1
At at Temperature coefficient for saturation m/sec 3.3e4 -
velocity
Tcijswgs tcjswg Temperature coefficient of Cjswgs 1/K 0 -
Tpbswgs tpbswg Temperature coefficient of Pbswgs V/K 0 -
Tcijswgd tcjswgd Temperature coefficient of Cjswgd 1/K Default to its -
source value
Tpbswgd tpbswgd Temperature coefficient of Pbswgd V/K Default to its -
source value
Cth0 cth0 Normalized thermal capacity (W*sec) 1e-5 -
/ mºC
Prt prt Temperature coefficient for Rdsw -m 0 -
Rth0 rth0 Normalized thermal resistance mºC/W 0 -
Ntrecf Ntrecf Temperature coefficient for Nrecf - 0 -
Ntrecr Ntrecr Temperature coefficient for Nrecr - 0 -
Xbjt xbjt Power dependence of jbjt on temperature - 1 -
Xdifs xdifs Power dependence of jdifs on temperature - Xbjt -
Xrecs xrecs Power dependence of jrecs on temperature - 1 -
Xtuns xtuns Power dependence of jtuns on temperature - 0 -
Xdifd xdifd Power dependence of jdifd on temperature - Xbjt -
Xrecd xrecd Power dependence of jrecd on temperature - 1 -
Xtund xtund Power dependence of jtund on temperature - 0 -
Wth0 Wth0 Minimum width for thermal resistance m 0 -
calculation
Tvbci tvbci Temperature coefficient for Vbci - 0
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Appendix B: Model Parameter List
B.7. BSIMSOI Built-In Potential Lowering (Vbi) Model Parameters
Symbol Symbol used Description Unit Default
used in in SPICE
equation
SoiMod soiMod SOI model selector. - 0
SoiMod=0: BSIMPD.
SoiMod=1: unified model for PD&FD.
SoiMod=2: ideal FD.
SoiMod=3: auto selection by BSIMSOI
Vnonideal vbsa Offset voltage due to non-idealities V 0
NOFF,FD nofffd Smoothing parameter in FD module - 1
VOFF,FD vofffd Smoothing parameter in FD module V 0
K1b K1b First backgate body effect parameter - 1
K2b K2b Second backgate body effect parameter - 0
for short channel effect
Dk2b dk2b Third backgate body effect parameter - 0
for short channel effect
Dvbd0 dvbd0 First short channel effect parameter in - 0
FD module
Dvbd1 dvbd1 Second short channel effect parameter - 0
in FD module
MoinFD moinfd Gate bias dependence coefficient of - 1e3
surface potential in FD module
Vbs0pd vbs0pd Upper bound of built-in potential V 0.0
lowering for BSIMPD operation
Vbs0fd vbs0fd Lowering bound of built-in potential V 0.5
lowering for ideal FD operation
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Appendix B: Model Parameter List
B.8. BSIMSOI RF Model Parameters
RgateMod rgateMod Gate resistance model selector - 0
rgateMod = 0 No gate resistance
rgateMod = 1 Constant gate resistance
rgateMod = 2 Rii model with
variable resistance
rgateMod = 3 Rii model with two
nodes
RbodyMod RbodyMod RbodyMod=0 No body resistance - 0
model
RbodyMod=1 Two-resistor body
resistance model
Rshg Rshg Gate electrode sheet resistance Ohm/s 0.1
quare
XRCRG1 xrcrg1 Parameter for distributed channel- - 12.0
resistance effect for intrinsic input
resistance
XRCRG2 xrcrg2 Parameter to account for the excess - 1.0
channel diffusion resistance for
intrinsic input resistance
NGCON ngcon Number of gate contacts - 1
XGW xgw Distance from the gate contact to the m 0.0
channel edge
XGL xgl Offset of the gate length due to m 0.0
variations in patterning
RBSB rbsb Resistance between sbNode and bNode Ohm 50.0
RBDB rbdb Resistance between dbNode and bNode Ohm 50.0
GBMIN gbmin Conductance parallel with RBSB/RBDB mho 1e-12
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Appendix B: Model Parameter List
B.9. BSIMSOI Noise Model Parameters
FnoiMod fnoiMod Flicker noise model selector - 1
TnoiMod TnoiMod Thermal noise model selector - 0
NTNOI ntnoi Noise factor for short-channel devices for - 1.0
TNOIMOD=0 or 2
TNOIA Tnoia Coefficient of channel length dependence of - 1.5
total channel thermal noise
TNOIB Tnoib Channel length dependence parameter for - 3.5
channel thermal noise partitioning
TNOIC Tnoic Length dependent parameter for - 3.5
Correlation Coefficient
RNOIC Rnoic Correlation Coefficient parameter - 0.395
RNOIA rnoia Thermal noise parameter - 0.577
RNOIB rnoib Thermal noise parameter - 0.37
W0FLK W0flk Flicker noise width dependence parameter - -1
BF bf Flicker noise length dependence exponent - 2.0
SCALEN SCALEN Correlated thermal noise scaling parameter 1e5
B.10. BSIMSOI Stress Model Parameters
SA sa Distance between OD edge to poly from one side m 0.0
(instance
parameter)
SB (instance sb Distance between OD edge to poly from another side m 0.0
parameter)
SD sd Distance between neighbouring fingers m 0.0
(instance
parameter)
SAREF saref Reference distance between OD and edge to poly of m 1e-6
one side
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Appendix B: Model Parameter List
SBREF sbref Reference distance between OD and edge to poly of m 1e-6
another side
WLOD Wlod Width parameter for stress effect M 0.0
KU0 Ku0 Mobility degradation/enhancement M 0.0
KVSAT Kvsat Saturation velocity degradation/enhancement M 0.0
parameter for stress effect
TKU0 TKU0 Temperature coefficient of KU0 0.0
LKU0 LKU0 Length dependence of KU0 0.0
WKU0 WKU0 width dependence of KU0 0.0
PKU0 PKU0 Cross-term dependence of KU0 0.0
LLODKU0 LLODKU0 Length parameter for u0 stress effect 0.0
WLODKU0 WLODKU Width parameter for u0 stress effect 0.0
0
KVTH0 KVTH0 Threshold shift parameter for stress effect Vm 0.0
LKVTH0 LKVTH0 Length dependence of KVHT0 0.0
WKVTH0 WKVTH0 Width dependence of KVHT0 0.0
PKVTH0 PKVTH0 Cross term dependence of KVHT0 0.0
LLODVTH Llodvth Length parameter for Vth stress effect 0.0
WLODVT Wlodvth Width parameter for Vth stress effect 0.0
H
STK2 Stk2 K2 shift factor related to Vth0 change M 0.0
LODK2 LODk2 K2 shift modification factor for stress effect 1.0
STETA0 Steta0 Eta0 shift factor related to vth0 change M 0.0
STETA0CV steta0cv Eta0CV shift factor related to vth0 change M STETA0
LODETA0 Lodeta0 Eta0 shift modification factor for stress effect 1.0
LODETA0CV lodeta0cv Eta0CV shift modification factor for stress effect LODETA0
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 88
Appendix B: Model Parameter List
B.11. New parameters added in BSIMSOIv4.5.0 corresponding to the various
material properties for mtrlMod=1
Description Default
Parameter
EGGBCP2 Bandgap in Agbcp2 region 1.12
EGGDEP Bandgap for gate depletion effect 1.12
AGB1 'A' for Igb1 Tunneling current model 3.7622E-07
BGB1 'B' for Igb1 Tunneling current model -3.1051E+10
AGB2 'A' for Igb2 Tunneling current model 4.9758E-07
BGB2 'B' for Igb2 Tunneling current model -2.357E+10
AGBC2N NMOS 'A' for tunneling current model 3.4254E-07
AGBC2P PMOS 'A' for tunneling current model 4.9723E-07
BGBC2N NMOS 'B' for tunneling current model 1.1665E+12
BGBC2P PMOS 'B' for tunneling current model 7.4567E+11
VTM00 Hard coded 25°C thermal voltage 0.026
B.12. Model Parameter Notes
nI-1. BSIMPD supports capmod=2 and 3 only. Capmod=0 and 1 are not supported.
nI-2. In modern SOI technology, source/drain extension or LDD are commonly used.
As a result, the source/drain junction depth (Xj) can be different from the silicon
film thickness (Tsi). By default, if Xj is not given, it is set to Tsi. Xj is not allowed
to be greater than Tsi.
nI-3. BSIMPD refers substrate to the silicon below buried oxide, not the well region in
BSIM3. It is used to calculate backgate flatband voltage (Vfbb) and parameters
related to source/drain diffusion bottom capacitance (Vsdth, Vsdfb, Csdmin). Positive
nsub means the same type of doping as the body and negative nsub means opposite
type of doping.
nC-1. If cgso is not given then it is calculated using:
if (dlc is given and is greater 0) then,
cgso = p1 = (dlc*cox) - cgs1
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Appendix B: Model Parameter List
if (the previously calculated cgso <0), then
cgso = 0
else cgso = 0.6 * Tsi * cox
nC-2. Cgdo is calculated in a way similar to Csdo
nC-3. If (nsub is positive)
kT 10 20 nsub
Vsdfb log 0.3
q ni ni
else
kT 10 20
Vsdfb log 0.3
q nsub
nC-4. If (nsub is positive)
kT nsub 5.753 10 12 nsub
sd 2 log , sd
q ni Cbox
Vsdth Vsdfb sd sd sd
else
kT nsub 5.753 10 12 nsub
sd 2 log sd
,
q ni Cbox
Vsdth Vsdfb sd sd sd
2 si sd si Csddep Cbox
nC-5. X sddep , Csddep , Csd min
q n sub 10 6 X sddep Csddep C box
nC-6. If cf is not given then it is calculated using
2 ox 4 10 7
CF ln 1
Tox
nT-1. For mobmod=1 and 2, the unit is m/V2. Default is -5.6E-11. For mobmod=3,
unit is 1/V and default is -0.056.
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 90
Appendix C: Equation List
Appendix C: Equation List
C1: Equation List for BSIMSOI Built-In Potential Lowering Calculation
If SoiMod=0 (default), the model equation is identical to BSIMPD equation.
If SoiMod=1 (unified model for PD&FD) or SoiMod=2 (ideal FD), the following equations (FD
module) are added on top of BSIMPD.
fdMod = 0
CSi qN CBOX
Vbi phi ch TSi 2 Vnonideal VDIBL e Ves VFBb
CSi CBOX 2 Si C Si C BOX
Si OX OX
where CSi , CBOX , COX
TSi TBOX TOX
Leff Leff
VDIBL Dvbd 0 exp Dvbd 1 2 exp Dvbd 1 Vbi 2 B
2l l
Leff L
e K 1b K 2b exp Dk 2b 2 exp Dk 2b eff
2l
l
fdMod = 1
Csi qN ch (1 Lpe 0 / Leff ) 2
Vbi Tsi Vnonideal
Csi CBOX CDSBS 2 Si
CBOX CDSBS
VbGS VFBb VSCE
Csi CBOX CDSBS Csi CBOX CDSBS
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Appendix C: Equation List
Leff Leff
VSCE DVBD0 exp DVBD1 2 exp DVBD1 Vds VSCE
2l l
C OX Vth ,FD V gs _ eff VOFF ,FD
phi phiON N OFF ,FDVt ln 1 exp
C OX C Si
1
C BOX
1 1
N OFF ,FDVt
V gsteff .FD V gsteff ,FD 2 K 1 2 B
phiON 2 B Vt ln 1
,
MoinFD K 1 Vt
2
V gs _ eff Vth ,FD VOFF ,FD
V gsteff ,FD N OFF ,FDVt ln 1 exp
N OFF ,FDVt
Here Nch is the channel doping concentration. VFBb is the backgate flatband voltage.
Vth,FD is the threshold voltage at Vbs=Vbs0(phi=2B). Vt is thermal voltage. K1 is the body effect
coefficient.
If SoiMod=1, the lower bound of Vbs (SPICE solution) is set to Vbs0. If SoiMod=2, Vbs is pinned
at Vbs0. Notice that there is no body node and body leakage/charge calculation in SoiMod=2.
The zero field body potential that will determine the transistor threshold voltage, Vbsmos, is then
calculated by
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Appendix C: Equation List
if Vbs Vbs 0 TOX
Vbs 0 TOX Vbs
CSi 2
Vbsmos Vbs
2qN chTSi
else
Vbsmos Vbs
The subsequent clamping of Vbsmos will use the same equation that utilized in BSIMPD.
If SoiMod=3 is specified, BSIMSOI will select the operation mode for the user based on the
estimated value of Vbs0 at phi=2B (bias independent), Vbs0t:
If Vbs0t > Vbs0fd, BSIMSOI will be in the ideal FD mode (SoiMod=2).
If Vbs0t < Vbs0pd, BSIMSOI will be in the BSIMPD mode (SoiMod=0).
Otherwise, BSIMSOI will be operated under SoiMod=1.
Notice that both Vbs0fd and Vbs0pd are model parameters.
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 93
Appendix C: Equation List
C2: Equation List for BSIMPD IV
Body Voltages
Vbsh is equal to the Vbs bounded between (Vbsc, s1 ). Vbsh is used in Vth and Abulk calculation
T1 Vbsc 0.5Vbs Vbsc Vbs Vbsc 2 4Vbsc , Vbsc 5V
Vbsh s1 0.5s1 T1 s1 T1 2 4T1 , s1 1.5V
Vbsh is further limited to 0.95 s to give Vbseff.
Vbseff s 0 0.5 s 0 Vbsh s 0 Vbsh 2 4Vbsh , s 0 0.95 s
Effective Channel Length and Width
Wl W W
dW ' Wint Wln
Wwwn Wln wl Wwn
L W L W
dW dW ' dWg Vgsteff dWb s Vbseff s
Ll L L
dL Lint Lln
Lwwn Lln wl Lwn
L W L W
Leff Ldrawn 2 dL
Weff Wdrawn N bc dWbc (2 N bc )dW
Weff ' Wdrawn N bc dWbc (2 N bc )dW '
Weff '
Wdiod Pdbcp
N seg
Weff '
Wdios Psbcp
N seg
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Appendix C: Equation List
Threshold Voltage
LPEB
Vth Vtho ( K1ox sqrtPhisExt K1eff s ) 1 K 2oxVbseff
Leff
LPE 0 T
K1ox ( 1 1) s ( K 3 K 3bVbseff ) ' ox s
Leff Weff Wo
Weff' Leff Weff' Leff
DVT 0 w (exp( DVT 1w ) 2 exp( DVT 1w ))(Vbi s )
2ltw ltw
Leff Leff
DVT 0 (exp( DVT 1 ) 2 exp( DVT 1 ))(Vbi s )
2lt lt
Leff Leff
(exp( Dsub ) 2 exp( Dsub ))( Etao EtabVbseff )Vds
2lto lto
Leff
nvt ln
Leff DVTP 0 (1 e DVTP1V
)
DS
DVTP 2
tanh( DVTP 4 Vds )
Leff DVTP 3
Note: The last term (DVTP2, DVTP3 and DVTP4) introduces the flexibility to capture DIBL
variation in longer channel. Considering backward compatibility, the old term (DVTP1 and
DVTP2) is kept.
lt si X dep / Cox (1 DVT 2Vbseff )
, s 2
1
sqrtPhisExt s Vbseff s Vbsh Vbseff
s s0
K
K1eff K1 1 ' 1w1
Weff K1w 2
TOX
K1ox K1eff
TOXM
TOX
K 2 ox K 2
TOXM
ltw si X dep Cox (1 DVT 2wVbseff ) lto si X dep 0 / Cox
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 95
Appendix C: Equation List
2 si ( s Vbseff ) 2 si s
X dep X dep 0
qN ch qN ch
N ch N DS
Vbi vt ln( )
ni 2
Poly depletion effect
ox Eox si E poly 2q si N gateV poly
2
1 qN gate X poly
V poly X poly E poly
2 2 si
V gs VFB x V poly Vox
a(Vgs VFB s Vpoly )2 Vpoly 0
2 ox
a
2q si N gateT 2 ox
q si Ngate T 2 ox 2 2ox (Vgs VFB s )
Vgs _eff VFB s 1 1
2 ox q si Ngate T 2 ox
Effective Vgst for all region (with Polysilicon Depletion Effect)
m *(Vgs _ eff Vth)
nvt ln[1 exp( )]
nvt
Vgsteff
2 s (1 m*)(Vgs _ eff Vth) Voff
m * nCox exp( )
q si N dep nvt
arctan(MINV)
m* 0.5
π
Leff Leff
(Cdsc Cdscd Vds Cdscb Vbseff )exp( DVT 1 ) 2 exp( DVT 1 )
si / X dep 2 lt lt Cit
n 1 N factor
Cox Cox Cox
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Appendix C: Equation List
Effective Bulk Charge Factor
2
K1ox 1 LPEB / Leff A0 Leff Leff B0
Abulk 1 1 A V
L 2 T X gs gsteff
Leff 2 Tsi X dep Weff' B1
2 (s Ketas)
Vbsh eff
si dep
1 Keta Vbsh
Abulk 0 Abulk Vgsteff 0
Mobility and Saturation Velocity
mtrlMod = 0
For Mobmod=1
o
eff
Vgsteff 2Vth Vgsteff 2Vth
1 (Ua Uc Vbseff )( ) Ub ( )2
Tox Tox
For Mobmod=2
o
eff
Vgsteff Vgsteff
1 (Ua Uc Vbseff )( ) Ub ( )2
Tox Tox
For Mobmod=3
0
eff
Vgstef 2Vth Vgsteff 2Vth
1 [Ua ( ) Ub ( )2 ](1 Uc Vbseff )
Tox Tox
For Mobmod=4
U0
eff
C VTH 0 VFB s
EU
V
1 UA UC Vbseff gsteff 0 TOXE UD
UCS
1 Vgsteff Vgsteff ,Vth
Vgsteff ,Vth Vgsteff Vgse Vth ,Vds Vbs 0
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Appendix C: Equation List
mtrlMod = 1
Vgsteff 2Vth 2 BSIM 4type ( PHIG EASUB Eg / 2 0.45) 3.9
Eeff
EOT EPSRSUB
For MobMod = 1
o
eff
1 (U a U cVbseff ) Eeff U b Eeff 2
For MobMod = 2
o
eff
Vgsteff U d Vgsteff U d
1 (U a U cVbseff )( ) Ub ( )2
Tox Tox
U d 2 BSIM 4type ( PHIG EASUB Eg / 2 0.45)
For MobMod = 3
0
eff
1 [U a Eeff U b Eeff 2 ](1 U cVbseff )
For MobMod = 4
U0
eff
C VTH 0 VFB s
EU
V
1 UA UC Vbseff gsteff 0 TOXE UD
UCS
1 Vgsteff Vgsteff ,Vth
Vgsteff ,Vth Vgsteff Vgse Vth ,Vds Vbs 0
Drain Saturation Voltage
For Rds0 or 1:
b b2 4ac
Vdsat
2a
1
a Abulk 2 Weff sat Cox Rds ( 1) Abulk
b (Vgsteff 2 t )( 1) Abulk Esat Leff 3 Abulk (Vgsteff 2 t )Weff sat Cox Rds
2
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 98
Appendix C: Equation List
c (Vgsteff 2 t )Esat Leff 2(Vgsteff 2 t )2 Weff sat Cox Rds
AV
1 gsteff A2
For Rds=0, =1:
Esat Leff (Vgsteff 2 t )
Vdsat
Abulk Esat Leff (Vgsteff 2 t )
2 sat
Esat
eff
Vdseff
Vdseff Vdsat
1
2
Vdsat Vds (Vdsat Vds ) 2 4Vdsat
Drain current expression
1 I ds 0 (Vdseff ) Vds Vdseff
I ds, MOSFET (1 )
N seg Rds Idso (Vdseff ) VA
1
Vdseff
Weff
eff Cox
Leff
Vdseff
Vgsteff 1 Abulk Vdseff
Idso
2 Vgsteff 2vt
Vdseff
1
Esat Leff
PvagV gsteff 1 1
V A V Asat 1 ( ) 1
Esat Leff V ACLM V ADIBLC
Abulk Esat Leff Vgsteff
VACLM (Vds Vdseff )
Pclm Abulk Esat litl
(Vgsteff 2 t ) Abulk Vdsat
VADIBLC (1 )
rout (1 PDIBLCBVbseff ) Abulk Vdsat 2 t
Leff Leff
rout PDIBLC1[exp( DROUT 2 exp( DROUT )] PDIBLC 2
2lt 0 lt 0
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 99
Appendix C: Equation List
Abulk Vdsat
Esat Leff Vdsat 2 Rds sat Cox Weff Vgsteff [1 ]
2(Vgsteff 2 t )
VAsat
2 / 1 Rds sat Cox Weff Abulk
siTox TSi
litl
ox
Drain/Source Resistance
• rdsMod = 0 (Bias Independent External Series Resistance, Bias Dependent Internal
Resistance)
(√ √ )
( )
( )
Rs = Rs,geo, Rd = Rd,geo
• rdsMod = 1 (External Rd(V) and Rs(V))
* +
( )
( )
( )
* +
( )
( )
( )
k BT N gate
Where, V fbsd ln 20 for NGATE larger than 0, otherwise, V fbsd 0 .
q 10
• rdsMod = 2 (Bias Dependent Internal Resistance, Rds(V))
(√ √ )
( )
( )
Where, The resistance Rs,geo and Rd,geo are simply calculated as the sheet resistance (RSH) times
the number of squares (NRS, NRD):
Rs,geo = NRS*RSH
Rd,geo = NRD*RSH
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 100
Appendix C: Equation List
Impact Ionization Current
Vdiff
Iii 0 ( I ds, MOSFET Fbjtii Ic ) exp
2
2 1Vdiff 0 Vdiff
Vdiff Vds Vdsatii
T L
Vdsatii VgsStep Vdsatii 0 1 Tii 1 ii
Tnom Leff
E satii Leff 1 S ii 0V gst
VgsStep S ii 2
1 E L 1 S V 1 S V
satii eff ii 1 gsteff iid ds
Gate-Induced-Drain-Leakage (GIDL)
gidlMod = 0
Vds Vgse EGIDL V fbsd 3 Toxe BGIDL Vdb3
I GIDL AGIDL Wdiod Nf exp
3 Toxe Vds Vgse EGIDL CGIDL Vdb3
Vds Vgse EGISL V fbsd 3 Toxe BGISL Vsb3
I GISL AGISL Wdios Nf exp
3 Toxe Vds Vgse EGISL CGISL Vsb3
gidlMod = 1
Vds RGIDL Vgse EGIDL V fbsd 3 Toxe BGIDL KGIDL
I gidl AGIDL Wdiod Nf exp exp
3 Toxe Vds Vgse EGIDL
Vbd FGIDL
Vds RGISL Vgse EGISL V fbsd 3 Toxe BGISL KGISL
I gisl AGISL Wdios Nf exp exp
3 Toxe Vds Vgse EGISL
Vbs FGISL
Here Vfbsd = 0 when mtrlMod = 0.
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 101
Appendix C: Equation List
Oxide tunneling current
In inversion,
J gb A
V gbVaux Toxref
N tox
exp
B α gb1 β gb1 Vox Tox
Tox2 Toxqm
1 Vox Vgb1
Vox φ g
Vaux VEVB ln 1 exp
VEVB
q3
A
8h b
8 2mox b3 2
B
3hq
b 4.2eV
mox 0.3m0
In accumulation,
J gb A
V gbVaux Toxref
N tox
exp
B α gb2 β gb2 Vox Tox
Tox2 Toxqm
1 Vox Vgb2
V gb V fb
Vaux VECBVt ln 1 exp
VECB
q3
A
8h b
8 2mox b3 2
B
3hq
b 3.1eV
mox 0.4m0
I g _ agbcp 2 A Aagbcp 2 min(Vgp V fb 2 , 0) Vgp _ eff ToxRatio
exp B Toxqm AIGBCP2 BIGBCP2 Vgp _ eff 1 CIGBCP2 V gp _ eff
V V fb 2 2 Vgp V fb 2
2
Vgp _ eff 0.5 gp
0.01
Body contact current
'
Weff N seg '
Weff N seg
|| R , R
Rbp Rbody
halo bodyext Rbsh N rb
Leff 2
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 102
Appendix C: Equation List
For 4-T device, I bp 0
For 5-T device,
Vbp
I bp
Rbp Rbodyext
Diode and BJT currents
Bipolar Transport Factor
Leff
2
bjt exp 0.5
Ln
Body-to-Source/drain diffusion
Vbs
I bs1 WdiosTsi jdifs exp 1
ndiodeVt
Vbd
I bd 1 Wdiod Tsi jdifd exp 1
ndiodedVt
Recombination/trap-assisted tunneling current in depletion region
Vbs Vrec0
I bs 2 WdiosTsi jrecs exp exp Vsb
0.026nrecf 0 . 026nrecr Vrec 0 V sb
Vbd Vdb Vrec0 d
I bd 2 Wdiod Tsi jrecd exp exp
0.026n
0. 026n V V
recfd recrd rec 0 d db
Reversed bias tunneling leakage
Vsb Vtun 0
I bs 4 WdiosTsi jtuns 1 exp
0.026ntun Vtun 0 Vsb
Vdb Vtun 0d
I bd 4 Wdiod Tsi jtund 1 exp
0.026ntund Vtun 0d Vdb
Recombination current in neutral body
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 103
Appendix C: Equation List
Vbs
I bs 3 1 bjt I en exp 1
1
ndiodeVt Ehli 1
Vbd
I bd 3 1 bjt I en exp 1
1
ndiodedVt Ehlid 1
N bjt
'
Weff 1 1
I ens Tsi jsbjt Lbjt 0
N seg Leff Ln
N bjt
'
Weff 1 1
I end Tsi jdbjt Lbjt 0
N seg Leff L n
Vbs
E hlis Ahli _ eff exp 1
diode t
n V
Vbd
E hlid Ahli _ eff exp 1
ndiodedVt
E g 300K T
Ahlis _ eff Ahli exp X bjt 1
ndiodeVt Tnom
E g 300K T
Ahlid _ eff Ahlid exp X bjt 1
ndiodedVt Tnom
BJT collector current
V V 1
I c bjt I en exp bs exp bd
ndiodesVt ndiodedVt E2 nd
Eely Eely 2 4 Ehli
E2 nd
2
Vbs Vbd
Eely 1
VAbjt Aely Leff
Ehli Ehlis Ehlid
Total body-source/drain current
I bs I bs1 Ibs 2 I bs 3 Ibs 4
Ibd Ibd1 Ibd 2 Ibd 3 Ibd 4
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 104
Appendix C: Equation List
Total body current
Iii + Idgidl + Isgisl + Igb - Ibs - Ibd - Ibp = 0
Temperature effects
Vth ( T ) Vth ( Tnom ) ( KT 1 Kt1l / Leff KT 2 Vbseff )(T / Tnom 1)
T te
o( T ) o( Tnom ) ( ) sat ( T ) sat ( Tnom ) AT (T / Tnom 1)
Tnom ,
T
Rdsw ( T ) Rdsw ( Tnom ) Prt ( 1)
Tnom
U a ( T ) U a ( Tnom ) U a1 (T / Tnom 1)
Ub ( T ) Ub ( Tnom ) Ub1 (T / Tnom 1)
Uc ( T ) Uc ( Tnom ) Uc1 (T / Tnom 1)
Rth0
'
Weff Wth0
Rth , C th C th0
W '
eff
Wth0 N seg N seg
E g (300K ) T
jsbjt isbjt exp X bjt 1
ndiodeVt Tnom
Eg (300 K ) T
jdbjt idbjt exp X bjt 1
ndiodedVt Tnom
E g (300 K ) T
jsdif i sdif exp X dif 1
ndiodeVt Tnom
E g (300 K ) T
jddif iddif exp X difd 1
ndiodedVt Tnom
E g (300 K ) T
jsrec isrec exp X rec 1
nrecf 0Vt Tnom
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 105
Appendix C: Equation List
E g (300K ) T
jdrec idrec exp X recd 1
nrecf 0dVt Tnom
T
jstun i stun exp X tun 1
Tnom
T
jdtun idtun exp X tund 1
Tnom
T
nrecfs nrecf 0 1 ntrecf 1
Tnom
T
nrecfd nrecf 0d 1 ntrecf 1
Tnom
T
nrecrs nrecr0 1 ntrecr 1
Tnom
T
nrecrd nrecr0d 1 ntrecr 1
Tnom
Eg is the energy gap energy.
Equation List for BSIMPD CV
Dimension Dependence
Wlc W W
Weff DWC Wln
Wwcwn Wln wlcWwn
L W L W
Llc L L
Leff DLC Lln
wcLwn
Lln wlcLwn
L W L W
Lactive Ldrawn 2Leff
LactiveB Lactive DLCB
LactiveBG LactiveB 2Lbg
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 106
Appendix C: Equation List
Wactive Wdrawn N bc dWbc ( 2 N bc )Weff
Wactive
WdiosCV Psbcp
N seg
Wactive
WdiodCV Pdbcp
N seg
Charge Conservation
QBf Qacc Qsub 0 Qsubs
Qinv Qinv , s Qinv , d
Qg Qinv QBf
Qb QBf Qe Q js Q jd
Qs Qinv , s Q js
Qd Qinv ,d Q jd
Qg Qe Qb Qs Qd 0
Intrinsic Charges
(1) capMod = 2
Front Gate Body Charge
Accumulation Charge
V fb Vgb
2
VFBeff V fb 0.5 V fb Vgb 2
where Vgb Vgs Vbseff
V fb Vth s K1eff s Vbseff delvt
W L
Qacc Fbody active activeB Agbcp Cox (VFBeff Vfb )
N seg
vgstcvMod = 0 and 1
V gs Vth delvt
V gsteffCV nvt ln 1 exp exp
nvt nvt
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 107
Appendix C: Equation List
vgstcvMod = 2
m*CV (Vgs _ eff Vth delvt )
nvt ln 1 exp( )
VgsteffCV nvt
2 s (1 m )(Vgs _ eff Vth delvt ) VoffCV
*
m*CV nCox exp( )
q si N dep nvt
arctan( MINVCV )
m*CV 0.5
Gate Induced Depletion Charge
Wactive LactiveB
1 1 4(Vgs VFBeff VgsteffCV Vbseff )
2
K1eff
Qsub0 Fbody
Agbcp Cox
N seg 2 2
K1eff
Drain Induced Depletion Charge
CLC CLE
VdsatCV VgsteffCV / AbulkCV , AbulkCV Abulk 0 1
LactiveB
1
VdsCV VdsatCV (VdsatCV Vds (VdsatCV Vds )2 4 VdsatCV )
2
W L V 2
Qsubs Fbody active activeB Agbcp K1eff Cox AbulkCV 1 dsCV
AbulkCV VdsCV
Nseg 2
12 VgsteffCV AbulkCV VdsCV 2
Back Gate Body Charge
W
Qe k b1 Fbody active activeBG Aebcp C box Ves V fbb Vbseff
L
N seg
Inversion Charge
Vcveff Vdsat ,CV 0.5 V4 V42 4 4 Vdsat ,CV whereV4 Vdsat ,CV Vds 4 ; 4 0.02
W L AbulkCV
2
AbulkCV Vcveff 2
Qinv active active Agbcp Cox VgsteffCV Vcveff
Nseg 2 A 2
12 VgsteffCV bulkCV Vcveff
2
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 108
Appendix C: Equation List
50/50 Charge Partition
Qinv,s Qinv,.d 0.5Qinv
40/60 Charge Partition
Wactive Lactive
Agbcp Cox
N seg V 4
2
2
2 3
Qinv,s 2 gsteffCV
3
VgsteffCV 2 AbulkCV Vcveff Vgsteff AbulkCV Vcveff AbulkCV Vcveff
A 3 3 15
2 VgsteffCV bulkCV Vcvefff
2
Wactive Lactive
Agbcp Cox
N seg V 5
1
2 3
Qinv,d 2 gsteffCV
3
VgsteffCV 2 AbulkCV Vcveff Vgsteff AbulkCV Vcveff AbulkCV Vcveff
A 3 5
2 VgsteffCV bulkCV Vcvefff
2
0/100 Charge Partition
Qinv ,s
Wactive Lactive Agbcp
Cox V gsteffCV
AbulkCV Vcveff
A bulkCV Vcveff 2
N seg 2 4 AbulkCV
24VgsteffCV Vcveff
2
Qinv ,d
Wactive Lactive Agbcp
Cox VgsteffCV 3 AbulkCV Vcveff
AbulkCV Vcveff
2
N seg 2 4 AbulkCV
8VgsteffCV Vcveff
2
(2) capMod = 3 (Charge-Thickness Model)
capMod = 3 only supports zero-bias flat band voltage, which is calculated from bias-independent
threshold voltage. This is different from capMod = 2. For the finite thickness ( X DC ) formulation,
refer to Chapter 4 of BSIM3v3.2 Users’s Manual.
Front Gate Body Charge
Accumulation Charge
V fb Vgb
2
VFBeff V fb 0.5 V fb Vgb 2
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 109
Appendix C: Equation List
where Vgb Vgs Vbseff
Vfb Vth s K1eff s Vbseff
W L
Qacc Fbody active activeB Agbcp Coxeff Vgbacc
N seg
Vgbacc 0.5 V0 V02 4V fb
V0 V fb Vbseff Vgs
Cox Ccen
Coxeff
Cox Ccen
Ccen Si X DC
Gate Induced Depletion Charge
Wactive LactiveB
1 1 4(Vgs VFBeff VgsteffCV Vbseff )
2
K1eff
Qsub0 Fbody
Agbcp Coxeff
N seg 2 2
K1eff
Drain Induced Depletion Charge
VdsatCV VgsteffCV / AbulkCV
VgsteffCV VgstefCV 2 K1eff 2 B
s 2 B vt ln 1
moinK1eff vt2
1
VdsCV VdsatCV (VdsatCV Vds (VdsatCV Vds )2 4 VdsatCV )
2
W L V 2
Qsubs Fbody active activeB Agbcp K1eff Coxeff AbulkCV 1 dsCV
AbulkCV VdsCV
N seg
2 12VgsteffCV AbulkCV VdsCV 2
Back Gate Body Charge
W
Qe k b1 Fbody active activeBG Aebcp C box Ves V fbb Vbseff
L
N seg
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 110
Appendix C: Equation List
Inversion Charge
Vcveff Vdsat ,CV 0.5V4 V42 4 4Vdsat ,CV whereV 4 Vdsat ,CV Vds 4 ; 4 0.02
WactiveLactive A A
2
V
2
Qinv Agbcp C oxeff V gsteffCV bulkCV Vcveff
bulkCV cveff
N seg 2 2
12V gsteffCV
A
Vcveff
bulkCV
2
50/50 Charge Partition
Qinv,s Qinv,.d 0.5Qinv
40/60 Charge Partition
Wactive Lactive
Agbcp C oxeff
V gsteffCV 3 4 V gsteffCV 2 AbulkCV Vcveff 2 V gsteff AbulkCV Vcveff 2 2 AbulkCV Vcveff 3
N seg
Qinv , s 2
A 3 3 15
2V gsteffCV bulkCV Vcvefff
2
Wactive Lactive
Agbcp C oxef
N
Qinv ,d seg
2
V gsteffCV 3 5 V gsteffCV 2 AbulkCV Vcveff V gstefCVf AbulkCV Vcveff 2 1 AbulkCV Vcveff 3
A 3 5
2V gsteffCV bulkCV Vcvefff
2
0/100 Charge Partition
Wactive Lactive Agbcp 2
Coxeff
V A V A V
Qinv , s
gsteffCV bulkCV cveff bulkCV cveff
N seg 2 4 AbulkCV
24V gsteffCV Vcveff
2
Qinv ,d
Wactive Lactive Agbcp
Coxeff V gsteffCV 3 AbulkCV Vcveff
AbulkCV Vcveff
2
N seg 2 4 AbulkCV
8V gsteffCV Vcveff
2
Overlap Capacitance
Source Overlap Charge
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 111
Appendix C: Equation List
1
V 4
2
Vgs _ overlap Vgs
2
gs
Qoverlap, s CKAPPA 4V gs _ overlap
CGS 0 V gs CGS1V gs V gs _ overlap 1 1
WdiosCV 2 CKAPPA
Drain Overlap Charge
1
Vgd
2
Vgd _ overlap Vgd 4
2
CKAPPA 4Vgd _ overlap
Qoverlap,d
CGD0 Vgd CGD1Vgd Vgd _ overlap 1 1
WdiodCV 2 CKAPPA
Gate Overlap Charge
Qoverlap, g Qoverlap,s Qoverlap,d
Source/Drain Junction Charge
For Vbs < 0.95 s
else
Q jswg Cbsdep (0.95s )Vbs 0.95s Qbsdif
For Vbd < 0.95 s
else
Q jdwg Cbddep 0.95s Vbd 0.95s Qbddif
where
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 112
Appendix C: Equation List
Pbswgs
1 M jswgs
T
Qbsdep WdioCV C jswgs si7 1 1 Vbs
10 1 M jswgs Pbswgs
Pbswgd
1 M jswgd
T
Qbddep WdioCV C jswgd si7 1 1 Vbd
10 1 M jswgd Pbswgd
C jswgs C jswgs 0 1 t cjswgs T Tnom
C jswgd C jswgd 0 1 tT Tnom
cjswgd
Pbswgs Pbswgs 0 t pbswgs T Tnom
Pbswgd Pbswgd 0 t pbswgd T Tnom
Weff ' 1
N dif
V
1 1
Qbsdif Tsi J sbjt 1 Ldif 0 Lbj 0 exp bs 1
Leff Ln
N seg
ndiosVt Ehlis 1
Weff ' 1
N dif
V
1 1
Qbddif Tsi J dbjt 1 Ldif 0 Lbj 0 exp bd 1
N seg
Leff Ln ndiodVt Ehlid 1
Extrinsic Capacitance
Bottom S/D to Substrate Capacitance (per unit area)
Cbox if Vs / d ,e Vsdfb
2
Vs / d ,e Vsdfb
box A
C
1
C box C
min
elseif
Vs / d ,e Vsdfb Asd Vsdth Vsdfb
Cesb
sd Vsdth Vsdfb
2
V V
Cmin
1
Cbox Cmin s / d ,e sdth elseif Vs / d ,e Vsdth
1 Asd Vsdth Vsdfb
Cmin else
Sidewall S/D to Substrate Capacitance (per unit length)
T
Cs / d ,esw Csdesw log1 si
Tbox
Finite Thickness Formulation
When capMod = 3, the finite thickness model is selected.
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 113
Appendix C: Equation List
mtrlMod = 0
Coxp Ccen
Coxeff
Coxp Ccen
Ccen si / X DC
(i) XDC for accumulation and depletion
1 NDEP
0.25
Vgse Vbseff VFBeff
X DC Ldebye exp ACDE 16
3 2 10 TOXP
For numerical stability,
X DC X max
1
2
X 0 X 02 4 x X max
X 0 X max X DC x
(ii) XDC of inversion charge
ADOS 1.9 109 m
X DC 0.7 BDOS
V 4 VTH 0 VFB s
1 gsteff
2TOXP
(iii) Body charge thickness in inversion
VgsteffCV (VgsteffCV 2K1ox 2 B
s 2 B t ln 1
MOIN K1ox 2 t
qinv Coxeff Vgsteff ,CV
eff
mtrlMod = 1
In this case, TOXP has to be calculated first:
3.9
TOXP EOT X DC V VDDEOT ,V V 0
EPSRSUB gs ds bs
Then, other procedures are same in mtrlMod = 0.
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 114
Appendix D: Parameter Extraction
Appendix D: Parameter Extraction
D.1. Extraction Strategy
The complicated physics in SOI MOSFETs makes parameter extraction quite involved [20].
It is always preferable to have more measurements so that the parameters extracted can have
more valid physical meaning. Similar to conventional bulk devices, two basic extraction
strategies can be used: single device extraction, and group device extraction. The group device
extraction is more popular because of several reasons. In analog circuit, channel length and
width scalability is very important. In digital circuit, statistical modeling is often used to predict
the circuit performance due to process variation. Hence channel length scalability is also
important. Besides, model parameters extracted from group device extraction have better
physical meaning than that from single device extraction. In this work, we shall emphasize on
group device extraction.
Parameter extraction using body contact devices is highly recommended because parameters
related to body effect, impact ionization and leakage currents can be directly extracted [18, 19].
This yields less ambiguity in extracting technology parameters for I-V fitting purposes. In the
followings, we suggest a set of measurement suitable for PD devices.
D.2. Suggested I-V Measurement
Measurement set A is used to extract basic MOS I-V parameters. For each body-contacted
device :
(A1) Ids vs. Vgs @ small Vds with different Vbs, Ves=0V.
(A2) Ids vs. Vgs @ Vds=Vdd with different Vbs, Ves=0V.
(A3) Ids vs. Vds with different Vgs and different Vbs, Ves=0V.
Parameters extracted include threshold voltage, body coefficient, delta L and W, series
resistance, mobility, short channel effect, and subthreshold swing. (A2) is used to extract DIBL
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 115
Appendix D: Parameter Extraction
parameters at subthreshold. (A3) is used to extract saturation velocity, body charge effect, output
resistance, body contact resistance and self-heating parameters.
Measurement set C is used to extract impact ionization current parameters. For each body-
contacted device :
(C1) Ib vs. Vgs @ different Vds, Vbs=0V, Ves=0V.
(C2) Ib vs. Vds @ different Vgs, Vbs=0V, Ves=0V.
Measurement set D is used to extract MOS temperature dependent parameter. For a long
channel body-contacted device:
(D1) Ids vs. Vgs @ small Vds, Vbs=0V, Ves=0V, repeat with several temperatures.
(D2) Ids vs. Vds @ different Vgs, Vbs=0V, Ves=0V, repeat with several temperatures.
Notice that the self-heating parameters have to be extracted from set A.
Measurement set E is used to extract diode parameters. For a long channel body-contacted
device or gated diode :
(E1) Idiode vs. Vbs @ Vgs=-1V, Ves=0V, repeat with several temperature
Measurement set F is used to extract BJT parameters. For each body-contacted device:
(F1) Ids vs. Ib @ Vgs=-1V, Ves=0V, Vds=1V.
Measurement set G is used to verify the floating body device data. For each floating-body
device :
(G1) Ids vs. Vgs @ small Vds.
(G2) Ids vs. Vgs @ Vds=Vdd.
(G3) Ids vs. Vds @ different Vgs.
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 116
Appendix E: Model Parameter Binning
Appendix E: Model Parameter Binning
Below is the information on parameter binning regarding which model parameters can or cannot
be binned. All those parameters which can be binned follow this implementation:
P P PP
P P0 L W
Leff Weff Leff Weff
For example, for the parameter k1: P0 = k1, PL = lk1, PW = wk1, PP = pk1. binUnit is a bining unit
selector. If binUnit = 1, the units of Leff and Weff used in the binning equation above have the units
of microns; otherwise in meters.
For example, for a device with Leff = 0.5m and Weff = 10m. If binUnit = 1, the parameter values
for vsat are 1e5, 1e4, 2e4, and 3e4 for vsat, lvsat, wvsat, and pvsat, respectively. Therefore, the
effective value of vsat for this device is
vsat = 1e5 + 1e4/0.5 + 2e4/10 + 3e4/(0.5*10) = 1.28e5
To get the same effective value of vsat for binUnit = 0, the values of vsat, lvsat, wvsat, and pvsat
would be 1e5, 1e-2, 2e-2, 3e-8, respectively. Thus,
vsat = 1e5 + 1e-2/0.5e-6 + 2e-2/10e-6 + 3e-8/(0.5e-6 * 10e-6) = 1.28e5
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 117
Appendix E: Model Parameter Binning
Model parameters that have been binned in B4SOI are listed as follows:
E.1. DC Parameters
Symbol Symbol
used in used in Description
equation SPICE
Vth0 vth0 Threshold voltage @Vbs=0 for long and wide device
K1 k1 First order body effect coefficient
K1w1 k1w1 First body effect width dependent parameter
K1w2 k1w2 Second body effect width dependent parameter
K2 k2 Second order body effect coefficient
K3 k3 Narrow width coefficient
K3b k3b Body effect coefficient of k3
Kb1 Kb1 Backgate body charge coefficient
W0 w0 Narrow width parameter
NLX nlx Lateral non-uniform doping parameter
Dvt0 Dvt0 first coefficient of short-channel effect on Vth
Dvt1 dvt1 Second coefficient of short-channel effect on Vth
Dvt2 dvt2 Body-bias coefficient of short-channel effect on Vth
Dvt0w dvt0w first coefficient of narrow width effect on Vth for small channel length
Dvt1w dvt1w Second coefficient of narrow width effect on Vth for small channel
length
Dvt2w dvt2w Body-bias coefficient of narrow width effect on Vth for small channel
length
0 u0 Mobility at Temp = Tnom
Ua ua First-order mobility degradation coefficient
Ub ub Second-order mobility degradation coefficient
Uc uc Body-effect of mobility degradation coefficient
vsat vsat Saturation velocity at Temp=Tnom
A0 a0 Bulk charge effect coefficient for channel length
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 118
Appendix E: Model Parameter Binning
Ags ags Gate bias coefficient of Abulk
B0 b0 Bulk charge effect coefficient for channel width
B1 b1 Bulk charge effect width offset
Keta keta Body-bias coefficient of bulk charge effect
Ketas Ketas Surface potential adjustment for bulk charge effect
A1 A1 First non-saturation effect parameter
A2 A2 Second non-saturation effect parameter
Rdsw rdsw Parasitic resistance per unit width
Prwb prwb Body effect coefficient of Rdsw
Prwg prwg Gate bias effect coefficient of Rdsw
Wr wr Width offset from Weff for Rds calculation
Nfactor nfactor Subthreshold swing factor
Wint wint Width offset fitting parameter from I-V without bias
Lint lint Length offset fitting parameter from I-V without bias
DWg dwg Coefficient of Weff’s gate dependence
DWb dwb Coefficient of Weff’s substrate body bias dependence
Voff voff Offset voltage in the subthreshold region for large W and L
Eta0 eta0 DIBL coefficient in subthreshold region
Etab etab Body-bias coefficient for the subthreshold DIBL effect
EtabCV etabcv Body-bias coefficient for the subthreshold DIBL effect for CV
Dsub dsub DIBL coefficient exponent
Cit cit Interface trap capacitance
Cdsc cdsc Drain/Source to channel coupling capacitance
Cdscb cdscb Body-bias sensitivty of Cdsc
Cdscd cdscd Drain-bias sensitivty of Cdsc
Pclm pclm Channel length modulation parameter
Pdibl1 pdibl1 First output resistance DIBL effect correction parameter
Pdibl2 pdibl2 Second output resistance DIBL effect correction parameter
Drout drout L dependence coefficient of the DIBL correction parameter in Rout
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 119
Appendix E: Model Parameter Binning
Pvag pvag Gate dependence of Early voltage
delta Effective Vds parameter
0 alpha0 The first parameter of impact ionization current
Fbjtii fbjtii Fraction of bipolar current affecting the impact ionization
0 beta0 First Vds dependent parameter of impact ionization current
1 beta1 Second Vds dependent parameter of impact ionization current
2 beta2 Third Vds dependent parameter of impact ionization current
Vdsatii0 vdsatii0 Nominal drain saturation voltage at threshold for impact ionization
current
Tii tii Temperature dependent parameter for impact ionization current
Lii lii Channel length dependent parameter at threshold for impact ionization
current
Esatii esatii Saturation channel electric field for impact ionization current
Sii0 sii0 First Vgs dependent parameter for impact ionization current
Sii1 sii1 Second Vgs dependent parameter for impact ionization current
Sii2 sii2 Third Vgs dependent parameter for impact ionization current
Siid siid Vds dependent parameter of drain saturation voltage for impact
ionization current
gidl Agidl GIDL constant
gidl Bgidl GIDL exponential coefficient
Ngidl GIDL Vds enhancement coefficient
ntun Ntun Reverse tunneling non-ideality factor
ndiode Ndiode Diode non-ideality factor
nrecf0 Nrecf0 Recombination non-ideality factor at forward bias
nrecr0 Nrecr0 Recombination non-ideality factor at reversed bias
isbjt Isbjt BJT injection saturation current
isdif Isdif Body to source/drain injection saturation current
isrec Isrec Recombination in depletion saturation current
istun Istun Reverse tunneling saturation current
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 120
Appendix E: Model Parameter Binning
Vrec0 Vrec0 Voltage dependent parameter for recombination current
Vtun0 Vtun0 Voltage dependent parameter for tunneling current
Nbjt Nbjt Power coefficient of channel length dependency for bipolar current
Lbjt0 Lbjt0 Reference channel length for bipolar current
Vabjt Vabjt Early voltage for bipolar current
Aely Aely Channel length dependency of early voltage for bipolar current
Ahli Ahli High level injection parameter for bipolar current
Vbsa vbsa "vbsa offset voltage"
Vsce vsce SCE parameter for improved dVbi model
Cdsbs cdsbs coupling from Vd to Vbs for improved dVbi model
Vofffd vofffd smoothing parameter in FD module
Nofffd nofffd smoothing parameter in FD module
Moinfd moinfd Coefficient for the gate-bias dependent surface potential in FD
K1b k1b First backgate body effect parameter
K2b k2b Second backgate body effect parameter
Dk2b dk2b Third backgate body effect parameter for short channel effect
Dvbd0 dvbd0 First short-channel effect parameter in FD module
Dvbd1 dvbd1 Second short-channel effect parameter in FD module
Vbs0pd vbs0pd Upper bound of built-in potential lowering for PD operation
Vbs0fd vbs0fd Lower bound of built-in potential lowering for PD operation
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 121
Appendix E: Model Parameter Binning
E.2. AC and Capacitance Parameters
Symbol Symbol
used in used in Description
equation SPICE
Vsdfb vsdfb Source/drain bottom diffusion capacitance flatband voltage
Vsdth vsdth Source/drain bottom diffusion capacitance threshold voltage
DelVt delvt Threshold voltage adjust for C-V
acde acde Exponential coefficient for charge thickness in capMod=3 for
accumulation and depletion regions.
moin moin Coefficient for the gate-bias dependent surface potential.
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 122
References
References
[1] Y. Cheng, M. C. Jeng, Z. H. Liu, J. Huang M. Chan, P. K. Ko, and C. Hu, “A Physical and
Scalable I-V Model in BSIM3v3 for Analog/Digital Circuit Simulation”, IEEE Trans. On Elec.
Dev., vol. 42, p. 2, Feb 1997.
[2] BSIM3SOIv1.3 Users’ Manual, UC Berkeley, Department of EECS.
[3] W. Jin, P. C. H. Chan, S. K. H. Fung, P. K. Ko, “A Physically-Based Low-Frequency Noise Model
for NFD SOI MOSFET’s”, IEEE Intl. SOI conf., pp. 23-24, 1998.
[4] BSIM3v3.2 Users’ Manual, UC Berkeley, Department of EECS.
[5] D. Suh, J. G. Fossum, “A physical charge-based model for non-fully depleted SOI MOSFET’s and
its use in assessing floating-body effects in SOI CMOS circuits”, IEEE Tran. on Electron Devices,
vol. 42, no. 4, pp. 728-37, April 1995.
[6] M. S. L. Lee, W. Redman-White, B. M. Tenbroek, M. Robinson, “Modelling of thin film SOI
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conf., pp. 150-151, 1993.
[7] D. Sinitsky, S. Tang, A. Jangity, F. Assaderaghi, G. Shahidi, C. Hu, “Simulation of SOI Devices
and Circuits using BSIM3SOI”, IEEE Electron Device Letters, vol. 19, no. 9, pp. 323-325,
September 1998.
[8] G. S. Gildenblat, VLSI Electronics: Microstructure Science, p. 11, vol. 18, 1989.
[9] M. C. Jeng, “Design and Modeling of Deep-Submicrometer MOSFETs”, Ph. D. Dissertation, UC
Berkeley.
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References
[10] D. Sinitsky, S. Fung, S. Tang, P. Su, M. Chan, P. Ko, C. Hu, “A Dynamic Depletion SOI MOSFET
Model for SPICE”, in Dig. Tech. Papers, Symp. VLSI Technology, 1998.
[11] D. Sinitsky, R. Tu, C. Liang, M. Chan, J. Bokor and C. Hu, “AC output conductance of SOI
MOSFETs and impact on analog applications”, IEEE Electron Device Letters, vol.18, no.2, pp. 36-
38, Feb 1997.
[12] T. Y. Chan, P. K. Ko and C. Hu, “A Simple Method to Characterize Substrate Current in
MOSFETs”, IEEE Electron Dev. Letts., EDL-5, Dec 1984, p. 505.
[13] S. A. Parke, J. E. Moon, H. C. Wann, P. K. Ko and C. Hu, “Design for suppression of gate-induced
drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model”, IEEE Trans.
On Electron Device, vol. 39, no. 7, pp. 1697-703, July 1992.
[14] J. Gautier and J. Y.-C. Sun, “On the transient operation of partially depleted SOI NMOSFET’s”,
IEEE Electron device letters, vol.16, no.11, pp. 497-499, Nov 1995.
[15] L. T. Su, D. A. Antoniadis, M. I. Flik, J. E. Chung, “Measurement and modeling of self- heating
effects in SOI nMOSFETs”, IEDM tech. Digest, pp. 357-360, 1994.
[16] R. H. Tu, C. Wann, J. C. King, P. K. Ko, C. Hu, “An AC Conductance Technique for Measuring
Self-Heating in SOI MOSFET’s”, IEEE Electron device letters, vol.16, no.2, pp. 67-69, Feb. 1995.
[17] P. Su, S. K. H. Fung, F. Assaderaghi, C. Hu, “A Body-Contact SOI MOSFET Model for Circuit
Simulation”, Proceedings of the 1999 IEEE Intl. SOI Conference, pp.50-51.
[18] P. Su, S. K. H. Fung, S. Tang, F. Assaderaghi and C. Hu, "BSIMPD: A Partial-Depletion SOI
MOSFET Model for Deep-Submicron CMOS Designs", Proceedings of the IEEE 2000 Custom
Integrated Circuits Conference, pp.197-200.
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 124
References
[19] H. Nakayama, P. Su , C. Hu, M. Nakamura, H. Komatsu, K. Takeshita, Y. Komatsu, “Methodology
of Self-Heating Free Parameter Extraction and Circuit Simulation for SOI CMOS”, Proceedings of
the IEEE 2001 Custom Integrated Circuits Conference, pp.381-384.
[20] P. Su, “An International Standard Model for SOI Circuit Design,” Ph. D. Dissertation, Department
of EECS, University of California at Berkeley, December 2002.
(http://www.eecs.berkeley.edu/~pinsu)
[21] http://www.eigroup.org/cmc
[22] P. Su, S. Fung, H. Wan, A. Niknejad, M. Chan and C. Hu, "An impact ionization model for SOI
circuit simulation," 2002 IEEE International SOI Conference Proceedings, Williamsburg, VA,
Oct. 2002, pp. 201-202.
[23] P. Su, K. Goto, T. Sugii and C. Hu, "A thermal activation view of low voltage impact ionization
in MOSFETs," IEEE Electron Device Letters, vol. 23, no. 9, September 2002.
[24] P. Su, K. Goto, T. Sugii and C. Hu, "Enhanced substrate current in SOI MOSFETs," IEEE
Electron Device Letters, vol. 23, no. 5, pp. 282-284, May 2002.
[25] P. Su et al., “On the body-source built-in potential lowering of SOI MOSFETs,” IEEE Electron
Device Letters, February 2003.
[26] BSIMSOI3.2 Users’ Manual, UC Berkeley, Department of EECS.
[27] BSIM4.5.0 Users’ Manual, UC Berkeley, Department of EECS.
[28] H. Wan, P. Su, S.K.H. Fung, C.L. Chen, P.W. Wyatt, A.M. Niknejad, C. Hu, “RF Modeling for
FDSOI MOSFET and Self Heating Effect on RF Parameter Extraction”, Eighth International Conference
on Modeling and Simulation of Microsystems, May 2005.
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 125
References
[29] K.W. Su, K.H. Chen, T.X. Chung, et. al, “Modeling Isolation-induced Mechanical Stress
Effect on SO1 MOS Devices”, IEEE International SOI conference Proceedings, pp 80-82, 2003.
[30] Xuemei Xi, Fei Li, Bogdan Tudor, Wenyuan Wang, Weidong Liu, Frank Lee, Ping Wang, Niraj
Subba, Jung-Suk Goo, “An Improved Impact Ionization Model for SOI Circuit Simulation”, Eleventh
International Conference on Modeling and Simulation of Microsystems, June 2008.
BSIMSOIv4.6.0 Manual Copyright © 2017, UC Berkeley Page 126
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