558 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO.

4, AUGUST 1987

BSIM: Berkeley Short-Channel IGFET

Model for MOS Transistors
BING J. SHEU, MEMBER, IEEE, DONALD L. SCHARFETTER, FELLOW, IEEE, PING-KEUNG KO, MEMBER, IEEE,
AND MIN-CHIE JENG

Afsstract —The Berkeley Short-chmsnel IGFET Model (BSIM), an ac- only as accurate as the models used. In the past, the
curate and computatfonally efficient MOS transistor model, and its associ- SPICE2 program has provided three built-in MOS tran-
ated characterization facility for advanced integrated-circuit design are
sistor models [6]. The Level-1 model, which contains fairly
described. Both the strong-inversion aud weak-inversion components of the
drain-current expression are included. In order to speed up the circnit-
simple expressions, is most suitable for preliminary analy-
simulation execution time, the dependence of the drain current on the sis. The Level-2 model, which contains expressions from
substrate bias has been modeled with a uumerical approximation. This detailed device physics, does not work well for small-
approximation also simplifies tfre transistor terminal charge expressions. geometry transistors. The Level-3 model represents an
The charge model was derived from its drain-cument counterpart to
attempt to pursue the semi-empirical modeling approach,
preserve consistency of device physics. Charge conservation is guaranteed
in this model.
which only approximates device physics and relies on the
The model parameters are extracted by an automated parmneter-extrac- proper choice of the empirical parameters to accurately
tion program. Use of this model to analyze device characteristics from reproduce device characteristics.
several NMOS and CMOS processes has resulted in good agreement Many articles on MOS transistor modeling have ap-
between measured and modeled results for transistors with effective chan-
peared in the literature [7]–[16] and efforts to model ever
nel lengths as smafl as 1 pm. Enhancements for submicrometer applica-
tions have been pointed out.
smaller and more complex MOS transistors continue at a
rapid pace. MOS transistor models widely used in circuit
analysis are essentially semi-empirical in nature. Terms
I. INTRODUCTION with strong physical meaning are employed to model the
fundamental physical effects while parameters are judi-

C OMPUTER-AIDED
pensable in integrated-circuit
Program with Integrated
design tools have become indis-
design. The Simulation
Circuit Emphasis (SPICE) pro-
ciously introduced
This approach
especially
to embrace subtle device characteristics.
serves best for circuit-analysis
as two- and three-dimensional
purposes
small-geometry
gram [1] has been widely accepted for circuit analysis since
effects become more important.
its introduction a decade ago. Circuit-simulation execution
In this paper, the development of a simple and accurate
time has been substantially reduced through algorithm
short-channel MOS transistor model, the Berkeley Short-
improvement and hardware enhancements in the past few
channel IGFET Model (BSIM), and its associated char-
years. Novel circuit-simulation algorithms, such as the
acterization facility for advanced integrated-circuit design
iterated-timing-analysis method [2] and the waveform-
are described. The BSIM builds upon AT&T Bell Labora-
relaxation method [3], promise to offer more than an order
tories’ CSIM with substantial enhancements [17] -[19]. The
of magnitude speed-up as compared with the conventional
characterization facility includes a fully automated param-
circuit simulator SPICE2. The dedicated-hardware ap-
eter-extraction program and implementation of the com-
proach, such as multiprocessor-based simulation schemes
plete model, which includes expressions for dc and capaci-
[4], [5], also drastically reduces the circuit-simulation time.
tance characteristics and extrinsic components, in SPICE2.
Device modeling plays an important role in VLSI circuit
Since a fully device-physics-oriented modeling approach
design because computer-aided circuit analysis results are
usually makes parameter extraction particularly difficult,
the semi-empirical approach was adopted in developing
BSIM to cope with the rapid advances of technologies and
Manuscript received July 18, 1986; revised February 27, 1987. This
to make automated parameter extraction possible. An ana-
work was supported by the Semiconductor Research Corporation.
B. J. Sheu was with the Department of ElectncaJ Engineenng and lytical representation with 17 electrical parameters per
Computer Sciences, University of California, Berkeley, CA 94720. He is
device size was found to be adequate for modeling the dc
now with the Department of Electrical Engineering and Information
Sciences Institute, University of Southern California, Los Angeles, CA characteristics. The parameter-extraction program gener-
90089.
ates a process file which contains a set of parameter values
D. L. Scharfetter was with the Department of Electrical Engineering
and Computer Sciences, University of California, Berkeley, CA 94720. He for circuit analysis. Circuit designers need only describe
is now with Automated Characterization Systems Inc., Cupertino, CA
the layout geometries of transistors and parasitic elements
95014.
P.-K. Ko and M.-C. Jeng are with the Department of Electrical to execute circuit simulation. Use of BSIM to analyze
Engineering and Computer Sciences, University of California, Berkeley,
device characteristics from several NMOS and CMOS
CA 94720.
IEEE Log Number 8714877. processes has resulted in good agreement between mea-

001 8-9200/87/0800-0558$01.00 01987 IEEE

SHEUet a[.: BERKELEY
SHORT-CHANNEL
IGFETMODELFORMOSTRANSISTORS 559

sured and modeled results with effective channel lengths 2. Triode Region [VGs > ~h and !3 < V,~ < VDsAT]:
down to 1 pm.

lDS= [I+uoo:s-v h)]

II. THE BSIM FORMULATION
w
The formulation of BSIM is based on the device physics
“XL (VG. –K, )VD. –;V;. (3)
of small-geometry MOS transistors. Special effects in- U1 ( )
cluded are: DS
“(l’= L )
a) vertical field dependence of carrier mobility;
where
b) carrier velocity saturation;
c) drain-induced barrier lowering; gK1
d) depletion charge sharing by the drain and the source; a=l+ (4)
2/=
e) nonuniform doping for ion-implanted devices;
f) channel-length modulation;
and
g) subthresholcl conduction; and
h) geometric dependencies. 1
g=l– (5)
The eight drain-current parameters which directly ap- 1.744 +0.8364(+s – VBs) “
pear in the threshold-voltage and drain-current expressions
3. Saturation Region [ VGs > ~h and VDs > VD sA~]:
are as follows:

v ~~
‘is
flat-band
surface-inversion
voltage,
potential,
COX;
(VGS– ~~)2

K1 body-effect coefficient, lDS=[l+uo(;:s-v,)~” 2aK

(6)

Kz source and drain depletion charge sharing coeffi-

cient, where
~ drain-induced barrier lowering coefficient,
l+uc+{li
U. vertical field mobility degradation coefficient,
K=
u, velocity saturation coefficient, and 2
P; carrier mobility. VGS– ~h
v D SAT= (7)
afi
A. Strong-Inversion Component
and
Five drain-current parameters, VFB, +~, Kl, Kz, and q,
‘1 (vGs–~h)
model the threshold voltage:
Vc =.-. (8)
L a“

The body-effect coefficient “a” makes ~SIM a close

numerical approximation of the standard textbook model
over a reasonable range of VBs and VDs. Detailed deriva-
tion of the BSIM expressions can be found in the ap-
pendices.
parameter K1 is equivalent to parameter Y in textbook
models [20], [21]. The K1 and K2 terms together model the
nonuniform doping effect. In addition, to model the 11. Including the Weak-Inversion Component
drain-induced barrier lowering effect, q also partially
Previous SPICE2 MOS transistor models include sub-
accounts for the channel-length modulation effect.
threshold conduction by matching the strong-inversion
Another three drain-current parameters, Uo, U1 and p o,
component with the weak-inversion component at a transi-
appear directly in the drain-current expressions. In BSIM,
tion point close to the threshold voltage. Discontinuity y of
mobility parameter I-Lo is a function of the substrate and
drain-current derivatives exists, as has been pointed out by
drain biases. A detailed description of the mobility depen-
Antognetti et al. [22], which jeopardizes the convergence of
dence will be given later. In order to speed up circuit-simu-
the simulation. Proper matching of the strong-inversion
lation execution time, the 3/2 power dependence of the
component and the weak-inversion component is not a
drain current on the substrate bias has been replaced by
trivial task because it has to be done on a multidimen-
the numerical approximation proposed in [17]–[19]. The
sional basis with respect to the gate, drain, and substrate
drain-current expressions in various operation regions are
biases. In BSIM, the total drain current is modeled as the
summarized below.
linear sum of a strong-inversion component IDS, S and a
1. Cutoff Region [VG~ < Kh]:
weak-inversion component JDs, w, which is given by

IDs=O. (2) I DS, total = lDS,.S + lDS, W’- (9)

560 IEEEJOURNAL
OFSOLID-STATE
CIRCUITS,
VOL.SC-22,NO,4, AUGUST1987

are used to find the 17 size-dependent electrical parame-

(?
process-f ile
ters.
program
At

according
the initial data-processing
stores 17 electrical
to the formula:
parameters
stage, the simulation
for each transistor

J/ Pi= Poi +
PLi Pwi
(14)
celcu late device
parameter for L ~~N– AL + W~~N– AW”
each transistor

Here LDR ~ and WD~N are drawn channel length and

width, while AL and AW are net size changes due to
various f abdication steps. The three components POi, P~i,
and Pwi of each electrical p=mekr P, rfw=fL r=p=-

cir it tively, its offset value, channel-length sensitivity, and chan-

topo ‘iOgy
nel-width sensitivity. For the subthreshold conduction,

w
there are nine additional size-independent parameters in
the process file from which three subthreshold parameters
[no) per transistor can be obtained. Subthreshold parameters
converge?
are also processed using (14). In circuit simulation, this
initialization step only needs to be done once for each
transistor.

2. Reduction from Bias-Independent Parameters to Drain-

Current Parameters: At the model-evaluation step, the 17
Fig. 1. Data flow in the process-oriented circuit simulation. electrical parameters of each transistor are mapped to
eight drain-current parameters. Parameters VF~, +~, K1,
and Kz are kept intact. The rules to map UO, Ul, V, and p ~
The weak-inversion component can be further expressed as
are listed below:
I~xP.Ifiti,
I (lo) U.= Uoz + uoBvB~ (15)
‘s’ w = Iexp + Ifiti,
u,= u,= + UIBVB. + UID(VD. – VDD) (16)
where (17)
T=~z+TBvBs +nD(vDs–vDD).

WkT2 Parameter p ~ is obtained by quadratic interpolation

I exp= l-l Ocox
-H
Lq

. e18e(q/~W~cS- ~/k)/’~ 1 — e–
[
‘DS(q/kT) ] (11)
through three data points: p o at V~~ = O, p o at V~~ = V~~,
and the sensitivity
with
of p o to the drain bias at VD~ = V~~,

and P’Ol(at P’DS=O) =/.lz+pzJ’B~ (18)

2
and
Pocox ~ . ~~
Ilimit = — (12) (19)
2“Lq” Pol(at P’DS=VDD) = Ps + PSBLW
(1

The factor e18 is empirically chosen to achieve best fits in A second-order polynomial function is used in this inter-
the subthreshold characteristics with minimum effect on polation.
the strong-inversion characteristics [23]. The subthreshold
parameters no, n ~, and n ~ are used to model the sub- 111. COMPARISON OF MEASURED AND MODELED RESULTS
threshold-slope coefficient
An integrated system for automated extraction of BSIM
n=no+n
BVB~+n DvD~. (13)
parameters has been developed. The extraction software
This approach does not introduce any discontinuity in the obtains parameter values and forms a process file for
drain-current expression and first derivatives, and thus circuit analysis. Fig. 2 shows the role of such an integrated
does not hamper convergence in circuit simulation. system in the advanced integrated-circuit design. The
parameter-extraction system hardware consists of three
C. Parameter Preprocessing major elements: a desktop computer, an H-P 4145B semi-
conductor parameter analyzer, and a probe station.
1. Conversion from Size-Independent Parameters to Elec- The BSIM extraction program employs a local extrac-
trical Parameters: Fig. 1 shows the data flow in the pro- tion technique. In each biasing region, only parameters
cess-oriented circuit-simulation approach. For each device with related physical origins are extracted together, instead
type in a process file, the 51 size-independent parameters of letting all the parameter values change on the fly as is
SHEU et a[.: BERKi7LEY
SHORT-CHANNEL
lGFETMODELFORMOSTR.4NS1STORS 561

-1.0

1
1 BSI M parameter
I extraction program ; -2..0
1 I
I 1 -5 -4 ‘-3 -2 -1 0
I I
I
Process-f i le~
VDS (v) ‘
1
(a)’

l.S (mA)
o

Fig. 2. A fully integrated

10S
&
approach for computer-aided
traction and circuit design.

(mA) v GS
parameter ex-
-1J3

-2$1
-5
D v.

/
*v
y

-4
‘
#?

-3
V=s(v)
(b)
-2 -1 0

5V
Fig. 4. Measured and modeled output characteristics of a W~RN = 20-

2.0 pm and L~R ~ = 2-pm p-channel transistor. TOX= 30.0 nm. (a) IDS
4V versus VDS at VBS = 2.0 V. (b) I~s versus VGS at VDS = – 3.0 V.

1.0 3V

2V IDS (uA) vGS

Iv 300 ~ ~---,.# ‘“ 5V
01
V:s(;) 4 5 .=-’
200 [ .“”’ I
(a)

IO:E; 01
$Ds ($)
45

Fig. 5. Output characteristics of a W~RN = 20-pm and I,~RN = 20-~m

n-channel transistor at VB~ = – 2,0 V. TOX= 30.0 nm.

012345
VGS
(v)
(b)

Fig. 3. Measured and modeled output characteristics of a W’~RN = 20-

pm and LDRN = 3.5-pm n-channel transistor. To, = 30.0 nm. (a) Z~~
versus VD~ at VB~ = O V. (b) 1~~ versus V& at VD~ = 0.1 V, I I
-5 -4 -3 -2 -1 0
VDS(v)

done in the global fitting approaches [24]–[27]. This makes Fig. 6. Output characteristics of a W~RN = 20-pm and LDRN = 20-pm

BSIM and the associated parameter-extraction software an p-channel transistor at VBS = 2.o V, Tax = 30.o nm.

excellent tool for statistical studies of transistor character-

istics [28]–[30]. The extraction software addresses the fol-
lowing issues effectively: program modularity, efficiency, displayed with cross marks. Fig. 4 shows a similar com-
accuracy, and user friendliness [31]. parison for a WDRN = 20-pm and LDRN = 2-pm p-channel
Experiments were carried out using devices fabricated at transistor. Comparisons of large-geometry n- and p-chan-
various industrial firms. Fig. 3 shows a comparison of nel transistors are shown in Figs. 5 and 6, respectively. The
measured and modeled output characteristics of a W~~N = gate-oxide thickness of the transistors is 30.0 nm.
20-pm and L~~N = 3.5-pm n-channel transistor. Modeled Comparison of measured and modeled total drain cur-
results are plotted with solid lines while measured data are rent for a W~RN = 3-pm and LD~N = 4-pm n’-channel
562 IEEEJOURNAL
OFSOLID-STATE
CIRCUITS,
VOL.SC-22,NO.4, AUGUST1987

Ins(A) .8 I I I I I I
&
W LCC,X triode saturation
region region
.7 - -t-

.6 -

.5

I .4 -

o 1 2 3
.3 -
~GS [V)

Fig. 7. Comparison of measured and modeled total drain current for

a W~R ~ = 3-Pm and LDR ~ = 4-pm n-channel transistor with T.x =
30.0 nm.
.1

I~s (A) 0
~b
I I I 1 I
‘-% 5V 3
-6 _’
v~.s= -
0 1 2 4 5 6 7
-lo \
VDS ( volt 1

-s \ Fig. 9. Selected plots of normalized capacitances versus the drain bias.

-lo
The parameter values are VB~ = – 3.0 V, V& = 6.0 V, u = 1.131, ~k ( V&
= – 3.0 V) = 1.4 V, K1 = 0.63 Vi/2, and qi~ = 0.62.
-lo
-lo
%s= 5’
31
\ .. ’,, TABLE I
-3 -2 -1 0
A COMPARISON
OFSELECTED
SPICE2 SIMULATION
VGS (v] EXECUTION
TIMES

Fig. 8, Comparison of measured and modeled totaf drain current for I I I

a W~R ~ = 2-pm and LDR ~ = 4-Pm p-channel transistor with T.x =
30.0 nm.

F&e Stage Inverter Chain 18.30 44.25

transistor is shown in Fig. 7. A similar comparison is
shown in Fig. 8 for a W~~N = 2-pm and LDRN = 4-pm I I

p-channel transistor. With threshold voltages properly de-

MOS Amplifier (dc & ac)
II 40.02 52.7o
I
termined, agreement between measured and modeled re- MOS Amplifier (transient) 75.08 137.50
sults in the subthreshold region is excellent.
One Stage Op-Amp 15.83 70.77

Binary-tuOctat D.wxder 262.37 586.28

N. THE CHARGE-IIASED CAPACITANCE MODEL AND
SPICE2 IMPLEMENTATION
Telecommunication Ckt. 1784.83 2717.32

The capacitance model for BSIM conserves charge and

has a nonreciprocal property. Charge conservation is guar-
anteed by using terminal charges as the state variables. V. DISCUSSION
The total stored charge in each of the gate, bulk, and
channel regions is obtained by integrating the distributed Enhancements can be made to extend BSIM for submi-
charge densities over the area of the active region. Selected crometer device applications. Inclusion of the source–drain
plots of MOS transistor capacitances normalized to the series resistance and improvement of the drain-current
total gate-oxide capacitance WLCOX are shown in Fig. 9. expression to take into account the buried-channel effect
The capacitance values are continuous at the boundary of are particularly important. The velocity saturation effect
the triode and saturation regions. has drastically changed the transistor capacitance char-
The BSIM has been implemented in the SPICE program acteristics. The present capacitance model needs to be
[32], [33]. Experimental results show that the BSIM greatly enhanced to more completely model short-channel effects.
reduces program execution time as compared with the In a VLSI chip, around 60 percent of the silicon area is
popular SPICE2 Level-2 MOSFET model. A comparison consumed by interconnection lines. Accurate modeling
of selected SPICE2 simulation execution times is listed in and parameter extraction for interconnection lines are
Table I. A DEC VAX-11/780 computer is used in the extremely important. The substrate current, which is a
comparison. good monitor of hot-electron effects, is the next candidate
 SHEU et al.: BERRELEY SHORT-CHANNEL IGFET MODEL FOR MOS TRANSISTORS 563

to be included in advanced circuit-simulation models. With

a substrate current model available, circuit designers will
have a very powerful tool to tackle the hot-carrier prob-
lems in the circuit environment.

VI. CONCLUSION

The BSIM has four important features. First, it is based

on a solid understanding of device physics. Second, the Electric ~eld [v/cm]
model formulation is very simple, which makes it suitable Fig. 10. Carrier velocity versus electric field [34],
for the simulation of both digital and analog circuits.
Third, the model can be easily enhanced to include new
effects. Fourth, the model parameters for a family of
devices can be obtained automatically by a dedicated Equation (A3) can be rearranged as
parameter-extraction program which generates a process

(1+$4[
file. Complete expressions for transistor dc characteristics,
%)vDS- ;% (As)
I“s=
(VGS -
capacitance characteristics, and extrinsic-element char- 1
acteristics are all included in BSIM. By using BSIM,
substantial improvements in circuit-simulation accuracy
and execution time can be achieved. This new model, where
coupled with its inherent autocharacterization characteris-
tics and immediate applicability to new processes, forms ~=/?R,a,. (A6)
the basis for a standard interface between IC process
facilities and integrated circuit designers.
The conventional definition of saturation voltage VD s*~ is
obtained from (Al) with QC = O. This condition is not
APPENDIX A realistic for modern short-channel devices. A more realistic
MODEL DERIVATION assumption is that at the point in the channel where O.
goes to V~ s~= the channel current is limited by velocity
The BSIM builds upon AT&T Bell Laboratories’ CSIM saturation, i.e.,
[18], [19]. The channel-charge expression has the simplified
form Qt. -+.. COx(VGs – ~h – aV~~A~). (A7)
sat

Q.= ‘cox(v..-~h - a+.). (Al)

Substitution of the above expression into (Al) yields an
upper limit for the drain-current integration formula as
If we use the continuous velocity-saturation curve (see
Fig. 10) [34], which can be expressed as
(A8)
% + ‘“AT= ;[(VGS– ~fi)– ~DSAT&at].
ILOEy
~=

() 1+:
c
By
upper
carrying
limit,
in the saturation
out
the following
the drain-current

region
expression
can be obtained:
integration
for the drain
with
current
this

with

when
I DSAT=~
[
(vGs-~h -lDsATR,at)vD,A, -
a ‘i
z
SAT

1 ~

(A9)
EY+w (A2)
Equation (A9) can be rearranged as
to best portray the device characteristics, then the drain-
current expression in the triode region becomes I D,AT= $(VGS - ~, - ~DSAT&,)2
(A1O)

a
IDS = i
[
(VGS – Kh – Iz@sat) ‘DS – ~ ‘:S
1 (A3)
which
comparison
is a quadratic
with
equation
the usual expression,
for ID sAT. To
we define
facilitate

where

1 B(vGs-L)2
R,a, = (A4) ID (All)
SAT =
Wcoxv,at “ 2aK
564 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, IWO.4, AUGUST 1987

60–
where K is obtained by equating (AlO) and (Al 1), i.e., — FuNCTION
o APPROXIMATION
@s-VBSz20.7v

K2_K l+_.
‘1 (h-h)
50 –

[ L a 1 16.7V
$-
> 12.7V
U1 2 (vG~–vJ2 40 -
+y. = O (A12) 8.7V
(1 (2a)2 G
>;
4.7V
or & 30 –

G
l+uc+/~ >Q 0.7V
K= (A13)
z 20 -
2

where
10 –
‘1 (VGS–~h)
UC= —.-. (A14)
L a“
o
0 2 4 6 8 10
If UC<< 1, then
y)~ (v]

UI (vGS–~k) Fig. 11. Approximating the function F( V~~, $~ – VB.S).

K+l+y. (A15)
a“

If UC>> 1, then can be expanded as

0.25 V&
‘1 (VGS–~k)
K+y. (A16) F(vDs>vA)=~vDs+ ~ +.. (B2)
2a
and The above expansion is invalid when VA is much greater
I ~ ~*~ + COXUJV( V& – Vth) . (A17) than V~~. To alleviate this problem, the expansion is
changed to
The above expression is well known, and states that in the
limit of carrier velocity being fully saturated at u,.,, the o.25gv;~
qvDs, VA) =JZVDS + (B3)
saturation current is linear instead of squared with respect K
to vG~ – ~k, and its value is independent of the channel
length. One can obtain the saturation drain voltage from where g( VA) is determined by requiring the expansion in
(A8) and (All): (B3) to give the best fit to F(V~~, VA) in the desired voltage
range.

vD
(vGS- ~/z) (A18)
The value of VA is considered in the range 0.7-20.7 Vat
SAT z
a@ “ 2-V increments. For each fixed VA, a parameter g is
determined such that the expansion
In the case of U1/L c(VG~ – ~~) <<1

vD SAT +
vc~ – ~h
(A19)
~vD. + 0“2’2’
a“

In the case of U1/L. (Vcs – ~fi) >>1 will give the best fit to F( V~s, VA) in a least-square sense,
over a range of V~s from O to 10 V at 0.5-V increments. It

‘-r=%
is found that g can be accurately expressed as a function
(A20) of VA in the following form:

1
—= P1+P2. VA (B4)
l–g
APPENDIX B
NUMERICAL APPROXIMATION OF THE where PI and P2 are determined by a least-square fitting
SUBSTRATI+BIAS EFFECT over the range of VA from 0.7 to 20.7 V. The results are

The ‘aim here is to find an accurate approximation of PI= 1.744 (B5)

F( V~s, OS– V~s) over a reasonable voltage range of V~s and
and ( +s – V~s) [17]–[19]. For convenience, let VA - @s– P2 = 0.8364. (B6)
V&. The function
The root-mean-square error of the approximation in (B3)
3/2_ (VA)3V2] (111) using the above value of PI and P2 is 2 percent and is
WDSY2=:[(VDS+L) illustrated by Fig. 11.
 SHEU et al.: BERKELEY SHORT-CHANNEL IGFET MODEL FOR ktos TRANSISTORS 565

ACKNOWLEDGMENT [26] E. Khalily, P. H. Decher, and D. A. Teegarden, “ TECAP: k

interactive device characterization and model development system,”
~49~;;i IEEE Int. Conf. Computer-Aided Design, Nov. 1984, pp.
The authors wish to thank Prof. D. O. Pederson and
[27] P. Yang’ and P. K. Chatterjee, “An optimal parameter extraction
Prof. D. A. Hodges for their continuous ertcouragement
program for MOSFET models: ZEEE Trans. Electron Devices, vol.
and Dr. H. C. Peon for his initial work on the AT&T Bell ED-30, no. 9, pp. 1214-1219, Sept. 1983.
[28] N. Herr, B. Garbs, and J. J. Barnes, “A statistical modeling
Laboratories’ CSIM model. The efforts made by B. S.
approach for simulation of MOS VLSI circuit designs,” in ZEDM
Messenger, R. C.-L. Liu, J. R. Pierret, A. H. Fung, and Tech. Dig., 1982, pp. 290-293.
[29] P. Yang and P. Chatterjee, “Statistical modeling of small geometry
T. K. Young are appreciated.,
MOSFETS.” in IEDM Tech. Dir.. 1982. rm. 286:289.
[30] P. Cox, P. Yang, S. S. Malmrtt-S~etti, an/P. K. Chatterjee, “ Statis-
tical modeling for efficient mmrnetric vield estimation of MOS
VLSI circuits?’ IEEE Trans.’ Electron D;uices, vol. ED-32, no. 2,
pp. 471–478, Feb. 1985.
REFERENCES
[31] M.-C. Jeng, B. J. Sheu, P. K. Ko, and D. L. Scharfetter, “Parameter
extraction for Berkeley short-channel IGFET model (B SIM),” in
[1] L. W. Nagel, “ SPICE2: A computer program to simulate semicon- preparation.
ductor circuits,” Electron. Res. Lab., Univ. of Calif., Berkeley, [32] B. J. Sheu, D. L. Scharfetter, and P. K. Ko, “SPICE2 implementa-
Memo ERL-M520, May 1975. tion of BSIM,” Electron. Res. Lab., Univ. of Calif., Berkeley,
[2] R. A. Saleh, J. E. Kleckner, and A. R. Newton. “Iterated timinsz Memo ERL-M85/42, May 1985.
analysis and SPLICE1,” presented at the IEEE’ Int. Conf. Com~ [33] B. J. Sheu, “ MOS transistor modeling and characterization for
puter-Aided Design, Santa Clara, CA., Sept. 1983. circuit simulation,” Ph.D. dissertation, Electron. Res. Lab., Univ.
[3] J. White and A. Sangiovanni-Vincentelli, “ RELAX2: A new wave- of Cafif., Berkeley, Memo ERL-M85/22, Oct. 1985.
form relaxation approach for the anafysis of LSI MOS circuits,” [34] .S.. . M.
. Sze, Physics of . . .Semiconductor
. . Devices, 2nd ed. New York:
presented at the IEEE Int. Symp. Circuits and Systems, Newport Wdey-lntersclence, 1981, p. 46.
Beach, Ca, May 1983.
[4] J. T. Deutsch and A. R. Newton, “A multiprocessor implementa-
tion of relaxation-based electrical circuit simulation,” presented at
the ACM/IEEE 21st Design Automation Conf., Albuquerque,
NM Time 19X4 Bing J. Sheu (S’81-M85) was born in Taiwan in
[5] J. ‘T. ‘De&;ch,”” “Algorithms and architecture for multiprocessor- 1955. He received the B. S.E.E. degree in 1978
based circuit simulation; Electron. Res. Lab., Univ. of Calif.,
from the Nationaf Taiwan University, and the
Berkeley, Memo ERL-M85/39, May 1985.
M.S. and Ph.D. degrees in electrical engineering
[6] A. Vfadimirescu and S. Liu, “The simulation of MOS integrated
circuits using SPICE2,” Electron. Res. Lab., Univ. of Calif., Berke- from the University of Crdifomia, Berkeley, in
ley, Memo ERL-M80\7, Oct. 1980. 1983 and 1985, respectively.
[7] H. K. J. Ihantola and J. L, Mon. “Design theorv of a surface effect In 1981 he was involved in integrated-circuit
transistor,” Solid-State Electron.; vol. 7~pp. 42~-430, June 1964. design for a speech recognition system at
[8] H. C. Pao and C. T. Sah, “Effects of diffusion current on character- Threshold Technology Inc., Cupertino, CA. From
istics of metal-oxide (insulator)-semiconductor transistors (MOST),” 1982 to 1985 he was a Research Assistant in the
Solid-State Electron., vol. 9? pp. 927-937, 1966.
Electronics Research Laboratory, the University
[9] Y. A. E1-Mansy, “ Modehng of insulated-gate field-effect tran-
of California, Berkeley, working on integrated-circuit design. In 1985 he
sistors,” Ph.D. dissertation, Carleton Univ., Ottawa, Ont., Canada,
Nov. 1974. joined the faculty in Electrical Engineering at the University of Southern
[10] J. R. Brews, “A charge-sheet model of the MOSFET)” Solid-State California, Los Angeles, as an Assistant Professor. Since 1983 he has
Electron., vol. 21, pp. 345-355, 1978. served as a consultant to the electronics industry. His research interests
[11] R. M. Swanson and J. D. Memdl, ‘<Ion-implanted complementary include computer-aided design of analog and digitaf integrated circuits,
MOS transistor in low voltage circuits.” IEEE J. Solid-State Cir- and transistor modeling with automated parameter extraction for circuit
cuits, vol. SC-7, pp. 146–153~Apr. 1972. simulation,
[12] R. R. Troutman, “ Subthreshold design considerations for Dr. Sheu is a’member of Phi Tau Phi.
IGFET’s,” IEEE J. Solid-State Circuits, vol. SC-9, no. 2, pp.
55-60, Apr. 1974.
[13] G. W. Taylor, ‘<Subthreshold conduction in MOSFET,” IEEE
Trans. Electron Devices, vol. ED-25, vol. 3, pp. 337-350, Mar. 1978.
[14] G. W. Taylor, “A unified device model for a short-channel
Donald L. Seharfetter (S’61-M63-SM75-F’76)
MOSFET,” presented at the IEEE 39th Annuaf Device Research
obtained the B.S. M. S.. and Ph.D. degrees in
Conf., 1981. ”
[15] W. Fichtner, “ Three-dimensionaf numericaf modeling of small-size electrical engineering from Carnegie~Mellon
MOSFET’s~’ presented at the IEEE 39th Annual Device Research University, Pittsburgh, PA, in 1960, 1961, and
Conf., 1981. 1962, respectively.
[16] S. Liu, “A unified CAD model for MOSFETS,” Electron. Res. He was with Bell Telephone Laboratories,
Lab., Univ. of Calif., Berkeley, Memo ERL-M81/31, May 1981. Murray Hill, NJ, from 1962 to September 1977,
[17] H. C. Peon, private communication, 1979. where he was Manager of the design group re-
[18] S. Liu and L. W. Nazel. “ Smafl-siznal MOSFET models for analog sponsible for Bell Labs first microprocessor,
circuit ‘design,” IEEE J. Solid-Sta~e Circuits, vol. SC-17, no. 6, pp;
Manager of the CMOS standard-cell based semi-
983-998, Dec. 1982.
[19] B. J. Sheu, D. L. Scharfetter, and H. C. Peon, ‘<Compact short- custom desism moum and had management re-
channel IGFET model (CSIM),” Electron. Res. Lab., Univ. of sponsibility for design of a family or 1-;s E~L MSI circuits. ~rom 1972
Calif., Berkeley, Memo ERL-M84/20, Mar. 1984. to 1974 he managed the group responsible for Bell Lab’s IC process,
[20] P. R. Gray and R. G. Meyer, Analysis and Design of Analog device, and circuit design aids. Eadier work provided fundamental under-
Integrated Circuits, 2nd ed. New York: Wiley, 1984, p. 63. standing of Schottky barrier diodes, bipolar transistors, and microwave
[21] D. A. Hodges and H. G. Jackson, Analysis and Design of Digital (avalanche) diodes. For the academic year 1977-1978 he held the position
Integrated Circuits. New York: McGraw-Hill, 1983, p. 47. of Professor of ElectncaJ Engineering at Carnegie-Mellon University, and
[22] P. Antognetti, D. D. Cavigia, and E, Profumo, ‘<CAD model for
was a consultant to Xerox. He was employed by the Xerox Corporation
threshold and subthreshold conduction in MOSFETs~’ IEEE J.
at their Pafo Alto, CA, Research Center from 1978 through 1983. Initially
Solid-State Circuits, vol. SC-17, no. 3, pp. 454-458, June 1982.
[23] A. H.-C. Fung, “A subthreshold conduction model for BSIM; as Manager of Integrated Circuit planing, he ~SO had respOnsibifity fOr
Electron. Res. Lab., Univ. of Cafif.j Berkeley, Memo. ERL-M85/22, process, device, and circuit-simulation design aids as well as testing and
Mar. 1985. process characterization. Beginning in March of 1983, he spent a year as
[24] K. Doganis and D. L. Scharfetter, “General optimization and Mackay Professor of Electrical Engineering and Computer Sciences at the
extraction of IC device model parameters,” IEEE Trans. Electron University of California, Berkeley, where he directed the BSIM project.
Deuices, vol. ED-30, no. 9,, pp. 1219-1228, Sept. 1983.
In March of 1984 he formed Automated Characterization Systems,
[25] D. E. Ward and K. Dogams, “Optimized extraction of MOS model
Cupertino, CA, to develop and market software for the characterization
parameters’ IEEE Trans. Computer-Aided Des., vol. CAD-1, no. 4,
pp. 163-168, Oct. 1982. of MOS devices. He has published over 40 highly regarded technical
566 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 4, AUGUST 1987

publications and has five issued patents. His current interests are in and Computer Sciences at the University of California at Berkeley where
productivity improvement in the development of advanced CMOS in- he is at presently an Associate Professor. His research interest is in
tegrated circuits. high-speed integrated-circuit technologies and device modeling for circuit
Dr. Scharfetter is active in IEEE professional activities. He was Chair- simulation.
man of the 1981 International Devices Meeting, organized the first West
Coast Test Workshop, and has served on the program committee of the
Intemationaf Solid-State Circuits Conference, the Device Research Con-
ference, and the joint U.S. and Japanese Symposium on VLSI. His work MhWlrie Jeng was born in Taiwan in 1959. He
received the B.S. degree from the Department of
on microwave (avafanche) diodes earned him the IEEE grade of Fellow.
Electrical Engineering, Nationaf Taiwan Univer-
sity in 1980, and the M.S. degree from the Uni-
versity of Maryland in 1983, He is currently
Ping-Keung Ko (S’78-M82) was born in Hong working toward the Ph.D. degree at the Univer-
Kong in 1951. He received the B. SC. (special sity of California, Berkeley.
honors) degree in physics in 1974 from the Uni- From 1980 to 1982 he served in the Chinese
versit y of Hong Kong, and the Ph.D. degree in Army as a Radar Maintenance Officer. In 1983
electncaJ engineering in 1982 from the Univer- he was a Research Assistant in the Department
sity of California at Berkeley. of Electrica3 Engineering, University of Mary
From 1982 to 1983 he was with the silicon- land, and a Guest Worker in the Nationaf Bureau of Standards, Gaithers-
research group at Bell Laboratories, Holmdel, burg, MD, working on ultrafast optoelectronic stitchings. Since 1984 he
NJ, where he developed a submicrometer high- has been a Research Assistant in the Electronics Research Laboratory,
speed NMOS technology. In January 1984 he University of Cafifomia, Berkeley. His main interests are MOS device
joined the Department of Electrical Engineering physics, modeling, and parameter extraction.