Advanced Process

Technologies
Prof. Adam Teman Special credit to Alvin Loke
and Or Nahum for the material
16 March 2022 and wonderful explanations!
 Lecture Overview

2 © Adam
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Teman,
16, 2022
The Third FinFET FinFET Parasitics Current
Dimension Fabrication Layout and LDE Trends

Moving to the third

dimension
The breakdown of Dennard’s Law
• Robert Dennard (1974) observed that continuous scaling is enabled by:
• Scaling the transistor dimensions by 30%
• Scaling the supply voltage by 30%
• This results in:
• 2X area reduction
• 30%-40% increase in frequency
• Constant power density
• However:
• Voltage wasn’t scaled according to the model
• Frequency was raised faster than the model
• Leakage, due to VT scaling, wasn’t taken into account
• This led to the infamous power crisis
© Adam
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Teman,
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 The problem with voltage scaling
• In order to keep constant power density, f  C V 2
S  S −1  S 2
the supply voltage needs to be scaled PD = =
DD
A S2
• However, this also requires W
I sat = n Cox (VDD − VT )
2
scaling of the threshold voltage
L
• But the off current of a transistor is
exponentially dependent on VT
W −VT nT W −VT S
I off  nA  = 100 e = 100 10
L L
• This is limited by both
subthreshold swing and DIBL.

5 Loke, CICC 2019 © Adam

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 The Multi-Gate Solution
• Moving to the third dimension enables
better channel control
→ Smaller subthreshold slope
→ Can use Lower VTs

https://www.realworldtech.com/intel-22nm-finfet/

https://www.fz-juelich.de/
6 © Adam
M. G. Bardon (IMEC) ICICDT March
(2015) Teman,
16, 2022
 Introducing the FinFET

• 3D Structure
• More Ion & gm per area
• Fully depleted channel
• Less DIBL
• Less RDF mismatch
• Negligible body effect
• Quantized channel width
• Problematic Parasitics
• High S/D resistance
• High S/D coupling to gate
Planar transistor FinFET transistor
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 Main Parameters
• Lower power
• Lower leakage
• Higher intrinsic gain
• Better switch
• Better mismatch
• Smaller area

• Summary:
Improved PPA
Loh, Mediatek
Loke, BCICTS
8 © Adam
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 The Third FinFET FinFET Parasitics Current
Dimension Fabrication Layout and LDE Trends

Fabricating a FinFET

9
 Planar vs. FinFET Fabrication
• We’ll start by remembering how planar CMOS is constructed.
• We patterned the poly gate, oxide and diffusions using a self aligned process
• Now the backend layers can be made by litho, etch, clean, deposit, polish
• But how do we make Fins above the substrate plane?
• We carve them out of the substrate!
• And then cover them with oxide and poly.

10 © Adam
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 The roads to higher performance

Technology Foundry Reason

Innovation Debut Required
Mechanical Mobility boost for more
40nm FET drive & higher Ion/Ioff
stressors
HKMG 28nm (HK-first) Higher Cox for more FET
replacement gate 20nm (HK-last) drive & channel control
Sub-80nm pitch
Multiple-patterning 20nm lithography without EUV
(13.5nm l = 193 nm)

Complex Contact FET diffusion &

20nm gate with tighter CPP
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middle-end-of-line © Adam March
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 Fin and Gate Patterning
• The first critical step of the FinFET process is to make
very thin fins at a very tight pitch and build tightly pitched gates.

• Immersion Litho
• Phase shifting
• Double patterning
(a.k.a. LE-LE)
• Self-aligned
Patterning
k l (SADP/SAQP)
• How can we do this with 193nm litho? CD =
n sin 
12 Fins and Gates Source/Drain Hi-K - MG MEOL BEOL © Adam
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 Double Patterning (LE-LE)
• Introduce “colored” masks for pitch splitting
• Limited by misalignment between masks.
Minimum Pitch

13 Fins and Gates Source/Drain Hi-K - MG MEOL BEOL © Adam

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 Self-Aligned Double Patterning (SADP)
• We can achieve the same resolution using a self-aligned technique
• Start by constructing “mandrels” with the minimum litho pitch.
• Next, create spacers around the mandrels.
• Remove the hard mask and the spacers are at half the pitch.
• Note that Line Edge Roughness is correlated, reducing L variation!

Minimum Pitch
Half Pitch

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 Self-Aligned Quadruple Patterning (SADP)
• And just repeat the process to double the resolution again.
• Just remember that this cost us another few masks and many steps.

Half Pitch

Quarter
Pitch

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 Additional Advanced Litho Points
• You can only print one line width!
• To get multiple line widths,
change mandrel width and spacing.
• Each multi-patterned layer is unidirectional.
• No more wrong-way routes or jogs!
• Use orthogonal cut masks to break patterns.
Woo, et al. Globalfoundries
• Orthogonal cut mask according to CD.
Auth, et al. Intel
• Eliminate corner rounding on fins/gates.
• Self-aligned vias Brain, et al.
Intel

• Via etch only at

intersection of
trench & via masks
16 Fins and Gates Source/Drain Hi-K - MG MEOL BEOL © Adam
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 Source/Drain Regions
• We have seen how to make the “array” of fins and gates.
• But we have a few problems with the S/D regions:
1. They are really small and delicate → hard to contact to.
2. They have high resistance.
3. We need to apply stressors to improve mobility.
• Therefore, we build an epitaxial area on the fins

Start by The result is a

Then grow diamond shape.
building a
an epi layer Note that a
spacer
of a stressor PMOS diamond
between the
gate and
on the is much “cleaner”
exposed fin than an NMOS
diffusion

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 A note about Stress
• A silicon channel is piezoresistive
• Lattice strain affects mobility.
Faricelli, AMD, 2010
• Tensile stress improves NMOS,
compressive stress for PMOS
• Depends on lattice orientation:
(100) fin top vs. (110) fin sidewall

• Stress has been more effective for PMOS

• This has caused beta (N/P) ratio to
fall to about unity at 7nm.
• Expected to change for nanosheets
Loke, CICC, 2019
Nahum, Intel

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 High-K – Metal Gate (HKMG)
• Two problems with the transistor gate:
1. Thinning Oxide → Gate Leakage
2. Polysilicon → high resistance,
poly diffusion
• Therefore, at 45nm-28nm move to HKMG
• High-K dielectrics enable thicker oxides
• Metal gates improve resistance, EOT
• However:
• High-K Materials have lower Energy Bandgap Touati, et al., J. New Technol. Mater.

• Metal gates are sensitive to high temperatures during annealing

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 Metal Gate and VT adjustment
Flatband Condition (VGS=VFB)
• VT of a transistor is primarily set by:
• The workfunction difference The workfunction of
a material is the
between gate and substrate energy gap between
the Fermi energy
• The doping in the junction level and the
vacuum.
• The backgate capacitance
• In older technologies Fermi-Dirac
distribution function

• VT adjustment was achieved through channel implants

• However, random doping fluctuations caused huge variation
• FinFETs have intrinsic channels
• Therefore, RDF has basically “gone away”
• VT adjustment is done through the
workfunction of the metal gate
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 Replacement Metal Gate (RMG)
• Metal Gates are sensitive to high-temperature process
steps required for S/D engineering (epi, stress, etc.)
• Therefore, a “gate-last” approach is used:
• Form the gates with polysilicon.
Also known as a dummy gate.
• After S/D formation, etch poly gates.
• Partially fill in with barrier
and workfunction metal.
• Fill in with low resistance metal.
• This also impairs the Silicide,
increasing S/D resistance
Jacob, et al., Globalfoundries

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 Middle-end-of-the-line (MEOL)
• In older technologies, making contacts was easy
• The contacted gate pitch (CGP) was large enough
to place gates and contacts next to each other.
• But at tight gate pitches,
any misalignment can short the contact to the gate.
• Therefore, Self-Aligned Contacts (SAC) were introduced
• A dielectric cap is added on top of the gate so that
if the contact overlaps the gate, no short occurs.

wikichip

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 Middle-end-of-the-line (MEOL)
• SAC process is more complex in FinFET
• RMG is harder to recess than gate-last approach
• Contact Over Active Gate (COAG) is desired
• Introduced by Intel in 10nm process
• The MEOL process now includes many steps
• Cap gate and create SAC
• Cap contact and create COAG
• Create additional VIA0 to go through caps
• Disadvantages:
• High Gate to S/D Contact capacitance
• High S/D, MEOL & lower BEOL resistance
Yang, Qualcomm
Auth, et al. Intel

23 Fins and Gates Source/Drain Hi-K - MG MEOL BEOL © Adam

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 Backend-of-the-line (BEOL)
• Copper interconnect replaced aluminum
• Lower resistance, Improved electromigration
• Dual Damascene Process Jacob, et al., Globalfoundries

• However, a barrier and liner are required

• Plated copper area is reduced, increasing resistance
• At 10nm Intel started using Cobalt on M0 & M1
• 5-10X Electromigration, 2X resistance
Liner
Cu
Cu

ILD
ES barrier

Cu
Intel 10nm metal interconnects cross section
wikichip
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 The Third FinFET FinFET Parasitics Current
Dimension Fabrication Layout and LDE Trends

FinFET Layout

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 Layout Complexity

Leary, Qualcomm

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 Planar vs. FinFET
Traditional Planar MOSFET Layout FinFET Layout

Diffusion Fin

Contact
Contact

Poly Poly

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 FinFET Stack (5nm)

M1
M1 V0
M1
V0 V0 M1 V0
M0
V0
M0 M0
VD
M0
VD VD VG
VG
VD
MD MD
FIN
FIN OD MD MD

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 Layout in FinFET Technologies
Poly can have different L MD can connect
in different areas NMOS/PMOS diffusions
CUT Poly

M0 VD VDD VD Unidirectional
Metal Routes
MD MD
VD
VOUT
M0
CUT OD Constant Fin Grid

OD MD
VGM0 VIN
OD VG OD

Cut layers in
MD MD non-critical
dimension
M0 VD GND VD

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 Diffusion Breaks
• A diffusion break is required between two active areas:
• Blocks Epitaxial growth
• Provides “back wall” for stressors
• “Double Diffusion Break” (DDB) is
done with two dummy gates and STI

• This wastes a lot of area Jacob, et al., Globalfoundries Yang, et al., Qualcomm

• Instead use only one dummy gate

• “Single diffusion break” (SDB)
saves area but is complex to process

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 Density & Floorplan Considerations
• Critical process steps are extremely sensitive to pattern density & loading
• 1000s of DRCs, many very tough to pass, increasingly restrictive & foreign
• DRCs reduce unmodeled long-range systematic & random variation
• ➜ iterative rework of smaller cells
• Area, perimeter, gradient Example Mixed-Signal Floorplan
• Contacts, vias, cuts, tight-pitch metal
• Larger checking windows
• Density union of multiple metal levels
• Floorplanning more tedious & bloated
• More dummy gates, well taps, guard rings
• Wasteful transitions between different
device types & pattern densities

Yang, et al., Qualcomm

31 © Adam
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 The Third FinFET FinFET Parasitics Current
Dimension Fabrication Layout and LDE Trends

Layout Dependent Effects

and Parasitics

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 Layout Dependent Effects (LDEs)
• Fabricated device characteristics have shown a high
dependency on layout features for several generations:
• Well Proximity Effects (WPE)
• Length of Diffusion (LOD)
• Oxide-to-Oxide Spacing (OSE)
• FinFETs further introduce LDEs:
• Stress LDEs more significant Ou, et al., IEEE TCAD, 2016 Faricelli, AMD, 2010

due to stronger stressors

• Gate cut stress
• HKMG LDEs
• All of this causes more pre- to post-layout simulation differences

33 © Adam
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 Stress LDEs in FinFETs
• Stress LDEs are caused by:
• Longer diffusions (OD Length)
• Wider diffusions (ID/fin not constant vs. # fins)
• Oxide spacing
• Gate pitch Length of OD Gate Pitch
• Models capture Δµ & ΔVT
(some effects as early
OD Oxide Space
as 130nm) Width

Faricelli, AMD
Lee et al., Samsung
Sato et al., IBM
Bardon, et al., imec
NMOS PMOS
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 Gate Cut Stress LDE
• Gate cut disrupts mechanical support of continuous gate & stress near cut
• → Δµ & ΔVT, modeled in post-layout netlist starting in 16/14nm

Yang et al, Qualcomm

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 HKMG LDEs
• Metal Boundary Effect
• ΔVT near border of different ΦM
due to Interdiffusion of ΦM.
• Mitigated with gate cut but costs area
• Models capture Δµ & ΔVT.
Hamaguchi et al., Toshiba

• Density Gradient Effect (DGE)

• Gate density gradients
• →ΔVT & variation from RMG CMP dishing
• ΦM influenced by metal fill & sidewall ΦM
• Not modeled, contained with DRC
Yang et al., Qualcomm

36 © Adam
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 Process Loading Variation
• Local pattern density modulates deposition rate, etch rate/profile & CD
• Deposition loading: Spacer width variation (gate and metal CD)
• Epitaxy loading: S/D volume variation (S/D resistance & channel stress)
• Etch loading: Depth/profile variation (Lgate, fin & metal height)
• Rapid Thermal Annealing (device variation)
• Chemical Mechanical Polishing (variation in STI, poly, RMG, MEOL & BEOL)

Spacer width variation Loke, BCICTS 2020 Epitaxy loading variation Etch loading variation
37 © AdamMarch
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 Parasitic Resistance and Capacitance
• High Resistance:
• Contacts, Metal Gate, Low Metals
• High Capacitance:
• Tight metal pitches
• S/D trench contacts & gate
form vertical plate capacitors

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 Gate Resistance
• Metal gate should have lower resistance than poly gate
• But gates are very thin.
• Workfunction Metals have high resistance.
• Lower resistance metal filled on top of workfunction metal
• But still, this is very little conductive metal

• Another point
• It’s tough to make
thick oxide I/Os!

Loke, ICCD
Wu & Chan, HKUST / Lee, Intel
40 © Adam
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 Diffusion & MEOL Resistance
• Traditionally:
• Try to share diffusions for smaller S/D capacitance
• But S/D resistance is now a much bigger problem than capacitance
• This becomes challenging for high-current circuits
• e.g., I/O drivers, clock buffers

• Therefore:
• Double-source layout
→ S/D Rcontact is halved
• Extend self aligned contact (MD)
to land extra diffusion via
Loke, ICCD

41 © Adam
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 BEOL Resistance
• Copper interconnect used for low resistivity
• However, copper diffuses into ILD.
• Need barrier, liner and seed layers.
• Local interconnect (MX) aggressive pitch scaling
• Dense logic routing→less die area & cost
• But not much copper left in the wire…
• 6X rise in resistance from 80nm to 48nm pitch!
• Therefore:
• Remove seed, liner layers.
• Use cobalt & ruthenium which don’t require a barrier
• Despite higher ρ – less wire resistance! Loke, ICCD

• Use M3 and up for inter-cell routing.

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 Parasitics Summary…

Half of your performance

from scaling is going here!

Courtesy of Greg Yeric, ARMTechCon 2016

43 https://madematics.com/2011/09/13/nanotoilet/ © Adam
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 FinFET Node Models
• FET models
• BSIM-CMG – based on channel surface potential, less equation fitting
• Target-based for latest nodes, more silicon influence in mature nodes
• Prone to model-vs.-silicon gap from increasing density & loading effects
• BEOL models
• Electrical information provided, limited to no physical stack-up details
• Less pessimistic corners for relaxed timing closure (customer pressure)
• Usual reliability models (HCI, BTI, TDDB, EM)
• Vague allowable VDD, depends on application
• Foundries extremely paranoid to protect their technology IP from competitors
• Process corner methodologies & many model parameters encrypted
• Limited physical information available – even basic dimensions (e.g., Lgate) not real
• CD bias & mask booleans to conceal process details (e.g., RMG flow for multiple VT)
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 Overcoming Process/Model Immaturity
• “All models are wrong, but some are useful”
George Box (1919-2013), British Statistician

• Corollary:
“All simulations are wrong,
but some are useful”
Alvin Loke, NXP/TSMC

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 The Third FinFET FinFET Parasitics Current
Dimension Fabrication Layout and LDE Trends

Some Current Trends

46
 A note about process node naming
• Scaling rate slower than 0.7x per node
• Node name just marketing number for equivalent PPA
• Physical gate lengths haven’t scaled below ~14nm
• 193i Single exposure pitch limit ~80nm
• “Intra Nodes” on official scaling roadmaps
• Process optimizations for performance
improvements and yield enhancements Loke, BCICTS

47
Zheng Guo et al. Intel © Adam
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 Squeezing Out What’s Left in FinFETs
• Really tough after 4 FinFET generations
• Realistically, never been any low hanging fruit with each new node
• Process innovations & complexity for only incremental gain
• +5% ring oscillator frequency is a big deal
• Areas of development (no stones unturned)
• Short-channel control ➜ narrower fins, tradeoff vs. µ reduction
• Channel mobility ➜ high-µ fin material, e.g., TSMC 5nm
• EOT ➜ higher K, thinner & reliable gate dielectrics
• Device variation ➜ fin uniformity & geometry control
• Volumeless VT tuning using only HK dipoles
• Rcontact ➜ contact resistivity (interface quality) & area
• Rgate ➜ selective bottom-up HKMG deposition
• CGS & CGD ➜ gate spacer K, air gap spacers
• MEOL & BEOL resistance ➜ metal resistivity, Rvia Yeap et al., TSMC
Cai, TSMC

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 Vertical Scaling and Fin Depopulation

Synopsys
49 TSMC
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 Migrating to Gate-All-Around (GAA)
• FinFET has poor short-channel control with further Lgate scaling
• Need better short-channel control & more Weff per die area
• Stacked GAA nanowires & nanosheets are promising
• Nanowires offer better SCE, nanosheets offer better area scaling

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 FinFET ➜ Nanosheet
• Current mostly flows along (100) surface
• Electrons ☺, Holes →NMOS again stronger
• Need inner spacers to reduce gate-to-S/D capacitance
• Disable parasitic planar FET below nanosheets
https://technewsrooms.com/

Loke, BCICTS
Cai, TSMC
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 Backside power delivery
• Burying the power rails under the transistors
• Power rails do not take up routing resources
• →Reduced design area
• →Improved IR drop and voltage droops Intel’s
PowerVia

• →Reduced power. backside

power delivery

Prasad, et al., IEDM 2019 Gupta, et al., IEDM 2020

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 Conclusions
• “Moore’s Law is well and alive.
It's not slowing down.
It’s not even sick”
Phillip Wong, TSCM, HotChips 2019

• SoC area scaling now driven primarily

by device innovation & DTCO, less by
feature size reduction.

• Understand & exploit technology for

maximum PPA benefit & efficient
design productivity
Wong, TSMC, HotChips, 2019
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 Main References
• Alvin Loke, et al., “Nanoscale FinFET Technology for Circuit Designers”,
2019 CICC Education Sessions, 2020 BCICTS, 2021 MTT-SCV
• Or Nahum, “FinFET Process Overview”, 2021
• www.halbleiter.org “Semiconductor Technology from A to Z”
• Jacob, et al., “Scaling Challenges for Advanced CMOS Devices” Globalfoundries

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