Roll Number:
Thapar Institute of Engineering & Technology, Patiala
Department of Computer Science and Engineering
END SEMESTER EXAMINATION
B. E. (Third Year): Semester-V (2019/20) Course Code: UCS507
(COE) Course Name: Computer Architecture and
Organization
14th December, 2019 2:00-5:00 p.m.
Time: 3 Hours, M. Marks: 100 Name of Faculty: Dr. Anju Bala, Dr. Rupali
Bhardwaj, Dr. Raahat Devender Singh, Mr.
Sahil Sharma
Note: Attempt all questions with proper justification. Assume missing data, if any, suitably.
Q1 (a) Design the 8x3 bit priority encoder using logic diagram and truth table. (6)
Q1 (b) The outputs of four registers RO, R1, R2 and R3 are connected through 4-to-1- line (8)
multiplexers to the inputs of a fifth register, R5. Each register is eight bits long. The
required transfers are dictated by four timing variables To through T3 as follows:
To : R5 <— R0
T, : R5 4- R,
T2 : R5 <— R2
T3 :R5 <- R3
The timing variables are mutually exclusive, which means that only one variable is
equal to one at any given time, while the other three are equal to 0.Draw the block
diagram showing the hardware implementation of register transfers include the
connections necessary from the four timing variables to the selection inputs of the
multiplexers and to the load input of register R5.
Q1 (c) Find the decimal equivalent of the given number 40400000H(H-hexadecimal)
after converting it into IEEE 754 single-precision floating point format. (6)
Q1(d) A computer has 8 registers, an ALU with 16 arithmetic and 16 logic operations and (5)
a shifter with 4 operations, all connected to a common bus system.
(i) Formulate a control word for a micro operation and specify the number of bits
in each field of the control word.
(ii) Show the bits of the control word that specify the micro operation R4=R14-R6.
Q2 (a) Design the block diagram for the control unit of a Basic Computer. (7)
Q2(b) Show the contents of registers AC, QR using Booth's multiplication during the (8)
process of multiplication of two binary numbers where BR= 10111 (multiplicand),
QR= 10011 (multiplier).
Q2 (c) Design the 4-bit combinational incrementer circuit using control input D. When (7)
D=0, the circuit increments by one, but when D=1, the circuit increments by two.
Q2(d) A RAM chip has a capacity of 1024 words and each word is of 1 byte. To construct (3)
a 16K x 16 main memory from 1K x 8 RAM specify the following terms:
i) What is the size of decoder ii) number of decoders iii) number of RAM chips.
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Q3(a) Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 (6)
words. The CPU generates a 20-bit address of a word in main memory. What are
the number of bits in the TAG, LINE and WORD fields respectively?
Q3(b) Design the Block diagram for directly transferring data between memory and I/O (6)
devices using DMA controller.
Q3(c) The microinstructions stored in the control memory of a processor has a width of (6)
26 bits. Each microinstruction is divided into three fields: a micro-operation field
of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status
bits in the inputs of the MUX.
Load 1
• Control
D O
Increment
Address Register
Control
Memory
MUX
Y 113
I
Status Bitsi 8 Micro
X
operations
How many bits are there in the X and Y fields, and what is the size of the control
memory in number of words?
Q3(d) A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode(ID), (7)
Operand Fetch(OF), Perform Operation(PO) and Write Operand(WO) stages. The
IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage
takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL
instruction, and 6 clock cycles for DIV instruction respectively. Operand
forwarding is used in the pipeline. What is the number of clock cycles needed to
execute the following sequence of instructions?
Instruction Meaning of instruction
10: MUL R2 ,R0 ,R1 R2 <— RO *R1
Il: DIV R5 ,R3 ,R4 R5 +- R3/R4
12:ADD R2 ,R5 ,R2 R2 <— R5+R2
13:SUB R5 ,R2 ,R6 R5 <— R2-R6
Q4(a) An 8-bit computer has register R1 having value #D6 (in hexadecimal). Determine (6)
the values of C, S, Z, and V (status flags) after the execution of following instructions
using immediate addressing mode by assuming input as in hexadecimal:
(i) AND R1, #75 (ii) ADD R1, #FF (iii) SUB R1, #B7
Q4(b) How many characters per second can be transmitted over a 1200-baud line in each (6)
of the following modes? (Assume a character code of eight bits.)
(i) Synchronous serial transmission
(ii) Asynchronous serial transmission with two stop bits.
(iii) Asynchronous serial transmission with one stop bit.
Q4(c) Describe the instruction format for CPSR in ARM 7.0. (5)
Q4(d) Differentiate between the following: (3,5)
(i) Programmed I/O and interrupt initiated I/O modes of transfer.
(ii) BUN and BSA memory reference instructions with diagram.
Note The students can see their evaluated answer sheets on 24th Dec. 2019 at 1:00 p.m. in
LP105, LP106, LP104 and LP103.
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