Electronic Devices

Final Term
Lecture - 06

Reference book:
Electronic Devices and Circuit Theory (Chapter-7)
Robert L. Boylestad and L. Nashelsky , (11th Edition)

Faculty of Engineering
American International University-Bangladesh
OBJECTIVES
• Be able to perform a dc analysis of JFET, MOSFET, and MESFET
networks.

• Become proficient in the use of load-line analysis to examine FET

• Develop confidence in the dc analysis of networks with both FETs and

• Understand how to use the Universal JFET Bias Curve to analyze the
various FET configurations.

Faculty of Engineering
American International University-Bangladesh
 GENERAL RELATIONSHIPS

• For all FETs: IG  0A ID = IS

• BJT: Linear Relationship between IB and IC

• FET: Non-linear Relationship between VGS and ID.

Faculty of Engineering
American International University-Bangladesh
 COMMON FET BIASING CIRCUITS
• JFET
• Fixed – Bias
• Self-Bias
• Voltage-Divider Bias

• Depletion-Type MOSFET
• Self-Bias
• Voltage-Divider Bias

• Enhancement-Type MOSFET
• Feedback Configuration
• Voltage-Divider Bias

Faculty of Engineering
American International University-Bangladesh
 FIXED-BIAS JFET
• The simplest biasing arrangements:

IG  0A ID = IS
VGS 2
ID = IDSS(1− )
VP
• For the DC analysis,
• Capacitors are open circuits

IG  0A V RG = I G RG = (0 A) RG = 0V
• The zero-volt drop across RG permits replacing
RG by a short-circuit.

Faculty of Engineering
American International University-Bangladesh
 FIXED-BIAS JFET

• Can be solved using either Mathematical Approach or Graphical Approach:

Mathematical Approach Graphical Approach

VDS = VDD − I D RD

VS = 0

VD = VDS

VG = VGS

VGS 2
I D = I DSS (1 − )
VP

Faculty of Engineering
American International University-Bangladesh
FIXED-BIAS JFET EXAMPLE

• Determine VGSQ, IDQ, VDS, VD, VG, VS.

Faculty of Engineering
American International University-Bangladesh
FIXED-BIAS JFET EXAMPLE

Graphical Approach

VGS ID
0 IDSS
0.3VP IDSS/2
0.5VP IDSS/4
VP 0mA

Faculty of Engineering
American International University-Bangladesh
 JFET: SELF-BIAS CONFIGURATION

• The self-bias configuration eliminates the need for two dc supplies.

IG  0A

ID = IS

VGS 2
ID = IDSS(1− )
VP

Faculty of Engineering
American International University-Bangladesh
SELF-BIAS CONFIGURATION

• Can be solved using either Mathematical Approach or Graphical Approach:

VGS = − I D RS

VDS = VDD − I D ( RS + RD )
2
 V 
I D = I DSS 1 − GS 
 VP 
2
 I R 
I D = I DSS 1 + D S 
 VP 

Faculty of Engineering
American International University-Bangladesh
SELF-BIAS CONFIGURATION
Graphical Approach
• Draw the device transfer characteristic using shorthand method.
• Draw the network load line
• Use VGS = − I D RS to draw straight line.
• First point, I D = 0, VGS = 0
• Second point, any point from ID = 0 to ID = IDSS. Choose
I DSS
ID = then
2
I R
VGS = − DSS S
2

• The Q-point obtained at the intersection of the straight line plot and the device
characteristic curve.
• The quiescent value for ID and VGS can then be determined and used to find the other
quantities of interest.

Faculty of Engineering
American International University-Bangladesh
 SELF-BIAS CONFIGURATION

Faculty of Engineering
American International University-Bangladesh
SELF-BIAS EXAMPLE
Determine VGSQ, IDQ,VDS,VS,VG and VD.

VGS = − I D RS

VDS = VDD − I D ( RS + RD )
2
 V 
I D = I DSS 1 − GS 
 VP 
2
 I R 
ID = I DSS 1 + D S 
 VP 
VGS = − I D RS
VGS = -2.6 mA x 1 k
= -2.6 V
Faculty of Engineering
American International University-Bangladesh
 End of
Lecture-6

Faculty of Engineering
American International University-Bangladesh