FET Biasing

From Chapter 7 of Electronic Devices and Circuit Theory, Eleventh Edition. Robert L. Boylestad,
Louis Nashelsky. Copyright © 2013 by Pearson Education, Inc. All rights reserved.

433
 FET Biasing

Chapter ObjeCtives
l
l Be able to perform a dc analysis of JFET, MOSFET, and MESFET networks.
l Become proficient in the use of load-line analysis to examine FET networks.
l Develop confidence in the dc analysis of networks with both FETs and BJTs.
l Understand how to use the Universal JFET Bias Curve to analyze the various FET
configurations.

1 intrOduCtiOn
l
The biasing levels for a silicon transistor configuration can be obtained using the
approximate characteristic equations VBE = 0.7 V, IC = bIB, and IC  IE. The link
between input and output variables is provided by b, which is assumed to be fixed in
magnitude for the analysis to be performed. The fact that beta is a constant establishes
a linear relationship between IC and IB. Doubling the value of IB will double the level
of IC, and so on.
For the field-effect transistor, the relationship between input and output quantities is
nonlinear due to the squared term in Shockley’s equation. Linear relationships result in
straight lines when plotted on a graph of one variable versus the other, whereas nonlinear
functions result in curves as obtained for the transfer characteristics of a JFET. The nonlin-
ear relationship between ID and VGS can complicate the mathematical approach to the dc
analysis of FET configurations. A graphical approach may limit solutions to tenths-place
accuracy, but it is a quicker method for most FET amplifiers. Since the graphical approach
is in general the most popular, the analysis of this chapter will have graphical solutions
rather than mathematical solutions.
Another distinct difference between the analysis of BJT and FET transistors is that:

The controlling variable for a BJT transistor is a current level, whereas for the FET a
voltage is the controlling variable.

In both cases, however, the controlled variable on the output side is a current level that also
defines the important voltage levels of the output circuit.

434
 The general relationships that can be applied to the dc analysis of all FET amplifiers are FET Biasing

IG  0 A (1)

and ID = IS (2)

For JFETs and depletion-type MOSFETs and MESFETs, Shockley’s equation is applied
to relate the input and output quantities:

VGS 2
ID = IDSS a 1 - b (3)
VP

For enhancement-type MOSFETs and MESFETs, the following equation is applicable:

ID = k(VGS - VT)2 (4)

It is particularly important to realize that all of the equations above are for the
field-effect transistor only! They do not change with each network configuration so
long as the device is in the active region. The network simply defines the level of cur-
rent and voltage associated with the operating point through its own set of equations.
In reality, the dc solution of BJT and FET networks is the solution of simultaneous
equations established by the device and the network. The solution can be determined
using a mathematical or graphical approach—a fact to be demonstrated by the first few
networks to be analyzed. However, as noted earlier, the graphical approach is the most
popular for FET networks.
The first few sections of this chapter are limited to JFETs and the graphical approach
to analysis. The depletion-type MOSFET will then be examined with its increased range
of operating points, followed by the enhancement-type MOSFET. Finally, problems of a
design nature are investigated to fully test the concepts and procedures introduced in the
chapter.

2 Fixed-bias COnFiguratiOn
l
The simplest of biasing arrangements for the n-channel JFET appears in Fig. 1. Referred to
as the fixed-bias configuration, it is one of the few FET configurations that can be solved
just as directly using either a mathematical or a graphical approach. Both methods are
included in this section to demonstrate the difference between the two methods and also to
establish the fact that the same solution can be obtained using either approach.

Fig. 1
Fixed-bias configuration.

435
 FET Biasing The configuration of Fig. 1 includes the ac levels Vi and Vo and the coupling capacitors
(C1 and C2). Recall that the coupling capacitors are “open circuits” for the dc analysis and
low impedances (essentially short circuits) for the ac analysis. The resistor RG is present
to ensure that Vi appears at the input to the FET amplifier for the ac analysis. For the dc
analysis,
IG  0 A
and VRG = IG RG = (0 A)RG = 0 V
The zero-volt drop across RG permits replacing RG by a short-circuit equivalent, as appear-
ing in the network of Fig. 2, specifically redrawn for the dc analysis.
The fact that the negative terminal of the battery is connected directly to the defined
positive potential of VGS clearly reveals that the polarity of VGS is directly opposite to that
of VGG. Applying Kirchhoff’s voltage law in the clockwise direction of the indicated loop
of Fig. 2 results in
-VGG - VGS = 0

and VGS = -VGG (5)

Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the des-
ignation “fixed-bias configuration.”
The resulting level of drain current ID is now controlled by Shockley’s equation:
VGS 2
ID = IDSS a 1 - b
VP
Fig. 2
Network for dc analysis.
Since VGS is a fixed quantity for this configuration, its magnitude and sign can simply be
substituted into Shockley’s equation and the resulting level of ID calculated. This is one of
the few instances in which a mathematical solution to a FET configuration is quite direct.
A graphical analysis would require a plot of Shockley’s equation as shown in Fig. 3.
Recall that choosing VGS = VP >2 will result in a drain current of IDSS >4 when plotting
the equation. For the analysis of this chapter, the three points defined by IDSS, VP, and the
intersection just described will be sufficient for plotting the curve.

ID (mA) ID (mA)

IDSS IDSS
Device

Network

Q-point
(solution) ID
Q
IDSS
4

VP VP 0 VGS VP VGSQ = –VGG 0 VGS

2

Fig. 3 Fig. 4
Plotting Shockley’s equation. Finding the solution for the fixed-bias
configuration.

In Fig. 4, the fixed level of VGS has been superimposed as a vertical line at VGS = -VGG.
At any point on the vertical line, the level of VGS is -VGG—the level of ID must simply be
determined on this vertical line. The point where the two curves intersect is the common
solution to the configuration—commonly referred to as the quiescent or operating point.
The subscript Q will be applied to the drain current and gate-to-source voltage to identify
their levels at the Q-point. Note in Fig. 4 that the quiescent level of ID is determined by
drawing a horizontal line from the Q-point to the vertical ID axis. It is important to realize

436
that once the network of Fig. 1 is constructed and operating, the dc levels of ID and VGS FET Biasing
that will be measured by the meters of Fig. 5 are the quiescent values defined by Fig. 4.

IDQ

VDD Ammeter

RD
VGSQ

Voltmeter
G

– S
VGG
+

Fig. 5
Measuring the quiescent values of ID and VGS.

The drain-to-source voltage of the output section can be determined by applying

Kirchhoff’s voltage law as follows:

+VDS + IDRD - VDD = 0

and VDS = VDD - ID RD (6)

Recall that single-subscript voltages refer to the voltage at a point with respect to ground.
For the configuration of Fig. 2,

VS = 0 V (7)

Using double-subscript notation, we have

VDS = VD - VS
or VD = VDS + VS = VDS + 0 V

and VD = VDS (8)

In addition, VGS = VG - VS
or VG = VGS + VS = VGS + 0 V

and VG = VGS (9)

The fact that VD = VDS and VG = VGS is fairly obvious from the fact that VS = 0 V,
but the derivations above were included to emphasize the relationship that exists between
double-subscript and single-subscript notation. Since the configuration requires two dc sup-
plies, its use is limited and will not be included in the forthcoming list of the most common
FET configurations.

437
 FET Biasing
exaMpLe 1 Determine the following for the network of Fig. 6:
a. VGSQ. 16 V
b. IDQ.
c. VDS.
d. VD. 2 kΩ
e. VG.
f. VS.
D

G I DSS = 10 mA
+ VP = –8 V
VGS
1 MΩ – S
–
2V
+

Fig. 6
Example 1.

Solution:
Mathematical approach
a. VGSQ = -VGG = 22 V
VGS 2 -2 V 2
b. IDQ = IDSS a 1 - b = 10 mA a 1 - b
VP -8 V
2 2
= 10 mA(1 - 0.25) = 10 mA(0.75) = 10 mA(0.5625)
= 5.625 mA
c. VDS = VDD - ID RD = 16 V - (5.625 mA)(2 kV)
= 16 V - 11.25 V = 4.75 V
d. VD = VDS = 4.75 V
e. VG = VGS = 22 V
f. VS = 0 V

graphical approach The resulting Shockley curve and the vertical line at VGS = -2 V
are provided in Fig. 7. It is certainly difficult to read beyond the second place without

ID (mA)

IDSS = 10 mA
9
8
7
6
Q-point I D = 5.6 mA
Q
5
4
3 IDSS = 2.5 mA
2 4

–8 –7 – 6 –5 – 4 – 3 –2 –1 0 VGS
VP = –8 V VP V = –V = –2 V
= –4 V GS Q GG
2

Fig. 7
Graphical solution for the network of Fig. 6.

438
significantly increasing the size of the figure, but a solution of 5.6 mA from the graph of FET Biasing
Fig. 7 is quite acceptable.
a. Therefore,
VGSQ = -VGG = 22 V
b. IDQ = 5.6 mA
c. VDS = VDD - ID RD = 16 V - (5.6 mA)(2 kV)
= 16 V - 11.2 V = 4.8 V
d. VD = VDS = 4.8 V
e. VG = VGS = 22 V
f. VS = 0 V
The results clearly confirm the fact that the mathematical and graphical approaches
generate solutions that are quite close.

3 seLF-bias COnFiguratiOn
l
The self-bias configuration eliminates the need for two dc supplies. The controlling gate-
to-source voltage is now determined by the voltage across a resistor RS introduced in the
source leg of the configuration as shown in Fig. 8.

Fig. 8
JFET self-bias configuration.

For the dc analysis, the capacitors can again be replaced by “open circuits” and the resis-
tor RG replaced by a short-circuit equivalent since IG = 0 A. The result is the network of
Fig. 9 for the important dc analysis.
The current through RS is the source current IS, but IS = ID and
VRS = ID RS
For the indicated closed loop of Fig. 9, we find that
-VGS - VRS = 0
and VGS = -VRS
Fig. 9
DC analysis of the self-bias
or VGS = -IDRS (10) configuration.

Note in this case that VGS is a function of the output current ID and not fixed in magnitude
as occurred for the fixed-bias configuration.
Equation (10) is defined by the network configuration, and Shockley’s equation relates
the input and output quantities of the device. Both equations relate the same two variables,
ID and VGS, permitting either a mathematical or a graphical solution.

439
 FET Biasing A mathematical solution could be obtained simply by substituting Eq. (10) into Shock-
ley’s equation as follows:
VGS 2
ID = IDSS a 1 - b
VP
-ID RS 2
= IDSS a 1 - b
VP
ID RS 2
or ID = IDSS a 1 + b
VP
By performing the squaring process indicated and rearranging terms, we obtain an equation
of the following form:
I2D + K1ID + K2 = 0
The quadratic equation can then be solved for the appropriate solution for ID.
The sequence above defines the mathematical approach. The graphical approach re-
quires that we first establish the device transfer characteristics as shown in Fig. 10. Since
Eq. (10) defines a straight line on the same graph, let us now identify two points on the graph
that are on the line and simply draw a straight line between the two points. The most obvi-
ous condition to apply is ID = 0 A since it results in VGS = -ID RS = (0 A)RS = 0 V. For
Eq. (10), therefore, one point on the straight line is defined by ID = 0 A and VGS = 0 V,
as appearing on Fig. 10.

IDSS
4
VGS = 0 V, ID = 0 A (VGS = –ID RS)

VP
2

Fig. 10
Defining a point on the self-bias line.

The second point for Eq. (10) requires that a level of VGS or ID be chosen and the cor-
responding level of the other quantity be determined using Eq. (10). The resulting levels
of ID and VGS will then define another point on the straight line and permit the drawing of
the straight line. Suppose, for example, that we choose a level of ID equal to one-half the
saturation level. That is,
IDSS
ID =
2
IDSS RS
Then VGS = -ID RS = -
2
The result is a second point for the straight-line plot as shown in Fig. 11. The straight line
as defined by Eq. (10) is then drawn and the quiescent point obtained at the intersection of
the straight-line plot and the device characteristic curve. The quiescent values of ID and
VGS can then be determined and used to find the other quantities of interest.
The level of VDS can be determined by applying Kirchhoff’s voltage law to the output
circuit, with the result that
VRS + VDS + VRD - VDD = 0
and VDS = VDD - VRS - VRD = VDD - IS RS - ID RD

440
 ID FET Biasing
IDSS

IDSS
2
Q-point
ID
Q

VP VGSQ 0 VGS
I R
VGS = _ DSS S
2

Fig. 11
Sketching the self-bias line.

but ID = IS

and VDS = VDD - ID(RS + RD) (11)

In addition,
VS = ID RS (12)

VG = 0 V (13)

and VD = VDS + VS = VDD - VRD (14)

exaMpLe 2 Determine the following for the network of Fig. 12:

a. VGSQ.
b. IDQ.
c. VDS.
RD
d. VS.
e. VG.
f. VD.

RG

Fig. 12
Example 2.

Solution:
a. The gate-to-source voltage is determined by
VGS = -IDRS
Choosing ID = 4 mA, we obtain
VGS = -(4 mA)(1 kV) = -4 V
The result is the plot of Fig. 13 as defined by the network.

441
 FET Biasing ID = 8 mA, VGS = –8 V
ID (mA)
8
7
ID = 4 mA, VGS = – 4V
6
Network
5
4
3
2
1 V = 0 V, I = 0 mA
GS D

– 8 –7 – 6 – 5 – 4 – 3 –2 – 1 0 VGS (V)

Fig. 13
Sketching the self-bias line for the network of Fig. 12.

If we happen to choose ID = 8 mA, the resulting value of VGS would be -8 V, as

shown on the same graph. In either case, the same straight line will result, clearly dem-
onstrating that any appropriate value of ID can be chosen as long as the corresponding
value of VGS as determined by Eq. (10) is employed. In addition, keep in mind that the
value of VGS could be chosen and the value of ID determined graphically.
For Shockley’s equation, if we choose VGS = VP >2 = -3 V, we find that
ID = IDSS >4 = 8 mA>4 = 2 mA, and the plot of Fig. 14 will result, representing the
characteristics of the device. The solution is obtained by superimposing the network
characteristics defined by Fig. 13 on the device characteristics of Fig. 14 and finding the
point of intersection of the two as indicated on Fig. 15. The resulting operating point
results in a quiescent value of gate-to-source voltage of
VGSQ = 22.6 V

ID (mA)

8
7
6
5
4
3
Q-point I D = 2.6 mA
Q
2
1

– 6 – 5 – 4 – 3 –2 –1 0 VGS (V)
VGSQ = – 2.6 V

Fig. 14 Fig. 15
Sketching the device characteristics for the Determining the Q-point for the network of
JFET of Fig. 12. Fig. 12.

b. At the quiescent point

IDQ = 2.6 mA
c. Eq. (11): VDS = VDD - ID (RS + RD)
= 20 V - (2.6 mA)(1 kV + 3.3 kV)
= 20 V - 11.18 V
= 8.82 V

442
d. Eq. (12): VS = IDRS FET Biasing
= (2.6 mA)(1 kV)
= 2.6 V
e. Eq. (13): VG = 0 V
f. Eq. (14): VD = VDS + VS = 8.82 V + 2.6 V = 11.42 V
or VD = VDD - ID RD = 20 V - (2.6 mA)(3.3 kV) = 11.42 V

exaMpLe 3 Find the quiescent point for the network of Fig. 12 if:
a. RS = 100 V.
b. RS = 10 kV.

Solution: Both RS 5 100 V and RS 5 10 kV are plotted on Fig. 16.

a. For RS 5 100 V:
IDQ  6.4 mA
and from Eq. (10),
VGSQ  20.64 V
b. For RS = 10 kV
VGSQ  24.6 V
and from Eq. (10),
IDQ  0.46 mA
In particular, note how lower levels of RS bring the load line of the network closer to the
ID axis, whereas increasing levels of RS bring the load line closer to the VGS axis.

ID (mA)

8
RS = 100 Ω 7
I D = 4 mA, VGS = – 0.4 V Q-point I D ≅ 6.4 mA
6 Q

5
4
RS = 10 kΩ
VGS = –4 V, ID = 0.4 mA 3
2
Q-point 1

– 6 – 5 – 4 – 3 –2 –1 0 VGS (V)
VGSQ ≅ – 4.6 V

Fig. 16
Example 3.

4 vOLtage-divider biasing
l
The voltage-divider bias arrangement applied to BJT transistor amplifiers is also applied to
FET amplifiers as demonstrated by Fig. 17. The basic construction is exactly the same, but
the dc analysis of each is quite different. IG = 0 A for FET amplifiers, but the magnitude
of IB for common-emitter BJT amplifiers can affect the dc levels of current and voltage in
both the input and output circuits. Recall that IB provides the link between input and output
circuits for the BJT voltage-divider configuration, whereas VGS does the same for the FET
configuration.

443
 FET Biasing

Fig. 17
Voltage-divider bias arrangement.

The network of Fig. 17 is redrawn as shown in Fig. 18 for the dc analysis. Note that all
the capacitors, including the bypass capacitor CS, have been replaced by an “open-circuit”
equivalent in Fig. 18b. In addition, the source VDD was separated into two equivalent
sources to permit a further separation of the input and output regions of the network.
Since IG = 0 A, Kirchhoff’s current law requires that IR1 = IR2, and the series equivalent
circuit appearing to the left of the figure can be used to find the level of VG. The volt-
age VG, equal to the voltage across R2, can be found using the voltage-divider rule and
Fig. 18a as follows:

R2VDD
VG = (15)
R1 + R2

VDD VDD VDD

RD
R1 R1
ID
D
IG ≅ 0 A
G
VG
+
+ + VGS –S IS

R2 R2 VG
+
VRS RS
– –
–
(a) (b)

Fig. 18
Redrawn network of Fig. 17 for dc analysis.

Applying Kirchhoff’s voltage law in the clockwise direction to the indicated loop of
Fig. 18 results in

VG - VGS - VRS = 0
and VGS = VG - VRS

444
Substituting VRS = IS RS = ID RS, we have FET Biasing

VGS = VG - ID RS (16)

The result is an equation that continues to include the same two variables appearing in
Shockley’s equation: VGS and ID. The quantities VG and RS are fixed by the network con-
struction. Equation (16) is still the equation for a straight line, but the origin is no longer
a point in the plotting of the line. The procedure for plotting Eq. (16) is not a difficult one
and will proceed as follows. Since any straight line requires two points to be defined, let us
first use the fact that anywhere on the horizontal axis of Fig. 19 the current ID = 0 mA. If
we therefore select ID to be 0 mA, we are in essence stating that we are somewhere on the
horizontal axis. The exact location can be determined simply by substituting ID = 0 mA
into Eq. (16) and finding the resulting value of VGS as follows:
VGS = VG - IDRS
= VG - (0 mA)RS

and VGS = VG 0 ID = 0 mA (17)

The result specifies that whenever we plot Eq. (16), if we choose ID = 0 mA, the value of
VGS for the plot will be VG volts. The point just determined appears in Fig. 19.

IDQ

VGSQ

Fig. 19
Sketching the network equation for the voltage-divider configuration.

For the other point, let us now employ the fact that at any point on the vertical axis VGS = 0 V
and solve for the resulting value of ID:
VGS = VG - IDRS
0 V = VG - IDRS

VG
and ID = ` (18)
RS VGS = 0 V

The result specifies that whenever we plot Eq. (16), if VGS = 0 V, the level of ID is deter-
mined by Eq. (18). This intersection also appears on Fig. 19.
The two points defined above permit the drawing of a straight line to represent Eq. (16).
The intersection of the straight line with the transfer curve in the region to the left of the verti-
cal axis will define the operating point and the corresponding levels of ID and VGS.
Since the intersection on the vertical axis is determined by ID = VG >RS and VG is fixed
by the input network, increasing values of RS will reduce the level of the ID intersection as

445
 FET Biasing

Fig. 20
Effect of RS on the resulting Q-point.

shown in Fig. 20. It is fairly obvious from Fig. 20 that:

Increasing values of RS result in lower quiescent values of ID and declining values
of VGS.
Once the quiescent values of IDQ and VGSQ are determined, the remaining network analy-
sis can be performed in the usual manner. That is,

VDS = VDD - ID(RD + RS) (19)

VD = VDD - ID RD (20)
VS = ID RS (21)
VDD
IR1 = IR2 = (22)
R1 + R2

exaMpLe 4 Determine the following for the network of Fig. 21:

a. IDQ and VGSQ.
b. VD.
c. VS.
d. VDS.
e. VDG. RD
R1

D
C1 C2
G

R2
RS CS

Fig. 21
Example 4.

446
Solution: FET Biasing
a. For the transfer characteristics, if ID = IDSS >4 = 8 mA>4 = 2 mA, then VGS =
VP >2 = -4 V>2 = -2 V. The resulting curve representing Shockley’s equation
appears in Fig. 22. The network equation is defined by
R2VDD
VG =
R1 + R2
(270 kV)(16 V)
=
2.1 MV + 0.27 MV
= 1.82 V
and VGS = VG - IDRS
= 1.82 V - ID(1.5 kV)

ID (mA)
8 (I DSS )
7
6
5
4
3
Q-point I D = 2.4 mA
2 Q
I D = 1.21 mA ( VGS = 0 V)
1

–4 –3 –2 –1 0 1 2 3
(VP) VGSQ = –1.8 V VG = 1.82 V
( I D = 0 mA )
Fig. 22
Determining the Q-point for the network of Fig. 21.

When ID = 0 mA,
VGS = +1.82 V
When VGS = 0 V,
1.82 V
ID = = 1.21 mA
1.5 kV
The resulting bias line appears on Fig. 22 with quiescent values of
IDQ = 2.4 mA
and VGSQ = 21.8 V
b. VD = VDD - IDRD
= 16 V - (2.4 mA)(2.4 kV)
= 10.24 V
c. VS = IDRS = (2.4 mA)(1.5 kV)
= 3.6 V
d. VDS = VDD - ID(RD + RS)
= 16 V - (2.4 mA)(2.4 kV + 1.5 kV)
= 6.64 V
or VDS = VD - VS = 10.24 V - 3.6 V
= 6.64 V

447
 FET Biasing e. Although seldom requested, the voltage VDG can easily be determined using
VDG = VD - VG
= 10.24 V - 1.82 V
= 8.42 V

5 COMMOn-gate COnFiguratiOn
l
The next configuration is one in which the gate terminal is grounded and the input signal
typically applied to the source terminal and the output signal obtained at the drain terminal
as shown in Fig. 23a. The network can also be drawn as shown in Fig. 23b.

VDD
ID

RD
C2 I DSS
D Vo VP
C1 C2
G S D
I DSS Vi Vo
VP

S Vi RS G RD
C1
RS
– +
VSS
+ –VDD
VSS
(a) (b)

Fig. 23
Two versions of the common-gate configuration.

The network equation can be determined using Fig. 24.

Applying Kirchhoff’s voltage law in the direction shown in Fig. 24 will result in
-VGS - ISRS + VSS = 0
and VGS = VSS - ISRS
but IS = ID

so VGS = VSS - ID RS (23)

Applying the condition ID = 0 mA to Eq. 23 will result in

VGS = VSS - (0)RS

and VGS = VSS 0 ID = 0mA (24)

Fig. 24
Determining the network
equation for the configuration of Applying the condition VGS = 0 V to Eq. 23 will result in
Fig. 23. 0 = VSS - IDRS

VSS
and ID = ` (25)
RS VGS = 0 V

The resulting load-line appears in Fig. 25 intersecting the transfer curve for the JFET as
shown in the figure.
The resulting intersection defines the operating current IDQ and voltage VDQ for the net-
work as also indicated in the network.

448
 ID (mA) FET Biasing
IDSS

Q-point ID
Q
VSS
ID =
RS

VP 0
VGSQ VSS
( I D = 0 mA )
Fig. 25
Determining the Q-point for the network of Fig. 24.

Applying Kirchhoff’s voltage law around the loop containing the two sources, the JFET
and the resistors RD and RS in Fig. 23a and Fig. 23b will result in
+VDD - IDRD - VDS - ISRS + VSS = 0
Substituting IS = ID we have
+VDD + VSS - VDS - ID(RD + RS) = 0

so that VDS = VDD + VSS - ID(RD + RS) (26)

with VD = VDD - ID RD (27)

and VS = -VSS + ID RS (28)

exaMpLe 5 Determine the following for the common-gate configuration of Fig. 26:
a. VGSQ
b. IDQ
c. VD
d. VG
e. VS
f. VDS

RD

C2

C1

RS

Fig. 26
Example 5.

449
 FET Biasing Solution: Even though VSS is not present in this common-gate configuration the equa-
tions derived above can still be used by simply substituting VSS = 0 V into each equation
in which it appears.
a. For the transfer characteristics Eq. 23 becomes
VGS = 0 - IDRS
and VGS = -IDRS
For this equation the origin is one point on the load line while the other must be
determined at some arbitrary point. Choosing ID = 6 mA and solving for VGS will
result in the following:
VGS = -IDRS = -(6 mA)(680 V) = -4.08 V
as shown in Fig. 27.

ID (mA)

12 I DSS
11
10
9
8
7
6
5
4
Q-point I D ≅ 3.8 mA
Q
3
2
1

–6 –5 –4 –3 –2 –1 0
VP VGSQ ≅ –2.6 V

Fig. 27
Determining the Q-point for the network of Fig. 26.

The device transfer curve is sketched using

IDSS 12 mA
ID = = = 3 mA(at VP >2)
4 4
and VGS  0.3VP = 0.3(-6 V) = -1.8 V (at ID = IDSS >2)
The resulting solution is:
VGSQ  22.6 V
b. From Fig. 27,
IDQ  3.8 mA
c. VD = VDD - IDRD
= 12 V - (3.8 mA)(1.5 kV) = 12 V - 5.7 V
= 6.3 V
d. VG = 0 V
e. VS = ID RS = (3.8 mA)(680 V)
= 2.58 V
f. VDS = VD - VS
= 6.3 V - 2.58 V
= 3.72 V

450
6 speCiaL Case: VGSQ 5 0 v FET Biasing
l
A network of recurring practical value because of its relative simplicity is the configuration
of Fig. 28. Note that direct connection of the gate and source terminals to ground resulting in
VGS = 0 V. It specifies that for any dc condition the gate to source voltage must be zero
volts. This will result in a vertical load line at VGSQ = 0 V as shown in Fig. 29.

ID
VDD

Q-point IDSS

RD

D
G I DSS
+ VP
VGSQ = 0V load line
VGS – S

VP 0 VGS

Fig. 28 Fig. 29
Special case VGSQ = 0 V Finding the Q-point for the network of Fig. 28.
configuration.

Since the transfer curve of a JFET will cross the vertical axis at IDSS the drain current
for the network is set at that level.

Therefore, IDQ = IDSS (29)

Applying Kirchhoff’s voltage law:

VDD - IDRD - VDS = 0

and VDS = VDD - IDRD (30)

with VD = VDS (31)

and VS = 0 V (32)

7 depLetiOn-type MOsFets
l
The similarities in appearance between the transfer curves of JFETs and depletion-type
MOSFETs permit a similar analysis of each in the dc domain. The primary difference
between the two is the fact that depletion-type MOSFETs permit operating points with posi-
tive values of VGS and levels of ID that exceed IDSS. In fact, for all the configurations dis-
cussed thus far, the analysis is the same if the JFET is replaced by a depletion-type MOSFET.
The only undefined part of the analysis is how to plot Shockley’s equation for positive
values of VGS. How far into the region of positive values of VGS and values of ID greater than
IDSS does the transfer curve have to extend? For most situations, this required range will be
fairly well defined by the MOSFET parameters and the resulting bias line of the network.
A few examples will reveal the effect of the change in device on the resulting analysis.

exaMpLe 6 For the n-channel depletion-type MOSFET of Fig. 30, determine:

a. IDQ and VGSQ.
b. VDS.

451
 FET Biasing

RD
R1
C2
D Vo

G
Vi
C1
S

R2
RS

Fig. 30
Example 6.

Solution:
a. For the transfer characteristics, a plot point is defined by ID = IDSS >4 = 6 mA>4 = 1.5 mA
and VGS = VP >2 = -3 V>2 = -1.5 V. Considering the level of VP and the fact that
Shockley’s equation defines a curve that rises more rapidly as VGS becomes more positive,
a plot point will be defined at VGS = +1 V. Substituting into Shockley’s equation yields
VGS 2
ID = IDSS a 1 - b
VP
+1 V 2 1 2
= 6 mA a 1 - b = 6 mA a 1 + b = 6 mA (1.778)
-3 V 3
= 10.67 mA
The resulting transfer curve appears in Fig. 31. Proceeding as described for JFETs, we
have
10 MV(18 V)
Eq. (15): VG = = 1.5 V
10 MV + 110 MV
Eq. (16): VGS = VG - IDRS = 1.5 V - ID(750 V)

Fig. 31
Determining the Q-point for the network of Fig. 30.
452
 Setting ID = 0 mA results in FET Biasing
VGS = VG = 1.5 V
Setting VGS = 0 V yields
VG 1.5 V
ID = = = 2 mA
RS 750 V
The plot points and resulting bias line appear in Fig. 31. The resulting operating point
is given by
IDQ = 3.1 mA
VGSQ = 20.8 V
b. Eq. (19):
VDS = VDD - ID(RD + RS)
= 18 V - (3.1 mA)(1.8 kV + 750 V)
 10.1 V

exaMpLe 7 Repeat Example 6 with RS = 150 V.

Solution:
a. The plot points are the same for the transfer curve as shown in Fig. 32. For the bias line,
VGS = VG - ID RS = 1.5 V - ID (150 V)
Setting ID = 0 mA results in
VGS = 1.5 V
Setting VGS = 0 V yields
VG 1.5 V
ID = = = 10 mA
RS 150 V

Fig. 32
Example 7.

The bias line is included on Fig. 32. Note in this case that the quiescent point results in
a drain current that exceeds IDSS, with a positive value for VGS. The result is
IDQ = 7.6 mA
VGSQ = 0.35 V
b. Eq. (19):
VDS = VDD - ID(RD + RS)
= 18 V - (7.6 mA)(1.8 kV + 150 V)
= 3.18 V
453
 FET Biasing
exaMpLe 8 Determine the following for the network of Fig. 33:
a. IDQ and VGSQ.
b. VD.

20 V

RD 6.2 kΩ

C2
D Vo

I DSS = 8 mA
G
Vi VP = – 8 V
C1 S

RG 1 MΩ RS 2.4 kΩ

Fig. 33
Example 8.

Solution:
a. The self-bias configuration results in
VGS = -IDRS
as obtained for the JFET configuration, establishing the fact that VGS must be less than
0 V. There is therefore no requirement to plot the transfer curve for positive values of
VGS, although it was done on this occasion to complete the transfer characteristics. A
plot point for the transfer characteristics for VGS 6 0 V is
IDSS 8 mA
ID = = = 2 mA
4 4
VP -8 V
and VGS = = = -4 V
2 2
and for VGS 7 0 V, since VP = -8 V, we will choose
VGS = +2 V
VGS 2 +2 V 2
and ID = IDSS a 1 - b = 8 mA a 1 - b
VP -8 V
= 12.5 mA
The resulting transfer curve appears in Fig. 34. For the network bias line, at
VGS = 0 V, ID = 0 mA. Choosing VGS = -6 V gives
VGS -6 V
ID = - = - = 2.5 mA
RS 2.4 kV
The resulting Q-point is given by
IDQ = 1.7 mA
VGSQ = 24.3 V
b. VD = VDD - IDRD
= 20 V - (1.7 mA)(6.2 kV)
= 9.46 V
The example to follow employs a design that can also be applied to JFET transistors. At
first impression it appears rather simplistic, but in fact it often causes some confusion
when first analyzed due to the special point of operation.

454
 FET Biasing

Fig. 34
Determining the Q-point for the network of Fig. 33.

exaMpLe 9 Determine VDS for the network of Fig. 35.

Solution: The direct connection between the gate and source terminals requires that
VGS = 0 V +
IDSS = 10 mA
Since VGS is fixed at 0 V, the drain current must be IDSS (by definition). In other words, VDS
VP = –4 V
VGSQ = 0 V –
and IDQ = 10 mA
There is therefore no need to draw the transfer curve, and
VD = VDD - IDRD = 20 V - (10 mA)(1.5 kV)
= 20 V - 15 V
= 5V Fig. 35
Example 9.

8 enhanCeMent-type MOsFets
l
The transfer characteristics of the enhancement-type MOSFET are quite different from
those encountered for the JFET and depletion-type MOSFETs, resulting in a graphical
solution quite different from those of the preceding sections. First and foremost, recall that
for the n-channel enhancement-type MOSFET, the drain current is zero for levels of gate-
to-source voltage less than the threshold level VGS(Th), as shown in Fig. 36. For levels of
VGS greater than VGS(Th), the drain current is defined by

ID = k(VGS - VGS(Th))2 (33)

Since specification sheets typically provide the threshold voltage and a level of drain
current (ID(on)) and its corresponding level of VGS(on), two points are defined immedi-
ately as shown in Fig. 36. To complete the curve, the constant k of Eq. (33) must be
determined from the specification sheet data by substituting into Eq. (33) and solving for
k as follows:
ID = k(VGS - VGS(Th))2
ID(on) = k(VGS(on) - VGS(Th))2

455
 FET Biasing ID (mA)

ID2

ID = k (VGS – VGS(Th) )2

ID (on)

ID1

VGS(Th) VGS1 VGS2 VGS

ID = 0 mA VGS(on)

Fig. 36
Transfer characteristics of an n-channel enhancement-type MOSFET.

ID(on)
and k = (34)
(VGS(on) - VGS(Th))2

Once k is defined, other levels of ID can be determined for chosen values of VGS. Typically,
a point between VGS(Th) and VGS(on) and one just greater than VGS(on) will provide a sufficient
number of points to plot Eq. (33) (note ID1 and ID2 on Fig. 36).

Feedback biasing arrangement

A popular biasing arrangement for enhancement-type MOSFETs is provided in Fig. 37.
The resistor RG brings a suitably large voltage to the gate to drive the MOSFET “on.” Since
IG = 0 mA, VRG = 0 V and the dc equivalent network appears as shown in Fig. 38.

IG = 0 A
RG C2

C1

Fig. 37 Fig. 38
Feedback biasing arrangement. DC equivalent of the
network of Fig. 37.

A direct connection now exists between drain and gate, resulting in

VD = VG

and VDS = VGS (35)

For the output circuit,

VDS = VDD - IDRD

456
which becomes the following after substituting Eq. (27): FET Biasing

VGS = VDD - IDRD (36)

The result is an equation that relates ID to VGS, permitting the plot of both on the same set
of axes.
Since Eq. (36) is that of a straight line, the same procedure described earlier can be
employed to determine the two points that will define the plot on the graph. Substituting
ID = 0 mA into Eq. (36) gives

VGS = VDD 0 ID = 0 mA (37)

Substituting VGS = 0 V into Eq. (36), we have

VDD
ID = ` (38)
RD VGS = 0 V

The plots defined by Eqs. (33) and (36) appear in Fig. 39 with the resulting operating
point.

Fig. 39
Determining the Q-point for the network of Fig. 37.

exaMpLe 10 Determine IDQ and VDSQ for the enhancement-type MOSFET of Fig. 40.

RD

RG C2

C1
G

Fig. 40
Example 10.

457
 FET Biasing Solution:
plotting the transfer Curve Two points are defined immediately as shown in Fig. 41.
Solving for k, we obtain
ID(on)
Eq. (34): k =
(VGS(on) - VGS(Th))2
6 mA 6 * 10-3
= = A>V2
(8 V - 3 V)2 25
= 0.24 : 1023 A , V2

VGS = 10 V, ID = 11.76 mA

I D(on)

VGS = 6 V, ID = 2.16 mA

VGS(Th) VGS(on)

Fig. 41
Plotting the transfer curve for the MOSFET of Fig. 40.

For VGS = 6 V (between 3 and 8 V):

ID = 0.24 * 10-3(6 V - 3 V)2 = 0.24 * 10-3(9)
= 2.16 mA
as shown on Fig. 41. For VGS = 10 V (slightly greater than VGS(Th)),
ID = 0.24 * 10-3(10 V - 3 V)2 = 0.24 * 10-3(49)
= 11.76 mA
as also appearing on Fig. 41. The four points are sufficient to plot the full curve for the
range of interest as shown in Fig. 41.

For the network bias Line

VGS = VDD - IDRD
= 12 V - ID(2 kV)
Eq. (37): VGS = VDD = 12 V 0 ID = 0 mA
VDD 12 V
Eq. (38): ID = = = 6 mA 0 VGS = 0 V
RD 2 kV
The resulting bias line appears in Fig. 42.
At the operating point,
IDQ = 2.75 mA
and VGSQ = 6.4 V
with VDSQ = VGSQ = 6.4 V

458
 ID = mA FET Biasing

12
11
10
9
8
7
VDD
6
RD
5
4
I D = 2.75 mA 3 Q-point
Q
2
1

0 1 2 3 4 5 6 7 8 9 10 11 12 VGS
(VDD)
VGSQ = 6.4 V

Fig. 42
Determining the Q-point for the network of Fig. 40.

voltage-divider biasing arrangement

A second popular biasing arrangement for the enhancement-type MOSFET appears in
Fig. 43. The fact that IG = 0 mA results in the following equation for VGG as derived from
an application of the voltage-divider rule:

R2VDD
VG = (39)
R1 + R2 IG = 0 A

Applying Kirchhoff’s voltage law around the indicated loop of Fig. 43 results in
+ VGS –
+VG - VGS - VRS = 0
and VGS = VG - VRS

or VGS = VG - IDRS (40)

For the output section,

Fig. 43
VRS + VDS + VRD - VDD = 0 Voltage-divider biasing
and VDS = VDD - VRS - VRD arrangement for an n-channel
enhancement MOSFET.
or VDS = VDD - ID(RS + RD) (41)

Since the characteristics are a plot of ID versus VGS and Eq. (40) relates the same two
variables, the two curves can be plotted on the same graph and a solution determined at their
intersection. Once IDQ and VGSQ are known, all the remaining quantities of the network such
as VDS, VD, and VS can be determined.

exaMpLe 11 Determine IDQ, VGSQ, and VDS for the network of Fig. 44.
Solution:
network
R2VDD (18 MV)(40 V)
Eq. (39): VG = = = 18 V
R1 + R2 22 MV + 18 MV
Eq. (40): VGS = VG - IDRS = 18 V - ID(0.82 kV)

459
 FET Biasing

Fig. 44
Example 11.

When ID = 0 mA,
VGS = 18 V - (0 mA)(0.82 kV) = 18 V
as appearing on Fig. 45. When VGS = 0 V,
VGS = 18 V - ID(0.82 kV)
0 = 18 V - ID(0.82 kV)
18 V
ID = = 21.95 mA
0.82 kV
as appearing on Fig. 45.

ID (mA)

30

VG
= 21.95 mA
RS 20

10
I D ≅ 6.7 mA Q-point
Q

0 5 10 15 20 25 VGS
VGS (Th) VGSQ = 12.5 V VG = 18 V

Fig. 45
Determining the Q-point for the network of Example 11.

device
VGS(Th) = 5 V, ID(on) = 3 mA with VGS(on) = 10 V
ID(on)
Eq. (34): k =
(VGS(on) - VGS(Th))2
3 mA
= = 0.12 * 10-3 A>V2
(10 V - 5 V)2
and ID = k(VGS - VGS(Th))2
= 0.12 * 10-3(VGS - 5)2

460
which is plotted on the same graph (Fig. 45). From Fig. 45, FET Biasing
IDQ  6.7 mA
VGSQ = 12.5 V
Eq. (41): VDS = VDD - ID(RS + RD)
= 40 V - (6.7 mA)(0.82 kV + 3.0 kV)
= 40 V - 25.6 V
= 14.4 V

9 suMMary tabLe
l
Table 1 reviews the basic results and demonstrates the similarity in approach for a number
of FET configurations. It also reveals that the analysis of dc configurations for FETs is
fairly straightforward. Once the transfer characteristics are established, the network bias
line can be drawn and the Q-point determined at the intersection of the device transfer
characteristic and the network bias curve. The remaining analysis is simply an application
of the basic laws of circuit analysis.

10 COMbinatiOn netwOrks
l
Now that the dc analysis of a variety of BJT and FET configurations is established, the
opportunity to analyze networks with both types of devices presents itself. Fundamentally,
the analysis simply requires that we first approach the device that will provide a terminal
voltage or current level. The door is then usually open to calculating other quantities and
concentrating on the remaining unknowns. These are usually particularly interesting prob-
lems due to the challenge of finding the opening and then using the results of the past few
sections to find the important quantities for each device. The equations and relationships
used are simply those we have employed on more than one occasion—there is no need to
develop any new methods of analysis.

exaMpLe 12 Determine the levels of VD and VC for the network of Fig. 46.

RD

R1
G

RG

R2
RE

Fig. 46
Example 12.

461
 TABLE 1
FET Bias Configurations

Type Configuration Pertinent Equations Graphical Solution

VDD ID
RD IDSS
JFET VGSQ = -VGG
Fixed-bias RG VDS = VDD - IDRS Q-point
VGG –
+ VP VGG 0 VGS

ID
VDD
IDSS
RD
JFET VGS = -IDRS
I'D
Self-bias VDS = VDD - ID(RD + RS) Q-point
RG RS
VP V' 0 VGS
GS

VDD ID
RD R2VDD IDSS
JFET R1 VG =
R1 + R2 VG
Voltage-divider
VGS = VG - IDRS Q-point RS
bias R2 RS
VDS = VDD - ID(RD + RS)
VP 0 VG VGS

VDD ID
RD IDSS
JFET VGS = VSS - IDRS VSS
Q-point RS
Common-gate VDS = VDD + VSS - ID(RD + RS)
RS
–VSS VP 0 VSS VGS

ID
VDD VGS = -IDRS IDSS
RD
JFET VD = VDD
(RD = 0 V) VS = IDRS I'D
Q-point
VDS = VDD - ISRS
VP V'GS 0 VGS

VDD ID
RD Q-point IDSS
JFET
VGSQ = 0 V
Special case VGS = 0 V
IDQ = IDSS Q
(VGSQ = 0 V) RG
VGG
VP 0 VGS

ID
VDD
Depletion-type Q-point
MOSFET VGSQ = +VGG IDSS
Fixed-bias RG VDS = VDD - IDRS
RS
(and MESFETs)
VP 0 VGG VGS

VG ID
Depletion-type VDD R2VDD
MOSFET R1 RD VG = RS Q-point
R1 + R2 IDSS
Voltage-divider
R2 VGS = VG - ISRS
bias RS
VDS = VDD - ID(RD + RS)
(and MESFETs) VP 0 VG VGS

VDD ID
Enhancement VDD
RD RD
type MOSFET RG ID(on)
VGS = VDS
Feedback Q-point
VGS = VDD - IDRD
configuration
(and MESFETs) 0 VGS(Th) VDD VGS
VGS(on)

Enhancement VDD VG ID
R2VDD RS
type MOSFET R1
RD
VG =
Voltage-divider R1 + R2 Q-point
bias R2 RS VGS = VG - IDRS
(and MESFETs) 0 VGS(Th) VG VGS

462
Solution: From experience we now realize that VGS is typically an important quantity to FET Biasing
determine or write an equation for when analyzing JFET networks. Since VGS is a level for
which an immediate solution is not obvious, let us turn our attention to the transistor con-
figuration. The voltage-divider configuration is one where the approximate technique can
be applied (bRE = 180 * 1.6 kV = 288 kV 7 10R2 = 240 kV), permitting a determi-
nation of VB using the voltage-divider rule on the input circuit.
For VB,
24 kV(16 V)
VB = = 3.62 V
82 kV + 24 kV
Using the fact that VBE = 0.7 V results in
VE = VB - VBE = 3.62 V - 0.7 V
= 2.92 V
VRE VE 2.92 V
and IE = = = = 1.825 mA
RE RE 1.6 kV
with IC  IE = 1.825 mA
Continuing, we find for this configuration that
ID = IS = IC
and VD = 16 V - ID(2.7 kV)
= 16 V - (1.825 mA)(2.7 kV) = 16 V - 4.93 V
= 11.07 V
The question of how to determine VC is not as obvious. Both VCE and VDS are unknown
quantities, preventing us from establishing a link between VD and VC or from VE to VD. A
more careful examination of Fig. 46 reveals that VC is linked to VB by VGS (assuming that
VRG = 0 V). Since we know VB if we can find VGS, VC can be determined from
VC = VB - VGS
The question then arises as to how to find the level of VGSQ from the quiescent value of
ID. The two are related by Shockley’s equation:
VGSQ 2
IDQ = IDSS a 1 - b
VP
and VGSQ could be found mathematically by solving for VGSQ and substituting numerical
values. However, let us turn to the graphical approach and simply work in the reverse
order employed in the preceding sections. The JFET transfer characteristics are first
sketched as shown in Fig. 47. The level of IDQ = ISQ = ICQ = IEQ is then established by a
horizontal line as shown in the same figure. VGSQ is then determined by dropping a line
down from the operating point to the horizontal axis, resulting in
VGSQ = 23.7 V

ID (mA)

12 I DSS

10

Q-point 2
I D = 1.825 mA
Q
– 6 –5 –4 –3 –2 –1 0
VP
VGS ≅ – 3.7 V
Q

Fig. 47
Determining the Q-point for the network of Fig. 46.

463
 FET Biasing The level of VC is given by
VC = VB - VGSQ = 3.62 V - (-3.7 V)
= 7.32 V

exaMpLe 13 Determine VD for the network of Fig. 48.

Solution: In this case, there is no obvious path for determining a voltage or current level for
RC the transistor configuration. However, turning to the self-biased JFET, we can derive an equa-
RB
tion for VGS and determine the resulting quiescent point using graphical techniques. That is,
C VGS = -IDRS = -ID(2.4 kV)
B resulting in the self-bias line appearing in Fig. 49, which establishes a quiescent point at
VGSQ = -2.4 V
D, E
IDQ = 1 mA

ID (mA)
G 8 IDSS
S 7
6
RS 5
4
3
2 1.67 mA
Fig. 48 1 I D = 1 mA
Q
Example 13.
– 4 –3 –2 –1 0
VP
VGS = –2.4 V
Q

Fig. 49
Determining the Q-point for the network of Fig. 48.

For the transistor,

IE  IC = ID = 1 mA
IC 1 mA
and IB = = = 12.5 mA
b 80
VB = 16 V - IB(470 kV)
= 16 V - (12.5 mA)(470 kV) = 16 V - 5.88 V
= 10.12 V
and VE = VD = VB - VBE
= 10.12 V - 0.7 V
= 9.42 V
D
G
11 design
l
S The design process is a function of the area of application, level of amplification desired,
signal strength, and operating conditions. The first step is normally to establish the proper dc
levels of operation.
For example, if the levels of VD and ID are specified for the network of Fig. 50, the
level of VGSQ can be determined from a plot of the transfer curve and RS can then be de-
termined from VGS = -IDRS. If VDD is specified, the level of RD can then be calculated
Fig. 50 from RD = (VDD - VD)>ID. Of course, the values of RS and RD may not be standard
Self-bias configuration commercial values, requiring that the nearest commercial values be employed. However,
to be designed. with the tolerance (range of values) normally specified for the parameters of a network,

464
the slight variation due to the choice of standard values will seldom cause a real concern FET Biasing
in the design process.
The above is only one possibility for the design phase involving the network of Fig. 50. It
is possible that only VDD and RD are specified together with the level of VDS. The device to
be employed may have to be specified along with the level of RS. It appears logical that the
device chosen should have a maximum VDS greater than the specified value by a safe margin.
In general, it is good design practice for linear amplifiers to choose operating points
that do not crowd the saturation level (IDSS) or cutoff (VP) regions. Levels of VGSQ close to
VP >2 or levels of IDQ near IDSS >2 are certainly reasonable starting points in the design. Of
course, in every design procedure the maximum levels of ID and VDS as appearing on the
specification sheet must not be exceeded.
The examples to follow have a design or synthesis orientation in that specific levels are
provided and network parameters such as RD, RS, VDD, and so on, must be determined. In
any case, the approach is in many ways the opposite of that described in previous sections.
In some cases, it is just a matter of applying Ohm’s law in its appropriate form. In particular,
if resistive levels are requested, the result is often obtained simply by applying Ohm’s law
in the following form:

VR
Runknown = (42)
IR

where VR and IR are often parameters that can be found directly from the specified voltage
and current levels.

exaMpLe 14 For the network of Fig. 51, the levels of VDQ and IDQ are specified. Determine
the required values of RD and RS. What are the closest standard commercial values?
20 V
I D = 2.5 mA
Q
RD

VD = 12 V
G
I DSS = 6 mA
VP = – 3 V
S

RS

Fig. 51
Example 14.

Solution: As defined by Eq. (42),

ID (mA)
VRD VDD - VDQ
RD = = 6 IDSS
IDQ IDQ 5
20 V - 12 V 8V 4
and = = = 3.2 k 3
2.5 mA 2.5 mA I = 2.5 mA
2 DQ
Plotting the transfer curve in Fig. 52 and drawing a horizontal line at IDQ = 2.5 mA
1
results in VGSQ = -1 V, and applying VGS = -IDRS establishes the level of RS:
-(VGSQ ) -(-1 V) –3 –2 –1 0 VGS
RS = = = 0.4 k VP
IDQ 2.5 mA VGS = – 1 V
Q
The nearest standard commercial values are
Fig. 52
RD = 3.2 kV 1 3.3 k Determining VGSQ for the network
RS = 0.4 kV 1 0.39 k of Fig. 51.

465
 FET Biasing
exaMpLe 15 For the voltage-divider bias configuration of Fig. 53, if VD = 12 V and
VGSQ = -2 V, determine the value of RS.

RD
R1
D
G

S
R2
RS

Fig. 53
Example 15.

Solution: The level of VG is determined as follows:

47 kV(16 V)
VG = = 5.44 V
47 kV + 91 kV
VDD - VD
with ID =
RD
16 V - 12 V
= = 2.22 mA
1.8 kV
The equation for VGS is then written and the known values substituted:
VGS = VG - IDRS
-2 V = 5.44 V - (2.22 mA)RS
-7.44 V = -(2.22 mA)RS
7.44 V
and RS = = 3.35 k
2.22 mA
The nearest standard commercial value is 3.3 kV.

exaMpLe 16 The levels of VDS and ID are specified as VDS = 12VDD and ID = ID(on) for
the network of Fig. 54. Determine the levels of VDD and RD.
VDD
Solution: Given ID = ID(on) = 4 mA and VGS = VGS(on) = 6 V, for this configuration,
RD VDS = VGS = 12VDD
10 MΩ and 6 V = 12VDD
so that VDD = 12 V
VGS(on) = 6 V
I D(on) = 4 mA
Applying Eq. (42) yields
VGS(Th) = 3 V VRD VDD - VDS VDD - 21VDD 1
2 VDD
RD = = = =
ID ID(on) ID(on) ID(on)
6V
and RD = = 1.5 k
4 mA
Fig. 54 which is a standard commercial value.
Example 16.

466
12 trOubLeshOOting FET Biasing
l
How often has a network been carefully constructed only to find that when the power is
applied, the response is totally unexpected and fails to match the theoretical calculations?
What is the next step? Is it a bad connection? A misreading of the color code for a resistive
element? An error in the construction process? The range of possibilities seems vast and
often frustrating. The troubleshooting process first described in the analysis of BJT transis-
tor configurations should narrow down the list of possibilities and isolate the problem area
following a definite plan of attack. In general, the process begins with a rechecking of the
network construction and the terminal connections. This is usually followed by the check-
ing of voltage levels between specific terminals and ground or between terminals of the red
network. Seldom are current levels measured since such maneuvers require disturbing the
network structure to insert the meter. Of course, once the voltage levels are obtained, cur-
rent levels can be calculated using Ohm’s law. In any case, some idea of the expected volt-
age or current level must be known for the measurement to have any importance. In total,
therefore, the troubleshooting process can begin with some hope of success only if the black
basic operation of the network is understood along with some expected levels of voltage or
current. For the n-channel JFET amplifier, it is clearly understood that the quiescent value
of VGSQ is limited to 0 V or a negative voltage. For the network of Fig. 55, VGSQ is limited
to negative values in the range 0 V to VP. If a meter is hooked up as shown in Fig. 55, with
the positive lead (normally red) to the gate and the negative lead (usually black) to the
Fig. 55
source, the resulting reading should have a negative sign and a magnitude of a few volts.
Checking the dc operation of the
Any other response should be considered suspicious and needs to be investigated. JFET self-bias configuration.
The level of VDS is typically between 25% and 75% of VDD. A reading of 0 V for VDS
clearly indicates that either the output circuit has an “open” or the JFET is internally short-
circuited between drain and source. If VD is VDD volts, there is obviously no drop across RD,
due to the lack of current through RD, and the connections should be checked for continuity.
If the level of VDS seems inappropriate, the continuity of the output circuit can easily be
checked by grounding the negative lead of the voltmeter and measuring the voltage levels
from VDD to ground using the positive lead. If VD = VDD, the current through RD may be
zero, but there is continuity between VD and VDD. If VS = VDD, the device is not open be-
tween drain and source, but it is also not “on.” The continuity through to VS is confirmed,
however. In this case, it is possible that there is a poor ground connection between RS and
ground that may not be obvious. The internal connection between the wire of the lead and
the terminal connector may have separated. Other possibilities also exist, such as a shorted
device from drain to source, but the troubleshooter will simply have to narrow down the
possible causes for the malfunction.
The continuity of a network can also be checked simply by measuring the voltage across
any resistor of the network (except for RG in the JFET configuration). An indication of 0 V im-
mediately reveals the lack of current through the element due to an open circuit in the network.
The most sensitive element in the BJT and JFET configurations is the amplifier itself.
The application of excessive voltage during the construction or testing phase or the use
of incorrect resistor values resulting in high current levels can destroy the device. If you
question the condition of the amplifier, the best test for the FET is the curve tracer since
it not only reveals whether the device is operable, but also its range of current and voltage
levels. Some testers may reveal that the device is still fundamentally sound but do not reveal
whether its range of operation has been severely reduced.
The development of good troubleshooting techniques comes primarily from experience
and a level of confidence in what to expect and why. There are, of course, times when the
reasons for a strange response seem to disappear mysteriously when you check a network.
In such cases, it is best not to breathe a sigh of relief and continue with the construction.
The cause for such a sensitive “make or break” situation should be found and corrected, or
it may reoccur at the most inopportune moment.

13 p-ChanneL Fets
l
The analysis thus far has been limited solely to n-channel FETs. For p-channel FETs, a
mirror image of the transfer curves is employed, and the defined current directions are
reversed as shown in Fig. 56 for the various types of FETs.

467
 FET Biasing

D
G

S ID
Q

VGS
Q

(a)

S ID
Q

VGS
Q

(b)

G ID
Q - point Q

S
VGS
Q

(c)

Fig. 56
p-Channel configurations: (a) JFET; (b) depletion-type MOSFET;
(c) enhancement-type MOSFET.

Note for each configuration of Fig. 56 that each supply voltage is now a negative volt-
age drawing current in the indicated direction. In particular, note that the double-subscript
notation for voltages continues as defined for the n-channel device: VGS, VDS, and so on. In
this case, however, VGS is positive (positive or negative for the depletion-type MOSFET)
and VDS negative.
Due to the similarities between the analysis of n-channel and p-channel devices, one can
assume an n-channel device and reverse the supply voltage and perform the entire analysis.
When the results are obtained, the magnitude of each quantity will be correct, although the
current direction and voltage polarities will have to be reversed. However, the next example

468
will demonstrate that with the experience gained through the analysis of n-channel devices, FET Biasing
the analysis of p-channel devices is quite straightforward.

exaMpLe 17 Determine IDQ, VGSQ, and VDS for the p-channel JFET of Fig. 57.

ID
RD
R1
+

VDS
+
VGS – –
R2
RS

Fig. 57
Example 17.

Solution: We have
20 kV(-20 V)
VG = = -4.55 V
20 kV + 68 kV
Applying Kirchhoff’s voltage law gives
VG - VGS + IDRS = 0
and VGS = VG + IDRS
Choosing ID = 0 mA yields
VGS = VG = -4.55 V
as appearing in Fig. 58.

ID (mA)

8
7
6
5
4
I D = 3.4 mA Q- point
Q

2
1

– 5 – 4 –3 – 2 – 1 0 1 2 3 4 VGS
VP
VGS = 1.4 V
Q

Fig. 58
Determining the Q-point for the JFET configuration of Fig. 57.

Choosing VGS = 0 V, we obtain

VG -4.55 V
ID = - = - = 2.53 mA
RS 1.8 kV
as also appearing in Fig. 58.

469
 FET Biasing The resulting quiescent point from Fig. 58 is given by
IDQ = 3.4 mA
VGSQ = 1.4 V
For VDS, Kirchhoff’s voltage law results in
-IDRS + VDS - IDRD + VDD = 0
and VDS = -VDD + ID(RD + RS)
= -20 V + (3.4 mA)(2.7 kV + 1.8 kV)
= -20 V + 15.3 V
= 24.7 V

14 universaL jFet bias Curve

l
Since the dc solution of a FET configuration requires drawing the transfer curve for each
analysis, a universal curve was developed that can be used for any level of IDSS and VP.
The universal curve for an n-channel JFET or depletion-type MOSFET (for negative val-
ues of VGSQ) is provided in Fig. 59. Note that the horizontal axis is not that of VGS but of a
normalized level defined by VGS > 0 VP 0 , the 0 VP 0 indicating that only the magnitude of VP is
to be employed, not its sign. For the vertical axis, the scale is also a normalized level of
ID >IDSS. The result is that when ID = IDSS, the ratio is 1, and when VGS = VP, the ratio
VGS > 0 VP 0 is -1. Note also that the scale for ID >IDSS is on the left rather than on the right as
encountered for ID in past exercises. The additional two scales on the right need an intro-
duction. The vertical scale labeled m can in itself be used to find the solution to fixed-bias
configurations. The other scale, labeled M, is employed along with the m scale to find the

ID VP VG G
I DSS m= M= m

+
RS IDSS VP
1.0 5 1.0

0.8 4 0.8

0.6 3 0.6

Normalized curve
V 2
of ID = I DSS 1 – GS
VP
0.4 2 0.4

0.2 1 0.2

0
–1 – 0.8 – 0.6 – 0.4 – 0.2 0
VGS
VP

Fig. 59
Universal JFET bias curve.

470
solution to voltage-divider configurations. The scaling for m and M come from a mathe- FET Biasing
matical development involving the network equations and normalized scaling just intro-
duced. The description to follow will not concentrate on why the m scale extends from 0 to
5 at VGS > 0 VP 0 = -0.2 and the M scale ranges from 0 to 1 at VGS > 0 VP 0 = 0, but rather on
how to use the resulting scales to obtain a solution for the configurations. The equations
for m and M are the following, with VG as defined by Eq. (15):

0 VP 0
m = (43)
IDSS RS

VG
M = m * (44)
0 VP 0

R2VDD
with VG =
R1 + R2
Keep in mind that the beauty of this approach is the elimination of the need to sketch the
transfer curve for each analysis, that the superposition of the bias line is a great deal easier,
and that the calculations are fewer. The use of the m and M axes is best described by
examples employing the scales. Once the procedure is clearly understood, the analysis can
be quite rapid, with a good measure of accuracy.

exaMpLe 18 Determine the quiescent values of ID and VGS for the network of Fig. 60.

I DQ

RD

D
C1 C2
G
+
VGSQ
–S
RG
RS

Fig. 60
Example 18.

Solution: Calculating the value of m, we obtain

0 VP 0 0 -3 V 0
m = = = 0.31
IDSS RS (6 mA)(1.6 kV)
The self-bias line defined by RS is plotted by drawing a straight line from the origin through
a point defined by m = 0.31, as shown in Fig. 61.
The resulting Q-point:
ID VGS
= 0.18 and = -0.575
IDSS 0 VP 0
The quiescent values of ID and VGS can then be determined as follows:
IDQ = 0.18IDSS = 0.18(6 mA) = 1.08 mA
and VGSQ = -0.575 0 VP 0 = -0.575(3 V) = 21.73 V

471
 FET Biasing ID VP VG G
m= M= m

+
I DSS IDSS RS VP

1.0 5 1.0

0.8 4 0.8

0.6 3 0.6
ID Q - point (Ex. 6.20)
= 0.53
I DSS
m = 0.625

0.4 2 0.4
0.365

ID 0.2 Q - point (Ex. 6.19) 1 0.2

= 0.18
I DSS

m = 0.31

–1.0 –0.8 –0.6 –0.4 –0.2 0

VGS VGS
= –0.575 = –0.26
VP VP

Fig. 61
Universal curve for Examples 18 and 19.

exaMpLe 19 Determine the quiescent values of ID and VGS for the network of Fig. 62.

I DQ

RD
R1

C2
C1

+
VGSQ
–
R2
RS

Fig. 62
Example 19.

Solution: Calculating m gives

0 VP 0 0 -6 V 0
m = = = 0.625
IDSS RS (8 mA)(1.2 kV)

472
Determining VG yields FET Biasing
R2VDD (220 kV)(18 V)
VG = = = 3.5 V
R1 + R2 910 kV + 220 kV
Finding M, we have
VG 3.5 V
M = m * = 0.625a b = 0.365
ƒVP ƒ 6V
Now that m and M are known, the bias line can be drawn on Fig. 61. In particular, note
that even though the levels of IDSS and VP are different for the two networks, the same
universal curve can be employed. First find M on the M axis as shown in Fig. 61. Then
draw a horizontal line over to the m axis and, at the point of intersection, add the magni-
tude of m as shown in the figure. Using the resulting point on the m axis and the M inter-
section, draw the straight line to intersect with the transfer curve and define the Q-point.
That is,
ID VGS
= 0.53 and = -0.26
IDSS 0 VP 0
and IDQ = 0.53IDSS = 0.53(8 mA) = 4.24 mA
with VGSQ = -0.26 0 VP 0 = -0.26(6 V) = 21.56 V

15 praCtiCaL appLiCatiOns
l
The applications described here take full advantage of the high input impedance of field-
effect transistors, the isolation that exists between the gate and drain circuits, and the linear
region of JFET characteristics that permit approximating the device by a resistive element
between the drain and source terminals.

voltage-Controlled resistor (noninverting amplifier)

One of the most common applications of the JFET is as a variable resistor whose resis-
tance value is controlled by the applied dc voltage at the gate terminal. In Fig. 63a, the
linear region of a JFET transistor has been clearly indicated. Note that in this region
the various curves all start at the origin and follow a fairly straight path as the drain-to-
source voltage and drain current increase. Recall from your basic dc courses that the plot
of a fixed resistor is nothing more than a straight line with its origin at the intersection
of the axes.
In Fig. 63b, the linear region has been expanded to a maximum drain-to-source voltage
of about 0.5 V. Note that even though the curves do have some curvature to them, they can
easily be approximated by fairly straight lines, all having their origin at the intersection of
the axes and a slope determined by the gate-to-source dc voltage. Recall from earlier dis-
cussions that for an I–V plot where the current is the vertical axis and the voltage the
horizontal axis, the steeper the slope, the less is the resistance; and the more horizontal
the curve, the greater is the resistance. The result is that a vertical line has 0 V resistance
and a horizontal line has infinite resistance. At VGS = 0 V, the slope is the steepest and
the resistance the least. As the gate-to-source voltage becomes increasingly negative, the
slope decreases until it is almost horizontal near the pinch-off voltage.
It is important to remember that this linear region is limited to levels of VDS that are
relatively small compared to the pinch-off voltage. In general, the linear region of a JFET
is defined by VDS f VDSmax and 0 VGS 0 f 0 VP 0 .
Using Ohm’s law, let us calculate the resistance associated with each curve of Fig. 63b
using the current that results at a drain-to-source voltage of 0.4 V.
VDS 0.4 V
VGS = 0 V: RDS = = = 100 
IDS 4 mA
VDS 0.4 V
VGS = -0.5 V: RDS = = = 160 
IDS 2.5 mA
VDS 0.4 V
VGS = -1 V: RDS = = = 267 
IDS 1.5 mA

473
 ID (mA)

5
0V
=
S
VG
4 100 Ω

ID (mA) IDSS = 6 mA
Increasing resistance RDS
VP = –3 V 5V
6 3 –0.
VGS = 0 V
5 160 Ω
Linear region
4 –0.5 V 2 267 Ω
–1 V
3
444 Ω
–1 V –1.5 V
2 1
800 Ω –2 V
1 –1.5 V
–2 V –2.5 V
–2.5 V
0 1 2 3 4 5 6 7 8 VDS (volts) 0 0.1 0.2 0.3 0.4 0.5 VDS (volts)
3.3 kΩ

(a) (b)

Fig. 63
JFET characteristics: (a) defining the linear region; (b) expanding the linear region.

VDS 0.4 V
VGS = -1.5 V: RDS = = = 444 
IDS 0.9 mA
VDS 0.4 V
VGS = -2 V: RDS = = = 800 
IDS 0.5 mA
VDS 0.4 V
VGS = -2.5 V: RDS = = = 3.3 k
IDS 0.12 mA
In particular, note how the drain-to-source resistance increases as the gate-to-source
voltage approaches the pinch-off value.
The results just obtained can be verified by Eq. (6.1) using the pinch-off voltage of -3 V
and Ro = 100 V at VGS = 0 V. We have
Ro 100 V
RDS = =
VGS 2 VGS 2
a1 - b a1 - b
VP -3 V
100 V
VGS = -0.5 V: RDS = = 144  (versus 160 V above)
-0.5 V 2
a1 - b
-3 V
100 V
VGS = -1 V: RDS = = 225  (versus 267 V above)
-1 V 2
a1 - b
-3 V
100 V
VGS = -1.5 V: RDS = = 400  (versus 444 V above)
-1.5 V 2
a1 - b
-3 V

474
 100 V FET Biasing
VGS = -2 V: RDS = = 900  (versus 800 V above)
-2 V 2
a1 - b
-3 V
100 V
VGS = -2.5 V: RDS = = 3.6 k (versus 3.3 kV above)
-2.5 V 2
a1 - b
-3 V
Although the results are not an exact match, for most applications the equation
ro
rd = provides an excellent approximation to the actual resistance level
(1 - VGS >VP)2
for RDS.
Keep in mind that the possible levels of VGS between 0 V and pinch-off are infinite,
resulting in the full range of resistor values between 100 Æ and 3.3 kÆ. In general, therefore,
the above discussion is summarized by Fig. 64a. For VGS = 0 V, the equivalence of Fig.
64b would result; for VGS = -1.5 V, the equivalence of Fig. 64c; and so on.

D D

G G for VDS << VDSmax

RDS = f(VGS) VGS << VP
+ +
VGS VGS
– S – S

(a)

D D

G G
RDS 100  RDS 400 
+ –
0V 1.5 V
– S + S

VGS = 0 V VGS = –1.5 V

(b) (c)

Fig. 64
JFET voltage-controlled drain resistance: (a) general equivalence;
(b) with VGS = 0 V; (c) with VGS = -1.5 V.

Let us now investigate the use of this voltage-controlled drain resistance in the nonin-
verting amplifier of Fig. 65a—noninverting indicates that the input and output signals
are in phase.
If Rf = R1, the resulting gain is 2, as shown by the in-phase sinusoidal signals of
Fig. 65a. In Fig. 65b, the variable resistor has been replaced by an n-channel JFET. If
Rf = 3.3 kV and the transistor of Fig. 63 were employed, the gain could extend from
1 + 3.3 kV >3.3 kV = 2 to 1 + 3.3 kV >100 V = 34 for VGS varying from -2.5 V to
0 V, respectively. In general, therefore, the gain of the amplifier can be set at any value
between 2 and 34 by simply controlling the applied dc biasing voltage. The effect of this
type of control can be extended to an extensive variety of applications. For instance, if the
battery voltage of a radio should start to drop due to extended use, the dc level at the gate of
the controlling JFET will drop, and the level of RDS will decrease also. A drop in RDS will
result in an increase in gain for the same value of Rf, and the output volume of the radio can
be maintained. A number of oscillators (networks designed to generate sinusoidal signals
of specific frequencies) have a resistance factor in the equation for the frequency generated.
If the frequency generated should start to drift, a feedback network can be designed that
changes the dc level at the gate of a JFET and therefore its drain resistance. If that drain
resistance is part of the resistance factor in the frequency equation, the frequency generated
can be stabilized or maintained.

475
 FET Biasing vi vo
vi 2 mV
1 mV +
Rf (Rf = R1)
vo = (1 + )v
R1 i

– π

Rf

R1

(a)

vi
+
Rf
vo = (1 + R ) vi
DS

Rf
D D

G
+ RDS
VGS
– S S

(b)

Fig. 65
(a) Noninverting op-amp configuration; (b) using the voltage-controlled drain-to-source resistance
of a JFET in the noninverting amplifier.

One of the most important factors that affect the stability of a system is tempera-
ture variation. As a system heats up, the usual tendency is for the gain to increase, which in
turn will usually cause additional heating and may eventually result in a condition referred
to as “thermal runaway.” Through proper design, a thermistor can be introduced that will
affect the biasing level of a voltage-controlled variable JFET resistor. As the resistance
of the thermistor drops with increase in heat, the biasing control of the JFET can be such
that the drain resistance changes in the amplifier design to reduce the gain—establishing
a balancing effect.
Before leaving the subject of thermal problems, note that some design specifications
(often military type) require that systems that are overly sensitive to temperature variations
be placed in a “chamber” or “oven” to establish a constant heat level. For instance, a 1-W
resistor may be placed in an enclosed area with an oscillator network to establish a constant
ambient heat level in the region. The design then centers on this heat level, which would be
so high compared to the heat normally generated by the components that the variations in
temperature levels of the elements could be ignored and a steady output frequency assured.
Other areas of application include any form of volume control, musical effects, meters,
attenuators, filters, stability designs, and so on. One general advantage of this type of sta-
bility is that it avoids the need for expensive regulators in the overall design, although it
should be understood that the purpose of this type of control mechanism is to “fine-tune”
rather than to provide the primary source of stability.

476
 For the noninverting amplifier, one of the most important advantages associated with FET Biasing
using a JFET for control is the fact that it is dc rather than ac control. For most systems,
dc control not only results in a reduced chance of adding unwanted noise to the system, but
also lends itself well to remote control. For example, in Fig. 66a, a remote control panel
controls the amplifier gain for the speaker by an ac line connected to the variable resistor.

+
RF pickup (long unshielded wire) –

ac
2-mV signal, 1-mV noise
100 k Poor S/N ratio
RF pickup Gain control
(large R)

(a)

+
–

Biasing level –2 V dc
Vdc 1-mV noise, Large dc/N ratio
1 k

(b)

RF noise

6" or less in length

(c)

Fig. 66
Demonstrating the benefits of dc control: system with (a) ac control; (b) dc control;
(c) RF noise pickup.

477
 FET Biasing The long line from the amplifier can easily pick up noise from the surrounding air
as generated by fluorescent lights, local radio stations, operating equipment (even
computers), motors, generators, and so on. The result may be a 2-mV signal on the line
with a 1-mV noise level—a terrible signal-to-noise ratio, which would only contribute to
further deterioration of the signal coming in from the microphone due to the loop gain of
the amplifier. In Fig. 66b, a dc line controls the gate voltage of the JFET and the variable
resistance of the noninverting amplifier. Even though the dc line voltage on the line may
be only 22 V, a ripple of 1 mV picked up by the long line will result in a very large signal-
to-noise ratio, which could essentially be ignored in the distortion process. In other words,
the noise on the dc line would simply move the dc operating point slightly on the device
characteristics and would have almost no effect on the resulting drain resistance—isolation
between the noise on the line and the amplifier response would be almost ideal.
Even though Figures 66a and 66b have a relatively long control line, the control line
may only be 60 long, as shown in the control panel of Fig. 66c, where all the elements of the
amplifier are housed in the same container. Consider, however, that just 10 is enough to
pick up RF noise, so dc control is a favorable characteristic for almost any system. Further-
more, since the control resistance in Fig. 66a is usually quite large (hundreds of kilohms),
whereas the dc voltage control resistors of the dc system of Fig. 66b are usually quite small
(a few kilohms), the volume control resistor for the ac system will absorb a great deal more
ac noise than the dc design. This phenomenon is a result of the fact that RF noise signals
in the air have a very high internal resistance, and therefore the larger the pickup
resistance, the greater is the RF noise absorbed by the receiver. Recall Thévenin’s
theorem, which states that for maximum power transfer, the load resistance should equal
the internal resistance of the source.
As noted above, dc control lends itself to computer and remote control systems
since they operate off specific fixed dc levels. For instance, when an infrared (IR) sig-
nal is sent out by a remote control to the receiver in a TV or VCR, the signal is passed
through a decoder–counter sequence to define a particular dc voltage level on a staircase
of voltage levels that can be fed into the gate of the JFET. For a volume control, that
gate voltage may control the drain resistance of a noninverting amplifier controlling the
volume of the system.

timer network
The high isolation between gate and drain circuits permits the design of a relatively simple
timer such as shown in Fig. 67. The switch is a normally open (NO) switch, which, when
closed, will short out the capacitor and cause its terminal voltage to quickly drop to 0 V.
The switching network can handle the rapid discharge of voltage across the capacitor

Fig. 67
JFET timer network.

478
because the working voltages are relatively low and the discharge time is extremely short. FET Biasing
Some would say it is a poor design, but in the practical world it is frequently used and not
looked on as a terrible crime.
When power is first applied, the capacitor will respond with its short-circuit equivalence
since the voltage across the capacitor cannot change instantaneously. The result is that
the gate-to-source voltage of the JFET will immediately be set to 0 V, the drain current ID
will equal IDSS, and the bulb will turn on. However, with the switch in the normally open
position, the capacitor will begin to charge to -9 V. Because of the parallel high input
impedance of the JFET, it has essentially no effect on the charging time constant of the
capacitor. Eventually, when the capacitor reaches the pinch-off level, the JFET and bulb
will turn off. In general, therefore, when the system is first turned on, the bulb will light for
a very short period of time and then turn off. It is now ready to perform its timing function.
When the switch is closed, it will short out the capacitor (R3 V R1, R2) and will set the
voltage at the gate to 0 V. The resulting drain current is IDSS, and the bulb will burn brightly.
When the switch is released, the capacitor will charge toward 29 V, and eventually when
it reaches the pinch-off level, the JFET and bulb will turn off. The period during which the
bulb is on will be determined by the time constant of the charging network, determined by
t = (R1 + R2)C and the level of the pinch-off voltage. The more negative the pinch-off
level, the longer the bulb will be on. Resistor R1 is included to be sure that there is some re-
sistance in the charging circuit when the power is turned on. Otherwise, a very heavy current
could result that might damage the network. Resistor R2 is a variable resistor, so the “on”
time can be controlled. Resistor R3 was added to limit the discharge current when the switch
is closed. When the switch across the capacitor is closed, the discharge time of the capacitor
will be only 5t = 5RC = 5(1 kV)(33 mF) = 165 ms = 0.165 ms = 0.000165 s. In sum-
mary, therefore, when the switch is pressed and released, the bulb will come on brightly,
and then, as time goes on, it will become dimmer until it shuts off after a period of time
determined by the network time constant.
One of the most obvious applications of such a timing system is in a hallway or travel
corridor where you want light for a short period of time so that you can pass safely but then
want the system to turn off on its own. When you enter or leave a car, you may want a light
on for a short period of time but don’t want to worry about turning it off. There are endless
possibilities for a timing network such as just described. Just consider the variety of other
electrical or electronic systems that you would like to turn on for specific periods of time,
and the list of uses grows exponentially.
One might ask why a BJT would not be a good alternative to the JFET for the same
application. First, the input resistance of the BJT may be only a few kilohms. That would
affect not only the time constant of the charging network, but also the maximum voltage
to which the capacitor could charge. Just draw an equivalent network with the transistor
replaced by a 1-kÆ resistor, and the above will immediately become clear. In addition, the
control levels will have to be designed with a great deal more care since the BJT transistor
turns on at about 0.7 V. The voltage swing from off to on is only 0.7 V rather than 4 V for
the JFET configuration. One final note: You might have noticed the absence of a series re-
sistor in the drain circuit for the situation when the bulb is first turned on and the resistance
of the bulb is very low. The resulting current could be quite high until the bulb reaches its
rated intensity. However, again, as described above for the switch across the capacitor, if
the energy levels are small and the duration of stress minimal, such designs are often ac-
cepted. If there were any concern, adding a resistor of 0.1 to 1 Æ in series with the bulb
would provide some security.

Fiber Optic systems

The introduction of fiber optic technology has had a dramatic effect on the communica-
tions industry. The information-carrying capacity of fiber optic cable is significantly
greater than that provided by conventional methods with individual pairs of wire. In addi-
tion, the cable size is reduced, the cable is less expensive, crosstalk due to electromagnetic
effects between current-carrying conductors is eliminated, and noise pickup due to exter-
nal disturbances such as lightning are eliminated.
The fiber optic industry is based on the fact that information can be transmitted on a
beam of light. Although the speed of light through free space is 3 3 108 meters per second,

479
 FET Biasing or approximately 186,000 miles per second, its speed will be reduced by encounters with
other media, causing reflection and refraction. When light information is passed through
a fiber optic cable, it is expected to bounce off the walls of the cable. However, the angle
at which the light is injected into the cable is critical, as is the actual design of the cable.
In Fig. 68, the basic elements of a fiber optic cable are defined. The glass or plastic core
Cladding
(glass or plastic)
of the cable can be as small as 8 mm, which is close to 1/10 the diameter of a human hair.
The core is surrounded by an outer layer called the cladding, which is also made of glass
or plastic, but has a different refractive index to ensure that the light in the core that hits the
Protective coating
outer surface of the core is reflected back into the core. A protective coating is then added
to protect the two layers from outside environmental effects.
Most optical communication systems work in the infrared frequency range, which
extends from 3 * 1011 Hz to 5 * 1014 Hz. This spectrum is just below the visible light
Core (glass or plastic)
spectrum, which extends from 5 * 1014 Hz to 7.7 * 1014 Hz. For most optical systems the
Fig. 68 frequency range of 1.87 * 1014 Hz to 3.75 * 1014 Hz is used. Because of the very high
Basic elements of a fiber optic frequencies, each carrier can be modulated by hundreds or thousands of voice channels si-
cable. multaneously. In addition, very high speed computer transmission is a possibility, although
one must be sure that the electronic components of the modulators can also operate success-
fully at the same frequency. For distances over 30 nautical miles, repeaters (a combination
receiver, amplifier, and transmitter) must be used, which require an additional electrical
conductor in the cable that carries a current of about 1.5 A at 2500 V.
The basic components of an optical communication system are shown in Fig. 69. The
input signal is applied to a light modulator whose sole purpose is to convert the input signal
to one of corresponding levels of light intensity to be directed down the length of fiber optic
cable. The information is then carried through the cable to the receiving station, where a
light demodulator converts the varying light intensities back to voltage levels that match
those of the original signal.

Each section of the transatlantic optic fiber connection

Light is about 30 miles in length (the distance
Input modulator between regenerators).
signal
(voice, video (TV), data, etc.)

Fiberoptic cable
Light
demodulator Output
signal

Fig. 69
Basic components of an optical communication system.

An electronic equivalent for the transmission of computer transistor-transistor-logic

(TTL) information is provided in Fig. 70a. With the Enable control in the “on” or 1-state,
the TTL information at the input to the AND gate can pass through to the gate of the
JFET configuration. The design is such that the discrete levels of voltage associated with
the TTL logic will turn the JFET on and off (perhaps 0 V and -5 V, respectively, for a
JFET with VP = -4 V). The resulting change in current levels will result in two distinct
levels of light intensity from the LED in the drain circuit. That emitted light will then
be directed through the cable to the receiving station, where a photodiode will react to
the incident light and permit different levels of current to pass through as established
by V and R. The current for photodiodes is a reverse current having the direction shown
in Fig. 70a, but in the ac equivalent the photodiode and the resistor R are in parallel as
shown in Fig. 70b, establishing the desired signal with the polarity shown at the gate
of the JFET. Capacitor C is simply an open circuit to dc to isolate the biasing arrange-
ment for the photodiode from the JFET and a short circuit as shown for the signal vs.
The incoming signal will then be amplified and will appear at the drain terminal of the
output JFET.
As mentioned above, all the elements of the design, including the JFETs, LED, photo-
diode, capacitors, and so on, must be carefully chosen to ensure that they function properly

480
 VDD1

RD1
V VDD2
V
Enable AND gate
Fiberoptic cable RD2
R
vo
TTL
data CC
+
C
vgs
–

Imodulated

Photodiode
or
Modulated
phototransistor
reverse current

(a)

– +

Im R vs vgs = –vs

+ –

(b)

Fig. 70
TTL fiber optic communication channel: (a) JFET design; (b) passing on the signal generated across the photodiode.

at the high frequency of transmission. In fact, laser diodes are frequently used instead of
LEDs in the modulator because they work at higher information rates and higher powers
and have lower coupling and transmission losses. However, laser diodes are a great deal
more expensive and more temperature sensitive, and they typically have a shorter lifetime
than LEDs. For the demodulator side, the photodiodes are either of the pin photodiode or
the avalanche photodiode variety. The pin abbreviation comes from the p-intrinsic-n con-
struction process, and the term avalanche from the rapidly growing ionization process that
develops during operation.
In general, the JFET is excellent for this application because of its high isolation at the
input side and its ability to quickly “snap” from one state to the other due to the TTL input.
At the output side the isolation blocks any effect of the demodulator sensing circuit from
affecting the ac response, and it provides some gain for the signal before it is passed on to
the next stage.

MOsFet relay driver

The MOSFET relay driver to be described in this section is an excellent example of how
the FETs can be used to drive high-current/high-voltage networks without drawing
current or power from the driving circuit. The high input impedance of FETs essen-
tially isolates the two parts of the network without the need for optical or electromag-
netic linkages. The network to be described can be used for a variety of applications, but
our application will be limited to an alarm system activated when someone or something
passes the plane of the transmitted light.
The IR (infrared—not visible) LED of Fig. 71 is directing its light through a di-
rectional funnel to hit the face of a photoconductive cell of the controlling network.
The photoconductive cell has a range of resistance from about 200 kÆ as its dark

481
 FET Biasing 6V

Counter,
alarm,
R1 100 k
lamp,
Threshold etc.
control R2 Relay High-current or high-voltage
50 k system

VG MOSFET
+
VGS –

IR LED
Photoconductive
cell
1 k 200 k

Fig. 71
MOSFET relay driver.

resistance level down to less than 1 kÆ at high illumination levels. Resistor R1 is a variable
resistance that can be used to set the threshold level of the depletion-type MOSFET. A
medium-power MOSFET was employed because of the high level of drain current through
the magnetizing coil.
When the system is on and the light consistently hitting the photoconductive cell, the
resistance of the cell may drop to 10 kÆ. At this level an application of the voltage-divider
rule will result in a voltage of about 0.54 V at the gate terminal (with the 50-kÆ potentiom-
eter set to 0 kÆ). The MOSFET will be on, but not at a drain current level that will cause
the relay to change state. When someone passes by, the light source will be cut off, and the
resistance of the cell may quickly (in a few microseconds) rise to 100 kÆ. The voltage at
the gate will then rise to 3 V, turning on the MOSFET and activating the relay and turning
on the system under control. An alarm circuit has its own control design to ensure that it
will not turn off when light returns to the photoconductive cell.
In essence, therefore, we have controlled a high-current network with a relatively small
dc voltage level and a rather inexpensive design. The only obvious flaw in the design is
the fact that the MOSFET will be on even when there is no intrusion. This can be rem-
edied through the use of a more sophisticated design, but keep in mind that MOSFETs
are typically low-power-consumption devices, so the power loss, even over time, is not
that great.

16 suMMary
l
important Conclusions and Concepts
1. A fixed-bias configuration has, as the label implies, a fixed dc voltage applied from
gate to source to establish the operating point.
2. The nonlinear relationship between the gate-to-source voltage and the drain current
of a JFET requires that a graphical or mathematical solution (involving the solution of
two simultaneous equations) be used to determine the quiescent point of operation.
3. All voltages with a single subscript define a voltage from a specified point to ground.
4. The self-bias configuration is determined by an equation for VGS that will always pass
through the origin. Any other point determined by the biasing equation will establish
a straight line to represent the biasing network.
5. For the voltage-divider biasing configuration, one can always assume that the gate cur-
rent is 0 A to permit an isolation of the voltage-divider network from the output sec-
tion. The resulting gate-to-ground voltage will always be positive for an n-channel
JFET and negative for a p-channel JFET. Increasing values of RS result in lower
quiescent values of ID and more negative values of VGS for an n-channel JFET.

482
 6. The method of analysis applied to depletion-type MOSFETs is the same as applied to FET Biasing
JFETs, with the only difference being a possible operating point with an ID level
above the IDSS value.
7. The characteristics and method of analysis applied to enhancement-type MOSFETs
are entirely different from those of JFETs and depletion-type MOSFETs. For values
of VGS less than the threshold value, the drain current is 0 A.
8. When analyzing networks with a variety of devices, first work with the region of the
network that will provide a voltage or current level using the basic relationships asso-
ciated with those devices. Then use that level and the appropriate equations to find other
voltage or current levels of the network in the surrounding region of the system.
9. The design process often requires finding a resistance level to establish the desired volt-
age or current level. With this in mind, remember that a resistance level is defined by the
voltage across the resistor divided by the current through the resistor. In the design
process, both of these quantities are often available for a particular resistive element.
10. The ability to troubleshoot a network requires a clear, firm understanding of the termi-
nal behavior of each of the devices in the network. That knowledge will provide an
estimate of the working voltage levels of specific points of the network, which can be
checked with a voltmeter. The ohmmeter section of a multimeter is particularly helpful
in ensuring that there is a true connection between all the elements of the network.
11. The analysis of p-channel FETs is the same as that applied to n-channel FETs except
for the fact that all the voltages will have the opposite polarity and the currents the
opposite direction.

equations
JFETs/depletion-type MOSFETs:
Fixed@bias configuration: VGS = -VGG = VG
Self@bias configuration: VGS = -ID RS
R2VDD
Voltage@divider biasing: VG =
R1 + R2
VGS = VG - ID RS
Enhancement-type MOSFETs:
Feedback biasing: VDS = VGS
VGS = VDD - ID RD
R2VDD
Voltage@divider biasing: VG =
R1 + R2
VGS = VG - ID RS

17 COMputer anaLysis
l
pspice windows
jFet voltage-divider Configuration The results of Example 19 will now be verified
using PSpice Windows. The network of Fig. 72 is constructed using different computer
methods. The J2N3819 JFET is obtained from the EVAL library, and Edit-PSpice model
is used to set Beta to 0.222 mA/V2 and Vto to -6 V. The Beta value is determined using
beta = IDSS >VP2 and the provided IDSS and VP. The results of the Simulation appear in Fig.
73 with the dc bias voltage and current levels. The resulting drain current is 4.225 mA,
compared to the calculated level of 4.24 mA—an excellent match. The voltage VGS is
3.504 V - 5.070 V = -1.57 V versus the calculated level of -1.56 V in Example 19—
another excellent match.

Combination network Next, the result of Example 12 with both a transistor and JFET
will be verified. For the transistor Bf is set to 180, whereas for the JFET, Beta is set to
0.333 mA/V2 and Vto to -6 V as called for in the example. The results for all the dc levels
appear in Fig. 73. Note again the excellent comparison with the calculator solution, with
VD at 11.44 V compared to 11.07 V, VS = VC at 7.138 V compared to 7.32 V, and VGS at
3.380 V - 7.138 V = 23.76 V compared to -3.7 V.

483
 FET Biasing

Fig. 72 Fig. 73
JFET voltage-divider configuration with PSpice Verifying the hand-calculated solution of Example 12
Windows results for current and voltage levels. using PSpice Windows.

Multisim
The results of Example 2 will now be verified using Multisim (Fig. 74). The JFET is
obtained by selecting Transistor, the fourth key down on the first vertical toolbar. A
Select a Component dialog box will appear, in which JFET_N can be selected under the
Family listing. A long Component list appears, in which 2N3821 is selected for this
application. An OK, and it can be placed on the screen. After double-clicking the symbol
on the screen, a JFET_N dialog box will appear in which Value can be selected, followed

Fig. 74
Verifying the results of Example 2 using Multisim.

484
by Edit Model. An Edit Model dialog box will appear in which Beta and Vto can be set LasT H1FET
HEad 473
Biasing
to 0.222 mA/V2 and 26 V, respectively. The value of Beta is determined using the equa-
IDSS
tion Beta = (A>V2) and the parameters of the network as follows:
VP 2
IDSS 8 mA 8 mA
Beta = = = = 0.222 mA>V2
0 VP 0 2
0 -6 V 0 2
36 V2
Once the change is made, be sure to select Change Part Model before leaving the dialog
box. The JFET_N dialog box will appear again, but an OK, and the changes will be made.
The labels IDSS 5 8 mA and Vp 5 26 V are added using Place-Text. A blinking verti-
cal bar will appear marking the place where the label can be entered. Once entered, it can
easily be moved by simply clicking the area and dragging it to the desired position while
holding the clicker down.
Using the Indicator option on the first vertical toolbar displays the drain and source
voltages as shown in Fig. 74. In both cases the VOLTMETER_V option was chosen in
the Select a Component dialog box.
Selecting Simulate-Run or moving the switch to the 1 position results in the display of
Fig. 74. Note that VGS at -2.603 V is an exact match with the hand-calculated solution of
-2.6 V. Although the indicator is connected from source to ground, be aware that this is also
the gate-to-source voltage because the voltage drop across the 1-MÆ resistor is assumed to
be 0 V. The level of 11.405 V at the drain is very close to the hand-calculated solution of
11.42 V—in all, a complete verification of the results of Example 2.

prObLeMs
l
*Note: Asterisks indicate more difficult problems.
2 Fixed-bias Configuration
1. For the fixed-bias configuration of Fig. 75:
a. Sketch the transfer characteristics of the device.
b. Superimpose the network equation on the same graph.
c. Determine IDQ and VDSQ.
d. Using Shockley’s equation, solve for IDQ and then find VDSQ. Compare with the solutions of
part (c).

14 V

1.8 kV

Fig. 75
Problems 1 and 37.

2. For the fixed-bias configuration of Fig. 76, determine:

a. IDQ and VGSQ using a purely mathematical approach.
b. Repeat part (a) using a graphical approach and compare results.
c. Find VDS, VD, VG, and VS using the results of part (a).
3. Given the measured value of VD in Fig. 77, determine:
a. ID.
b. VDS.
c. VGG.

485
 474
FET Biasing
sEmiconducTor
diodEs 3V

1.2 MV
IDSS = 8 mA
VD = 6 V VP = –4 V
+ VDS –
12 V 2.2 k

ID

1 M

–VGG

Fig. 76 Fig. 77
Problem 2. Problem 3.

4. Determine VD and VGS for the fixed-bias configuration of Fig. 78.

5. Determine VD and VGS for the fixed-bias configuration of Fig. 79.

Fig. 78 Fig. 79
Problem 4. Problem 5.

3 self-bias Configuration
6. For the self-bias configuration of Fig. 80:
a. Sketch the transfer curve for the device.
b. Superimpose the network equation on the same graph.
c. Determine IDQ and VGSQ.
d. Calculate VDS, VD, VG, and VS.
*7. Determine IDQ for the network of Fig. 80 using a purely mathematical approach. That is, estab-
lish a quadratic equation for ID and choose the solution compatible with the network character-
istics. Compare to the solution obtained in Problem 6.
8. For the network of Fig. 81, determine:
a. VGSQ and IDQ.
b. VDS, VD, VG, and VS.
9. Given the measurement VS = 1.7 V for the network of Fig. 82, determine:
a. IDQ.
b. VGSQ.
c. IDSS.
d. VD.
e. VDS.

486
 LasT H1FET
HEad 475
Biasing

3V

Fig. 80 Fig. 81 Fig. 82

Problems 6, 7, and 38. Problem 8. Problem 9.

*10. For the network of Fig. 83, determine:

a. ID.
b. VDS.
c. VD.
d. VS.
*11. Find VS for the network of Fig. 84.

4V

Fig. 83 Fig. 84
Problem 10. Problem 11.

4 voltage-divider biasing
12. For the network of Fig. 85, determine:
a. VG.
b. IDQ and VGSQ.
c. VD and VS.
d. VDSQ.
13. a. Repeat Problem 12 with RS = 0.51 kV (about 50% of the value of that of Problem 12).
What is the effect of a smaller RS on IDQ and VGSQ?
b. What is the minimum possible value of RS for the network of Fig. 85?
14. For the network of Fig. 86, VD = 12 V. Determine:
a. ID.
b. VS and VDS.
c. VG and VGS.
d. VP.

487
 476
FET Biasing
sEmiconducTor 18 V
diodEs
ID

2 kΩ

VD = 12 V
+
VG
12 V VDS IDSS = 8 mA
680 kΩ +
VGS VS
–
–
110 kΩ
0.68 kΩ

Fig. 85 Fig. 86
Problems 12 and 13. Problem 14.

15. Determine the value of RS for the network of Fig. 87 to establish VD = 10 V.

16 V

RD 2 k
R1 36 k
VD = 10 V
IDSS = 12 mA
VP = –8 V

R2 12 k RS

Fig. 87
Problem 15.
5 Common-gate Configuration
*16. For the network of Fig. 88, determine:
a. IDQ and VGSQ.
b. VDS and VS.
*17. Given VDS = 4 V for the network of Fig. 89, determine:
a. ID.
20 V
b. VD and VS.
c. VGS.

1.2 k

2V

Fig. 88 Fig. 89
Problems 16 and 39. Problem 17.

488
6 special Case: VGSQ 5 0 v LasT H1FET
HEad 477
Biasing
18. For the network of Fig. 90.
a. Find IDQ.
b. Determine VDQ and VDSQ.
c. Find the power supplied by the source and dissipated by the device.
19. Determine VD and VGS for the network of Fig. 91 using the provided information.

18 V

RD 1.8 kΩ

ID

+ VD 4V
I DSS = 4 mA
VDS
VP = –2 V 1.8 k 1 k
– 16 V
–
VGS
+ IDSS = 4 mA
3.6 k VP = –6 V
1.2 kΩ
1.2 k

Fig. 90 Fig. 91
Problem 18. Problem 19.

7 depletion-type MOsFets
20. For the self-bias configuration of Fig. 92, determine:
a. IDQ and VGSQ.
b. VDS and VD.
*21. For the network of Fig. 93, determine:
a. IDQ and VGSQ.
b. VDS and VS.

Fig. 92 Fig. 93
Problem 20. Problem 21.

8 enhancement-type MOsFets
22. For the network of Fig. 94, determine:
a. IDQ.
b. VGSQ and VDSQ.
c. VD and VS.
d. VDS.
23. For the voltage-divider configuration of Fig. 95, determine:
a. IDQ and VGSQ.
b. VD and VS.

489
 478
FET Biasing
sEmiconducTor 24 V
diodEs

2.2 kΩ
10 MΩ ID
Q

VGS(Th) = 3 V
I D(on) = 5 mA
+ VGS(on) = 6 V
VGS
Q
–
6.8 MΩ
0.75 kΩ

Fig. 94 Fig. 95
Problem 22. Problem 23.

10 Combination networks
*24. For the network of Fig. 96, determine:
a. VG.
b. VGSQ and IDQ.
c. IE.
d. IB.
e. VD.
f. VC.
*25. For the combination network of Fig. 97, determine:
a. VB and VG.
b. VE.
c. IE, IC, and ID.
d. IB.
e. VC, VS, and VD.
f. VCE.
g. VDS.

VS ,VC

VG IB

VE

Fig. 96 Fig. 97
Problem 24. Problem 25.

490
11 design LasT H1FET
HEad 479
Biasing
*26. Design a self-bias network using a JFET transistor with IDSS = 8 mA and VP = -6 V to have
a Q-point at IDQ = 4 mA using a supply of 14 V. Assume that RD = 3RS and use standard
values.
*27. Design a voltage-divider bias network using a depletion-type MOSFET with IDSS = 10 mA
and VP = - 4 V to have a Q-point at IDQ = 2.5 mA using a supply of 24 V. In addition, set
VG = 4 V and use RD = 2.5RS with R1 = 22 MV. Use standard values.
28. Design a network such as appears in Fig. 39 using an enhancement-type MOSFET with
VGS(Th) = 4 V and k = 0.5 * 10-3 A>V2 to have a Q-point of IDQ = 6 mA. Use a supply of
16 V and standard values.

12 troubleshooting
*29. What do the readings for each configuration of Fig. 98 suggest about the operation of the net-
work?

Fig. 98
Problem 29.

*30. Although the readings of Fig. 99 initially suggest that the network is behaving properly, deter-
mine a possible cause for the undesirable state of the network.
*31. The network of Fig. 100 is not operating properly. What is the specific cause for its failure?

Fig. 99 Fig. 100

Problem 30. Problem 31.

491
 480
FET Biasing
sEmiconducTor 13 p-Channel Fets
diodEs 32. For the network of Fig. 101, determine:
a. IDQ and VGSQ.
b. VDS.
c. VD.
33. For the network of Fig. 102, determine:
a. IDQ and VGSQ.
b. VDS.
c. VD.

Fig. 101 Fig. 102

Problem 32. Problem 33.

14 universal jFet bias Curve

34. Repeat Problem 1 using the universal JFET bias curve.
35. Repeat Problem 6 using the universal JFET bias curve.
36. Repeat Problem 12 using the universal JFET bias curve.
37. Repeat Problem 16 using the universal JFET bias curve.

15 Computer analysis
38. Perform a PSpice Windows analysis of the network of Problem 1.
39. Perform a PSpice Windows analysis of the network of Problem 6.
40. Perform a Multisim analysis of the network of Problem 16.
41. Perform a Multisim analysis of the network of Problem 33.

sOLutiOns tO seLeCted Odd-nuMbered prObLeMs

l
1. (c) IDQ  4.7 mA, VDSQ  5.54 V
(d) IDQ = 4.69 mA, VDSQ = 5.56 V
3. (a) ID 5 2.727 mA (b) VDS 5 6 V (c) VGG 5 1.66 V
5. VD 5 18 V, VGS 5 24 V
7. IDQ = 2.6 mA
9. (a) IDQ = 3.33 mA (b) VGSQ  -1.7 V (c) IDSS 5 10.06 mA (d) VD 5 11.34 V
(e) VDS 5 9.64 V
11. VS 5 1.4 V
13. (a) VG 5 2.16 V IDQ  5.8 mA, VGSQ  -0.85 V VD 5 7.24 V, VS 5 6.38 V
VDSQ = 0.86 V (b) VGS 5 0 V, VG 5 ID RS 5 IDSS RS and RS 5 216 V
15. RS 5 2.67 kV
17. (a) ID 5 3.33 mA (b) VD 5 10 V, VS 5 6 V (c) VGS 5 26 V
19. VD 5 8.8 V, VGS 5 0 V
21. (a) IDQ  9 mA, VGSQ  0.5 V (b) VDS 5 7.69 V, VS 5 20.5 V
23. (a) IDQ  5 mA, VGSQ  6 V

492
25. (a) VB 5 VG 5 3.2 V (b) VE 5 2.5 V (c) IE 5 2.08 mA, IC 5 2.08 mA, ID 5 2.08 mA LasT H1FET
HEad 481
Biasing
(d) IB 5 20.8 mA (e) VC 5 5.67 V, VS 5 5.67 V, VD 5 11.42 V (f) VCE 5 3.17 V
(g) VDS 5 5.75 V
27. VGS 5 22 V, RS 5 2.4 kV, RD 5 6.2 kV, R2 5 4.3 MV
29. (a) JFET in saturation (b) JFET nonconducting (c) Short from gate to drain (JFET or
circuit)
31. JFET in saturation, open circuit between gate and voltage-divider network
33. (a) IDQ _ 4.4 mA, VGSQ  -7.25 V (b) VDS 5 27.25 V (c) VD 5 27.25 V
35. (a) VGSQ = -1.96 V, IDQ = 2.7 mA (b) VDS 5 11.93 V, VD 5 13.95 V, VG 5 0 V,
VS 5 2.03 V
37. (a) IDQ = 2.76 mA, VGSQ = -2.04 V (b) VDS 5 7.86 V, VS 5 2.07 V

493