Phase Noise in Frequency Divider Circuits

Melina Apostolidou Peter G.M. Baltus Cicero S. Vaucher

Research, NXP Semiconductors Technical University of Eindhoven Research, NXP Semiconductors
HTC 37, 5656 AE Eindhoven PT5, 5600 MB Eindhoven HTC 37, 5656 AE Eindhoven
Email: melina.apostolidou@nxp.com Email: P.G.M.Baltus@tue.nl Email: cicero.vaucher@nxp.com

Abstract— We identify limitations of the models for phase noise II. M ODELS OF P HASE N OISE IN FREQUENCY DIVIDERS
in frequency dividers by Egan and by Phillips and present a
new model applicable to both high frequency and low power Several models for classifying and describing the phase
frequency divider design. Further, we design both synchronous noise of digital FDs are available [1]–[3]. Levantino et al. in
and asynchronous frequency divider test chips that allow us to [3] present a physical derivation of phase noise in a source-
observe experimentally the effects of noise accumulation, sam- coupled logic Dlatch. However, they do not quantify the total
pling frequency and biasing conditions on the total phase noise
performance of frequency dividers. We use our measurements divider-by-N phase noise. Phillips and Egan in [1] and [2]
to validate the simulated values obtained by time domain phase attempt to model the phase noise of digital FD architectures.
noise analysis offered by the commercial simulator Spectre RF. However, they make certain assumptions that limit the design
The measured data show good agreement with the simulation space at which their model is applicable. In the following,
results. we identify the limitations of the existing models and extend
Phillip’s model to include noise sources and effects that occur
I. I NTRODUCTION in a generic divider architecture.
Low power consumption and high performance are often
A. Phillips’ and Extended Phillips’ model
contradictory requirements and this constitutes a design trade-
off. In particular, achieving a low phase noise in the phase The total divider output phase noise according to Phillips’
locked loop (PLL) of frequency synthesizers is one of the most model is
stringent requirements. Normally, the current trend towards  2  2
φin vn 2H
lower power consumption degrades phase noise performance. φ2out = + +φ2p,1 +φ2p,2 +...+φ2p,M , (1)
N Kp N
Therefore, we need to define an appropriate way of optimizing
towards low power consumption without sacrificing the phase where φin is the narrow-band “input phase noise”, vn models
noise performance of the PLL. To comprehend in depth this driving source noise, as well as device input noise in between
design trade-off, one should identify the internal phase noise divider interstages, H is the maximum significant harmonic,
mechanisms intrinsic to each block constituting a PLL. N is the division ratio, Kp is the zero crossing slope measured
We choose the frequency dividers (FD) as the focus of in volts/radian, and φ2p,n is the “propagation-delay noise” of
this work. The phase noise generated by a FD affects the the nth gate [1].
synthesizer noise performance within the PLL band, especially In the first term on the right hand side of equation (1),
if a high division factor is used. Additionally, the digital FD the 1/N 2 −dependence is derived from FM theory. The sec-
is in general responsible for a significant portion of the total ond term represents the equivalent input phase noise power
power consumption of the PLL. However, a decrease in the (from input noise voltages) 2vn2 /Kp2 , divided by N 2 also
power consumption of the divider degrades its phase noise according to FM theory and simultaneously multiplied by
performance. HN to incorporate the “sampling effect” (sampling results
Therefore, we need, first, to identify the fundamental trade- into a replication (aliasing) of the wide-band noise spectrum
off between noise and power consumption in this particular at a rate αfout , where fout is the output frequency of the
block and, second, to have a robust and reliable way of divider stage and α equals 2 or 1 for sampling once or
simulating phase noise of “sample and hold” based circuits twice per cycle, respectively). In the following, we prefer to
such as a digital FD. Section II addresses the former problem. formulate the “sampling effect” in a different way. As Fig. 1
We identify the limitations in the FD phase noise models shows, the bandwidth BW of the divider stage determines how
suggested by Phillips [1] and by Egan [2] and propose a new many of the replicated spectra (due to sampling) contribute
model that captures the power and phase noise trade-off for a to the total noise. The aliased spectra are responsible for
fixed operating frequency. In Section III, we present the divider the extra gain factor of αBW/fout , and thus one needs to
architectures and test chips that are used for measurements. multiply 2vn2 /(Kp N )2 by this factor. This factor equals N
In the same section, measurements are compared against only under the condition that BW = N fout = fin which
simulations, and deviations from theory are identified and yields the minimum bandwidth for which correct division can
explained. Finally, Section IV concludes this paper. be sustained.

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  2  2 
φin BW1 vn,1 2
φ2out,1 = +α + φ2p,1 , (4)
N1 fout,1 Kp,1 N12
 2  2 
φout,1 BW2 vn,2 2
φ2out,2 = +α +φ2p,2 . (5)
N2 fout,2 Kp,2 N22
Substituting eq. (4) in eq. (5), we obtain the expression for
the total output phase noise power,
Fig. 1. The smaller bandwidth of a down-scaled divider reduces the amount  2  2 
of aliased spectra and therefore its contribution to the total noise. 2 φin φp,1 2
φout,2 = + +φp,2
N1 N2 N22
 2  2 
Phillips assumes that a total of M gates contribute to the vn,1 2 BW1 vn,2 2 BW2
+α + .
total propagation delay φ2p,1 +φ2p,2 +...+φ2p,M of a synchronous Kp,1 N12 N22 fout,1 Kp,2 N22 fout,2
divider stage. This does not include the case of asynchronous
stages. In the case of M asynchronous divider stages, the total Here, Kp,i is the zero crossing slope of the driving signal,
2
propagation-delay noise at the output of the M-th stage is 2vn,i is the noise power in rms values within the Nyquist
band, and φp,i represents the propagation delay noise of the
φ2p,1 φ2p,2 ith component.
2
+ + ... + φ2p,M , (2)
(N2 N3 ...NM ) (N3 ...NM )2 Note that the parameters determining the bandwidth BW
where Ni is the division ratio of the i-th asynchronous divider influence the value of Kp which drives the subsequent divider
stage. stage. We identify here one design trade-off: (a) BW should
Finally, similarly to Egan, Phillips assumes that the only be as small as possible to decrease the gain due to sampling
point where an AM to PM noise transformation occurs is at while (b) BW should be as large as possible to increase
the input of the total divider structure. This is true if and only Kp . Additionally, the extended model covers cases where the
if the signals driving the divider inter-stages are resembling synchronous division ratios N1 and N2 are unequal and larger
square waves which is unrealistic at higher frequencies. than or equal to 2, as well as cases where the driving signals
Despite these limitations, Phillips’ model can be easily between divider stages are not square-like. The first enhances
made into a model that, first, takes into account the sam- the generic character of the model. The latter models the
pling effect for all wide-band noise sources; second, does additive phase noise in between divider-stages. Finally, φi and
not assume square-like driving signals; and third, concerns a vn,i are phase noise parameters intrinsic to the unit elements
generic divider structure consisting of both synchronous and of each divider stage and hence, are treated as an independent
asynchronous stages. modeling procedure. Such a model is presented by Levantino
We start by modifying eq. (1) so as to incorporate the et al. in [3].
sampling effect into the model. For a synchronous divider- Understanding the impact that design parameters, such
by-N, one may write as BW , division number N , and number of asynchronous
 2  2  stages, have on the total output phase noise, helps us choose
2 φin BW vn 2 their values. However, we are still missing a reliable way of
φout = +α + φ2p . (3)
N fout Kp N2 predicting the phase noise values of a FD. In the following, we
will evaluate the “time domain” (strobed) phase noise analysis
Here, the aliasing of the additive input voltage noise is
offered by the commercial simulator Spectre RF.
accounted for by multiplying this noise types by αBW/fout .
To obtain the general form of Phillips’ model, we con- III. T EST CHIPS FOR MEASUREMENTS
sider two stages of synchronous dividers coupled in an To verify the accuracy of the “strobed” phase noise analysis
asynchronous fashion as depicted in Fig. 2. The first syn- against measured values, we layout two different designs
under test (DU T ), namely a synchronous and an asynchronous
divider-by-4 architecture. Fig. 3 shows their block diagrams.
To ensure sufficient reliability of the measurements, one
must isolate the DU T from any external noise source. We use
the typical I/Q measurement setup [2]. Two identical dividers
Fig. 2. Two stages of synchronous dividers, coupled asynchronously. (DU T 1 and DU T 2) are driven by the same signal generated
by an on-wafer input amplifier used to convert the single-ended
chronous divider realizes a division-by-N1 and the second one source input to a differential one at the clock inputs. DU T 2
a division-by-N2. The total division is, thus, N1 N2 . We apply is preset to be 90o out of phase with respect to DU T 1 (this is
eq. (3) on each divider stage to obtain the total noise at the the proper condition for operation of a balanced-mixer phase
output of the first- and second-asynchronous stages, detector). The I and Q signals are fed into the mixer, which is

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Fig. 3. The asynchronous (a) and synchronous (b) divider-by-4 architectures.

Fig. 5. Setup for phase noise measurements.

internal to the phase noise measurement equipment, see Fig. 5.
TABLE I
Half of the measured noise power is ascribed to each of the
M EASURED AND SIMULATED DIVIDER PHASE NOISE AT fm = 2MH Z .
two FDs. Since both dividers have a common input, phase
noise from the source and from the input amplifier (which is
correlated noise in the I/Q paths) tends to cancel. Measured divider phase noise at fm = 2MHz.
Igate = 2Ilatch Div-4 Synchr Div-4 Asynchr
A. Divider-by-2 cell 10 GHz −152.5 dBc/Hz −152 dBc/Hz
20 GHz N/A −148.5 dBc/Hz
Igate = Ilatch Div-4 Synchr Div-4 Asynchr
10 GHz −154.5 dBc/Hz −153.5 dBc/Hz
20 GHz N/A −147.5 dBc/Hz
Simulated divider phase noise at fm = 2MHz.
Igate = 2Ilatch Div-4 Synchr Div-4 Asynchr
10 GHz −153 dBc/Hz −152 dBc/Hz
20 GHz N/A −149 dBc/Hz
Igate = Ilatch Div-4 Synchr Div-4 Asynchr
10 GHz −155 dBc/Hz −153.5 dBc/Hz
20 GHz N/A −148.5 dBc/Hz

Fig. 4. Schematic view of the divider-by-2 cell.

The divider-by-2 cells, that are used in each DU T , are the the absolute noise floor of the system. Table I shows the
state-of-the-art adaptive FD cells [4], see Fig. 4. We recall that, measured and simulated phase noise results at fm = 2 MHz.
in the adaptive architecture, the cross-coupled stage and the These results were obtained under different input frequencies,
amplifier stage in each Dlatch are biased independently. By cross-coupled pair current biasing and divider architectures.
biasing the cross-coupled pair Ilatch with lower current than We mark as N/A the set of conditions for which division was
the one in the amplifier stage Igate , we extend the frequency impossible. Simulations match the measurements within 1 dB.
of operation.
D. Theory versus measurements
B. Measurement set-up
Since theory only models the various effects qualitatively
Calibration of the measurement set-up (depicted in Fig. 5 and not quantitatively, we can only compare relative theoretical
excluding the test chip in its path) shows that its noise floor values. In particular, we focus on replacing an asynchronous
is L(2M Hz) = −155dBc/Hz at fout = 5GHz. The high 1/f by a synchronous architecture (accumulation effect), doubling
noise present in GaAs low noise amplifiers (LN As) restricts the input frequency (sampling effect) and decreasing the
our experiment only within the white noise region. Unfortu- biasing current in the cross-coupled pair.
nately, we cannot eliminate these LN As, since amplification 1) Asynchronous against Synchronous: Theoretically, the
of the output I/Q signals is necessary. asynchronous divider-by-4 contributes 3 dB more phase noise
C. Simulations versus measurements than its synchronous divider-by-4 equivalent. The total phase
noise at the output node of the asynchronous architectures is
To measure the phase noise generated by our DU T , we
perform ”phase noise without a PLL” measurements, involving Sv,1 (fm ) Sv,2 (fm )
Sφ,asyn (fm ) = (2πfout,1 )2 +(2πfout,2 )2 ,
the calibration of the phase detector constant which determines 2Slope21 Slope22

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where fout,x , Sv,x and Slopex denote the frequency, the 3) Biasing conditions: We recall the “adaptive frequency”
spectrum of the noise (in V 2 /Hz) and the slope of the divider architecture depicted in Fig. 4 and its feature of
driving signal at node x, see Fig. 3. Since fout,1 = 2fout,2 , extending the maximum frequency of operation by decreasing
Sv,1 = Sv,2 /2 and Slope1 = Slope2 , Sφ,asyn (fm ) becomes the biasing current at the cross-coupled pair [4]. During our
measurements, we observe that the improvement in maximum
Sv,2 (fm )
Sφ,asyn (fm ) = 2(2πfout,2 )2 . (6) frequency of operation does not come at the cost of an
Slope22 increased phase noise performance. To the contrary, phase
noise measurements performed with Ilatch = Igate /2 prove
For the synchronous divider-by-4 architecture, only the second
equally or less noisy than under Ilatch = Igate . The shot noise,
divider stage is important,
which in great extent defines Sv (fm ), decreases with Ilatch .
Sv,2 (fm ) At moderate frequencies f < fo , Slope follows BW ; hence, a
Sφ,sync (fm ) = (2πfout,2 )2 . (7) higher Ilatch means a higher Slope value, Fig. 7. However, for
Slope22
Subtracting eq. (7) from eq. (6) (reexpressed in dB units), we
obtain Sφ,async (fm ) − Sφ,sync (fm ) = 3 dB, which deviates
from the simulated and measured 1 dB value. We recall
that input and output slope values are equal in both divider
stages in our theoretical calculations. However, Slope2 may
be deteriorated with respect to Slope1 , since the loading
conditions for each of the divider-by-2 stages are unequal,
and hence, the percentage of total phase noise attributed to
the second divider stage increases. Fig. 7. Gain versus frequency at different biasing condition.
2) Sampling effect: We perform phase noise measurements
at fin = 10 GHz and fin = 20 GHz and observe an increase of high frequencies f ≥ 2fo , where the gain is limited, the Slope
3.5 dB. Theoretical calculations show that doubling the input does not depend on BW any more, see Fig. 7. Therefore,
frequency fin increases the output phase noise by 3dB. For phase noise becomes solely a function of Sv (fm ) at these
the asynchronous architecture, we calculate frequencies.
IV. C ONCLUSIONS
Sv,2new (fm )
Sφ,f in (fm ) = (2πfout,2new )2 . (8) We extended Phillips’ model to include noise sources and
Slope2new
effects occurring in a generic divider architecture. We also
Fig. 6 assists us in extracting a set of relations. Since changed the model to include high frequency effects (such as
AM to PM transformation in the divider interstages) as well
as design parameters such as bandwidth of each synchronous
divider stage BWi , the number of asynchronous divider stages,
and the division ratios Ni , that are better suited to our design
objectives (high frequency, low phase noise and low power).
The measurements on the taped-out test-structures, at dif-
ferent biasing and frequency conditions, allowed us to observe
the accumulation and sampling effects on the phase noise
performance of the FD. We also observed that lowering the
biasing current of the cross-coupled pair degrades the phase
noise performance at moderate frequencies while it improves
Fig. 6. Replicated spectra at the output of a divider when doubling fin . it at higher frequencies. Measurements and simulations match
within 1 dB. Therefore, the “time domain” phase noise sim-
fin,new = 2fin , it holds that fout,2new = 2fout,2 , Sv,2new = ulations of Spectre RF estimate accurately the phase noise in
Sv,2 /2 and Slopenew = Slope. Then, eq. (8) becomes all cases considered in this paper.
R EFERENCES
Sv,2 (fm )
Sφ,2fin (fm ) = 2(2πfout,2 )2 . (9) [1] D.E. Phillips, “Random Noise in Digital Gates and Dividers,” IEEE 41st
Slope2 Annual Frequency Control Symposium, pp. 507-511, 1987.
[2] W.F. Egan, “Modeling Phase Noise in Frequency Dividers,” IEEE Trans-
Subtracting eq. (8) from eq. (9) (reexpressed in dB units), actions on Ultrasonics, Ferroelectrics,and Frequency Control, Vol. 37,
we obtain Sφ,2fin (fm ) − Sφ,f in (fm ) = 3 dB. The theoretical No. 4, pp. 307-315, July 1990.
calculations validate the measurements with the precondition [3] S. Levantino et al. “Phase Noise in Digital Frequency Dividers,” IEEE
Journal of Solid-State Circuits, Vol. 39, No. 5, pp. 775-784, May 2004.
that the value of Slope at the output of the divider stages is [4] C.S. Vaucher and M. Apostolidou, “A Low-Power 20GHz Static Fre-
analogous to BW . As we show subsequently, this assumption quency Divider with Programmable Input Sensitivity,” IEEE Radio Fre-
is under certain conditions invalid. quency Integrated Circuits (RFIC) Symposium, No. 02, pp. 235-238, 2002

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