LNK64x4-64x8

LinkSwitch-3 Family
Energy-Efficient, Accurate Primary-Side Regulation
CV/CC Switcher for Adapters and Chargers

Product Highlights

+
DC
Dramatically Simplifies CV/CC Converters Output
• Eliminates optocoupler and all secondary CV/CC control circuitry
• Eliminates all control loop compensation circuitry

Advanced Performance Features Wide Range

• Compensates for transformer inductance tolerances High-Voltage
• Compensates for input line voltage variations DC Input
D
• Compensates for cable voltage drop FB
• Compensates for external component temperature variations LinkSwitch-3 BP
• Very accurate IC parameter tolerances using test trimming technology
• Frequency jittering greatly reduces EMI filter cost S

• Programmable switching frequency up to 85 kHz to reduce trans-

former size
• Minimum operation frequency fixed to improve transient load PI-6907-020515
response Figure 1. Typical Application – Not a Simplified Circuit.
Advanced Protection/Safety Features
• Auto-restart protection reduces power delivered by >90% for output
short-circuit and control loop faults (open and shorted components) Output Power Table1,2,3,4
• Hysteretic thermal shutdown – automatic recovery reduces power
supply returns from the field 90-264 VAC
• Meets high-voltage creepage requirements between DRAIN and all Product5 D (SO-8C) Package
other pins both on the PCB and at the package
Adapter Open Frame
EcoSmart™– Energy Efficient LNK6404D / LNK6424D 3.5 W 4.1 W
• Easily meets all global energy efficiency regulations with no added
LNK6405D / LNK6415D /
components 4.5 W 5.1 W
LNK6425D
• No-load consumption at 230 VAC input with bias winding <10 mW for
LNK64x4-LNK64x6 and <30 mW for LNK64x7-LNK64x8 LNK6406D / LNK6416D /
• ON/OFF control provides constant efficiency down to very light loads LNK6426D / LNK6436D / 5.5 W 6.1 W
– ideal for CEC regulations LNK6446D
• No current sense resistors – maximizes efficiency LNK6407D / LNK6417D /
7.5 W 7.5 W
LNK6427D
Green Package
• Halogen free and RoHS compliant package E (eSIP-7C) and
Product5 K (eSOP-12B) Packages
Applications
• Chargers for cell/cordless phones, PDAs, MP3/portable audio Adapter Open Frame
devices, adapters, etc. LNK6407K / LNK6417K /
8.5 W 9W
LNK6427K
Description
LNK6408K / LNK6418K /
10 W 10 W
The LinkSwitch™-3 family of ICs dramatically simplifies low power CV/ LNK6428K / LNK6448K
CC charger designs by eliminating an optocoupler and secondary LNK6408E / LNK6418E /
control circuitry. The device introduces a revolutionary control 10 W 10 W
LNK6428E / LNK6448E
technique to provide very accurate output voltage and current
regulation, compen-sating for transformer and internal parameter Table 1. Output Power Table.
tolerances along with input voltage variations. Notes:
1. Assumes minimum input DC voltage >90 VDC, KP ≥1 (Recommend KP ≥1.15
The device incorporates a 725 V power MOSFET, a novel ON/OFF control for accurate CC regulation), η >78%, DMAX <55%.
state machine, a high-voltage switched current source for self biasing, 2. Output power capability is reduced if a lower input voltage is used.
3. Minimum continuous power with adequate heat sink measured at 50 °C
frequency jittering, cycle-by-cycle current limit and hysteretic thermal ambient with device junction below 110 °C.
shutdown circuitry onto a monolithic IC. 4. Assumes bias winding is used to supply BYPASS pin.
5. Package: D: SO-8C, E: eSIP-7C, K: eSOP-12B.

www.power.com March 2016

This Product is Covered by Patents and/or Pending Patent Applications.

 LNK64x4-64x8

DRAIN
(D)
REGULATOR
BYPASS 6V
(BP)
+
FB 6V -
+ OUT Reset 5V
FEEDBACK D Q STATE
VTH - MACHINE
(FB) VILIMIT
tSAMPLE-OUT
ILIM Drive
CABLE DROP VILIMIT DCMAX
COMPENSATION

FAULT
6.5 V FB AUTO-RESTART
OPEN-LOOP
THERMAL
INDUCTANCE
SHUTDOWN
CORRECTION
tSAMPLE-INPUT DCMAX
tSAMPLE-OUT
SAMPLE
tSAMPLE-INPUT DELAY
OSCILLATOR
SOURCE
+ (S)
SOURCE ILIM VILIMIT
CONSTANT -
(S) CURRENT Current Limit
Comparator LEADING
EDGE
BLANKING

PI-6660-020515

Figure 2 Functional Block Diagram.

Pin Functional Description

E Package
DRAIN (D) Pin: (eSIP-7C)
This pin is the power MOSFET drain connection. It provides
Exposed Pad
internal operating current for both start-up and steady-state (On Back Side)
operation. Internally
Connected to
BYPASS (BP) Pin: SOURCE Pin
D Package (SO-8C)
This pin is the connection point for an external 1 mF bypass capacitor
for the internally generated 6 V supply.
FB 1 8S
FEEDBACK (FB) Pin: BP 2 7S
During normal operation, switching of the power MOSFET is 12345 7
D
FB
BP
NC
NC
S

controlled by this pin. This pin senses the AC voltage on the 6S

bias winding. This control input regulates both the output D4 5S
voltage in CV mode and output current in CC mode based on
the flyback voltage of the bias winding. The internal induc-
tance correction circuit uses the forward voltage on the bias Exposed Pad (On Bottom)
Internally Connected to K Package
winding to sense the bulk capacitor voltage. SOURCE Pin (eSOP-12B)
SOURCE (S) Pin: FB 1 12 S
This pin is internally connected to the output MOSFET source BP 2 11 S
for high-voltage power and control circuit common returns. NC 3 10 S
NC 4 9S
8S
D6 7S

PI-6906-020515

Figure 3. Pin Configuration.

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LinkSwitch-3 Functional Description Auto-Restart and Open-Loop Protection

In the event of a fault condition such as an output short or an
The LinkSwitch-3 combines a high-voltage power MOSFET switch with open-loop condition the LinkSwitch-3 enters into an appropriate
a power supply controller in one device. It uses an ON/OFF control to protection mode as described below.
regulate the output voltage. In addition, the switching frequency is
modulated to regulate the output current to provide a constant current In the event the FEEDBACK pin voltage during the flyback period falls
characteristic. The LinkSwitch-3 controller consists of an oscillator, below 0.7 V before the FEEDBACK pin sampling delay (~2.5 ms) for a
feedback (sense and logic) circuit, 6 V regulator, over-temperature duration in excess of ~300 ms (auto-restart on-time (t AR-ON) the
protection, frequency jittering, current limit circuit, leading-edge converter enters into auto-restart, wherein the power MOSFET is
blanking, inductance correction circuitry, frequency control for disabled for 1500 ms. The auto-restart alternately enables and
constant current regulation and ON/OFF state machine for CV control. disables the switching of the power MOSFET until the fault condition
is removed.
Inductance Correction Circuitry
If the primary magnetizing inductance is either too high or low the In addition to the conditions for auto-restart described above,
converter will automatically compensate for this by adjusting the if the sensed FEEDBACK pin current during the forward period of the
oscillator frequency. Since this controller is designed to operate in conduction cycle (switch “on” time) falls below 120 mA, the converter
discontinuous-conduction mode the output power is directly annunciates this as an open-loop condition (top resistor in potential
proportional to the set primary inductance and its tolerance can be divider is open or missing) and reduces the auto-restart time from
completely compensated with adjustments to the switching 300 ms to approximately 6 clock cycles (90 ms), whilst keeping the
frequency. disable period of 2 seconds.

Constant Current (CC) Operation Over-Temperature Protection

As the output voltage and therefore the flyback voltage across the The thermal shutdown circuitry senses the die temperature. The
bias winding ramps up, the FEEDBACK pin voltage increases. The threshold is set at 142 °C typical with a 60 °C hysteresis. When the
switching frequency is adjusted as the FEEDBACK pin voltage increases die temperature rises above this threshold (142 °C) the power
to provide a constant output current regulation. The constant current MOSFET is disabled and remains disabled until the die temperature
circuit and the inductance correction circuit are designed to operate falls by 60 °C, at which point the MOSFET is re-enabled.
concurrently in the CC region.
Current Limit
Constant Voltage (CV) Operation The current limit circuit senses the current in the power MOSFET.
As the FEEDBACK pin approaches 2 V from the constant current When this current exceeds the internal threshold (ILIMIT), the power
regulation mode, the power supply transitions into CV operation. MOSFET is turned off for the remainder of that cycle. The leading
The switching frequency at this point is at its maximum value, edge blanking circuit inhibits the current limit comparator for a short
corresponding to the peak power point of the CV/CC characteristic. time (tLEB) after the power MOSFET is turned on. This leading edge
The controller regulates the FEEDBACK pin voltage to remain at blanking time has been set so that current spikes caused by
FEEDBACK pin threshold (VFBTH) using an ON/OFF state-machine. capacitance and rectifier reverse recovery time will not cause
The FEEDBACK pin voltage is sampled 2.5 ms after the turn-off of the premature termination of the MOSFET conduction. The LinkSwitch-3
high-voltage switch. also contains a “di/dt” correction feature to minimize CC variation across
the input line range.
At light loads the current limit is also reduced to decrease the
transformer flux density and the FEEDBACK pin sampling is done 6 V Regulator
earlier. The 6 V regulator charges the bypass capacitor connected to the
BYPASS pin to 6 V by drawing a current from the voltage on the
Output Cable Compensation DRAIN, whenever the MOSFET is off. The BYPASS pin is the internal
This compensation provides a constant output voltage at the end of supply voltage node. When the MOSFET is on, the device runs off of
the cable over the entire load range in CV mode. As the converter the energy stored in the bypass capacitor. Extremely low power
load increases from no-load to the peak power point (transition point consumption of the internal circuitry allows the LinkSwitch-3 to
between CV and CC) the voltage drop introduced across the output operate continuously from the current drawn from the DRAIN pin
cable is compensated by increasing the FEEDBACK pin reference however for the best no-load input power, the BYPASS pin should be
voltage. The controller determines the output load and therefore the supplied current of IS1 from the bias winding at no-load conditions.
correct degree of compensation based on the output of the state A bypass capacitor value of 1 mF is sufficient for both high frequency
machine. The amount of cable drop compensation is determined by decoupling and energy storage.
the third digit in the device part number.

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Applications Example reducing the output diode voltage stress by allowing a greater
transformer turns ratio. The device is completely self-powered from
Circuit Description the BYPASS pin and decoupling capacitor C7. For the LNK64xx
This circuit shown in Figure 4 is configured as a primary-side devices, there are 4 options for different amount of cable drop
regulated flyback power supply utilizing the LNK6448K. With an compensation determined by the third digit in the device part
average efficiency of 78% and <30 mW no-load input power this number. Table 2 shows the amount of compensation for each device.
design easily exceeds the most stringent current energy efficiency The LNK644x devices do not provide cable drop compensation.
requirements. The optional bias supply formed by D3 and C8 provides the operating
Input Filter current for U1 via resistor R8. This reduces the no-load consumption
AC input power is rectified by bridge BR1. The rectified DC is filtered from ~200 mW to <30 mW and also increases light load efficiency.
by the bulk storage capacitors C1 and C2. Inductors L2 and L3, The rectified and filtered input voltage is applied to one side of the
together with C1 and C2 form a pi (π) filter, which attenuates primary winding of T1. The other side of the transformer’s primary
conducted differential-mode EMI noise. This configuration along with winding is driven by the integrated MOSFET in U1. The leakage
Power Integrations transformer E-Shield™ technology allows this inductance drain voltage spike is limited by an RCD-R clamp
design to meet EMI standard EN55022 class B with good margin consisting of D2, R3, R11, and C6.
without requiring a Y capacitor, even with the output connected to
safety earth ground. A ferrite bead for L3 is sufficient especially Output Rectification
when the output of the supply is floating. Fuse F1 provides protection The secondary of the transformer is rectified by D1, a 10 A, 45 V
against catastrophic failure. NTC (Negative Thermal Coefficient) Schottky barrier type for higher efficiency, and filtered by C3, L1 and
thermistor RT1 is used to limit the rush current to below the peak C4. If lower efficiency is acceptable then this can be replaced with a
specification of BR1 during start-up especially at high-line input 5 A PN junction diode for lower cost. In this application C3 and C4
voltage. High-line results in the highest current into C1 and C2. F1 are sized to meet the required output voltage ripple specification with
and RT1 can be replaced by a single fusible resistor. If the reduction a ferrite bead L1, which eliminates the high switching noise on the
in efficiency is acceptable, a bridge with a higher IFSM rating may also output. A pre-load resistor R2 is used to meet the regulation
allow removal of RT1. If a fusible resistor is selected, use a specification. If the battery self-discharge is required, the pre-load
flameproof type. It should be suitably rated (typically a wire wound resistor can be replaced with a series resistor and Zener network.
type) to withstand the instantaneous dissipation while the input
Output Regulation
capacitors charge when first connected to the AC line.
The LNK64xx family of devices regulates the output using ON/OFF
LNK6448K Primary control in the constant voltage (CV) regulation region of the output
The LNK6448K device (U1) incorporates the power switching device, characteristic and frequency control for constant current (CC)
oscillator, CC/CV control engine, start-up, and protection functions. regulation. The feedback resistors (R6 and R7) were selected using
The integrated 725 V MOSFET provides a large drain voltage margin standard 1% resistor values to center both the nominal output
in universal input AC applications, increasing reliability and also voltage and constant current regulation thresholds.

C5
R1 1 nF
10 Ω 50 V
R10
4.7 kΩ L1
R11 T1 Ferrite Bead
200 kΩ EPC17 (3.5 × 7.6 mm) 5 V, 2 A
5 FL1
L2 J1-1
1 mH C6 D1 C3 C4 R2
470 pF SBR1045SP5-13 680 µF 680 µF 2.55 kΩ
BR1
B10S-G 250 V 10 V 10 V 1%
1000 V RTN
6 FL2

4
J1-4
R3
150 Ω 6.0 PI-7309-020515

3 115 VAC
D2 230 VAC
S1ML 5.0
Output Voltage (V)

C1 C2
10 µF 15 µF 4.0
F1 RT1 400 V 400 V R5
t R6
O

1A 10 Ω 2.4 Ω
44.2 kΩ
1% 3.0
90 - 265 LinkSwitch-3
VAC U1 D3
LNK6448K RS1ML
L N D 2.0
TP1 TP2 FB
BP 1.0
S R8
C7 R7 2.37 kΩ C8
L3 1 µF 10 kΩ 10 µF 0.0
Ferrite Bead 1%
50 V 1% 25 V 0 0.5 1 1.5 2 2.5 3
(3.5 × 7.6 mm)
PI-7209-020515
Output Current (A)

Figure 4. Energy Efficient USB Charger Power Supply (78% Average Efficiency, <30 mW No-load Input Power).

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Key Application Considerations LinkSwitch-3 Layout Considerations

Output Power Table Circuit Board Layout
LinkSwitch-3 is a highly integrated power supply solution that
The data sheet maximum output power table (Table 1) repre- sents integrates on a single die, both, the controller and the high- voltage
the maximum practical continuous output power level that can be MOSFET. The presence of high switching currents and voltages
obtained under the following assumed conditions: together with analog signals makes it especially important to follow
1. Assumes minimum input DC voltage >90 VDC, KP ≥1 (Recom- good PCB design practice to ensure stable and trouble free operation
mend KP ≥1.15 for accurate CC regulation), η >78%, DMAX <55%. of the power supply. See Figure 5 for a recommended circuit board
2. Output power capability is reduced if a lower input voltage layout for LinkSwitch-3.
is used. When designing a printed circuit board for the LinkSwitch-3 based
3. Minimum continuous power with adequate heat sink measured at power supply, it is important to follow the following guidelines:
50 °C ambient with device junction below
110 °C. Single Point Grounding
4. Assumes bias winding is used to supply BYPASS pin. Use a single point (Kelvin) connection at the negative terminal of the
input filter capacitor for the LinkSwitch-3 SOURCE pin and bias
Output Tolerance winding return. This improves surge capabilities by returning surge
LinkSwitch-3 provides an overall output tolerance (including currents from the bias winding directly to the input filter capacitor.
line, component variation and temperature) of ±5% for the output
voltage in CV operation and ±10% for the output current during CC Bypass Capacitor
operation over a junction temperature range of 0 °C to 110 °C. The BYPASS pin capacitor should be located as close as possible to
the SOURCE and BYPASS pins.
BYPASS Pin Capacitor Selection
A 1 mF BYPASS pin capacitor is recommended. The capacitor Feedback Resistors
voltage rating should be greater than 7 V. The capacitor’s dielectric Place the feedback resistors directly at the FEEDBACK pin of the
material is not important but tolerance of capacitor should be ≤ LinkSwitch-3 device. This minimizes noise coupling.
±50%. The capacitor must be physically located adjacent to the
Thermal Considerations
LinkSwitch-3 BYPASS pin.
The copper area connected to the SOURCE pins provides the
Cable Drop Compensation LinkSwitch-3 heat sink. A good estimate is that the LinkSwitch-3 will
The amount of output cable compensation is determined by the third dissipate 10% of the output power. Provide enough copper area to
digit in the device part number. Table 2 shows the amount of keep the SOURCE pin temperature below 110 °C is recommended to
compensation for each LinkSwitch-3 device. provide margin for part to part RDS(ON) variation.

The output voltage that is entered into PIXls design spreadsheet is Secondary Loop Area
the voltage at the end of the output cable when the power supply is To minimize leakage inductance and EMI the area of the loop connecting
delivering maximum power. The output voltage at the terminals of the secondary winding, the output diode and the output filter capacitor
the supply is the value measured at the end of the cable multiplied by should be minimized. In addition, sufficient copper area should be
the output voltage change factor. provided at the anode and cathode terminal of the diode for heat
sinking. A larger area is preferred at the quiet cathode terminal.
A large anode area can increase high frequency radiated EMI.
LinkSwitch-3 Output Cable Voltage
Drop Compensation Electrostatic Discharge Spark Gap
A spark gap is created between the output and the AC input. The
Device Output Voltage Change Factor (±1%) spark gap directs ESD energy from the secondary back to the AC
LNK640x 1.02 input. The trace from the AC input to the spark gap electrode should
be spaced away from other traces to prevent unwanted arcing
LNK641x 1.04 occurring and possible circuit damage.
LNK642x 1.06 Drain Clamp Optimization
LNK643x 1.08 LinkSwitch-3 senses the feedback winding on the primary-side to
regulate the output. The voltage that appears on the feedback
LNK644x 1.01 winding is a reflection of the secondary winding voltage while the
internal MOSFET is off. Therefore any leakage inductance induced
Table 2. Cable Compensation Change Factor vs. Device. ringing can affect output regulation. Optimizing the drain clamp to

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Figure 5. PCB (Bottom Layer on Left) (Top Layer on Right) Layout Example Showing 10 W Design using K Package.

minimize the high frequency ringing will give the best regulation. 0.7 mA typ.) is the IC supply current and VBP (6.2 V typ.) is the
Figure 6 shows the desired drain voltage waveform compared to BYPASS pin voltage. The parameters IS2 and VBP are provided in the
Figure 7 with a large undershoot due to the leakage inductance parameter table of the LinkSwitch-3 data sheet. Diode D3 can be any
induced ring. This will reduce the output voltage regulation low cost diode such as FR102, 1N4148 or BAV19/20/21.
performance. To reduce this adjust the value of the resistor in series
with the clamp diode. Quick Design Checklist
As with any power supply design, all LinkSwitch-3 designs should be
Addition of a Bias Circuit for Higher Light Load
verified on the bench to make sure that component specifications are
Efficiency and Lower No-load Input Power
not exceeded under worst-case conditions.
Consumption
The following minimum set of tests is strongly recommended:
The addition of a bias circuit can decrease the no-load input power
from ~200 mW down to less than 30 mW at 230 VAC input. Light 1. Maximum drain voltage – Verify that peak VDS does not exceed
load efficiency also increases which may avoid the need to use a 680 V at the highest input voltage and maximum output power.
Schottky barrier vs. PN junction output diode while still meeting 2. Maximum drain current – At maximum ambient temperature,
average efficiency requirements. maximum input voltage and maximum output load, verify drain
current waveforms at start-up for any signs of transformer
The power supply schematic shown in Figure 4 has only one winding saturation and excessive leading edge current spikes.
for both feedback and bias circuit. Diode D3, C8, R5 and R8 form the LinkSwitch-3 has a leading edge blanking time of 170 ns to
bias circuit. The feedback winding voltage is designed at 11 V, this prevent premature termination of the ON-cycle.
provides a high enough voltage to supply the BYPASS pin even during 3. Thermal check – At maximum output power, both minimum and
low switching frequency operation at no-load. maximum input voltage and maximum ambient temperature;
A 10 mF capacitance value is recommended for C8 to hold up the bias verify that temperature specifications are not exceeded for
voltage at the low switching frequencies that occur at light to LinkSwitch-3, transformer, output diodes and output capacitors.
no-load. The capacitor type is not critical but the voltage rating Enough thermal margin should be allowed for part-to-part variation
should be above the maximum value of VBIAS. The recommended of the RDS(ON) of LinkSwitch-3, as specified in the data sheet.
current into the BYPASS pin is equal to IC supply current (0.6 mA to Design Tools
0.7 mA) at the minimum bias winding voltage. The BYPASS pin
current should not exceed 10 mA at the maximum bias winding Up-to-date information on design tools can be found at the Power
voltage. The value of R8 is calculated according to (VBIAS – VBP)/IS2, Integrations web site: www.power.com
where VBIAS (10 V typ.) is the voltage across C8, IS2 (0.6 mA to

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PI-5093-020515

PI-5094-020515
An overshoot
is acceptable

Negative ring may

increase output
ripple and/or
degrade output
regulation

Figure 6. Desired Drain Voltage Waveform with Minimal Leakage Figure 7. Undesirable Drain Voltage Waveform with Large Leakage
Ringing Undershoot. Ring Undershoot.

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Absolute Maximum Ratings(1,5)

DRAIN Voltage .........................................................-0.3 V to 725 V Notes:
DRAIN Pin Peak Current: LNK64x4............................. 400 (600) mA(4) 1. All voltages referenced to SOURCE, TA = 25 °C.
LNK64x5..............................504 (750) mA(4) 2. Duration not to exceed 2 ms.
LNK64x6 .............................654 (980) mA(4) 3. 1/16 in. from case for 5 seconds.
LNK64x7............................ 670 (1003) mA(4) 4. The higher peak DRAIN current is allowed while the DRAIN voltage
LNK64x8............................ 718 (1076) mA(4) is simultaneously less than 400 V.
Peak Negative Pulsed Drain Current................................... -100 mA(2) 5. Maximum ratings specified may be applied, one at a time without
FEEDBACK Pin Voltage .................................................. -0.3 to 9 V(6) causing permanent damage to the product. Exposure to Absolute
FEEDBACK Pin Current..........................................................100 mA Maximum ratings for extended periods of time may affect product
BYPASS Pin Voltage......................................................... -0.3 to 9 V reliability.
BYPASS Pin Current................................................................10 mA 6. -1 V for current pulse ≤5 mA out of the pin and a duration
Storage Temperature .................................................. -65 to 150 °C of ≤500 ns.
Operating Junction Temperature(7)................................ -40 to 150 °C 7. Normally limited by internal circuitry.
Lead Temperature...............................................................260 °C(3)

Thermal Resistance
Thermal Resistance: D Package: Notes:
(qJA) .............................. 100 °C/W(2), 80 °C/W(3) 1. Measured on pin 8 (SOURCE) close to plastic interface.
(qJC)(1)................................................ 30 °C/W 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
E Package 3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
(qJA)...................................... 105 °C/W(4) 4. Free standing with no heat sink.
(qJC)..........................................2 °C/W(5) 5. Measured at the back surface of tab.
K Package 6. Soldered (including exposed pad for K package) to typical
(qJA) ...................... 45 °C/W(6), 38 °C/W(7) application PCB with a heat sinking area of 0.36 sq. in.
(qJC)..........................................2 °C/W(5) (232 mm2), 2 oz. (610 g/m2) copper clad.
7. Soldered (including exposed pad for K package) to typical
application PCB with a heat sinking area of 1 sq. in. (645 mm2),
2 oz. (610 g/m2) copper clad.

Conditions
Parameter Symbol SOURCE = 0 V; TJ = 0 to 100 °C Min Typ Max Units
(Unless Otherwise Specified)
Control Functions
TJ = 25 °C
Programmable
fOSC tON × IFB = 1.4 mA-ms VFB = VFBth 85 kHz
Maximum Frequency
See Notes A, F

LNK64x4-64x6 350
Minimum Operation TJ = 25 °C
fOSC(MIN) LNK64x7 760 Hz
Frequency VFB = VFBth
LNK64x8 560

Frequency Ratio TJ = 25 °C
fRATIO(CC) 1.42 1.47 1.53
(Constant Current) Between VFB = 1.3 V and VFB = 1.9 V

Frequency Ratio
Between tON × IFB = 1.4 mA and
(Inductance fRATIO(IC) 1.16 1.21 1.26
tON × IFB = 2 mA-ms
Correction)

Peak-to-Peak Jitter Compared to Average

Frequency Jitter ±7 %
Frequency, TJ = 25 °C

Maximum Duty Cycle DCMAX See Notes D, E 55 %

LNK6404/6405/
TJ = 25 °C 1.915 1.940 1.965
FEEDBACK Pin Voltage VFBth 6406/6446 V
CBP = 1 mF
LNK6415/6416 1.955 1.980 2.005

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Conditions
Parameter Symbol SOURCE = 0 V; TJ = 0 to 100 °C Min Typ Max Units
(Unless Otherwise Specified)
Control Functions (cont.)
LNK6424/6425/
1.995 2.020 2.045
6426

6436 2.035 2.060 2.085

TJ = 25 °C
FEEDBACK Pin Voltage VFBth LNK6407, V
CBP = 1 mF 1.915 1.940 1.965
LNK6408, LNK6448

LNK6417, LNK6418 1.955 1.980 2.005

LNK6427, LNK6428 1.995 2.020 2.045

FEEDBACK Pin Voltage

VFB(AR) 1.14 1.22 1.30 V
at Turn-Off Threshold

Minimum Switch
tON(MIN) See Note E 700 ns
ON-Time

FEEDBACK Pin
tFB See Note G 2.55 2.75 2.95 ms
Sampling Delay

FB Voltage > VFBth

IS1 300 380 mA
(MOSFET Not Switching

LNK64x4 480 540

DRAIN Supply Feedback Voltage = LNK64x5 500 560

Current VFBth -0.1 V,
IS2 Switch ON-Time = LNK64x6 550 620 mA
tON (MOSFET
Switching at fOSC) LNK64x7 600 680

LNK64x8 700 780

LNK64x4 -5.2 -4.4 -2.7

LNK64x5 -6.8 -5.8 -3.3
ICH1 VBP = 0 V LNK64x6 -7.5 -6.1 -3.5
LNK64x7 -7.5 -6.1 -3.5

BYPASS Pin LNK64x8 -7.5 -6.1 -3.5

mA
Charge Current LNK64x4 -5 -2.8 -1.5
LNK64x5 -6.4 -4.0 -1.8
ICH2 VBP = 4 V LNK64x6 -7 -4.2 -2
LNK64x7 -7 -4.2 -2.0
LNK64x8 -7 -4.2 -2.0

BYPASS Pin
VBP 5.65 5.90 6.25 V
Voltage

BYPASS Pin
VBPH 0.70 0.95 1.20 V
Voltage Hysteresis

BYPASS Pin
VSHUNT 6.2 6.4 6.8 V
Shunt Voltage

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 LNK64x4-64x8

Conditions
Parameter Symbol SOURCE = 0 V; TJ = 0 to 100 °C Min Typ Max Units
(Unless Otherwise Specified)

Circuit Protection
di/dt = 60 mA/ms
VBP = 5.9 V LNK64x4 232 250 268
TJ = 25 °C

di/dt = 75 mA/ms
VBP = 5.9 V LNK64x5 290 315 340
TJ = 25 °C

di/dt = 95 mA/ms
Current Limit ILIMIT VBP = 5.9 V LNK64x6 359 390 421 mA
TJ = 25 °C

di/dt = 105 mA/ms

VBP = 5.9 V LNK64x7 390 420 449
TJ = 25 °C

di/dt = 120 mA/ms

VBP = 5.9 V LNK64x8 446 480 513
TJ = 25 °C

Minimum Current
ILIMIT(MIN) 0.27 0.32 0.38
Limit Scale Factor

Normalized Output
IO TJ = 25 °C 0.975 1.000 1.025
Current

Leading Edge TJ = 25 °C
tLED 125 170 ns
Blanking Time Set Note D

Thermal Shutdown
tSD 135 142 150 °C
Temperature

Thermal Shutdown
tSDH 60 °C
Hysteresis
Output
TJ = 25 °C 19.7 23.7
LNK64x4
ID = 96 mA TJ = 100 °C 30.0 36.0

TJ = 25 °C 13.2 15.8
LNK64x5
ID = 105 mA TJ = 100 °C 19.8 23.8

TJ = 25 °C 7.7 9.3
ON-State LNK64x6
RDS(ON) W
Resistance ID = 105 mA TJ = 100 °C 11.5 13.8

TJ = 25 °C 4.8 5.8
LNK64x7
ID = 96 mA TJ = 100 °C 7.2 8.5

TJ = 25 °C 3.1 3.8
LNK64x8
ID = 105 mA TJ = 100 °C 4.6 5.5

VDS = 560 V
IDSS1 50
OFF-State TJ = 125 °C See Note C
mA
Leakage VDS = 375 V
IDSS2 15
TJ = 50 °C

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 LNK64x4-64x8

Conditions
Parameter Symbol SOURCE = 0 V; TJ = 0 to 100 °C Min Typ Max Units
(Unless Otherwise Specified)

Output (cont.)
Breakdown
BVDSS TJ = 25 °C 725 V
Voltage

DRAIN Supply
50 V
Voltage

Auto-Restart
t AR-ON See Notes A, E 300 ms
ON-Time

Auto-Restart
t AR-OFF 1.5 s
OFF-Time

Open-Loop
FEEDBACK Pin IOL See Note E -90 mA
Current Threshold

Open-Loop
See Note E 90 ms
ON-Time

NOTES:
A. Auto-restart ON-time is a function of switching frequency programmed by tON × IFB and minimum frequency in CC mode.
B. The current limit threshold is compensated to cancel the effect of current limit delay. As a result the output current stays constant across
the input line range.
C. IDSS1 is the worst-case OFF-state leakage specification at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a typical
specification under worst-case application conditions (rectified 265 VAC) for no-load consumption calculations.
D. When the duty cycle exceeds DCMAX the LinkSwitch-3 operates in on-time extension mode.
E. This parameter is derived from characterization.
F. The switching frequency is programmable between 60 kHz to 85 kHz.
G. At light load tFB is reduced at 1.8 ms typical.

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 LNK64x4-64x8

Typical Performance Characteristics

1.200 1.200

PI-7558-032615

PI-5086-020515
1.000 1.000
(Normalized to 25 °C)

(Normalized to 25 °C)
0.800 0.800
Current Limit

Frequency
0.600 0.600

0.400 0.400

0.200 0.200

0.000 0.000
-40 -15 10 35 60 85 110 135 -40 -15 10 35 60 85 110 135
Temperature (°C) Temperature (°C)
Figure 8. Current Limit vs. Temperature. Figure 9. Output Frequency vs. Temperature.

1.200 1.200
PI-5087-020515

PI-5088-020515
1.000 1.000
(Normalized to 25 °C)

(Normalized to 25 °C)
Frequency Ratio

Frequency Ratio

0.800 0.800

0.600 0.600

0.400 0.400

0.200 0.200

0.000 0.000
-40 -15 10 35 60 85 110 135 -40 -15 10 35 60 85 110 135
Temperature (°C) Temperature (°C)
Figure 10. Frequency Ratio vs. Temperature (Constant Current). Figure 11. Frequency Ratio vs. Temperature (Inductor Current).

1.200 1.200
PI-7559-032615
PI-5089-020515

Normalized Output Current

1.000 1.000
(Normalized to 25 °C)

(Normalized to 25 °C)
Feedback Voltage

0.800 0.800

0.600 0.600

0.400 0.400

0.200 0.200

0.000 0.000
-40 -15 10 35 60 85 110 135 -40 -15 10 35 60 85 110 135
Temperature (°C) Temperature (°C)
Figure 12. Feedback Voltage vs. Temperature. Figure 13. Normalized Output Current vs. Temperature.

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 LNK64x4-64x8

Typical Performance Characteristics (cont.)

1.1 300

PI-7201-020415
PI-2213-020515
Scaling Factors:
LNK64x4 1.0
250 LNK64x5 1.5
(Normalized to 25 °C)

LNK64x6 2.5

Drain Current (mA)

Breakdown Voltage

LNK64x7 4.0
200 LNK64x8 6.5

1.0 150

100

TCASE=25 °C
50 TCASE=100 °C

0.9 0
-50 -25 0 25 50 75 100 125 150 0 2 4 6 8 10
Junction Temperature (°C) DRAIN Voltage (V)
Figure 14. Breakdown vs. Temperature. Figure 15. Output Characteristic.

1000 50

PI-7203-020415
PI-7202-020415

Scaling Factors: Scaling Factors:

LNK64x4 1.0 LNK64x4 1.0
LNK64x5 1.5 LNK64x5 1.5
Drain Capacitance (pF)

LNK64x6 2.5
40 LNK64x6 2.5
LNK64x7 4.0 LNK64x7 4.0
100 LNK64x8 6.5 LNK64x8 6.5
Power (mW)

30

20
10

10

1 0
0 100 200 300 400 500 600 0 200 400 600
Drain Voltage (V) DRAIN Voltage (V)

Figure 16. COSS vs. Drain Voltage. Figure 17. Drain Capacitance Power.

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 LNK64x4-64x8

SO-8C (D Package)
0.10 (0.004) C A-B 2X
2 DETAIL A
4 B
4.90 (0.193) BSC

A 4
D
8 5

GAUGE
PLANE
SEATING
PLANE
2 3.90 (0.154) BSC 6.00 (0.236) BSC o
C 0-8
0.25 (0.010)
1.04 (0.041) REF
BSC
0.10 (0.004) C D
0.40 (0.016)
2X 1
Pin 1 ID 4 0.20 (0.008) C 1.27 (0.050)
1.27 (0.050) BSC 2X
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D

1.35 (0.053) 1.25 - 1.65

1.75 (0.069) DETAIL A
(0.049 - 0.065)

0.10 (0.004) 0.10 (0.004) C H

0.25 (0.010) 7X
SEATING PLANE

C 0.17 (0.007)
0.25 (0.010)

Reference
Solder Pad +
Dimensions
Notes:
1. JEDEC reference: MS-012.
2.00 (0.079) 4.90 (0.193) 2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
+ + + 5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
1.27 (0.050) 0.60 (0.024)
D07C PI-4526-012315

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 LNK64x4-64x8

eSIP-7C (E Package)

2
0.403 (10.24) C
0.397 (10.08) 0.264 (6.70)
A 0.081 (2.06) Ref.
0.077 (1.96)
B

Detail A
2
0.325 (8.25) 0.290 (7.37)
Ref. 0.198 (5.04) Ref.
0.320 (8.13)
0.519 (13.18)
Ref.

Pin #1 0.207 (5.26)

0.140 (3.56) 0.016 (0.41)
I.D. 0.187 (4.75)
0.120 (3.05) Ref.

0.070 (1.78) Ref. 0.047 (1.19) 3 4

0.033 (0.84)
0.050 (1.27) 0.100 (2.54) 6×
3 0.016 (0.41) 6×
0.028 (0.71)
0.011 (0.28) 0.118 (3.00)
0.010 M 0.25 M C A B
0.020 M 0.51 M C
FRONT VIEW SIDE VIEW BACK VIEW

10° Ref. 0.100 (2.54)

All Around 0.021 (0.53)
0.019 (0.48)
0.060 (1.52) 0.020 (0.50) 0.050 (1.27)
Ref. 0.050 (1.27)
PIN 1

0.048 (1.22) 0.059 (1.50) 0.155 (3.93)

0.378 (9.60) 0.046 (1.17)
Ref. 0.019 (0.48) Ref.
0.023 (0.58)
PIN 7
END VIEW
0.027 (0.70)
0.059 (1.50)
DETAIL A
Notes:
0.100 (2.54) 0.100 (2.54)
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost extremes of the plastic MOUNTING HOLE PATTERN
body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but (not to scale)
including any mismatch between the top and bottom of the plastic body.
Maximum mold protrusion is 0.007 [0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches (mm).
PI-4917-020515

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 LNK64x4-64x8

eSOP-12B (K Package)

0.010 [0.25]
0.356 [9.04] Ref.
2 Ref. 0.055 [1.40] Ref.
0.004 [0.10] C A 2X
0.400 [10.16]
Pin #1 I.D. 0.325 [8.26] H
(Laser Marked) Max. 7 0.010 [0.25]
2X 7 12
Gauge
0.004 [0.10] C B Plane
Seating Plane
0.059 [1.50]
0 °- 8°
C
2 0.034 [0.85]
Ref, Typ 0.225 [5.72]
0.460 [11.68] 0.350 [8.89] 0.026 [0.65]
Max. 7
0.059 [1.50]
Ref, Typ
DETAIL A (Scale = 9X)

0.008 [0.20] C 1 2 3 4 6 B 6 1 0.049 [1.23]

3 4 0.028 [0.71] 0.046 [1.16]
2X, 5/6 Lead Tips 0.023 [0.58] 0.120 [3.05] Ref
11× Ref.
0.018 [0.46]
0.070 [1.78]
0.010 (0.25) M C A B

TOP VIEW BOTTOM VIEW

0.019 [0.48]
Ref.
0.020 [0.51]
Ref. 0.022 [0.56]
0.092 [2.34] Ref.
0.098 [2.49] 0.032 [0.80] 3
0.086 [2.18] 0.029 [0.72] 0.086 [2.18]
0.016 [0.41]
0.011 [0.28]
11×
Seating
Plane
0.006 [0.15] 0.004 [0.10] C C 0.306 [7.77]
0.000 [0.00] Ref.
Detail A
Seating plane to
package bottom
SIDE VIEW END VIEW
standoff

0.067 [1.70] Land Pattern

0.217 [5.51]
Dimensions
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
1 12 2. Dimensions noted are determined at the outermost
0.028 [0.71] extremes of the plastic body exclusive of mold flash,
2 11 tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom of
the plastic body. Maximum mold protrusion is 0.007
3 10 [0.18] per side.
0.321 [8.15] 3. Dimensions noted are inclusive of plating thickness.
4 9 4. Does not include interlead flash or protrusions.
5. Controlling dimensions in inches [mm].
8 6. Datums A and B to be determined at Datum H.
7. Exposed pad is nominally located at the centerline of
6 7 Datums A and B. “Max” dimensions noted include both
size and positional tolerances.
0.429 [10.90]
PI-5748a-020515

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 LNK64x4-64x8

Part Ordering Information

• LinkSwitch Product Family
• 3 Series Number
• Package Identifier
D SO-8C
E eSIP-7C
K eSOP-12B
• Tape & Reel and Other Options
Blank Standard Configuration
LNK 64x7 D - TL TL Tape & Reel, 2.5 k pcs for D package, 1 k pcs for K package.

17
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 Revision Notes Date
A Code A. 10/16/13
A Specified Max BYPASS Pin Current. 03/13/14
A Code L. Updated Table 1 and Table 2. 06/11/14
Added LNK64x4, 64x5 and 64x6 parts. Updated fRATIO(CC), ILIMIT(MIN), tFB, VFB(AR), fOSC(MIN), t AR-OFF and IOL. Updated ms values in
B 03/31/15
Auto-Restart section on page 3. Removed fOSC(AR) and updated t AR-ON.
C Added Note G on page 11. 03/16

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at http://www.power.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.

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