A High Resolution and High Accuracy R-2R DAC

Based on Ordered Element Matching

You Li, Tao Zeng and Degang Chen
Department of Electrical and Computer Engineering, Iowa State University
Ames, Iowa 50011 USA

Abstract—Random mismatch errors in the resistor networks are I in

one of the dominant nonlinearity sources for high resolution and Vin
high accuracy resistor DACs. This paper applies the theory of
ordered element matching in a high resolution segmented R-2R
DAC. It can achieve high matching accuracy by regrouping the
resistors in the MSB array according to their resistance ranks
I out
obtained by the INL test. The implementation only requires
adding some additional digital circuits to the typical design. A Vout
behavioral model of 18-bit segmented R-2R DAC is created in
MATLAB. The statistical results show a significant resistor area b1B b2B bLB b1U b2U U
bM
reduction compared with state of the art.

I. INTRODUCTION

Up until now, the performance of digital circuits is Figure 1. Current-output segmented R-2R DAC
constantly enhanced by the scaling of device dimension and
supply voltage. However, the technology advancement does elements to minimize the mismatch errors. Unfortunately, this
not benefit many analog and mixed-signal circuits and in fact technique usually demands high expenses such as extra layer
it poses higher requirements on their performance. Digital-to- or more die area for trim-pads and the achieved accuracy is
analog converter (DAC) is one of the circuits facing high reduced by the temperature and aging effects [5].
performance demand in high-resolution high-accuracy signal Besides these, calibration is another popular technique, but
processing and telecommunication applications. it is mainly used in other types of DACs. It could cut down
The R-2R DACs offer high resolution and simple structure, the mismatch errors by feed-back signals from error
which makes them easy to realize and widely used. Fig.1 measuring circuits such as a high-resolution high-accuracy
illustrates a typical structure of the current-output segmented analog-to-digital converter (ADC) [6]-[7]. Due to its design
R-2R DAC which is extensively used in high accuracy complexity, this technique is rarely used in R-2R DACs.
applications such as sensors and digital instruments. Ordered element matching (OEM) theory [3] showed the
However, the accuracy of a R-2R DAC is very sensitive to capability of significantly reducing the random mismatch
the matching performance of the resistor networks. Yet, the errors in unary weighted circuit components. By combining
integrated-circuit (IC) fabrication technology always produces and grouping components with complementary mismatch
imperfectly matched resistors and with the process scaling the errors together, the total random mismatch errors could be cut
random mismatch errors deteriorate significantly [1]-[2]. down. It mainly consists of two steps, firstly sort the circuit
Therefore, random mismatch is regarded as one of the major components according to their parameter magnitudes, and
sources of errors that degrade the linearity and yield then pair and sum the complementary ordered components
performance of a R-2R DAC. (which is called “folding” operation). The random mismatch
The most straightforward approach to reduce random errors can be further decreased if the folding operation
mismatch errors is to enlarge the area of R-2R DAC. From continues and eventually transforms the unary weighted array
[3], 1-bit linearity enhancement will lead to a quadruple of into a binary weighted array, which is called “complete
circuit area, which is a huge cost increase especially for the folding” [3] [8].
high resolution designs. Moreover, parasitic capacitance In this paper, a novel segmented R-2R DAC design based
effects of the large size devices undermine the performance of on OEM theory is presented. We get the order of unary
the DACs and often bring up more power consumption [4]. weighted resistors from the INL test and implement complete
Additionally, several other techniques can be applied to folding according to their order. Statistical results based on
compensate random mismatch errors for R-2R DACs. The MATLAB model show that an 18-bit segmented R-2R DAC
most popular one is trimming technique, which could be achieves the same accuracy in much smaller resistor area
mainly divided into two categories: the laser-trimming and compared to state of the art.
fuse-trimming. Laser-trimming employs the laser beams to This paper is organized as follows. In Section II, the OEM
accurately adjust the resistor parameters at the wafer level; based R-2R DAC is presented in details. The MATLAB
while fuse trimming utilizes the fuse or anti-fuses for opening behavioral model and statistical results are provided in
or closing the interconnections of a network of resistive Section III. Finally the conclusion is drawn in Section IV.

978-1-4673-5762-3/13/$31.00 ©2013 IEEE 1974

 Subtract (3) from (4):
'' ' 1
I out − I out = Vin × (5)
RTM+1
From (5) the value of the (T+1)th MSB resistor ( RTM+1 ) could
be estimated by measuring the difference of output current
when switching (T+1)th unary bit from 0 to 1.
Now considering the INL test, the INL at digital input
code D can be written as:
I out ( D) − I out (0)
INL ( D ) = −D (6)
[ I out ( N ) − I out (0)] / N
where, N = 2 n − 1 and n is the DAC’s resolution. If we write
the INL at D1 as:
Fiugre 2. INL curve of 14 bits current-output with 3-11 segmentation L T
R-2R DAC INLTb B ...b B = INL(∑ bkB × 2k −1 + ∑ 2 L ) (7)
1 L
k =1 k =1

II. R-2R DAC BASED ON OEM and assuming I out (0) = 0 , then (7) equals to:
L T

A. Analysis of the typical R-2R DAC I out (∑ bkB × 2k −1 + ∑ 2 L )

The current-output segmented R-2R DAC often consists INLTb B ...b B = k =1 k =1
1 L
I out ( N ) / N (8)
of unary weighted bits ( b1U − bMU ) and binary weighted bits
L T
( b1B − bLB ). The former part is often called the most significant −(∑ bkB × 2k −1 + ∑ 2 L )
bit (MSB) array, whereas the other part is named as the least k =1 k =1

significant bit (LSB) array as shown in Fig.1. The MSB input Similarly, we can write the INL at D2 as:
bits need a binary to unary decoder, while the delay equalizer L T +1

is used to align the timing of LSB with the MSB bits. I out (∑ bkB × 2k −1 + ∑ 2 L )
Based on the accurate matched resistors, the output current INLTb B+...1 b B = k =1 k =1

can be calculated as:

1 L
I out ( N ) / N (9)
L T +1
L
bkB M
bU −(∑ bkB × 2k −1 + ∑ 2 L )
I out = I in (∑ M
+ ∑ kM ) (1)
k =1 k + ∑ bi k =1 1+ ∑ bi k =1 k =1
U U

2 i=1 2 i=1 then, subtract (8) from (9), and take (5) into the equation:
where, I in is the input current, and L and M are the resolutions I" − I '
INLTb B+...1 b B − INLTb B ...b B = out out − 2 L
of LSB and MSB array, respectively. It is well-known that the 1 L 1 L
I out ( N ) / N
R-2R DAC’s accuracy is mainly decided by the matching (10)
level of the resistors in the MSB array. As a result, most of Vin / RTM+1 L
= −2
our works in this paper focus on minimizing the MSB resistor I out ( N ) / N
mismatch errors. Based on (10), it is obvious that the (T+1)th MSB resistor
( RTM+1 ) could be estimated by evaluating the INL difference
B. Resistor order extractions from INL test when (T+1)th unary bit change from 0 to 1.
It is easy to simplify (1) into: Additionally, in order to minimize the noise effect, we will
1 M
bkU keep the unary bits of D1 and D2 unchanged but sweep their
I out = Vin × ( + ∑ )
Re(b1B ...bLB ) k =1 RkM
(2) binary bits ( b1B − bLB ) from all ‘0’ to all ‘1’, and then calculate
where, Vin is the input voltage; RkM is the kth MSB resistor the average difference of INL as:
value; Re is the equivalent resistor value of LSB array and it INLTmv+1 = INLTbB+...1 bB − INLTbB ...bB
1 L 1 L
is determined by the binary weighted bits. " ' (11)
If we arbitrarily choose one digital input code D1 where I −I V / RM
= out
− 2 L = in T +1 − 2 L
out
its first T unary weighted MSB bits set to ‘1’ and the rest of I out ( N ) / N I out ( N ) / N
unary weighted bits set to ‘0’, the output current at D1 is:
T where, INLTb B+...1 b B and INLTb B ...b B are the intended average INLs
1 1
+∑ M )
' 1 L 1 L
I out = Vin × ( B B
(3) " '
Re(b1 ...bL ) k =1 Rk for D1 and D2, respectively; I out and I out are the related
Now define another input code as D2 where we switch the output currents. Then, a more accurate estimation for (T+1)th
(T+1)th unary bit from ‘0’ to ‘1’ and keep all other bits the MSB resistor ( RTM+1 ) can be obtained .
same, the output current changes to:
T +1
1 1
''
I out = Vin × ( + ∑
Re(b1 ...bL ) k =1 RkM
B B
) (4)

1975
 weighted array is converted into 3-bit binary weighted array,
the mismatch errors are further reduced. This process is so-
called "complete-folding" [3].
In [8], the complete-folding technique was introduced for
current-steering DACs. It requires an accurate analog
comparator to measure the difference between the currents to
rank all the MSB current sources. However, in this paper, the
ranks of resistors are directly obtained from the INL test, so
there is no requirement for additional analog circuitry and we
only need replace the binary-to-unary decoder with a register
and mux array as shown in Fig. 4. Then, each MSB resistor
contains one mux and register. The address code obtained
from the complete-folding operation is stored into each
register, and based on those codes the MUX chooses the
appropriate input bit to control the corresponding MSB
resistor. The register and mux array can easily be
implemented and they scale with the IC technology.

III. MATLAB SIMULATION RESULTS

Figure 3. Complete folding for a 3-bit unary weighted resistors array
A MATLAB model of an 18-bit current output R-2R DAC
with 7-11 segmentation is built based on Fig. 1 to verify the
OEM based matching performance. In order to compare with
state of the art, three types of R-2R DAC models are included,
i.e., the original DAC without any mismatch compensation,
the trimmed DAC with technique presented in [9], and the
OEM based DAC proposed in the last section.
Before anything, it is worth mentioning the setup of each
DAC model. The original DAC just utilizes large resistor area
to compensate random mismatch errors. In [9] the new laser
trimming technique allows trimming MSB resistors with at
least 48-ppm accuracy over a range about 0.1%. The trimmed
Figure 4. Register and mux array DAC model uses this technique but increases the trimming
accuracy from 48-ppm to 10-ppm in the simulations. This
From (11), it is clear that all the unary resistors can be change will bring up the implementation cost. The OEM
ranked from the INL test. To illustrate this concept, we will based DAC needs 6-time folding operations, and 24 extra
take a 14-bit R-2R DAC with 3-11 segmentation as an MSB resistors are included for outlier elimination to discard
example. Fig. 2 shows an INL curve of this DAC model. By the large defects in the design as presented in [3].
measuring the average INL difference between two MSB bit In Fig. 5, it shows DNL and INL distributions of 10,000
transitions, it could estimate the corresponding MSB resistor randomly generated 18-bit DACs with standard deviation
value. If we repeat this process, all the unary MSB resistors σ = 0.021% for each DAC model. From the comparisons, the
can be ranked according to their magnitudes. OEM based R-2R DAC achieves much better accuracy for the
same relative unit resistor standard deviation.
C. Resistor reorganization by complete-folding Fig. 6 indicates the yield estimations by Monte Carlo
simulation with DNL < 0.5 LSB and INL <0.5 LSB for all
As illustrated in Fig.3, each rectangle denotes a resistor three DAC models. In order to achieve yield >99.7% with
with random mismatch error. Based on INL test, all MSB INL <0.5 LSB, we can get the required standard deviation of
resistors are sorted according to their magnitudes. Next, all the the unit resistor for each model from Fig. 6(b). Then the area
complementary ordered resistors are paired, and only the deduction factor can be calculated based on these standard
resistor in the middle is left alone. This operation is called one deviations, and the results are concluded in TABLE 1. As one
“folding” [3]. In this way, the original 3-bit unary coded can see, for the same yield requirement the proposed R-2R
resistor array is converted into a 2-bit unary-weighted and 1- DAC has as large as 196 area reduction factor! Since the
bit binary-weighted array. In details, the resistor value of each mismatch error is dominated by the LSB array in the
2-bit unary weighted array is nearly twice of the last single simulation model, the area reduction factor can be improved
resistor, and the random variations in resistors are reduced. much more if we assign different areas for LSB and MSB
The mismatch errors are consistently diminishing after arrays.
each folding operation. As shown in Fig.3, if the INL test and
single folding operation are repeated until the 3-bit unary

1976
 Figure 5. DNL and INL distribution comparison of 10,000 randomly
generated resistor arrays in18-bit R-2R DAC with δ = 2.1×10−4

Furthermore, the OEM based DAC has big advantages in

implementation. The trimmed DAC requires special process,
and accurate test equipment, all of which demand high cost. In
comparisons, the OEM based DAC only needs to add some
digital circuits to the original design, which can easily be
implemented with the modern IC technologies. Besides these,
we can measure INL on-chip for some BIST applications so
that the mismatch errors can be continuously corrected using
our technique. Alternatively, we can obtain the optimal
groupings based on the INL test at productions. In this case,
similar to the traditional trimming technique, it will not
account for the temperature and aging effects, but the
implementation cost is greatly reduced. Figure 6. Yield comparisons of 18-bit segmented R-2R DACs with (a)
DNL<0.5LSB and (b) INL<0.5LSB
IV. CONCLUSION
TABLE1. REQUIRED STANDEARD DEVIATION AND AREA DEDUCTION
In this paper, a novel high resolution and high accuracy R- FOR YIELD>99.7% WITH INL<0.5LSB
Types of 18-bit R-2R Standard deviation Area deduction
2R DAC based on OEM theory has been presented. It
DAC (%) factor
achieves high accuracy by re-grouping the MSB resistors
Original R-2R DAC 0.001 1
corresponding to their magnitude orders obtained from the
INL test. Its implementation only requires adding some digital Trimmed R-2R DAC 0.005 25
circuits into the traditional design. A MATLAB behavioral
Proposed R-2R DAC 0.014 196
model of 18-bit segmented R-2R DAC is created. The
statistical results show that the proposed R-2R DAC can
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compared to state of the art. Dec. 2000.
[7] Y. Cong and R. L. Geiger, “A 1.5-V 14-bit 100MS/s self-calibrated
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