29 June – 1 July 2006, Sofia, Bulgaria

R-2R Digital-to-Analog Converter:

Analysis and Practical Design Considerations
Dimitar P. Dimitrov1

Abstract – The following article is an attempt to describe the D = (bN-1x2 N-1; bN-2x2 N-2;….b1x2 1; b0x2 0)
rudiments of R-2R structures in reverse connection and
their application in D/A converters. An important disadvantage of the current mode R-2R
Analysis of R-2R ladders is made simple and intuitive by structures is the need for an operational amplifier that
using Thevenin equivalent circuits. Formulae expressing performs the current-to-voltage conversion.
all the basic properties of R-2R structures are derived The opamp itself introduces errors such as offset voltage,
using this approach. Practical design considerations are limited slew rate, limited output swing, etc.
also discussed in great detail. To prove the theoretical The output of the voltage-mode R-2R DAC is voltage, so no
analysis, test structures are designed and fabricated in opamp is needed provided the load impedance is high enough,
1.0 µm
µ and 0.6µ µm double-poly, double-metal CMOS pro- which is usually the case in CMOS circuits.
cesses. Experimental results are then analyzed. In this article, the long-neglected voltage-mode R-2R DAC is
discussed in some more detail. Expressions are derived for all
Keywords – ADC, R-2R, mixed-signal, CMOS the basic properties of the R-2R ladders by means of Thevenin
equivalent circuits. The emphasis is on the practical design
I. INTRODUCTION considerations and design methodology.
The rudiments of R-2R ladder in voltage mode are discussed
R-2R structures of digital-to-analog converters (DAC) are in Section II.
very popular for their simplicity. For a DAC with a resolution Errors and error sources are dealt with in Section III
of N bits 2N+1 resistors and 2N switches are necessary. In Experimental results are given in Section IV.
addition, only two resistor values are needed: R and 2R.
Moreover, since 2R=R+R (and vice versa: R=2R//2R), only II. THE VOLTAGE-MODE R-2R DAC
one resistor value is actually required. Thus the entire R-2R
ladder is implemented as an array of equal resistors. Fig. 2 shows a network of N cascaded R-2R links, numbered
There are two basic types of R-2R DACs [1] [2] [3]: from 0 to N-1.
- current mode (current steering).
- voltage mode (R-2R ladder in inverse connection).
The current mode DAC has been considered as the
traditional approach. In this approach, the R-2R ladder is used
to produce a set of binary-weighted currents whose sum is
then converted to voltage (Fig.1)

Fig. 2. The voltage mode R-2R DAC

Note that in contrast to the current-steering ladder, the basic

R-2R links are connected in reverse order.
A terminating resistor of value R is connected to the leftmost
link (numbered 0), so that the equivalent impedance seen to
the left each link is exactly R and the equivalent impedance
Fig. 1. Current mode R-2R DAC seen at the output node VN-1 is also R.
The Thevenin equivalent circuit for an arbitrary R-2R link is
The voltage at the output of the current-mode DAC is Eq. 1: shown in Fig. 3

k =2n −1
R
VOUT = − RF × ∑ I k = −VREF × 2RF × D (1)
k =0

Where D is the digital word applied to the converter:

1
Dimitar P. Dimitrov works at Melexis-Bulgaria Ltd.
84 Ami Boue Str., 1612 Sofia, Bulgaria Fig. 3. Thevenin equivalent circuit of the voltage mode
e-mail: ddi@melexis-bg.com R-2R DAC

266
 Dimitar P. Dimitrov

For an arbitrary link K, the following expression holds: The power consumed from the digital supply is actually zero,
since no current flows through the switch gates.
V Nth−1 V
V Kth = + bit K × REF → for...bit K ⊂ (0,1) (2)
2 2 III. ERROR SOURCES IN VOLTAGE-MODE R-2R DAC
The index “th” stands for “Thevenin” equivalent circuit. Effects of tolerances and device mismatch
Applying this recurrent formula to the entire chain of N basic
links, numbered from 0 to N-1, yields the voltage at the last Device mismatch is the major source of error in any DAC.
node (the output of the DAC) Eq. 3 The stochastic matching between two identically designed
resistors is defined as the standard deviation of the normal
VREF VREF VREF distribution for the relative difference δR.
VOUT = VN −1 = bN −1 × + bN − 2 × + ...... + b0 ×
21 22 2N (3)
VREF ∆R
= ×D δR = (7)
2 N R
where D is the digital code applied: The matching of two identically designed resistors with size
W x L is described by the following model [4]:
D = (bN-1x2 N-1; bN-2x2 N-2;….b1x2 1; b0x2 0).
AR
In summary, the entire R-2R ladder can be replaced with a δR = (8)
Thevenin equivalent circuit with equivalent open-circuit W×L
voltage VOUT and output impedance ZOUT, Eq (4): where AR is a process-dependent matching parameter.
V REF The influence of device mismatch of each R-2R link increases
VOUT = ×D as its rank in the ladder increases. The Differential
2N (4)
Nonlinearity (DNL) and the Integral Nonlinearity (INL) are
Z OUT =R likely to reach their maximum around the major carry points
that involve the most significant bit (i.e transitions like
Power consumption 0111…111 -> 1000…000). The worst case occurs when all
A point worth mentioning is that in contrast to the current- resistors are at their minimum (maximum) values and only the
modeR-2R ladder, the power consumption of the voltage- 2R resistor of the most significant bit (bN-1) is at its maximum
mode R-2R ladder is not constant but varies with the code (minimum) value.
applied.
R = R − ∆R = R (1 − δ R )
(9)
For all bits = “0” power consumption is also zero (all 2R 2 R BITN −1 = 2( R + ∆R) = 2 R(1 + δ R )
resistors are connected to GND). When only one bit is “1” the
consumption is VREF/3R. Maximum consumption occurs at The equivalent Thevenin circuit is shown in Fig. 5
codes 010101…01 and 101010…11 (Fig. 4)

Fig. 4. The load applied to the reference source

Fig. 5. The effect of device mismatch
If the number of R-2R links (i.e. number of bits) is large
enough, the problem can be simplified by assuming that the Using this circuit the absolute values of DNL and INL can be
contribution of the resistors R01 and RT is negligible in expressed in terms of least-significant bits:
comparison to all the other resistors. Then all nodes across DNL = 2 N × δ R (10)
lines A-A and B-B would be at potentials VA and VB N −1
respectively. Thus the impedance seen by the reference is: INL = 2 ×δR (11)

2 R × 2 R 2R × 2 9R Switch imperfection
RE = + + = (5)
N N N N a) On-resistance of closed switches. The on-resistance of a
And the current flowing out of the reference is: closed switch adds to the resistance of the corresponding 2R
resistor. That is, its actual value becomes Ra=2R+RON. Since
V REF N the value of R resistors is not affected by switches, the actual
I VREF = = V REF × (6)
RE 9R division ratio of the basic R-2R link changes, resulting in
integral and differential nonlinearity.
This formula is accurate if the number of bits is large enough. The equivalent Thevenin circuit with RON included is shown
For N more than or equal to 8 bits the error is less than 10%. in Fig. 6.

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 R-2R Digital-to-Analog Converter: Analysis and Practical Design Considerations

Influence of the load impedance

As shown in Fig. 3 and Eq. 3, the voltage mode R-2R DAC
can be represented by its equivalent Thevenin circuit, which
has an open-circuit ideal voltage source and output impedance
ZO. When a finite load impedance ZL is applied, the actual
output voltage is:
Fig. 6 – The influence of the switches ZL
VOUT = V REF × D × (14)
Z L + ZO
With RON included, the expressions for DNL and INL are (in
terms of LSB): All codes are attenuated by the same factor. That is, the finite
N  R  load impedance causes an additional gain error expressed in
DNL = 2 ×  − δ R − ON  (11)
 4R  Eq. 12
 4 R × δ R − RON  IV. EXPERIMENTAL RESULTS
INL = 2 N ×  

(12)
 8 R + 2 RON  The voltage-mode DAC shown in Fig. 2 was fabricated in
Note that since δR can be either positive or negative, the first 1.0 µm and 0.6µm double-poly, double-metal CMOS
term in the brackets in Eq. (11) and (12) can also be either processes. Several R-2R structures were prepared for a
positive or negative. However, RON is always positive. resolution of 12, 10 and 8 bits. To check the influence of the
layout, three different layout schemes were employed for the
b) Switch leakage. Since every 2R resistor is connected either 8-bit DAC. Every effort was made at the layout phase to
to VREF or to GND, which are both low impedance nodes, the ensure good device matching and to keep the lengths of the
leakage currents flow into VREF or into GND rather than into interconnecting wires equal. Tests were performed by means
the resistor array. That is why switch leakage currents do not of a special test kit and a KEITHLY 2000 digital voltmeter.
affect DAC performance provided the reference source is low The test results are given in Fig. 7 – Fig. 10. The minimum
ohmic. Tests of real devices show that the effect of switch measured values are in blue, the maximum measured values
leakage is negligible. are in red. The increase of both INL and DNL at the major
carry point is easily seen. Device mismatch is the major
Poor layout source of error in voltage-mode R-2R DAC. The errors of the
Poor layout can significantly spoil device matching, thus converters are actually determined by the mismatch of the two
leading to INL and DNL. Straight-forward layout (devices in most significant bits. As predicted by Eq. 10 and Eq. 11, for
a row) is the simplest and most compact way to place a set of the same device mismatch, the DNL is (in terms of LSB)
resistors. However, it is prone to process deviations along the twice as big as INL. If DNL is higher than 1 LSB the
wafer. A layout with one axis of symmetry can significantly conversion monotonicity is not guaranteed. The improvement
compensate for process deviations along this axis. A layout of conversion linearity (both INL and DNL) for the
which is symmetrical in respect to two axes of symmetry symmetrical layouts (one axis of symmetry and common-
(common-centroid layout) can effectively compensate for the centroid) as compared to the straightforward layout is partially
process deviations along both the horizontal and the vertical due to the fact that in symmetrical layout schemes devices are
axes at the price of an increased die area and an elaborate split into several unit devices whose total area is larger than
interconnection scheme. the area of the straight-forward layout. Test results are
summarized in Table I:
Influence of the reference source
TABLE I
As mentioned above, the current flowing out of the reference
MEASURED R-2R DAC NONLINEAREITY
source varies with the digital code applied. The changes in the
current consumed cause changes in the voltage drop across the DAC type: process and INL [LSB] DNL [LSB]
output impedance RI of the reference. These code-dependent layout scheme
voltage drops result in integral nonlinearity. The error caused 12-bit; 1µm CMOS 1,5 2,6
by this parasitic voltage drop is: common-centroid layout
10-bit; 1µm CMOS 0,6 1,1
∆VREF RI (N − 3) one axis of symmetry
δ VREF = = (13)
VREF 9R 8-bit; 1 µm CMOS 0,18 0,32
one axis of symmetry
A fact which is often neglected at the layout phase is that the 8-bit; 0,6µm CMOS 0,11 0,22
wires connecting the converter to the reference source and to straightforward layout
ground also have parasitic resistance, which adds to the output 8-bit; 0,6µm CMOS 0,09 0,17
impedance of the reference source. one axis of symmetry
8-bit; 0,6µm CMOS 0,05 0,09
common-centroid layout

268
 Dimitar P. Dimitrov

V. CONCLUSIONS DNL
[LSB]
8-bit R-2R DAC; 0,6mm CMOS process; common-centroid layout
INL versus input code (min/max values); T=25oC; V REF=VDD=5V; test results
0,10
The voltage-mode R-2R DAC (R-2R in reverse connection) 0,08
has been discussed in this article as an effective way to 0,06
circumvent the problems associated with the opamp in 0,04
current-mode R-2R DACs. Theoretical analysis using 0,02
Thevenin equivalent circuits has been proposed that gives 0,00
insight into the voltage-mode R-2R DAC operation. The -0,02
derived expressions have been proved by means of design -0,04

experiment. Experimental results agree with the formulae -0,06

derived in Section II. Ways to reduce the INL and DNL by -0,08

means of proper layout techniques have also been discussed in -0,10 code
0 32 64 96 128 160 192 224 256 [dec]
brief.
Fig. 10. INL of 8-bit R-2R DAC; Common-centroid layout
INL 12-bit R-2R DAC; 1mm CMOS process; common-centroid layout
[LSB] INL versus input code (min/max values); T=25oC; VREF=VDD=5V; test results
1,5

1,0

0,5

0,0

-0,5 code
0 512 1024 1536 2048 2560 3072 3584 4096 [dec]
Fig. 11. Die photograph of 12-Bit DAC, 1µm CMOS process
Fig. 7. INL of 12-bit R-2R DAC

DNL 12-bit R-2R DAC; 1µ

µ m CMOS process; common-centroid layout
[LSB] DNL versus input code (min/max values); T=25 oC; V REF=VDD=5V; test results
1,5

1,0

0,5

0,0

-0,5

-1,0

-1,5

-2,0

-2,5

-3,0 code
0 512 1024 1536 2048 2560 3072 3584 4096 [dec]

Fig. 12. Die photograph of 8-Bit DAC, 0.6µm CMOS process;

Fig. 8. DNL of 12-bit R-2R DAC Straight-forward layout

INL 8-bit R-2R DAC; 0,6µ

µ m CMOS process; common-centroid layout
[LSB]
INL versus input code (min/max values); T=25 oC; VREF=VDD=5V; test results
0,06 REFERENCES
0,04 [1] Mikael Gustavsson, J. Jacob Wikner, Nianxiong Nick Tan,
“CMOS Data Converters for Communications”, Kluwer Academic
0,02
Publishers, 2002, pp. 64-79.
0,00
[2] R. Jacob Baker “CMOS, Mixed-Signal Circuit Design”, Wiley-
IEEE Press, July 2002
-0,02 [3] David A. Johnes, Ken Martin, “Analog Integrated Circuit
Design”, John Wiley & Sons, 1997, pp. 507-11.
-0,04 [4] Marcel J. M. Pelgrom, Aad C. J. Duinmaijer, Anton P. G.
Welber,s “Matching propertries of MOS transistors”, IEEE JSSC,
-0,06 code vol. SC-24, October 1989, pp. 1433-39
0 32 64 96 128 160 192 224 256 [dec]
[5] John A. Schoeff, “An inherently Monotonic 12 Bit DAC”, IEEE
JSSC vol. SC-14, December 1979
Fig. 9. INL of 8-bit R-2R DAC; Common-centroid layout

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