STM8L052C6

Value Line, 8-bit ultra-low-power MCU, 32-KB Flash, 256-byte data

EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC
Datasheet - production data

Features
 Operating conditions
– Operating power supply: 1.8 V to 3.6 V
– Temperature range: -40 °C to 85 °C
LQFP48
 Low-power features 7 x 7 mm
– Five low-power modes: Wait, Low-power
run (5.1 µA), Low-power wait (3 µA), Active-  DMA
halt with full RTC (1.3 µA), Halt (350 nA) – Four channels supporting ADC, SPI, I2C,
– Consumption: 195 µA/MHz + 440 µA USART, timers
– Ultra-low leakage per I/0: 50 nA – One channel for memory-to-memory
– Fast wakeup from Halt: 4.7 µs  12-bit ADC up to 1 Msps/25 channels
 Advanced STM8 core – Internal reference voltage
– Harvard architecture and 3-stage pipeline  Timers
– Max freq. 16 MHz, 16 CISC MIPS peak – Two 16-bit timers with two channels (used
– Up to 40 external interrupt sources as IC, OC, PWM), quadrature encoder
– One 16-bit advanced control timer with three
 Reset and supply management
channels, supporting motor control
– Low-power, ultra-safe BOR reset with five
– One 8-bit timer with 7-bit prescaler
selectable thresholds
– Two watchdogs: one Window, one
– Ultra-low-power POR/PDR
Independent
– Programmable voltage detector (PVD)
– Beeper timer with 1-, 2- or 4-kHz
 Clock management frequencies
– 32 kHz and 1 to 16 MHz crystal oscillator  Communication interfaces
– Internal 16 MHz factory-trimmed RC
– Synchronous serial interface (SPI)
– Internal 38 kHz low consumption RC
– Fast I2C 400 kHz SMBus and PMBus
– Clock security system
– USART (ISO 7816 interface and IrDA)
 Low-power RTC
 Up to 41 I/Os, all mappable on interrupt vectors
– BCD calendar with alarm interrupt
– Auto-wakeup from Halt w/ periodic interrupt  Development support
 LCD: up to 4x28 segments w/ step-up – Fast on-chip programming and non-
converter intrusive debugging with SWIM
– Bootloader using USART
 Memories
– 32 KB Flash program memory and
256 bytes data EEPROM with ECC, RWW
– Flexible write and read protection modes
– 2 Kbytes of RAM

March 2015 DocID023331 Rev 2 1/103

This is information on a product in full production. www.st.com
Contents STM8L052C6

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 Advanced STM8 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Low-power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6 LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10 System configuration controller and routing interface . . . . . . . . . . . . . . . 19
3.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.1 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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STM8L052C6 Contents

3.14.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 56
8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.3.9 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.3.11 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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Contents STM8L052C6

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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STM8L052C6 List of tables

List of tables

Table 1. Medium-density value line STM8L052C6 low-power device features and

peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. Legend/abbreviation for Table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4. Medium-density value line STM8L052C6pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 5. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 9. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 10. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 11. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 12. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 13. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 14. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 15. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 16. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 17. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 18. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 19. Total current consumption and timing in Low power run mode at VDD = 1.8 V
to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 63
Table 21. Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V. . . . . . 64
Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 65
Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 66
Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 25. Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 26. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 27. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 29. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 32. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 33. Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 34. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 36. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 37. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 38. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 78
Table 39. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 40. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 41. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 42. LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 43. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 44. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 46. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

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List of tables STM8L052C6

Table 47. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 48. RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 49. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 50. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 53. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . . 99
Table 54. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 55. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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STM8L052C6 List of figures

List of figures

Figure 1. Medium-density value line STM8L052C6 device block diagram . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Medium-density value line STM8L052C6 clock tree diagram . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3. STM8L052C6 48-pin LQFP48 package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 6. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 7. POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 8. Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 9. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 10. Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 11. Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 12. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 13. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 14. Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 15. Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 16. Typical VIL and VIH vs. VDD (high sink I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 17. Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 18. Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 19. Typical pull-up current Ipu vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 20. Typ. VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 21. Typ. VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 22. Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 23. Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 24. Typ. VDD - VOH @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 25. Typ. VDD - VOH @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 26. Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 27. Typical NRST pull-up current Ipu vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 28. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 29. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 30. SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 31. SPI1 timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 32. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 33. ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 34. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 35. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 94
Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 94
Figure 38. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 98
Figure 39. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 100
Figure 40. LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

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7
Introduction STM8L052C6

1 Introduction

This document describes the features, pinout, mechanical data and ordering information of
the medium-density value line STM8L052C6 microcontroller with 32-Kbyte Flash memory
density. For further details on the whole STMicroelectronics medium-density family please
refer to Section 2.2: Ultra-low-power continuum.
For detailed information on device operation and registers, refer to the reference manual
(RM0031).
For information on to the Flash program memory and data EEPROM, refer to the
programming manual (PM0054).
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).
Medium density value line devices provide the following benefits:
 Integrated system
– 32 Kbytes of medium-density embedded Flash program memory
– 256 bytes of data EEPROM
– 2 Kbytes of RAM
– Internal high-speed and low-power low-speed RC
– Embedded reset
 Ultra-low-power consumption
– 195 µA/MHZ + 440 µA (consumption)
– 0.9 µA with LSI in Active-halt mode
– Clock gated system and optimized power management
– Capability to execute from RAM for low-power wait mode and low-power-run
mode
 Advanced features
– Up to 16 MIPS at 16 MHz CPU clock frequency
– Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access
 Short development cycles
– Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals
– Wide choice of development tools
These features make the value line STM8L05xxx ultra-low-power microcontroller family
suitable for a wide range of consumer and mass market applications.
Refer to Table 1: Medium-density value line STM8L052C6 low-power device features and
peripheral counts and Section 3: Functional overview for an overview of the complete range
of peripherals proposed in this family.
Figure 1 shows the block diagram of the medium-density value line STM8L052C6 device.

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2 Description

The medium-density value line STM8L052C6 devices are members of the STM8L ultra-low-
power 8-bit family.
The value line STM8L05xxx ultra-low-power family features the enhanced STM8 CPU core
providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive In-application debugging and ultra-fast Flash programming.
Medium-density value line STM8L052C6 microcontrollers feature embedded data EEPROM
and low-power, low-voltage, single-supply program Flash memory.
All devices offer 12-bit ADC, real-time clock, 16-bit timers, one 8-bit timer as well as
standard communication interface such as SPI, I2C, USART and 4x28-segment LCD. The
4x 28-segment LCD is available on the medium-density value line STM8L052C6.
The STM8L052C6 operates from 1.8 V to 3.6 V and is available in the -40 to +85 °C
temperature range.
The modular design of the peripheral set allows the same peripherals to be found in
different ST microcontroller families including 32-bit families. This makes any transition to a
different family very easy, and simplified even more by the use of a common set of
development tools.
All value line STM8L ultra-low-power products are based on the same architecture with the
same memory mapping and a coherent pinout.

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Description STM8L052C6

2.1 Device overview

Table 1. Medium-density value line STM8L052C6 low-power device features and

peripheral counts
Features STM8L052C6

Flash (Kbytes) 32
Data EEPROM (bytes) 256
RAM (Kbytes) 2
LCD 4x28
1
Basic
(8-bit)
2
Timers General purpose
(16-bit)
1
Advanced control
(16-bit)
SPI 1
Communication
I2C 1
interfaces
USART 1
GPIOs 41(1)
12-bit synchronized ADC 1
(number of channels) (25)
RTC, window watchdog, independent watchdog,
Others 16-MHz and 38-kHz internal RC,
1- to 16-MHz and 32-kHz external oscillator
CPU frequency 16 MHz
Operating voltage 1.8 V to 3.6 V
Operating temperature -40 to +85 °C
Package LQFP48
1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the
NRST/PA1 pin as general purpose output only (PA1).

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2.2 Ultra-low-power continuum

The ultra-low-power value line STM8L05xxx and STM8L15xxx are fully pin-to-pin, software
and feature compatible. Besides the full compatibility within the STM8L family, the devices
are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes
STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of
performance, peripherals, system architecture, and features.
They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.
Note: 1 The STM8L05xxx is pin-to-pin compatible with STM8L101xx devices.
2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family.
Please refer to STM32L15x documentation for more information on these devices.

Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM® Cortex®-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.

Shared peripherals
STM8L05x, STM8L15x and STM32L15xx share identical peripherals which ensure a very
easy migration from one family to another:
 Analog peripheral: ADC1
 Digital peripherals: RTC and some communication interfaces

Common system strategy

To offer flexibility and optimize performance, the STM8L and STM32L devices use a
common architecture:
 Same power supply range from 1.8 to 3.6 V
 Architecture optimized to reach ultra-low consumption both in low power modes and
Run mode
 Fast startup strategy from low power modes
 Flexible system clock
 Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on
reset, power-down reset, brownout reset and programmable voltage detector

Features
ST ultra-low-power continuum also lies in feature compatibility:
 More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm
 Memory density ranging from 4 to 128 Kbytes

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Functional overview STM8L052C6

3 Functional overview

Figure 1. Medium-density value line STM8L052C6 device block diagram

OSC_IN, @VDD
OSC_OUT 1-16 MHz oscillator
VDD18 Power VDD1 =1.8 V
Clock to 3.6 V
16 MHz internal RC controller VSS1
OSC32_IN, VOLT. REG.
32 kHz oscillator and Clocks
OSC32_OUT
CSS to core and
38 kHz internal RC peripherals
RESET NRST
Interrupt controller
STM8 Core POR/PDR

Debug module BOR

SWIM
(SWIM)
PVD PVD_IN
2 channels 16-bit Timer 2
2 channels 16-bit Timer 3
32 Kbytes
3 channels 16-bit Timer 1 program memory
Address, control and data buses

8-bit Timer 4 256 bytes

data EEPROM
IR_TIM Infrared interface
2 Kbytes RAM

DMA1
(4 channels)
Port A PA[7:0]

SCL, SDA,
SMB I²C1 Port B PB[7:0]

MOSI, MISO,
SCK, NSS SPI1 Port C PC[7:0]

RX, TX, CK USART1 Port D PD[7:0]

VDDA PE[7:0]
VSSA @VDDA/VSSA Port E
ADC1_INx Port F PF0
VREF+ 12-bit ADC1
VREF-
Beeper BEEP

RTC ALARM, CALIB

VREFINT out
Internal reference
voltage IWDG
(38 kHz clock)

WWDG
VLCD = 2.5 V to
3.6 V LCD booster
LCD driver SEGx, COMx
4x28

1. Legend:
ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
I²C: Inter-integrated circuit multimaster interface
LCD: Liquid crystal display 
POR/PDR: Power on reset / power down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
IWDG: independent watchdog

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3.1 Low-power modes

The medium-density value line STM8L052C6 supports five low power modes to achieve the
best compromise between low power consumption, short startup time and available wakeup
sources:
 Wait mode: The CPU clock is stopped, but selected peripherals keep running. An
internal or external interrupt, event or a Reset can be used to exit the microcontroller
from Wait mode (WFE or WFI mode).
 Low power run mode: The CPU and the selected peripherals are running. Execution
is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode.
The microcontroller enters Low power run mode by software and can exit from this
mode by software or by a reset. 
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
 Low power wait mode: This mode is entered when executing a Wait for event in Low
power run mode. It is similar to Low power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the
system goes back to Low power run mode. 
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
 Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
can be triggered by RTC interrupts, external interrupts or reset.
 Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The RAM content is preserved. The wakeup is triggered by an external interrupt or
reset. A few peripherals have also a wakeup from Halt capability. Switching off the
internal reference voltage reduces power consumption. Through software configuration
it is also possible to wake up the device without waiting for the internal reference
voltage wakeup time to have a fast wakeup time of 5 µs.

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Functional overview STM8L052C6

3.2 Central processing unit STM8

3.2.1 Advanced STM8 core

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains six internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.

Architecture and registers

 Harvard architecture
 3-stage pipeline
 32-bit wide program memory bus - single cycle fetching most instructions
 X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
 8-bit accumulator
 24-bit program counter - 16-Mbyte linear memory space
 16-bit stack pointer - access to a 64-Kbyte level stack
 8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing
 20 addressing modes
 Indexed indirect addressing mode for lookup tables located anywhere in the address
space
 Stack pointer relative addressing mode for local variables and parameter passing

Instruction set
 80 instructions with 2-byte average instruction size
 Standard data movement and logic/arithmetic functions
 8-bit by 8-bit multiplication
 16-bit by 8-bit and 16-bit by 16-bit division
 Bit manipulation
 Data transfer between stack and accumulator (push/pop) with direct stack access
 Data transfer using the X and Y registers or direct memory-to-memory transfers

3.2.2 Interrupt controller

The medium-density value line STM8L052C6 features a nested vectored interrupt
controller:
 Nested interrupts with 3 software priority levels
 32 interrupt vectors with hardware priority
 Up to 40 external interrupt sources on 11 vectors
 Trap and reset interrupts

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3.3 Reset and supply management

3.3.1 Power supply scheme

The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power
supply pins must be connected as follows:
 VSS1 ; VDD1 = 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator.
Provided externally through VDD1 pins, the corresponding ground pin is VSS1.
 VSSA ; VDDA = 1.8 to 3.6 V: external power supplies for analog peripherals. VDDA and
VSSA must be connected to VDD1 and VSS1, respectively.
 VSS2 ; VDD2 = 1.8 to 3.6 V: external power supplies for I/Os. VDD2 and VSS2 must be
connected to VDD1 and VSS1, respectively.
 VREF+ ; VREF- (for ADC1): external reference voltage for ADC1. Must be provided
externally through VREF+ and VREF- pin.

3.3.2 Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active,
and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached,
the option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains
under reset when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need
for any external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3 Voltage regulator

The medium-density value line STM8L052C6 embeds an internal voltage regulator for
generating the 1.8 V power supply for the core and peripherals.
This regulator has two different modes:
 Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes
 Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and
Low power wait modes
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.

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48
Functional overview STM8L052C6

3.4 Clock management

The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.

Features
 Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
 Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register.
 Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
 System clock sources: 4 different clock sources can be used to drive the system
clock:
– 1-16 MHz High speed external crystal (HSE)
– 16 MHz High speed internal RC oscillator (HSI)
– 32.768 kHz Low speed external crystal (LSE)
– 38 kHz Low speed internal RC (LSI)
 RTC and LCD clock sources: The above four sources can be chosen to clock the
RTC and the LCD, whatever the system clock.
 Startup clock: After reset, the microcontroller restarts by default with an internal 
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
 Clock security system (CSS): This feature can be enabled by software. If a HSE
clock failure occurs, the system clock is automatically switched to HSI.
 Configurable main clock output (CCO): This outputs an external clock for use by the
application.

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Figure 2. Medium-density value line STM8L052C6 clock tree diagram

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DLK

1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE
bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031).
2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE
bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031).

3.5 Low-power real-time clock

The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.
Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,
year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31
day months are made automatically.It provides a programmable alarm and programmable
periodic interrupts with wakeup from Halt capability.
 Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is
from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach
36 hours.
 Periodic alarms based on the calendar can also be generated from every second to
every year.

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Functional overview STM8L052C6

3.6 LCD (Liquid crystal display)

The LCD is only available on STM8L052xx devices.
 The liquid crystal display drives up to 4 common terminals and up to 28 segment
terminals to drive up to 112 pixels. Internal step-up converter to guarantee contrast
control whatever VDD.
 Static 1/2, 1/3, 1/4 duty supported.
 Static 1/2, 1/3 bias supported.
 Phase inversion to reduce power consumption and EMI.
 Up to 4 pixels which can be programmed to blink.
 The LCD controller can operate in Halt mode.
Note: Unnecessary segments and common pins can be used as general I/O pins.

3.7 Memories
The medium-density value line STM8L052C6 has the following main features:
 2 Kbytes of RAM
 The non-volatile memory is divided into three arrays:
– 32 Kbytes of medium-density embedded Flash program memory
– 256 bytes of data EEPROM
– Option bytes
The EEPROM embeds the error correction code (ECC) feature. It supports the read-while-
write (RWW): it is possible to execute the code from the program matrix while
programming/erasing the data matrix.
The option byte protects part of the Flash program memory from write and readout piracy.

3.8 DMA
A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and
peripherals-from/to-memory transfer capability. The 4 channels are shared between the
following IPs with DMA capability: ADC1, I2C1, SPI1, USART1 and the four timers.

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3.9 Analog-to-digital converter

 12-bit analog-to-digital converter (ADC1) with 25 channels (including 1 fast channel)
and internal reference voltage
 Conversion time down to 1 µs with fSYSCLK= 16 MHz
 Programmable resolution
 Programmable sampling time
 Single and continuous mode of conversion
 Scan capability: automatic conversion performed on a selected group of analog inputs
 Analog watchdog
 Triggered by timer
Note: ADC1 can be served by DMA1.

3.10 System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate
functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.
The highly flexible routing interface allows application software to control the routing of
different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog
signals to ADC1 and the internal reference voltage VREFINT.

3.11 Timers
The medium-density value line STM8L052C6 contains one advanced control timer (TIM1),
two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4).
All the timers can be served by DMA1.
Table 2 compares the features of the advanced control, general-purpose and basic timers.

Table 2. Timer feature comparison

DMA1
Counter Counter Capture/compare Complementary
Timer Prescaler factor request
resolution type channels outputs
generation

Any integer
TIM1 3+1 3
from 1 to 65536
16-bit up/down
TIM2 Any power of 2
Yes 2
TIM3 from 1 to 128
None
Any power of 2
TIM4 8-bit up 0
from 1 to 32768

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48
Functional overview STM8L052C6

3.11.1 TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
 16-bit up, down and up/down autoreload counter with 16-bit prescaler
 3 independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse
mode output
 1 additional capture/compare channel which is not connected to an external I/O
 Synchronization module to control the timer with external signals
 Break input to force timer outputs into a defined state
 3 complementary outputs with adjustable dead time
 Encoder mode
 Interrupt capability on various events (capture, compare, overflow, break, trigger)

3.11.2 16-bit general purpose timers

 16-bit autoreload (AR) up/down-counter
 7-bit prescaler adjustable to fixed power of 2 ratios (1…128)
 2 individually configurable capture/compare channels
 PWM mode
 Interrupt capability on various events (capture, compare, overflow, break, trigger)
 Synchronization with other timers or external signals (external clock, reset, trigger and
enable)

3.11.3 8-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable
prescaler. It can be used for timebase generation with interrupt generation on timer
overflow.

3.12 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to
the applications.

3.12.1 Window watchdog timer

The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.

3.12.2 Independent watchdog timer

The independent watchdog peripheral (IWDG) can be used to resolve processor
malfunctions due to hardware or software failures.

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STM8L052C6 Functional overview

It is clocked by the internal LSI RC clock source, and thus stays active even in case of a
CPU clock failure.

3.13 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.

3.14 Communication interfaces

3.14.1 SPI
The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial
communication with external devices.
 Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave
 Full duplex synchronous transfers
 Simplex synchronous transfers on 2 lines with a possible bidirectional data line
 Master or slave operation - selectable by hardware or software
 Hardware CRC calculation
 Slave/master selection input pin
Note: SPI1 can be served by the DMA1 Controller.

3.14.2 I²C
The I2C bus interface (I2C1) provides multi-master capability, and controls all I²C bus-
specific sequencing, protocol, arbitration and timing.
 Master, slave and multi-master capability
 Standard mode up to 100 kHz and fast speed modes up to 400 kHz
 7-bit and 10-bit addressing modes
 SMBus 2.0 and PMBus support
 Hardware CRC calculation
Note: I2C1 can be served by the DMA1 Controller.

3.14.3 USART
The USART interface (USART1) allows full duplex, asynchronous communications with
external devices requiring an industry standard NRZ asynchronous serial data format. It
offers a very wide range of baud rates.
 1 Mbit/s full duplex SCI
 SPI1 emulation
 High precision baud rate generator
 SmartCard emulation
 IrDA SIR encoder decoder
 Single wire half duplex mode
Note: USART1 can be served by the DMA1 Controller.

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Functional overview STM8L052C6

3.15 Infrared (IR) interface

The medium-density value line STM8L052C6 contains an infrared interface which can be
used with an IR LED for remote control functions. Two timer output compare channels are
used to generate the infrared remote control signals.

3.16 Development support

Development tools
Development tools for the STM8 microcontrollers include:
 The STice emulation system offering tracing and code profiling
 The STVD high-level language debugger including C compiler, assembler and
integrated development environment
 The STVP Flash programming software
The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time
in-circuit debugging and fast memory programming.
The Single wire interface is used for direct access to the debugging module and memory
programming. The interface can be activated in all device operation modes.
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, CPU operation can also be monitored in real-
time by means of shadow registers.

Bootloader
A bootloader is available to reprogram the Flash memory using the USART1 interface. The
reference document for the bootloader is UM0560: STM8 bootloader user manual.
The bootloader is used to download application software into the device memories,
including RAM, program and data memory, using standard serial interfaces. It is a
complementary solution to programming via the SWIM debugging interface.

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STM8L052C6 Pin description

4 Pin description

Figure 3. STM8L052C6 48-pin LQFP48 package pinout (with LCD)

VDD2
VSS2
PE7
PE6
PC7
PC6
PC5
PC4
PC3
PC2

PC1
PC0
48 47 46 45 44 43 42 41 40 39 38 37
PA0 1 36 PD7
NRST/PA1 2 35 PD6
PA2 3 34 PD5
PA3 4 33 PD4
PA4 5 32 PF0
PA5 6 31 PB7
PA6 7 30 PB6
PA7 8 29 PB5
VSS1/VSSA/VREF- 9 28 PB4
VDD1 10 27 PB3
VDDA 11 26 PB2
VREF+ 12 25 PB1
13 14 15 16 17 18 19 20 21 22 23 24

VLCD
PE0
PE1
PE2
PE3
PE4
PE5
PD0
PD1
PD2
PD3
PB0
Table 3. Legend/abbreviation for Table 4
Type I= input, O = output, S = power supply
FT Five-volt tolerant
Level TT 3.6 V tolerant
Output HS = high sink/source (20 mA)

Port and control Input float = floating, wpu = weak pull-up

configuration Output T = true open drain, OD = open drain, PP = push pull
Bold X (pin state after reset release). 
Reset state Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).

Table 4. Medium-density value line STM8L052C6pin description

Pin # Input Output
Main function
High sink/source

(after reset)
Ext. interrupt
I/O level
Type
LQFP48

floating

Pin name Default alternate function

wpu

OD

PP

2 NRST/PA1(1) I/O X HS X Reset PA1

PA2/OSC_IN/ HSE oscillator input /
3 [USART1_TX](8)/ I/O X X X HS X X Port A2 [USART1 transmit] / [SPI1
[SPI1_MISO] (8) master in- slave out]
HSE oscillator output /
PA3/OSC_OUT/[USART1_
4 I/O X X X HS X X Port A3 [USART1 receive]/ [SPI1
RX](8)/[SPI1_MOSI](8)
master out/slave in]/

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Pin description STM8L052C6

Table 4. Medium-density value line STM8L052C6pin description (continued)

Pin # Input Output

Main function
High sink/source

(after reset)
Ext. interrupt
I/O level
Type
LQFP48

floating
Pin name Default alternate function

wpu

OD

PP
PA4/TIM2_BKIN/
Timer 2 - break input / 
5  I/O TT(2) X X X HS X X Port A4
LCD COM 0 / ADC1 input 2
LCD_COM0/ADC1_IN2
PA5/TIM3_BKIN/ Timer 3 - break input /
6 I/O TT(2) X X X HS X X Port A5
LCD_COM1/ADC1_IN1 LCD_COM 1 / ADC1 input 1
PA6/[ADC1_TRIG]/ [ADC1 - trigger] / LCD_COM2
7 I/O TT(2) X X X HS X X Port A6
LCD_COM2/ADC1_IN0 /ADC1 input 0
8 PA7/LCD_SEG0(3) I/O FT X X X HS X X Port A7 LCD segment 0
PB0(4)/TIM2_CH1/ Timer 2 - channel 1 / LCD
24 I/O TT(2) X(4) X(4) X HS X X Port B0
LCD_SEG10/ADC1_IN18 segment 10 / ADC1_IN18
PB1/TIM3_CH1/
Timer 3 - channel 1 / LCD
25 LCD_SEG11/ I/O TT(2) X X X HS X X Port B1
segment 11 / ADC1_IN17
ADC1_IN17
PB2/ TIM2_CH2/
Timer 2 - channel 2 / LCD
26 LCD_SEG12/ I/O TT(2) X X X HS X X Port B2
segment 12 / ADC1_IN16
ADC1_IN16
PB3/TIM2_ETR/
Timer 2 - external trigger /
27 LCD_SEG13/ I/O TT(2) X X X HS X X Port B3
LCD segment 13 /ADC1_IN15
ADC1_IN15
PB4(4)/[SPI1_NSS](8)/ [SPI1 master/slave select] /
28 LCD_SEG14/ I/O TT(2) X(4) X(4) X HS X X Port B4 LCD segment 14 /
ADC1_IN14 ADC1_IN14
PB5/[SPI1_SCK](8)/
[SPI1 clock] / LCD segment 15
29 LCD_SEG15/ I/O TT(2) X X X HS X X Port B5
/ ADC1_IN13
ADC1_IN13
PB6/[SPI1_MOSI](8)/ [SPI1 master out/slave in]/
30 LCD_SEG16/ I/O TT(2) X X X HS X X Port B6 LCD segment 16 /
ADC1_IN12 ADC1_IN12
PB7/[SPI1_MISO](8)/ [SPI1 master in- slave out]
31 LCD_SEG17/ I/O TT(2) X X X HS X X Port B7 /LCD segment 17 /
ADC1_IN11 ADC1_IN11
37 PC0(3)/I2C1_SDA I/O FT X X T(5) Port C0 I2C1 data
38 PC1(3)/I2C1_SCL I/O FT X X T(5) Port C1 I2C1 clock
USART1 receive / 
PC2/USART1_RX/
LCD segment 22 / ADC1_IN6
41 LCD_SEG22/ADC1_IN6/ I/O TT(2) X X X HS X X Port C2
/Internal voltage reference
VREFINT
output

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STM8L052C6 Pin description

Table 4. Medium-density value line STM8L052C6pin description (continued)

Pin # Input Output

Main function
High sink/source

(after reset)
Ext. interrupt
I/O level
Type
LQFP48

floating
Pin name Default alternate function

wpu

OD

PP
PC3/USART1_TX/
USART1 transmit / 
42 LCD_SEG23/ I/O TT(2) X X X HS X X Port C3
LCD segment 23 / ADC1_IN5
ADC1_IN5
USART1 synchronous clock /
PC4/USART1_CK/
I2C1_SMB / Configurable
I2C1_SMB/CCO/
43 I/O TT(2) X X X HS X X Port C4 clock output /
LCD_SEG24/
LCD segment 24/
ADC1_IN4
ADC1_IN4
PC5/OSC32_IN LSE oscillator input / [SPI1
44 /[SPI1_NSS](8)/ I/O X X X HS X X Port C5 master/slave select] /
[USART1_TX](8) [USART1 transmit]
PC6/OSC32_OUT/
LSE oscillator output / [SPI1
45 [SPI1_SCK](8)/ I/O X X X HS X X Port C6
clock] / [USART1 receive]
[USART1_RX](8)
PC7/LCD_SEG25/
46 I/O TT(2) X X X HS X X Port C7 LCD segment 25 /ADC1_IN3
ADC1_IN3
PD0/TIM3_CH2/ Timer 3 - channel 2 /
20 [ADC1_TRIG](8)/ I/O TT(2) X X X HS X X Port D0 [ADC1_Trigger] / LCD
LCD_SEG7/ADC1_IN22/ segment 7 / ADC1_IN22
PD1/TIM3_ETR/
Timer 3 - external trigger /
21 LCD_COM3/ I/O TT(2) X X X HS X X Port D1
LCD_COM3 / ADC1_IN21
ADC1_IN21
PD2/TIM1_CH1
Timer 1 - channel 1 / LCD
22 /LCD_SEG8/ I/O TT(2) X X X HS X X Port D2
segment 8 / ADC1_IN20
ADC1_IN20
PD3/ TIM1_ETR/ Timer 1 - external trigger /
23 I/O TT(2) X X X HS X X Port D3
LCD_SEG9/ADC1_IN19 LCD segment 9 / ADC1_IN19
PD4/TIM1_CH2
Timer 1 - channel 2 / LCD
33 /LCD_SEG18/ I/O TT(2) X X X HS X X Port D4
segment 18 / ADC1_IN10
ADC1_IN10
PD5/TIM1_CH3
Timer 1 - channel 3 / LCD
34 /LCD_SEG19/ I/O TT(2) X X X HS X X Port D5
segment 19 / ADC1_IN9
ADC1_IN9
PD6/TIM1_BKIN Timer 1 - break input / LCD
/LCD_SEG20/ (2) segment 20 / ADC1_IN8 /
35 I/O TT X X X HS X X Port D6
ADC1_IN8/RTC_CALIB/ RTC calibration / Internal
/VREFINT voltage reference output

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Pin description STM8L052C6

Table 4. Medium-density value line STM8L052C6pin description (continued)

Pin # Input Output

Main function
High sink/source

(after reset)
Ext. interrupt
I/O level
Type
LQFP48

floating
Pin name Default alternate function

wpu

OD

PP
PD7/TIM1_CH1N Timer 1 - inverted channel 1/
/LCD_SEG21/ LCD segment 21 / ADC1_IN7 /
36 I/O TT(2) X X X HS X X Port D7
ADC1_IN7/RTC_ALARM/V RTC alarm / Internal voltage
REFINT reference output
14 PE0(3)/LCD_SEG1 I/O FT X X X HS X X Port E0 LCD segment 1
PE1/TIM1_CH2N/ Timer 1 - inverted channel 2 /
15 I/O TT(2) X X X HS X X Port E1
LCD_SEG2 LCD segment 2
PE2/TIM1_CH3N/ Timer 1 - inverted channel 3 /
16 I/O TT(2) X X X HS X X Port E2
LCD_SEG3 LCD segment 3
17 PE3/LCD_SEG4 I/O TT(2) X X X HS X X Port E3 LCD segment 4
18 PE4/LCD_SEG5 I/O TT(2) X X X HS X X Port E4 LCD segment 5
PE5/LCD_SEG6/
19 I/O TT(2) X X X HS X X Port E5 LCD segment 6 / ADC1_IN23
ADC1_IN23
PE6/LCD_SEG26/
47 I/O TT(2) X X X HS X X Port E6 LCD segment 26/PVD_IN
PVD_IN
PE7/LCD_SEG27
48 I/O TT(2) X X X HS X X Port E7 LCD segment 27

ADC1_IN24
32 PF0/ADC1_IN24 I/O X X X HS X X Port F0

13 VLCD S LCD booster external capacitor

13 Reserved Reserved. Must be tied to VDD
10 VDD S Digital power supply
11 VDDA S Analog supply voltage
12 VREF+ S ADC1 positive voltage reference
I/O ground / Analog ground voltage / 
9 VSS1/VSSA/VREF- S
ADC1 negative voltage reference
39 VDD2 S IOs supply voltage
40 VSS2 S IOs ground voltage
[USART1 synchronous
PA0(6)/[USART1_CK](8)/ HS clock](8) / SWIM input and out-
1 I/O X X(6) X X X Port A0
SWIM/BEEP/IR_TIM (7) (7) put /Beep output 
/ Infrared Timer output
1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be
configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1
pin as general purpose output in the STM8L15x and STM8L16x reference manual (RM0031).
2. In the 3.6 V tolerant I/Os, protection diode to VDD is not implemented.

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STM8L052C6 Pin description

3. In the 5 V tolerant I/Os, protection diode to VDD is not implemented.

4. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.
5. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are
not implemented).
6. The PA0 pin is in input pull-up during the reset phase and after reset release.
7. High Sink LED driver capability available on PA0.
8. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).

Note: The slope control of all GPIO pins, except true open drain pins, can be programmed. By
default, the slope control is limited to 2 MHz.

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Pin description STM8L052C6

4.1 System configuration options

As shown in Table 4: Medium-density value line STM8L052C6pin description, some
alternate functions can be remapped on different I/O ports by programming one of the two
remapping registers described in the “Routing interface (RI) and system configuration
controller” section in the STM8L15x and STM8L16x reference manual (RM0031).

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STM8L052C6 Memory and register map

5 Memory and register map

5.1 Memory mapping

The memory map is shown in Figure 4.

Figure 4. Memory map

0x00 0000
RAM (2 Kbytes) (1)
including
0x00 07FF Stack (513 bytes) (1)
0x00 0800
Reserved
0x00 0FFF
0x00 1000
Data EEPROM
(256 bytes)
0x00 10FF
0x00 1100 0x00 5000
GPIO Ports
Reserved 0x00 5050
Flash
0x00 5070
0x00 47FF DMA1
0x00 4800 0x00 509E
SYSCFG
Option bytes 0x00 50A0
0x00 48FF ITC-EXTI
0x00 4900 0x00 50A6
WFE
0x00 50B0
RST
0x00 50B2
PWR
0x00 50C0
CLK
Reserved 0x00 50D3
WWDG
0x00 50E0
IWDG
0x00 50F3
BEEP
0x00 5140
RTC
0x00 4FFF 0x00 5200
SPI1
0x00 5000 0x00 5210
I2C1
GPIO and peripheral registers 0x00 5230
USART1
0x00 57FF 0x00 5250
0x00 5800 TIM2
0x00 5280
Reserved TIM3
0x00 5FFF 0x00 52B0
TIM1
0x00 6000 0x00 52E0
Boot ROM TIM4
0x00 52FF
(2 Kbytes) IRTIM
0x00 67FF 0x00 5340
ADC1
0x00 6800 0x00 5380
Reserved Reserved
0x00 5400
0x00 7EFF LCD
0x00 5430
0x00 7F00 RI
CPU/SWIM/Debug/ITC 0x00 5440
Reserved
Registers
0x00 7FFF
0x00 8000
Reset and interrupt vectors
0x00 807F
0x00 8080
Medium density
Flash program memory
(32 Kbytes)
0x00 FFFF

1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end
address.
2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware
registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.

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Memory and register map STM8L052C6

Table 5. Flash and RAM boundary addresses

Memory area Size Start address End address

RAM 2 Kbytes 0x00 0000 0x00 07FF

Flash program memory 32 Kbytes 0x00 8000 0x00 FFFF

5.2 Register map

Table 6. I/O port hardware register map
Reset
Address Block Register label Register name
status

0x00 5000 PA_ODR Port A data output latch register 0x00

0x00 5001 PA_IDR Port A input pin value register 0xXX
0x00 5002 Port A PA_DDR Port A data direction register 0x00
0x00 5003 PA_CR1 Port A control register 1 0x01
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005 PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR Port B input pin value register 0xXX
0x00 5007 Port B PB_DDR Port B data direction register 0x00
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A PC_ODR Port C data output latch register 0x00
0x00 500B PC_IDR Port C input pin value register 0xXX
0x00 500C Port C PC_DDR Port C data direction register 0x00
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
0x00 500F PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0xXX
0x00 5011 Port D PD_DDR Port D data direction register 0x00
0x00 5012 PD_CR1 Port D control register 1 0x00
0x00 5013 PD_CR2 Port D control register 2 0x00
0x00 5014 PE_ODR Port E data output latch register 0x00
0x00 5015 PE_IDR Port E input pin value register 0xXX
0x00 5016 Port E PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
0x00 5018 PE_CR2 Port E control register 2 0x00

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STM8L052C6 Memory and register map

Table 6. I/O port hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5019 PF_ODR Port F data output latch register 0x00

0x00 501A PF_IDR Port F input pin value register 0xXX
0x00 501B Port F PF_DDR Port F data direction register 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00

Table 7. General hardware register map

Reset
Address Block Register label Register name
status

0x00 501E to
Reserved area (44 bytes)
0x00 5049
0x00 5050 FLASH_CR1 Flash control register 1 0x00
0x00 5051 FLASH_CR2 Flash control register 2 0x00
Flash program memory unprotection key
0x00 5052 FLASH _PUKR 0x00
Flash register
0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00
Flash in-application programming status
0x00 5054 FLASH _IAPSR 0x00
register
0x00 5055 to
Reserved area (27 bytes)
0x00 506F

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Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

DMA1 global configuration & status

0x00 5070 DMA1_GCSR 0xFC
register
0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00
0x00 5072 to
Reserved area (3 bytes)
0x00 5074
0x00 5075 DMA1_C0CR DMA1 channel 0 configuration register 0x00
0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00
DMA1 number of data to transfer register
0x00 5077 DMA1_C0NDTR 0x00
(channel 0)
DMA1 peripheral address high register
0x00 5078 DMA1_C0PARH 0x52
(channel 0)
DMA1 peripheral address low register
0x00 5079 DMA1_C0PARL 0x00
(channel 0)
0x00 507A Reserved area (1 byte)
DMA1
DMA1 memory 0 address high register
0x00 507B DMA1_C0M0ARH 0x00
(channel 0)
DMA1 memory 0 address low register
0x00 507C DMA1_C0M0ARL 0x00
(channel 0)
0x00 507D
Reserved area (2 bytes)
0x00 507E
0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00
0x00 5080 DMA1_C1SPR DMA1 channel 1 status & priority register 0x00
DMA1 number of data to transfer register
0x00 5081 DMA1_C1NDTR 0x00
(channel 1)
DMA1 peripheral address high register
0x00 5082 DMA1_C1PARH 0x52
(channel 1)
DMA1 peripheral address low register
0x00 5083 DMA1_C1PARL 0x00
(channel 1)

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Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5084 Reserved area (1 byte)

DMA1 memory 0 address high register
0x00 5085 DMA1_C1M0ARH 0x00
(channel 1)
DMA1 memory 0 address low register
0x00 5086 DMA1_C1M0ARL 0x00
(channel 1)
0x00 5087
Reserved area (2 bytes)
0x00 5088
0x00 5089 DMA1_C2CR DMA1 channel 2 configuration register 0x00
0x00 508A DMA1_C2SPR DMA1 channel 2 status & priority register 0x00
DMA1 number of data to transfer register
0x00 508B DMA1_C2NDTR 0x00
(channel 2)
DMA1 peripheral address high register
0x00 508C DMA1_C2PARH 0x52
(channel 2)
DMA1 peripheral address low register
0x00 508D DMA1_C2PARL 0x00
(channel 2)
0x00 508E Reserved area (1 byte)
DMA1 memory 0 address high register
0x00 508F DMA1_C2M0ARH 0x00
(channel 2)
DMA1 DMA1 memory 0 address low register
0x00 5090 DMA1_C2M0ARL 0x00
(channel 2)
0x00 5091
Reserved area (2 bytes)
0x00 5092
0x00 5093 DMA1_C3CR DMA1 channel 3 configuration register 0x00
0x00 5094 DMA1_C3SPR DMA1 channel 3 status & priority register 0x00
DMA1 number of data to transfer register
0x00 5095 DMA1_C3NDTR 0x00
(channel 3)
DMA1_C3PARH_ DMA1 peripheral address high register
0x00 5096 0x40
C3M1ARH (channel 3)
DMA1_C3PARL_ DMA1 peripheral address low register
0x00 5097 0x00
C3M1ARL (channel 3)
0x00 5098 Reserved area (1 byte)
DMA1 memory 0 address high register
0x00 5099 DMA1_C3M0ARH 0x00
(channel 3)
DMA1 memory 0 address low register
0x00 509A DMA1_C3M0ARL 0x00
(channel 3)
0x00 509B to
Reserved area (3 bytes)
0x00 509D
0x00 509E SYSCFG_RMPCR1 Remapping register 1 0x00
0x00 509F SYSCFG_RMPCR2 Remapping register 2 0x00

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Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00

0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00
0x00 50A2 EXTI_CR3 External interrupt control register 3 0x00
ITC - EXTI
0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00
0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00
0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00
0x00 50A6 WFE_CR1 WFE control register 1 0x00
0x00 50A7 WFE_CR2 WFE control register 2 0x00
WFE
0x00 50A8 WFE_CR3 WFE control register 3 0x00
0x00 50AC to
Reserved area (4 bytes)
0x00 50AF
0x00 50B0 RST_CR Reset control register 0x00
RST
0x00 50B1 RST_SR Reset status register 0x01
0x00 50B2 PWR_CSR1 Power control and status register 1 0x00
PWR
0x00 50B3 PWR_CSR2 Power control and status register 2 0x00
0x00 50B4 to
Reserved area (12 bytes)
0x00 50BF
0x00 50C0 CLK_DIVR Clock master divider register 0x03
0x00 50C1 CLK_CRTCR Clock RTC register 0x00
0x00 50C2 CLK_ICKR Internal clock control register 0x11
0x00 50C3 CLK_PCKENR1 Peripheral clock gating register 1 0x00
0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x80
0x00 50C5 CLK_CCOR Configurable clock control register 0x00
0x00 50C6 CLK_ECKR External clock control register 0x00
0x00 50C7 CLK_SCSR System clock status register 0x01
0x00 50C8 CLK CLK_SWR System clock switch register 0x01
0x00 50C9 CLK_SWCR Clock switch control register 0bxxxx0000
0x00 50CA CLK_CSSR Clock security system register 0x00
0x00 50CB CLK_CBEEPR Clock BEEP register 0x00
0x00 50CC CLK_HSICALR HSI calibration register 0xxx
0x00 50CD CLK_HSITRIMR HSI clock calibration trimming register 0x00
0x00 50CE CLK_HSIUNLCKR HSI unlock register 0x00
0x00 50CF CLK_REGCSR Main regulator control status register 0bxx11100x
0x00 50D0 to
Reserved area (3 bytes)
0x00 50D2

34/103 DocID023331 Rev 2

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 50D3 WWDG_CR WWDG control register 0x7F

WWDG
0x00 50D4 WWDG_WR WWDR window register 0x7F
0x00 50D5 to
Reserved area (11 bytes)
00 50DF
0x00 50E0 IWDG_KR IWDG key register 0xXX
0x00 50E1 IWDG IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3 to
Reserved area (13 bytes)
0x00 50EF
0x00 50F0 BEEP_CSR1 BEEP control/status register 1 0x00
0x00 50F1
BEEP Reserved area (2 bytes)
0x00 50F2
0x00 50F3 BEEP_CSR2 BEEP control/status register 2 0x1F
0x00 50F4 to
Reserved area (76 bytes)
0x00 513F

DocID023331 Rev 2 35/103

48
Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5140 RTC_TR1 Time register 1 0x00

0x00 5141 RTC_TR2 Time register 2 0x00
0x00 5142 RTC_TR3 Time register 3 0x00
0x00 5143 Reserved area (1 byte)
0x00 5144 RTC_DR1 Date register 1 0x01
0x00 5145 RTC_DR2 Date register 2 0x21
0x00 5146 RTC_DR3 Date register 3 0x00
0x00 5147 Reserved area (1 byte)
0x00 5148 RTC_CR1 Control register 1 0x00
0x00 5149 RTC_CR2 Control register 2 0x00
0x00 514A RTC_CR3 Control register 3 0x00
0x00 514B Reserved area (1 byte)
0x00 514C RTC_ISR1 Initialization and status register 1 0x00
0x00 514D RTC_ISR2 Initialization and Status register 2 0x00
0x00 514E
Reserved area (2 bytes)
0x00 514F
0x00 5150 RTC_SPRERH(1) Synchronous prescaler register high 0x00(1)
0x00 5151 RTC RTC_SPRERL(1) Synchronous prescaler register low 0xFF(1)
0x00 5152 RTC_APRER(1) Asynchronous prescaler register 0x7F(1)
0x00 5153 Reserved area (1 byte)
0x00 5154 RTC_WUTRH(1) Wakeup timer register high 0xFF(1)
0x00 5155 RTC_WUTRL(1) Wakeup timer register low 0xFF(1)
0x00 5156 to
Reserved area (3 bytes)
0x00 5158
0x00 5159 RTC_WPR Write protection register 0x00
0x00 515A
Reserved area (2 bytes)
0x00 515B
0x00 515C RTC_ALRMAR1 Alarm A register 1 0x00
0x00 515D RTC_ALRMAR2 Alarm A register 2 0x00
0x00 515E RTC_ALRMAR3 Alarm A register 3 0x00
0x00 515F RTC_ALRMAR4 Alarm A register 4 0x00
0x00 5160 to
Reserved area (160 bytes)
0x00 51FF

36/103 DocID023331 Rev 2

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5200 SPI1_CR1 SPI1 control register 1 0x00

0x00 5201 SPI1_CR2 SPI1 control register 2 0x00
0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00
0x00 5203 SPI1_SR SPI1 status register 0x02
SPI1
0x00 5204 SPI1_DR SPI1 data register 0x00
0x00 5205 SPI1_CRCPR SPI1 CRC polynomial register 0x07
0x00 5206 SPI1_RXCRCR SPI1 Rx CRC register 0x00
0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00
0x00 5208 to
Reserved area (8 bytes)
0x00 520F
0x00 5210 I2C1_CR1 I2C1 control register 1 0x00
0x00 5211 I2C1_CR2 I2C1 control register 2 0x00
0x00 5212 I2C1_FREQR I2C1 frequency register 0x00
0x00 5213 I2C1_OARL I2C1 own address register low 0x00
0x00 5214 I2C1_OARH I2C1 own address register high 0x00
0x00 5215 Reserved (1 byte)
0x00 5216 I2C1_DR I2C1 data register 0x00
0x00 5217 I2C1_SR1 I2C1 status register 1 0x00
I2C1
0x00 5218 I2C1_SR2 I2C1 status register 2 0x00
0x00 5219 I2C1_SR3 I2C1 status register 3 0x0x
0x00 521A I2C1_ITR I2C1 interrupt control register 0x00
0x00 521B I2C1_CCRL I2C1 clock control register low 0x00
0x00 521C I2C1_CCRH I2C1 clock control register high 0x00
0x00 521D I2C1_TRISER I2C1 TRISE register 0x02
0x00 521E I2C1_PECR I2C1 packet error checking register 0x00
0x00 521F to
Reserved area (17 bytes)
0x00 522F

DocID023331 Rev 2 37/103

48
Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5230 USART1_SR USART1 status register 0xC0

0x00 5231 USART1_DR USART1 data register undefined
0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00
0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00
0x00 5234 USART1_CR1 USART1 control register 1 0x00
0x00 5235 USART1 USART1_CR2 USART1 control register 2 0x00
0x00 5236 USART1_CR3 USART1 control register 3 0x00
0x00 5237 USART1_CR4 USART1 control register 4 0x00
0x00 5238 USART1_CR5 USART1 control register 5 0x00
0x00 5239 USART1_GTR USART1 guard time register 0x00
0x00 523A USART1_PSCR USART1 prescaler register 0x00
0x00 523B to
Reserved area (21 bytes)
0x00 524F

38/103 DocID023331 Rev 2

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5250 TIM2_CR1 TIM2 control register 1 0x00

0x00 5251 TIM2_CR2 TIM2 control register 2 0x00
0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00
0x00 5253 TIM2_ETR TIM2 external trigger register 0x00
0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00
0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00
0x00 5256 TIM2_SR1 TIM2 status register 1 0x00
0x00 5257 TIM2_SR2 TIM2 status register 2 0x00
0x00 5258 TIM2_EGR TIM2 event generation register 0x00
0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00
0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00
0x00 525B TIM2 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00
0x00 525C TIM2_CNTRH TIM2 counter high 0x00
0x00 525D TIM2_CNTRL TIM2 counter low 0x00
0x00 525E TIM2_PSCR TIM2 prescaler register 0x00
0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF
0x00 5260 TIM2_ARRL TIM2 auto-reload register low 0xFF
0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00
0x00 5262 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00
0x00 5263 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00
0x00 5264 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00
0x00 5265 TIM2_BKR TIM2 break register 0x00
0x00 5266 TIM2_OISR TIM2 output idle state register 0x00
0x00 5267 to
Reserved area (25 bytes)
0x00 527F

DocID023331 Rev 2 39/103

48
Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5280 TIM3_CR1 TIM3 control register 1 0x00

0x00 5281 TIM3_CR2 TIM3 control register 2 0x00
0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00
0x00 5283 TIM3_ETR TIM3 external trigger register 0x00
0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00
0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00
0x00 5286 TIM3_SR1 TIM3 status register 1 0x00
0x00 5287 TIM3_SR2 TIM3 status register 2 0x00
0x00 5288 TIM3_EGR TIM3 event generation register 0x00
0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00
0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00
0x00 528B TIM3 TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00
0x00 528C TIM3_CNTRH TIM3 counter high 0x00
0x00 528D TIM3_CNTRL TIM3 counter low 0x00
0x00 528E TIM3_PSCR TIM3 prescaler register 0x00
0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF
0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF
0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00
0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00
0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00
0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00
0x00 5295 TIM3_BKR TIM3 break register 0x00
0x00 5296 TIM3_OISR TIM3 output idle state register 0x00
0x00 5297 to
Reserved area (25 bytes)
0x00 52AF

40/103 DocID023331 Rev 2

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 52B0 TIM1_CR1 TIM1 control register 1 0x00

0x00 52B1 TIM1_CR2 TIM1 control register 2 0x00
0x00 52B2 TIM1_SMCR TIM1 Slave mode control register 0x00
0x00 52B3 TIM1_ETR TIM1 external trigger register 0x00
0x00 52B4 TIM1_DER TIM1 DMA1 request enable register 0x00
0x00 52B5 TIM1_IER TIM1 Interrupt enable register 0x00
0x00 52B6 TIM1_SR1 TIM1 status register 1 0x00
0x00 52B7 TIM1_SR2 TIM1 status register 2 0x00
0x00 52B8 TIM1_EGR TIM1 event generation register 0x00
0x00 52B9 TIM1_CCMR1 TIM1 Capture/Compare mode register 1 0x00
0x00 52BA TIM1_CCMR2 TIM1 Capture/Compare mode register 2 0x00
0x00 52BB TIM1_CCMR3 TIM1 Capture/Compare mode register 3 0x00
0x00 52BC TIM1_CCMR4 TIM1 Capture/Compare mode register 4 0x00
0x00 52BD TIM1_CCER1 TIM1 Capture/Compare enable register 1 0x00
0x00 52BE TIM1_CCER2 TIM1 Capture/Compare enable register 2 0x00
0x00 52BF TIM1_CNTRH TIM1 counter high 0x00
0x00 52C0 TIM1_CNTRL TIM1 counter low 0x00
TIM1
0x00 52C1 TIM1_PSCRH TIM1 prescaler register high 0x00
0x00 52C2 TIM1_PSCRL TIM1 prescaler register low 0x00
0x00 52C3 TIM1_ARRH TIM1 Auto-reload register high 0xFF
0x00 52C4 TIM1_ARRL TIM1 Auto-reload register low 0xFF
0x00 52C5 TIM1_RCR TIM1 Repetition counter register 0x00
0x00 52C6 TIM1_CCR1H TIM1 Capture/Compare register 1 high 0x00
0x00 52C7 TIM1_CCR1L TIM1 Capture/Compare register 1 low 0x00
0x00 52C8 TIM1_CCR2H TIM1 Capture/Compare register 2 high 0x00
0x00 52C9 TIM1_CCR2L TIM1 Capture/Compare register 2 low 0x00
0x00 52CA TIM1_CCR3H TIM1 Capture/Compare register 3 high 0x00
0x00 52CB TIM1_CCR3L TIM1 Capture/Compare register 3 low 0x00
0x00 52CC TIM1_CCR4H TIM1 Capture/Compare register 4 high 0x00
0x00 52CD TIM1_CCR4L TIM1 Capture/Compare register 4 low 0x00
0x00 52CE TIM1_BKR TIM1 break register 0x00
0x00 52CF TIM1_DTR TIM1 dead-time register 0x00
0x00 52D0 TIM1_OISR TIM1 output idle state register 0x00
0x00 52D1 TIM1_DCR1 DMA1 control register 1 0x00

DocID023331 Rev 2 41/103

48
Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 52D2 TIM1_DCR2 TIM1 DMA1 control register 2 0x00

TIM1
0x00 52D3 TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00
0x00 52D4 to
Reserved area (12 bytes)
0x00 52DF
0x00 52E0 TIM4_CR1 TIM4 control register 1 0x00
0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00
0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00
0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00
0x00 52E4 TIM4_IER TIM4 Interrupt enable register 0x00
TIM4
0x00 52E5 TIM4_SR1 TIM4 status register 1 0x00
0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00
0x00 52E7 TIM4_CNTR TIM4 counter 0x00
0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00
0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00
0x00 52EA to
Reserved area (21 bytes)
0x00 52FE
0x00 52FF IRTIM IR_CR Infrared control register 0x00
0x00 5300 to
Reserved area (64 bytes)
0x00 533F

42/103 DocID023331 Rev 2

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5340 ADC1_CR1 ADC1 configuration register 1 0x00

0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00
0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F
0x00 5343 ADC1_SR ADC1 status register 0x00
0x00 5344 ADC1_DRH ADC1 data register high 0x00
0x00 5345 ADC1_DRL ADC1 data register low 0x00
0x00 5346 ADC1_HTRH ADC1 high threshold register high 0x0F
0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF
0x00 5348 ADC1_LTRH ADC1 low threshold register high 0x00
ADC1
0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00
0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00
0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00
0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00
0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00
0x00 534E ADC1_TRIGR1 ADC1 trigger disable 1 0x00
0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00
0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00
0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00
0x00 5352 to
Reserved area (174 bytes)
0x00 53FF
0x00 5400 LCD_CR1 LCD control register 1 0x00
0x00 5401 LCD_CR2 LCD control register 2 0x00
0x00 5402 LCD_CR3 LCD control register 3 0x00
0x00 5403 LCD_FRQ LCD frequency selection register 0x00
LCD
0x00 5404 LCD_PM0 LCD Port mask register 0 0x00
0x00 5405 LCD_PM1 LCD Port mask register 1 0x00
0x00 5406 LCD_PM2 LCD Port mask register 2 0x00
0x00 5407 Reserved area

DocID023331 Rev 2 43/103

48
Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5408 to
Reserved area (4 bytes)
0x00 540B
0x00 540C LCD_RAM0 LCD display memory 0 0x00
0x00 540D LCD_RAM1 LCD display memory 1 0x00
0x00 540E LCD_RAM2 LCD display memory 2 0x00
0x00 540F LCD_RAM3 LCD display memory 3 0x00
0x00 5410 LCD_RAM4 LCD display memory 4 0x00
0x00 5411 LCD_RAM5 LCD display memory 5 0x00
0x00 5412 LCD_RAM6 LCD display memory 6 0x00
0x00 5413 LCD_RAM7 LCD display memory 7 0x00
0x00 5414 LCD_RAM8 LCD display memory 8 0x00
0x00 5415 LCD_RAM9 LCD display memory 9 0x00
LCD
0x00 5416 LCD_RAM10 LCD display memory 10 0x00
0x00 5417 LCD_RAM11 LCD display memory 11 0x00
0x00 5418 LCD_RAM12 LCD display memory 12 0x00
0x00 5419 LCD_RAM13 LCD display memory 13 0x00
0x00 541A to
Reserved area (22 bytes)
0x00 542F

44/103 DocID023331 Rev 2

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5430 Reserved area (1 byte) 0x00

0x00 5431 RI_ICR1 Timer input capture routing register 1 0x00
0x00 5432 RI_ICR2 Timer input capture routing register 2 0x00
0x00 5433 RI_IOIR1 I/O input register 1 undefined
0x00 5434 RI_IOIR2 I/O input register 2 undefined
0x00 5435 RI_IOIR3 I/O input register 3 undefined
0x00 5436 RI_IOCMR1 I/O control mode register 1 0x00
0x00 5437 RI_IOCMR2 I/O control mode register 2 0x00
RI
0x00 5438 RI_IOCMR3 I/O control mode register 3 0x00
0x00 5439 RI_IOSR1 I/O switch register 1 0x00
0x00 543A RI_IOSR2 I/O switch register 2 0x00
0x00 543B RI_IOSR3 I/O switch register 3 0x00
0x00 543C RI_IOGCR I/O group control register 0x3F
0x00 543D RI_ASCR1 Analog switch register 1 0x00
0x00 543E RI_ASCR2 Analog switch register 2 0x00
0x00 543F RI_RCR Resistor control register 1 0x00
0x00 5440 to
Reserved area (5 bytes)
0x00 5444
1. These registers are not impacted by a system reset. They are reset at power-on.

Table 8. CPU/SWIM/debug module/interrupt controller registers

Reset
Address Block Register Label Register Name
Status

0x00 7F00 A Accumulator 0x00

0x00 7F01 PCE Program counter extended 0x00
0x00 7F02 PCH Program counter high 0x00
0x00 7F03 PCL Program counter low 0x00
0x00 7F04 XH X index register high 0x00
(1)
0x00 7F05 CPU XL X index register low 0x00
0x00 7F06 YH Y index register high 0x00
0x00 7F07 YL Y index register low 0x00
0x00 7F08 SPH Stack pointer high 0x03
0x00 7F09 SPL Stack pointer low 0xFF
0x00 7F0A CCR Condition code register 0x28

DocID023331 Rev 2 45/103

48
Memory and register map STM8L052C6

Table 8. CPU/SWIM/debug module/interrupt controller registers (continued)

Reset
Address Block Register Label Register Name
Status

0x00 7F0B to
Reserved area (85 bytes)
0x00 7F5F CPU
0x00 7F60 CFG_GCR Global configuration register 0x00
0x00 7F70 ITC_SPR1 Interrupt Software priority register 1 0xFF
0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF
0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF
0x00 7F73 ITC_SPR4 Interrupt Software priority register 4 0xFF
ITC-SPR
0x00 7F74 ITC_SPR5 Interrupt Software priority register 5 0xFF
0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF
0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF
0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF
0x00 7F78 to
Reserved area (2 bytes)
0x00 7F79
0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00
0x00 7F81 to
Reserved area (15 bytes)
0x00 7F8F
0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF
0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF
0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF
0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF
0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF
0x00 7F95 DM DM_BK2RL DM breakpoint 2 register low byte 0xFF
0x00 7F96 DM_CR1 DM Debug module control register 1 0x00
0x00 7F97 DM_CR2 DM Debug module control register 2 0x00
0x00 7F98 DM_CSR1 DM Debug module control/status register 1 0x10
0x00 7F99 DM_CSR2 DM Debug module control/status register 2 0x00
0x00 7F9A DM_ENFCTR DM enable function register 0xFF
0x00 7F9B to
Reserved area (5 bytes)
0x00 7F9F
1. Accessible by debug module only

46/103 DocID023331 Rev 2

STM8L052C6 Interrupt vector mapping

6 Interrupt vector mapping

Table 9. Interrupt mapping

Wakeup Wakeup Wakeup
Wakeup
IRQ Source from from Wait from Wait Vector
Description from Halt
No. block Active- (WFI (WFE address
mode
halt mode mode) mode)(1)

RESET Reset Yes Yes Yes Yes 0x00 8000

TRAP Software interrupt - - - - 0x00 8004
0 Reserved 0x00 8008
FLASH end of programing/
1 FLASH write attempted to - - Yes Yes 0x00 800C
protected page interrupt
DMA1 channels 0/1 half
2 DMA1 0/1 transaction/transaction - - Yes Yes 0x00 8010
complete interrupt
DMA1 channels 2/3 half
3 DMA1 2/3 transaction/transaction - - Yes Yes 0x00 8014
complete interrupt
RTC alarm A/
4 RTC Yes Yes Yes Yes 0x00 8018
wakeup
EXTI E/F/ External interrupt port E/F
5 Yes Yes Yes Yes 0x00 801C
PVD(2) PVD interrupt
6 EXTIB/G External interrupt port B/G Yes Yes Yes Yes 0x00 8020
7 EXTID/H External interrupt port D/H Yes Yes Yes Yes 0x00 8024
8 EXTI0 External interrupt 0 Yes Yes Yes Yes 0x00 8028
9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C
10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030
11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034
12 EXTI4 External interrupt 4 Yes Yes Yes Yes 0x00 8038
13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C
14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040
15 EXTI7 External interrupt 7 Yes Yes Yes Yes 0x00 8044
16 LCD LCD interrupt - - Yes Yes 0x00 8048
CLK system clock switch/
17 CLK/TIM1 CSS interrupt/ - - Yes Yes 0x00 804C
TIM 1 break
ACD1 end of conversion/
18 ADC1 analog watchdog/ Yes Yes Yes Yes 0x00 8050
overrun interrupt

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48
Interrupt vector mapping STM8L052C6

Table 9. Interrupt mapping (continued)

Wakeup Wakeup Wakeup
Wakeup
IRQ Source from from Wait from Wait Vector
Description from Halt
No. block Active- (WFI (WFE address
mode
halt mode mode) mode)(1)

TIM2 update/overflow/
19 TIM2 trigger/break - - Yes Yes 0x00 8054
interrupt
TIM2capture/
20 TIM2 - - Yes Yes 0x00 8058
compare interrupt
TIM3 update/overflow/
21 TIM3 - - Yes Yes 0x00 805C
trigger/break interrupt
TIM3 capture/compare
22 TIM3 - - Yes Yes 0x00 8060
interrupt
Update /overflow/trigger/
23 TIM1 - - - Yes 0x00 8064
COM
24 TIM1 Capture/compare - - - Yes 0x00 8068
TIM4 update/overflow/
25 TIM4 - - Yes Yes 0x00 806C
trigger interrupt
SPI1 TX buffer empty/
26 SPI1 RX buffer not empty/ Yes Yes Yes Yes 0x00 8070
error/wakeup interrupt
USART1transmit data
register empty/
27 USART1 - - Yes Yes 0x00 8074
transmission complete
interrupt
USART1 received data
ready/overrun error/
28 USART1 - - Yes Yes 0x00 8078
idle line detected/parity
error/global error interrupt
29 I2C1 I2C1 interrupt(3) Yes Yes Yes Yes 0x00 807C
1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. In WFE mode, the
interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode.
When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.
2. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port
E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).
3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

48/103 DocID023331 Rev 2

STM8L052C6 Option bytes

7 Option bytes

Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated memory block.
All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM
address. See Table 10 for details on option byte addresses.
The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for
the ROP and UBC values which can only be taken into account when they are modified in
ICP mode (with the SWIM).
Refer to the STM8L05x/15x Flash programming manual (PM0054) and STM8 SWIM and
Debug Manual (UM0470) for information on SWIM programming procedures.

Table 10. Option byte addresses

Option Option bits Factory
Address Option name byte default
No. 7 6 5 4 3 2 1 0 setting

Read-out
0x00 4800 protection OPT0 ROP[7:0] 0xAA
(ROP)
UBC (User
0x00 4802 OPT1 UBC[7:0] 0x00
Boot code size)
0x00 4807 Reserved 0x00
Independent
OPT3 WWDG WWDG IWDG IWDG
0x00 4808 watchdog Reserved 0x00
[3:0] _HALT _HW _HALT _HW
option
Number of
stabilization
0x00 4809 clock cycles for OPT4 Reserved LSECNT[1:0] HSECNT[1:0] 0x00
HSE and LSE
oscillators
Brownout reset OPT5 BOR_
0x00 480A Reserved BOR_TH 0x00
(BOR) [3:0] ON
0x00 480B Bootloader 0x00
OPTBL
option bytes OPTBL[15:0]
0x00 480C [15:0] 0x00
(OPTBL)

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Table 11. Option byte description

Option
byte Option description
No.

ROP[7:0] Memory readout protection (ROP)

0xAA: Disable readout protection (write access via SWIM protocol)
OPT0
Refer to Readout protection section in the STM8L05x/15x and STM8L16x reference manual
(RM0031).
UBC[7:0] Size of the user boot code area
0x00: UBC is not protected.
0x01: Page 0 is write protected.
0x02: Page 0 and 1 reserved for the UBC and write protected. It covers only the interrupt vectors.
OPT1
0x03: Page 0 to 2 reserved for UBC and write protected.
0x7F to 0xFF - All 128 pages reserved for UBC and write protected.
The protection of the memory area not protected by the UBC is enabled through the MASS keys.
Refer to User boot code section in the STM8L05x/15x and STM8L16x reference manual (RM0031).
OPT2 Reserved
IWDG_HW: Independent watchdog
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
IWDG_HALT: Independent window watchdog off on Halt/Active-halt
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
OPT3
WWDG_HW: Window watchdog
0: Window watchdog activated by software
1: Window watchdog activated by hardware
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
HSECNT: Number of HSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
OPT4 LSECNT: Number of LSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
Refer to Table 29: LSE oscillator characteristics on page 70.

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Table 11. Option byte description (continued)

Option
byte Option description
No.

BOR_ON:
0: Brownout reset off
OPT5 1: Brownout reset on
BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 20 for details on the thresholds according to
the value of BOR_TH bits.
OPTBL[15:0]:
This option is checked by the boot ROM code after reset. Depending on
OPTBL content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the
CPU jumps to the bootloader or to the reset vector.
Refer to the UM0560 bootloader user manual for more details.

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8 Electrical parameters

8.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

8.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
is indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3).

8.1.2 Typical values

Unless otherwise specified, typical data is based on TA = 25 °C, VDD = 3 V. It is given only as
design guidelines and is not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2).

8.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

8.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 5.

Figure 5. Pin loading conditions

STM8L PIN

50 pF

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8.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 6.

Figure 6. Pin input voltage

STM8L PIN

VIN

8.2 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 12. Voltage characteristics

Symbol Ratings Min Max Unit

External supply voltage (including VDDA

VDD- VSS - 0.3 4.0 V
and VDD2)(1)
Input voltage on true open-drain pins
VSS - 0.3 VDD + 4.0
(PC0 and PC1)
Input voltage on five-volt tolerant (FT)
VIN(2) VSS - 0.3 VDD + 4.0 V
pins (PA7 and PE0)
Input voltage on 3.6 V tolerant (TT) pins VSS - 0.3 4.0
Input voltage on any other pin VSS - 0.3 4.0
see Absolute maximum
VESD Electrostatic discharge voltage ratings (electrical sensitivity)
on page 96
1. All power (VDD1, VDD2, VDDA) and ground (VSS1, VSS2, VSSA) pins must always be connected to the
external power supply.
2. VIN maximum must always be respected. Refer to Table 13. for maximum allowed injected current values.

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Table 13. Current characteristics

Symbol Ratings Max. Unit

IVDD Total current into VDD power line (source) 80

IVSS Total current out of VSS ground line (sink) 80
Output current sunk by IR_TIM pin (with high sink LED driver
80
capability)
IIO
Output current sunk by any other I/O and control pin 25
Output current sourced by any I/Os and control pin - 25
mA
Injected current on true open-drain pins (PC0 and PC1)(1) - 5 / +0

Injected current on five-volt tolerant (FT) pins (PA7 and PE0) (1) - 5 / +0
IINJ(PIN)
Injected current on 3.6 V tolerant (TT) pins (1) - 5 / +0

Injected current on any other pin (2) - 5 / +5

IINJ(PIN) Total injected current (sum of all I/O and control pins) (3) ± 25
1. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 12. for maximum allowed input voltage values.
2. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 12. for maximum allowed input voltage values.
3. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).

Table 14. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150

°C
TJ Maximum junction temperature 150

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8.3 Operating conditions

Subject to general operating conditions for VDD and TA.

8.3.1 General operating conditions

Table 15. General operating conditions

Symbol Parameter Conditions Min. Max. Unit

System clock
fSYSCLK(1) 1.8 V VDD  3.6 V 0 16 MHz
frequency
Standard operating
VDD - 1.8 3.6 V
voltage
Analog operating Must be at the same
VDDA 1.8 3.6 V
voltage potential as VDD
Power dissipation at
PD(2) LQFP48 - 288 mW
TA= 85 °C
Power dissipation at
PD(3) TSSOP20 - 181 mW
TA= 85 °C
TA Temperature range 1.8 V VDD 3.6 V -40 85 °C
Junction temperature
TJ -40 °C TA 85 °C -40 105(4) °C
range
1. fSYSCLK = fCPU
2. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/JA with TJmax in this table and JA in “Thermal
characteristics” table.
3. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/JA with TJmax in this table and JA in “Thermal
characteristics” table.
4. TJmax is given by the test limit. Above this value, the product behavior is not guaranteed.

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8.3.2 Embedded reset and power control block characteristics

Table 16. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

BOR detector
VDD rise time rate
enabled 0(1) - (1)
tVDD µs/V
BOR detector
VDD fall time rate
enabled 20 (1) - (1)

tTEMP Reset release delay VDD rising - 3 - ms

VPDR (2)
Power-down reset threshold Falling edge 1.30 1.50 1.65 V

Brown-out reset threshold 0 Falling edge 1.67 1.70 1.74

VBOR0
(BOR_TH[2:0]=000) Rising edge 1.69 1.75 1.80

Brown-out reset threshold 1 Falling edge 1.87 1.93 1.97

VBOR1
(BOR_TH[2:0]=001) Rising edge 1.96 2.04 2.07

Brown-out reset threshold 2 Falling edge 2.22 2.3 2.35

VBOR2 V
(BOR_TH[2:0]=010) Rising edge 2.31 2.41 2.44

Brown-out reset threshold 3 Falling edge 2.45 2.55 2.60

VBOR3
(BOR_TH[2:0]=011) Rising edge 2.54 2.66 2.7

Brown-out reset threshold 4 Falling edge 2.68 2.80 2.85

VBOR4
(BOR_TH[2:0]=100) Rising edge 2.78 2.90 2.95
Falling edge 1.80 1.84 1.88
VPVD0 PVD threshold 0
Rising edge 1.88 1.94 1.99
Falling edge 1.98 2.04 2.09
VPVD1 PVD threshold 1
Rising edge 2.08 2.14 2.18
Falling edge 2.2 2.24 2.28
VPVD2 PVD threshold 2
Rising edge 2.28 2.34 2.38
Falling edge 2.39 2.44 2.48
VPVD3 PVD threshold 3 V
Rising edge 2.47 2.54 2.58
Falling edge 2.57 2.64 2.69
VPVD4 PVD threshold 4
Rising edge 2.68 2.74 2.79
Falling edge 2.77 2.83 2.88
VPVD5 PVD threshold 5
Rising edge 2.87 2.94 2.99
Falling edge 2.97 3.05 3.09
VPVD6 PVD threshold 6
Rising edge 3.08 3.15 3.20
1. Data guaranteed by design, not tested in production.
2. Data based on characterization results, not tested in production.

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Figure 7. POR/BOR thresholds

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8.3.3 Supply current characteristics

Total current consumption
The MCU is placed under the following conditions:
l All I/O pins in input mode with a static value at VDD or VSS (no load)
l All peripherals are disabled except if explicitly mentioned.
In the following table, data is based on characterization results, unless otherwise specified.
Subject to general operating conditions for VDD and TA.

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Table 17. Total current consumption in Run mode

Max
Para
Symbol
meter Conditions(1) Typ Unit
55 °C 85 °C

fCPU = 125 kHz 0.39 0.47 0.49

fCPU = 1 MHz 0.48 0.56 0.58
HSI RC osc.
fCPU = 4 MHz 0.75 0.84 0.86
(16 MHz)(3)
fCPU = 8 MHz 1.10 1.20 1.25

All fCPU = 16 MHz 1.85 1.93 2.12(5)

peripherals  fCPU = 125 kHz 0.05 0.06 0.09
Supply OFF,
current code fCPU = 1 MHz 0.18 0.19 0.20
IDD(RUN) HSE external mA
in run executed
(2) clock fCPU = 4 MHz 0.55 0.62 0.64
mode from RAM,
VDD from (fCPU=fHSE)(4)
fCPU = 8 MHz 0.99 1.20 1.21
1.8 V to 3.6 V
fCPU = 16 MHz 1.90 2.22 2.23(5)
LSI RC osc.
fCPU = fLSI 0.040 0.045 0.046
(typ. 38 kHz)
LSE external
clock fCPU = fLSE 0.035 0.040 0.048(5)
(32.768 kHz)
fCPU = 125 kHz 0.43 0.55 0.56
fCPU = 1 MHz 0.60 0.77 0.80
HSI RC
fCPU = 4 MHz 1.11 1.34 1.37
oscillator.(6)
fCPU = 8 MHz 1.90 2.20 2.23
fCPU = 16 MHz 3.8 4.60 4.75
All
peripherals fCPU = 125 kHz 0.30 0.36 0.39
Supply 
OFF, code
current fCPU = 1 MHz 0.40 0.50 0.52
IDD(RUN) executed mA
in Run  HSE external
from Flash, clock
mode fCPU = 4 MHz 1.15 1.31 1.40
VDD from
(f =f ) (4)
1.8 V to 3.6 V CPU HSE fCPU = 8 MHz 2.17 2.33 2.44
fCPU = 16 MHz 4.0 4.46 4.52

LSI RC osc. fCPU = fLSI 0.110 0.123 0.130

LSE ext. clock
(32.768 fCPU = fLSE 0.100 0.101 0.104
kHz)(7)
1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC oscillator, fCPU=fSYSCLK
2. CPU executing typical data processing
3. The run from RAM consumption can be approximated with the linear formula: 
IDD(run_from_RAM) = Freq * 90 µA/MHz + 380 µA

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4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE
consumption 
(IDD HSE) must be added. Refer to Table 28.
5. Tested in production.
6. The run from Flash consumption can be approximated with the linear formula: 
IDD(run_from_Flash) = Freq * 195 µA/MHz + 440 µA
7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE
consumption 
(IDD LSE) must be added. Refer to Table 29.

Figure 8. Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz


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In the following table, data is based on characterization results, unless otherwise specified.

Table 18. Total current consumption in Wait mode

Max
Symbol Parameter Conditions(1) Typ Unit
85°C
55°C
(2)

fCPU = 125 kHz 0.33 0.39 0.41

fCPU = 1 MHz 0.35 0.41 0.44

HSI fCPU = 4 MHz 0.42 0.51 0.52

fCPU = 8 MHz 0.52 0.57 0.58
CPU not 
clocked,  fCPU = 16 MHz 0.68 0.76 0.79
all peripherals
OFF,  fCPU = 125 kHz 0.032 0.056 0.068
Supply  code executed
IDD(Wait) current in  from RAM  f = 1 MHz 0.078 0.121 0.144 mA
HSE external CPU
Wait mode with Flash in clock fCPU = 4 MHz 0.218 0.26 0.30
IDDQ mode(3), (fCPU=fHSE)(4)
fCPU = 8 MHz 0.40 0.52 0.57
VDD from
1.8 V to 3.6 V fCPU = 16 MHz 0.760 1.01 1.05

LSI fCPU = fLSI 0.035 0.044 0.046

LSE(5)
external clock fCPU = fLSE 0.032 0.036 0.038
(32.768 kHz)
fCPU = 125 kHz 0.38 0.48 0.49
fCPU = 1 MHz 0.41 0.49 0.51

HSI fCPU = 4 MHz 0.50 0.57 0.58

fCPU = 8 MHz 0.60 0.66 0.68

CPU not fCPU = 16 MHz 0.79 0.84 0.86

clocked, 
Supply  all peripherals fCPU = 125 kHz 0.06 0.08 0.09
current in  OFF, 
IDD(Wait) Wait HSE(4) fCPU = 1 MHz 0.10 0.17 0.18 mA
code executed
external clock
mode from Flash, fCPU = 4 MHz 0.24 0.36 0.39
(fCPU=HSE)
VDD from 
fCPU = 8 MHz 0.50 0.58 0.61
1.8 V to 3.6 V
fCPU = 16 MHz 1.00 1.08 1.14

LSI fCPU = fLSI 0.055 0.058 0.065

LSE(5)
external clock fCPU = fLSE 0.051 0.056 0.060
(32.768 kHz)
1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC oscillator, fCPU = fSYSCLK
2. For temperature range 6.
3. Flash is configured in IDDQ mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.

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4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE
consumption 
(IDD HSE) must be added. Refer to Table 28.
5. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE
consumption 
(IDD HSE) must be added. Refer to Table 29.

Figure 9. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1)




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In the following table, data is based on characterization results, unless otherwise specified.

Table 19. Total current consumption and timing in Low power run mode at VDD = 1.8 V
to 3.6 V
Symbol Parameter Conditions(1) Typ Max Unit

TA = -40 °C to 25 °C 5.1 5.4

all peripherals OFF TA = 55 °C 5.7 6

LSI RC osc. TA = 85 °C 6.8 7.5

(at 38 kHz) TA = -40 °C to 25 °C 5.4 5.7

with TIM2 active(2) TA = 55 °C 6.0 6.3

Supply current in TA = 85 °C 7.2 7.8

IDD(LPR) A
Low power run mode TA = -40 °C to 25 °C 5.25 5.6
all peripherals OFF TA = 55 °C 5.67 6.1
(3)
LSE external TA = 85 °C 5.85 6.3
clock
(32.768 kHz) TA = -40 °C to 25 °C 5.59 6
(2) TA = 55 °C 6.10 6.4
with TIM2 active
TA = 85 °C 6.30 7
1. No floating I/Os
2. Timer 2 clock enabled and counter running
3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption 
(IDD LSE) must be added. Refer to Table 29

Figure 10. Typ. IDD(LPR) vs. VDD (LSI clock source)





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In the following table, data is based on characterization results, unless otherwise specified.

Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V
Symbol Parameter Conditions(1) Typ Max Unit

TA = -40 °C to 25 °C 3 3.3
all peripherals OFF TA = 55 °C 3.3 3.6
LSI RC osc. TA = 85 °C 4.4 5
(at 38 kHz) TA = -40 °C to 25 °C 3.4 3.7
with TIM2 active(2) TA = 55 °C 3.7 4
Supply current in TA = 85 °C 4.8 5.4
IDD(LPW) Low power wait A
mode TA = -40 °C to 25 °C 2.35 2.7
all peripherals OFF TA = 55 °C 2.42 2.82
LSE external
TA = 85 °C 3.10 3.71
clock(3)
TA = -40 °C to 25 °C 2.46 2.75
(32.768 kHz)
with TIM2 active (2) TA = 55 °C 2.50 2.81
TA = 85 °C 3.16 3.82
1. No floating I/Os.
2. Timer 2 clock enabled and counter is running.
3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption 
(IDD LSE) must be added. Refer to Table 29.

Figure 11. Typ. IDD(LPW) vs. VDD (LSI clock source)




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In the following table, data is based on characterization results, unless otherwise specified.

Table 21. Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V
Symbol Parameter Conditions (1) Typ Max Unit

TA = -40 °C to 25 °C 0.9 2.1

(2) TA = 55 °C 1.2 3
LCD OFF
TA = 85 °C 1.5 3.4
LCD ON  TA = -40 °C to 25 °C 1.4 3.1
(static duty/
TA = 55 °C 1.5 3.3
external
LSI RC VLCD) (3) TA = 85 °C 1.9 4.3
Supply current in
IDD(AH) A
Active-halt mode (at 38 kHz) LCD ON TA = -40 °C to 25 °C 1.9 4.3
(1/4 duty/
TA = 55 °C 1.95 4.4
external
VLCD) (4) TA = 85 °C 2.4 5.4
LCD ON TA = -40 °C to 25 °C 3.9 8.75
(1/4 duty/
TA = 55 °C 4.15 9.3
internal
VLCD) (5) TA = 85 °C 4.5 10.2
TA = -40 °C to 25 °C 0.5 1.2
LCD OFF(7) TA = 55 °C 0.62 1.4
TA = 85 °C 0.88 2.1
LCD ON  TA = -40 °C to 25 °C 0.85 1.9
(static duty/
TA = 55 °C 0.95 2.2
external
LSE external
clock  VLCD) (3) TA = 85 °C 1.3 3.2
Supply current in
IDD(AH) A
Active-halt mode (32.768 kHz) LCD ON  TA = -40 °C to 25 °C 1.5 2.5
(6) (1/4 duty/
TA = 55 °C 1.6 3.8
external
VLCD) (4) TA = 85 °C 1.8 4.2
LCD ON TA = -40 °C to 25 °C 3.4 7.6
(1/4 duty/
TA = 55 °C 3.7 8.3
internal
VLCD) (5) TA = 85 °C 3.9 9.2
TA = -40 °C to 25 °C 0.9 2.1
LSI RC (at 38 kHz) TA = 55 °C 1.2 3
Supply current in TA = 85 °C 1.5 3.4
IDD(AH) A
Active-halt mode TA = -40 °C to 25 °C 0.5 1.2
LSE external clock (32.768
TA = 55 °C 0.62 1.4
kHz)(8)
TA = 85 °C 0.88 2.1
Supply current during
wakeup time from
IDD(WUFAH) - 2.4 - mA
Active-halt mode
(using HSI)

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Table 21. Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V
Symbol Parameter Conditions (1) Typ Max Unit

tWU_HSI(AH)(9) Wakeup time from

(10)
Active-halt mode to - 4.7 7 s
Run mode (using HSI)
Wakeup time from
tWU_LSI(AH)(9)
Active-halt mode to - 150 - s
(10)
Run mode (using LSI)
1. No floating I/O, unless otherwise specified.
2. RTC enabled. Clock source = LSI
3. RTC enabled, LCD enabled with external VLCD = 3 V, static duty, division ratio = 256, all pixels active, no LCD connected.
4. RTC enabled, LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
5. LCD enabled with internal LCD booster VLCD = 3 V, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD
connected.
6. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption 
(IDD LSE) must be added. Refer to Table 29.
7. RTC enabled. Clock source = LSE.
8. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption 
(IDD LSE) must be added. Refer to Table 29.
9. Wakeup time until start of interrupt vector fetch. 
The first word of interrupt routine is fetched 4 CPU cycles after tWU.
10. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.

Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE
external crystal
Symbol Parameter Condition(1) Typ Unit

LSE 1.15
VDD = 1.8 V
(3)
LSE/32 1.05

Supply current in Active-halt LSE 1.30

IDD(AH) (2) VDD = 3 V µA
mode LSE/32(3) 1.20
LSE 1.45
VDD = 3.6 V
(3)
LSE/32 1.35
1. No floating I/O, unless otherwise specified.
2. Based on measurements on bench with 32.768 kHz external crystal oscillator.
3. RTC clock is LSE divided by 32.

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In the following table, data is based on characterization results, unless otherwise specified.

Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V
Symbol Parameter Condition(1) Typ Max Unit

TA = -40 °C to 25 °C 350 1400(2)

Supply current in Halt mode
IDD(Halt) (Ultra-low-power ULP bit =1 in TA = 55 °C 580 2000 nA
the PWR_CSR2 register)
TA = 85 °C 1160 2800(2)
Supply current during wakeup
IDD(WUHalt) time from Halt mode (using - 2.4 - mA
HSI)
Wakeup time from Halt to Run
tWU_HSI(Halt)(3)(4) - 4.7 7 µs
mode (using HSI)
Wakeup time from Halt mode
tWU_LSI(Halt) (3)(4) - 150 - µs
to Run mode (using LSI)
1. TA = -40 to 85 °C, no floating I/O, unless otherwise specified.
2. Tested in production.
3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
4. Wakeup time until start of interrupt vector fetch. 
The first word of interrupt routine is fetched 4 CPU cycles after tWU.

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Current consumption of on-chip peripherals

Table 24. Peripheral current consumption

Typ.
Symbol Parameter Unit
VDD = 3.0 V

IDD(TIM1) TIM1 supply current(1) 13

IDD(TIM2) TIM2 supply current (1) 8
IDD(TIM3) TIM3 supply current (1) 8
IDD(TIM4) TIM4 timer supply current (1) 3
IDD(USART1) USART1 supply current (2) 6
µA/MHz
IDD(SPI1) SPI1 supply current (2) 3
IDD(I2C1) I2C1 supply current (2) 5
IDD(DMA1) DMA1 supply current(2) 3
IDD(WWDG) WWDG supply current(2) 2
IDD(ALL) Peripherals ON(3) 44 µA/MHz
IDD(ADC1) ADC1 supply current(4) 1500
Power voltage detector and brownout Reset unit supply
IDD(PVD/BOR) 2.6
current (5)
IDD(BOR) Brownout Reset unit supply current (5) 2.4 µA
including LSI supply
0.45
current
IDD(IDWDG) Independent watchdog supply current
excluding LSI
0.05
supply current
1. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The
CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.
Not tested in production.
3. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion.
5. Including supply current of internal reference voltage.

Table 25. Current consumption under external reset

Symbol Parameter Conditions Typ Unit

VDD = 1.8 V 48
Supply current under All pins are externally
IDD(RST) VDD = 3 V 76 µA
external reset (1) tied to VDD
VDD = 3.6 V 91
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.

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8.3.4 Clock and timing characteristics

HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for VDD and TA.

Table 26. HSE external clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

External clock source

fHSE_ext 1 - 16 MHz
frequency(1)
OSC_IN input pin high level -
VHSEH 0.7 x VDD - VDD
voltage
V
OSC_IN input pin low level
VHSEL VSS - 0.3 x VDD
voltage
OSC_IN input
Cin(HSE) - - 2.6 - pF
capacitance(1)
OSC_IN input leakage
ILEAK_HSE VSS < VIN < VDD - - ±1 µA
current
1. Data guaranteed by Design, not tested in production.

LSE external clock (LSEBYP=1 in CLK_ECKCR)

Subject to general operating conditions for VDD and TA.

Table 27. LSE external clock characteristics

Symbol Parameter Min Typ Max Unit

fLSE_ext External clock source frequency(1) - 32.768 - kHz

VLSEH(2) OSC32_IN input pin high level voltage 0.7 x VDD - VDD
V
VLSEL(2) OSC32_IN input pin low level voltage VSS - 0.3 x VDD

Cin(LSE) OSC32_IN input capacitance(1) - 0.6 - pF

ILEAK_LSE OSC32_IN input leakage current - - ±1 µA

1. Data guaranteed by Design, not tested in production.
2. Data based on characterization results, not tested in production.

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HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

Table 28. HSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

High speed external oscillator

fHSE - 1 - 16 MHz
frequency
RF Feedback resistor - - 200 - k

C(1) Recommended load capacitance (2) - - 20 - pF

C = 20 pF, 2.5 (startup)

- -
fOSC = 16 MHz 0.7 (stabilized)(3)
IDD(HSE) HSE oscillator power consumption mA
C = 10 pF, 2.5 (startup)
- -
fOSC =16 MHz 0.46 (stabilized)(3)
gm Oscillator transconductance - 3.5(3) - - mA/V
tSU(HSE)(4) Startup time VDD is stabilized 1 - ms
1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Data guaranteed by Design. Not tested in production.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This
value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 12. HSE oscillator circuit diagram

fHSE to core
Rm

CO RF
Lm
CL1
Cm OSC_IN
gm
Resonator
Consumption
control
Resonator

STM8
OSC_OUT
CL2

HSE oscillator critical gm formula

2
g mcrit =  2    f HSE  2  R m  2Co + C 
Rm: Motional resistance (see crystal specification), Lm: Motional inductance (see crystal specification),
Cm: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),
CL1=CL2=C: Grounded external capacitance
gm >> gmcrit

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LSE crystal/ceramic resonator oscillator

The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

Table 29. LSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

Low speed external oscillator

fLSE - - 32.768 - kHz
frequency
RF Feedback resistor V = 200 mV - 1.2 - M

C(1) Recommended load capacitance (2) - - 8 - pF

- - - 1.4(3) µA
VDD = 1.8 V - 450 -
IDD(LSE) LSE oscillator power consumption
VDD = 3 V - 600 - nA
VDD = 3.6 V - 750 -
gm Oscillator transconductance - 3(3) - µA/V
tSU(LSE)(4) Startup time VDD is stabilized - 1 - s
1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value.
Refer to crystal manufacturer for more details.
3. Data guaranteed by Design. Not tested in production.
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.
This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 13. LSE oscillator circuit diagram

fLSE
Rm

CO RF
Lm
CL1
Cm OSC_IN
gm
Resonator
Consumption
control
Resonator

STM8
OSC_OUT
CL2

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Internal clock sources

Subject to general operating conditions for VDD, and TA.
High speed internal RC oscillator (HSI)
In the following table, data is based on characterization results, not tested in production,
unless otherwise specified.

Table 30. HSI oscillator characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit

fHSI Frequency VDD = 3.0 V - 16 MHz

(2) (2)
Accuracy of HSI VDD = 3.0 V, TA = 25 °C -1 - 1 %
ACCHSI oscillator (factory 1.8 V  VDD  3.6 V,
-5 - 5 %
calibrated) -40 °C TA  85 °C
HSI user trimming Trimming code multiple of 16 - 0.4 0.7 %
TRIM
step(3) Trimming code = multiple of 16 - ± 1.5 %
HSI oscillator setup
tsu(HSI) - - 3.7 6(4) µs
time (wakeup time)
HSI oscillator power
IDD(HSI) - - 100 140(4) µA
consumption
1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.
2. Tested in production.
3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16
(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for
more details.
4. Guaranteed by design, not tested in production.

Figure 14. Typical HSI frequency vs. VDD






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Low speed internal RC oscillator (LSI)

In the following table, data is based on characterization results, not tested in production.

Table 31. LSI oscillator characteristics

Symbol Parameter (1) Conditions(1) Min Typ Max Unit

fLSI Frequency - 26 38 56 kHz

tsu(LSI) (2)
LSI oscillator wakeup time - - - 200 µs
LSI oscillator frequency
IDD(LSI) 0 °C TA  85 °C -12 - 11 %
drift(3)
1. VDD = 1.8 V to 3.6 V, TA = -40 to 85 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. This is a deviation for an individual part, once the initial frequency has been measured.

Figure 15. Typical LSI frequency vs. VDD





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8.3.5 Memory characteristics

TA = -40 to 85 °C unless otherwise specified.

Table 32. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

VRM Data retention mode (1) Halt mode (or Reset) 1.8 - - V
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization, not tested in production.

Flash memory

Table 33. Flash program and data EEPROM memory

Max
Symbol Parameter Conditions Min Typ (1) Unit

Operating voltage 
VDD fSYSCLK = 16 MHz 1.8 3.6 V
(all modes, read/write/erase)
Programming time for 1 or 64 bytes (block)
- - 6 - ms
erase/write cycles (on programmed byte)
tprog
Programming time for 1 to 64 bytes (block)
- - 3 - ms
write cycles (on erased byte)
TA+25 °C, VDD = 3.0 V - -
Iprog Programming/ erasing consumption 0.7 mA
TA+25 °C, VDD = 1.8 V - -
Data retention (program memory) after 100
TRET+85 °C 30(1) - -
erase/write cycles at TA–40 to +85 °C
tRET(2) years
Data retention (data memory) after 100000
TRET +85 °C 30(1) - -
erase/write cycles at TA= –40 to +85 °C
Erase/write cycles (program memory) 100(1) - - cycles
NRW (3) TA –40 to +85 °C 100(1)
Erase/write cycles (data memory) (4) - - kcycles

1. Data based on characterization results, not tested in production.

2. Conforming to JEDEC JESD22a117
3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation
addresses a single byte.
4. Data based on characterization performed on the whole data memory.

8.3.6 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

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Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in the following table.

Table 34. I/O current injection susceptibility

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on true open-drain pins (PC0 and

-5 +0
PC1)

IINJ Injected current on all five-volt tolerant (FT) pins -5 +0 mA

Injected current on all 3.6 V tolerant (TT) pins -5 +0
Injected current on any other pin -5 +5

8.3.7 I/O port pin characteristics

General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.

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Table 35. I/O static characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit

Input voltage on true open-drain

VSS-0.3 - 0.3 x VDD
pins (PC0 and PC1)
Input voltage on five-volt
tolerant (FT) pins (PA7 and VSS-0.3 - 0.3 x VDD
VIL Input low level voltage(2) PE0) V

Input voltage on 3.6 V tolerant

VSS-0.3 - 0.3 x VDD
(TT) pins
Input voltage on any other pin VSS-0.3 - 0.3 x VDD

Input voltage on true open-drain

pins (PC0 and PC1)  - 5.2
with VDD < 2 V
0.70 x VDD
Input voltage on true open-drain
pins (PC0 and PC1)  - 5.5
with VDD 2 V

Input voltage on five-volt

VIH (2) tolerant (FT) pins (PA7 and - 5.2 V
Input high level voltage
PE0) with VDD < 2 V

Input voltage on five-volt

0.70 x VDD
tolerant (FT) pins (PA7 and - 5.5
PE0) with VDD  2 V

Input voltage on 3.6 V tolerant

- 3.6
(TT) pins
Input voltage on any other pin 0.70 x VDD - VDD+0.3

Schmitt trigger voltage I/Os - 200 -

Vhys mV
hysteresis (3) True open drain I/Os - 200 -
VSSVIN VDD
- - 50 (5)
High sink I/Os
VSSVIN VDD
- - 200(5)
Ilkg Input leakage current (4) True open drain I/Os nA
VSSVIN VDD
PA0 with high sink LED driver - - 200(5)
capability
Weak pull-up equivalent
RPU VINVSS 30 45 60 k
resistor(2)(6)
CIO I/O pin capacitance - - 5 - pF
1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Not tested in production.
6. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in
Figure 19).

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Figure 16. Typical VIL and VIH vs. VDD (high sink I/Os)


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Figure 17. Typical VIL and VIH vs. VDD (true open drain I/Os)


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Figure 18. Typical pull-up resistance RPU vs. VDD with VIN=VSS


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Figure 19. Typical pull-up current Ipu vs. VDD with VIN=VSS


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Electrical parameters STM8L052C6

Output driving current

Subject to general operating conditions for VDD and TA unless otherwise specified.

Table 36. Output driving current (high sink ports)

I/O
Symbol Parameter Conditions Min Max Unit
Type

IIO = +2 mA,
- 0.45 V
VDD = 3.0 V

IIO = +2 mA,
VOL (1) Output low level voltage for an I/O pin - 0.45 V
VDD = 1.8 V

IIO = +10 mA,

- 0.7 V
High sink

VDD = 3.0 V

IIO = -2 mA,
VDD-0.45 - V
VDD = 3.0 V

IIO = -1 mA,
VOH (2) Output high level voltage for an I/O pin VDD-0.45 - V
VDD = 1.8 V

IIO = -10 mA,

VDD-0.7 - V
VDD = 3.0 V

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 13 and the
sum of IIO (I/O ports and control pins) must not exceed IVDD.

Table 37. Output driving current (true open drain ports)

I/O
Symbol Parameter Conditions Min Max Unit
Type

IIO = +3 mA,
Open drain

- 0.45
VDD = 3.0 V
VOL (1) Output low level voltage for an I/O pin V
IIO = +1 mA,
- 0.45
VDD = 1.8 V

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.

Table 38. Output driving current (PA0 with high sink LED driver capability)
I/O
Symbol Parameter Conditions Min Max Unit
Type

IIO = +20 mA,

VOL (1)
IR

Output low level voltage for an I/O pin - 0.45 V

VDD = 2.0 V

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.

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Figure 20. Typ. VOL @ VDD = 3.0 V (high sink Figure 21. Typ. VOL @ VDD = 1.8 V (high sink
ports) ports)
 


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Figure 22. Typ. VOL @ VDD = 3.0 V (true open Figure 23. Typ. VOL @ VDD = 1.8 V (true open
drain ports) drain ports)
 

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Figure 24. Typ. VDD - VOH @ VDD = 3.0 V (high Figure 25. Typ. VDD - VOH @ VDD = 1.8 V (high
sink ports) sink ports)
 
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Electrical parameters STM8L052C6

NRST pin
Subject to general operating conditions for VDD and TA unless otherwise specified.

Table 39. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) NRST input low level voltage (1) - VSS - 0.8

VIH(NRST) NRST input high level voltage (1) - 1.4 - VDD

IOL = 2 mA
for 2.7 V  VDD  3.6 - - V

VOL(NRST) NRST output low level voltage (1) V 0.4

IOL = 1.5 mA
- -
for VDD < 2.7 V

10%VDD
VHYST NRST input hysteresis(3) - (2) - - mV

RPU(NRST) NRST pull-up equivalent resistor

- 30 45 60 k
(1)

VF(NRST) NRST input filtered pulse (3) - - - 50

ns
VNF(NRST) NRST input not filtered pulse (3) - 300 - -

1. Data based on characterization results, not tested in production.

2. 200 mV min.
3. Data guaranteed by design, not tested in production.

Figure 26. Typical NRST pull-up resistance RPU vs. VDD



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Figure 27. Typical NRST pull-up current Ipu vs. VDD


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The reset network shown in Figure 28 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL(NRST) max. level specified
in Table 39. Otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If the NRST signal is used to reset the
external circuitry, attention must be paid to the charge/discharge time of the external
capacitor to fulfill the external devices reset timing conditions. The minimum recommended
capacity is 10 nF.

Figure 28. Recommended NRST pin configuration

VDD

RPU
EXTERNAL NRST INTERNAL RESET
RESET Filter
CIRCUIT
0.1 µF STM8
(Optional)

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8.3.8 Communication interfaces

SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under ambient temperature, fSYSCLK frequency and VDD supply voltage
conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 40. SPI1 characteristics

Symbol Parameter Conditions(1) Min Max Unit

fSCK Master mode 0 8

SPI1 clock frequency MHz
1/tc(SCK) Slave mode 0 8
tr(SCK) SPI1 clock rise and fall
Capacitive load: C = 30 pF - 30
tf(SCK) time
tsu(NSS)(2) NSS setup time Slave mode 4 x 1/fSYSCLK -
th(NSS)(2) NSS hold time Slave mode 80 -
tw(SCKH) (2)
Master mode, 
SCK high and low time 105 145
tw(SCKL)(2) fMASTER = 8 MHz, fSCK= 4 MHz

tsu(MI) (2) Master mode 30 -

Data input setup time
tsu(SI)(2) Slave mode 3 -

th(MI) (2) Master mode 15 -

Data input hold time ns
th(SI)(2) Slave mode 0 -
ta(SO)(2)(3) Data output access time Slave mode - 3x 1/fSYSCLK
tdis(SO)(2)(4) Data output disable time Slave mode 30 -
tv(SO) (2) Data output valid time Slave mode (after enable edge) - 60
Master mode (after enable
tv(MO)(2) Data output valid time - 20
edge)
th(SO)(2) Slave mode (after enable edge) 15 -
Data output hold time Master mode (after enable
th(MO)(2) 1 -
edge)
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.

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STM8L052C6 Electrical parameters

Figure 29. SPI1 timing diagram - slave mode and CPHA=0

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Figure 30. SPI1 timing diagram - slave mode and CPHA=1(1)

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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

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Electrical parameters STM8L052C6

Figure 31. SPI1 timing diagram - master mode

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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

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STM8L052C6 Electrical parameters

I2C - Inter IC control interface

Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified.
The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication
protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).

Table 41. I2C characteristics

Standard mode
Fast mode I2C(1)
I2C
Symbol Parameter Unit

Min(2) Max (2) Min (2) Max (2)

tw(SCLL) SCL clock low time 4.7 - 1.3 -

s
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
th(SDA) SDA data hold time 0 - 0 900
tr(SDA) ns
SDA and SCL rise time - 1000 - 300
tr(SCL)

tf(SDA)
SDA and SCL fall time - 300 - 300
tf(SCL)

th(STA) START condition hold time 4.0 - 0.6 -

Repeated START condition setup s
tsu(STA) 4.7 - 0.6 -
time
tsu(STO) STOP condition setup time 4.0 - 0.6 - s
STOP to START condition time (bus
tw(STO:STA) 4.7 - 1.3 - s
free)
Cb Capacitive load for each bus line - 400 - 400 pF
1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).
2. Data based on standard I2C protocol requirement, not tested in production.

Note: For speeds around 200 kHz, the achieved speed can have a 5% tolerance
For other speed ranges, the achieved speed can have a  2% tolerance
The above variations depend on the accuracy of the external components used.

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Electrical parameters STM8L052C6

Figure 32. Typical application with I2C bus and timing diagram 1)
VDD VDD

4.7k 4.7k 100 SDA

I2C BUS 100 SCL

STM8L
REPEATED START
START
tsu(STA) tw(STO:STA)
START
SDA

tf(SDA) tr(SDA) tsu(SDA) th(SDA) STOP

SCL

th(STA) tw(SCLH) tw(SCLL) tr(SCL) tf(SCL) tsu(STO)

1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD

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8.3.9 LCD controller

In the following table, data is guaranteed by design. Not tested in production.

Table 42. LCD characteristics

Symbol Parameter Min Typ Max. Unit

VLCD LCD external voltage - - 3.6 V

VLCD0 LCD internal reference voltage 0 - 2.6 - V
VLCD1 LCD internal reference voltage 1 - 2.7 - V
VLCD2 LCD internal reference voltage 2 - 2.8 - V
VLCD3 LCD internal reference voltage 3 - 2.9 - V
VLCD4 LCD internal reference voltage 4 - 3.0 - V
VLCD5 LCD internal reference voltage 5 - 3.1 - V
VLCD6 LCD internal reference voltage 6 - 3.2 - V
VLCD7 LCD internal reference voltage 7 - 3.3 - V
CEXT VLCD external capacitance 0.1 - 2 µF
Supply current(1) at VDD = 1.8 V - 3 - µA
IDD
(1)
Supply current at VDD = 3 V - 3 - µA
RHN (2) High value resistive network (low drive) - 6.6 - M
(3)
RLN Low value resistive network (high drive) - 360 - k
V33 Segment/Common higher level voltage - - VLCDx V
V23 Segment/Common 2/3 level voltage - 2/3VLCDx - V
V12 Segment/Common 1/2 level voltage - 1/2VLCDx - V
V13 Segment/Common 1/3 level voltage - 1/3VLCDx - V
V0 Segment/Common lowest level voltage 0 - - V
1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels
active, no LCD connected.
2. RHN is the total high value resistive network.
3. RLN is the total low value resistive network.

VLCD external capacitor

The application can achieve a stabilized LCD reference voltage by connecting an external
capacitor CEXT to the VLCD pin. CEXT is specified in Table 42.

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8.3.10 Embedded reference voltage

In the following table, data is based on characterization results, not tested in production,
unless otherwise specified.

Table 43. Reference voltage characteristics

Symbol Parameter Conditions Min Typ Max. Unit

Internal reference voltage

IREFINT - - 1.4 - µA
consumption
ADC sampling time when
TS_VREFINT(1)(2) reading the internal reference - - 5 10 µs
voltage
Internal reference voltage buffer
IBUF(2) - - 13.5 25 µA
consumption (used for ADC)
VREFINT out Reference voltage output - 1.202(3) 1.224 1.242(3) V
Internal reference voltage low
ILPBUF(2) - - 730 1200 nA
power buffer consumption
IREFOUT(2) Buffer output current(4) - - - 1 µA
CREFOUT Reference voltage output load - - - 50 pF
Internal reference voltage
tVREFINT - - 2 3 ms
startup time
Internal reference voltage buffer
tBUFEN(2) - - 10 µs
startup time once enabled (1)
Accuracy of VREFINT stored in
ACCVREFINT the VREFINT_Factory_CONV - - ±5 mV
byte(5)
Stability of VREFINT over
-40 °C TA  85 °C - 20 50 ppm/°C
temperature
STABVREFINT
Stability of VREFINT over
0 °C TA  50 °C - - 20 ppm/°C
temperature
Stability of VREFINT after 1000
STABVREFINT - - - TBD ppm
hours
1. Defined when ADC output reaches its final value ±1/2LSB
2. Data guaranteed by Design. Not tested in production.
3. Tested in production at VDD = 3 V ±10 mV.
4. To guaranty less than 1% VREFOUT deviation.
5. Measured at VDD = 3 V ±10 mV. This value takes into account VDD accuracy and ADC conversion accuracy.

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8.3.11 12-bit ADC1 characteristics

In the following table, data is guaranteed by design, not tested in production.

Table 44. ADC1 characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.8 3.6 V

2.4 V VDDA3.6 V 2.4 VDDA V
Reference supply
VREF+
voltage 1.8 V VDDA 2.4 V VDDA V
VREF- Lower reference voltage - VSSA V
Current on the VDDA
IVDDA - - 1000 1450 µA
input pin
700
- - µA
Current on the VREF+ (peak)(1)
IVREF+ 400
input pin 450
- - µA
(average)(1)
Conversion voltage
VAIN
range
- 0(2) - VREF+

TA Temperature range - -40 - 85 °C

External resistance on on PF0 fast channel - -

RAIN 50(3) k
VAIN on all other channels - -

Internal sample and hold on PF0 fast channel - -

CADC 16 pF
capacitor on all other channels - -
2.4 VVDDA3.6 V
0.320 - 16 MHz
ADC sampling clock without zooming
fADC
frequency 1.8 VVDDA2.4 V
0.320 - 8 MHz
with zooming
VAIN on PF0 fast
channel
- - 1(4)(5) MHz
fCONV 12-bit conversion rate
VAIN on all other
channels
- - 760(4)(5) kHz

External trigger
fTRIG - - - tconv 1/fADC
frequency
tLAT External trigger latency - - - 3.5 1/fSYSCLK

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Table 44. ADC1 characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

VAIN on PF0 fast

channel 0.43(4)(5) - - µs
VDDA < 2.4 V
VAIN on PF0 fast
channel 0.22(4)(5) - - µs
tS Sampling time 2.4 V VDDA3.6 V
VAIN on slow channels
0.86(4)(5) - - µs
VDDA < 2.4 V
VAIN on slow channels
0.41(4)(5) - - µs
2.4 V VDDA3.6 V
- 12 + tS 1/fADC
tconv 12-bit conversion time
16 MHz 1(4) µs
Wakeup time from OFF
tWKUP - - - 3 µs
state

Time before a new TA +25 °C - - 1(7) s

tIDLE(6)
conversion TA +70 °C - - 20(7) ms
Internal reference refer to
tVREFINT - - - ms
voltage startup time Table 43
1. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
2. VREF- or VDDA must be tied to ground.
3. Guaranteed by design, not tested in production.
4. Minimum sampling and conversion time is reached for maximum Rext = 0.5 k.
5. Value obtained for continuous conversion on fast channel.
6. The time between 2 conversions, or between ADC ON and the first conversion must be lower than tIDLE.
7. The tIDLE maximum value is  on the “Z” revision code of the device.

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STM8L052C6 Electrical parameters

In the following three tables, data is guaranteed by characterization result, not tested in
production.

Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V

Symbol Parameter Conditions Typ Max Unit

fADC = 16 MHz 1 1.6

DNL Differential non linearity fADC = 8 MHz 1 1.6
fADC = 4 MHz 1 1.5
fADC = 16 MHz 1.2 2
INL Integral non linearity fADC = 8 MHz 1.2 1.8 LSB
fADC = 4 MHz 1.2 1.7
fADC = 16 MHz 2.2 3.0
TUE Total unadjusted error fADC = 8 MHz 1.8 2.5
fADC = 4 MHz 1.8 2.3
fADC = 16 MHz 1.5 2
Offset Offset error fADC = 8 MHz 1 1.5
fADC = 4 MHz 0.7 1.2
LSB
fADC = 16 MHz
Gain Gain error fADC = 8 MHz 1 1.5
fADC = 4 MHz

Table 46. ADC1 accuracy with VDDA = 2.4 V to 3.6 V

Symbol Parameter Typ Max Unit

DNL Differential non linearity 1 2 LSB

INL Integral non linearity 1.7 3 LSB

TUE Total unadjusted error 2 4 LSB

Offset Offset error 1 2 LSB
Gain Gain error 1.5 3 LSB

Table 47. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V

Symbol Parameter Typ Max Unit

DNL Differential non linearity 1 2 LSB

INL Integral non linearity 2 3 LSB

TUE Total unadjusted error 3 5 LSB

Offset Offset error 2 3 LSB
Gain Gain error 2 3 LSB

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Electrical parameters STM8L052C6

Figure 33. ADC1 accuracy characteristics

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1. Refer to Table 44 for the values of RAIN and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.

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STM8L052C6 Electrical parameters

Figure 35. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion

Sampling (n cycles) Conversion (12 cycles)

ADC clock

Iref+

700µA

300µA

Table 48. RAIN max for fADC = 16 MHz(1)

RAIN max (kohm)
Ts Ts
Slow channels Fast channels
(cycles) (µs)
2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V

4 0.25 Not allowed Not allowed 0.7 Not allowed

9 0.5625 0.8 Not allowed 2.0 1.0
16 1 2.0 0.8 4.0 3.0
24 1.5 3.0 1.8 6.0 4.5
48 3 6.8 4.0 15.0 10.0
96 6 15.0 10.0 30.0 20.0
192 12 32.0 25.0 50.0 40.0
384 24 50.0 50.0 50.0 50.0
1. Guaranteed by design, not tested in production.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 36 or Figure 37,
depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF
capacitors should be used. They should be placed as close as possible to the chip.

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Electrical parameters STM8L052C6

Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA)

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Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA)

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STM8L052C6 Electrical parameters

8.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
 ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000 standard.
 FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Table 49. EMS data

Level/
Symbol Parameter Conditions
Class

Voltage limits to be applied on VDD 3.3 V, TA +25 °C, 

VFESD any I/O pin to induce a functional fCPU16 MHz, 3B
disturbance conforms to IEC 61000
Fast transient voltage burst limits 
VDD 3.3 V, TA +25 °C,  4A
to be applied through 100 pF on Using HSI
VEFTB fCPU 16 MHz,
VDD and VSS pins to induce a
conforms to IEC 61000 Using HSE 2B
functional disturbance

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Electrical parameters STM8L052C6

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC61967-2 which specifies the board and the loading of each pin.

Table 50. EMI data(1)

Max vs.
Monitored
Symbol Parameter Conditions Unit
frequency band
16 MHz

VDD 3.6 V, 0.1 MHz to 30 MHz -3

TA +25 °C, 30 MHz to 130 MHz 9 dBV
SEMI Peak level LQFP32
conforming to 130 MHz to 1 GHz 4
IEC61967-2 SAE EMI Level 2 -
1. Not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: human body model and charge device model. This test conforms to the
JESD22-A114A/A115A standard.

Table 51. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Unit
value (1)

Electrostatic discharge voltage

VESD(HBM) 2000
(human body model)
TA +25 °C V
Electrostatic discharge voltage
VESD(CDM) 500
(charge device model)
1. Data based on characterization results, not tested in production.

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STM8L052C6 Electrical parameters

Static latch-up
 LU: 3 complementary static tests are required on 6 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.

Table 52. Electrical sensitivities

Symbol Parameter Class

LU Static latch-up class II

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Package information STM8L052C6

9 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

9.1 LQFP48 package information

Figure 38. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

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1. Drawing is not to scale.

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STM8L052C6 Package information

Table 53. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package information STM8L052C6

Figure 39. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint





 
 



 



 
 







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1. Dimensions are expressed in millimeters.

Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.

Figure 40. LQFP48 marking example (package top view)

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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.

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STM8L052C6 Part numbering

10 Part numbering

For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.

Table 54. Ordering information scheme

Example: STM8 L 052 C 6 T 6 x

Device family
STM8 microcontroller

Product type
L = Low-power

Sub-family
052 = STM8L052xx, ultra-low power with LCD

Pin count
C = 48 pins

Code size
6 = 32 Kbytes

Package
T = LQFP

Temperature range
6 = –40 to 85 °C

Options
xxx = programmed parts
TR = tape and reel

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Revision history STM8L052C6

11 Revision history

Table 55. Document revision history

Date Revision Changes

15-Jun-2012 1 Initial release.

Updated:
– the factory default setting for OPT5[3:0] in Table 10:
Option byte addresses
09-Mar-2015 2 – Section 10: Part numbering,
– the disclaimer.
Added:
– Figure 40: LQFP48 marking example (package top view).

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STM8L052C6

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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2015 STMicroelectronics – All rights reserved

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