Name: Huỳnh Ngọc Khánh

ID: 19119062

Expiriment no: 2

1.1 AIM:
o Draw and investigate I-V characteristic, then determine threshold Voltage of A nMOS.
o Create some typical logic gates using CMOS, such as the NOR, NAND, and INVERTER.
1.2 LEARNING OBJECTIVE:
o To establish the nMOS threshold voltage.
o Detect the cutoff, linear, and saturation zones of the nMOS to observe the change in Ids
output status when Vgs input changes.
o Should be aware of how to build a few basic CMOS logic gates.
1.3 TOOLS: PC, CADENCE TOOLS.
1.4 PROCEDURE:
 DETERMINE THRESHOLD VOLTAGE:

To retrieve elements from the Add Instance box, press I. Choose the necessary parts, such as:
gnd, vdc, and vpwl in the analogLib library; and nmos1v in the gpdk090 library. I then create the
diagram you see below:
Then, go to Setup -> Model Libraries to select the library of 90nmtechnologyfor nMOS.
Go to Analysis -> Choosing Analysis to choose a simulation method.

Select tran mode, set Stop Time to 10us to execute simulation in 10us

Next, select the values to investigate.

Go to Outputs -> To be Plotted -> Select On Schematic, select the input signal at pin D, and current Ids
After select, the final Analog Design environment window will appear and I click the run button

Finally, the result:

Conclude:

As we know, Ion/Ioff is used about 3000 times when forming a conducting channel. Therefore, the
Ion/Ioff channeling start timing is set to 1000 times. From the simulation results, Vg = 503.119 mV at this
point, which is also the desired threshold voltage.

 NMOS V-I CHARACTERISTIC:

Press I to get components from the Add Instance window.

● Select the necessary components including:

● nmos1v in the gpdk090 library.

● gnd, vdc in analogLib library.

● Then, I build a schematic as shown below:

Now, open Variables -> edit to open the table that I show below:
Now, I add two variables a and b with the same value 0.

Go to Analysis -> Choosing Analysis to choose a simulation method.

Select dc mode, set Variable Name: Vds, Start: 0, and Stop: 1 to executesimulation according to the
change of variable Vds from 0V to 1V
Finally, I perform simulations with different Vgs variables by going to Tool ->Parametric Analysis. Then
update the values to be simulated as shown.

We obtain waveforms representing different cases of Vgs values.

The graph correctly represents the characteristics of nMOS, the operating modes

are divided into 3 regions:

Cutoff region: when Vgs < Vt, current Ids = 0.

Linear region: when Vds < Vdsat (Vdsat = Vgs – Vt), current Ids will increaselinearly.
Saturation region: when Vds > Vdsat, current Ids is kept in saturation.

As you can see, the red line represents the case where vgs is only 0.4V, lower than the 0.5V threshold
voltage found in the previous post, so there is no apparent change between states.

 INVERTER GATE:

Press I to get components from the Add Instance window.

● Select the necessary components including:

● INV in the 19119062_Khanh library.

● gnd, vdc, vpulse in analogLib library.

● Then, I build a schema tic as shown bel ow:

The results are completely consistent with the logic state from true table.

 NAND GATE:

Pin VDD is connected to a Vdc 1V source.

Pin VSS is connected to Vdc 0V source.

Pin input1 will be given an input pulse that varies from 0V to 1V, with periodT=1us.

Pin input2 will be given an input pulse that varies from 0V to 1V, with periodT=2us.

Finally, the waveform of NAND gate:

Conclusion: The results consistent with the logic states from the true table of the NAND gate.

 NOR GATE:

Pin VDD is connected to a Vdc 1V source.

Pin VSS is connected to Vdc 0V source.

Pin input1 will be given an input pulse that varies from 0V to 1V, with periodT=1us.

Pin input2 will be given an input pulse that varies from 0V to 1V, with periodT=2us.

Finally, the waveform of NOR gate:

Conclusion: The obtained results are completely consistent with the logic states fromthetruth table of
the NOR gate: