512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM

Features

DDR2 SDRAM UDIMM

MT4HTF6464AZ – 512MB
MT4HTF12864AZ – 1GB

Features Figure 1: 240-Pin UDIMM (MO-237 R/C C)

Module Height: 30mm (1.181 in)
• 240-pin, unbuffered dual in-line memory module
• Fast data transfer rates: PC2-8500, PC2-6400,
PC2-5300, PC2-4200, or PC2-3200
• 512MB (64 Meg x 64), 1GB (128 Meg x 64)
• VDD = V DDQ = 1.8V
• VDDSPD = 1.7–3.6V
Options Marking
• JEDEC-standard 1.8V I/O (SSTL_18-compatible) • Operating temperature
• Differential data strobe (DQS, DQS#) option – Commercial (0°C ≤ T A ≤ +70°C) None
• 4n-bit prefetch architecture – Industrial (–40°C ≤ T A ≤ +85°C)1 I
• Multiple internal device banks for concurrent • Package
operation – 240-pin DIMM (halogen-free) Z
• Programmable CAS latency (CL) • Frequency/CL2
– 1.875ns @ CL = 7 (DDR2-1066) -1GA
• Posted CAS additive latency (AL)
– 2.5ns @ CL = 5 (DDR2-800) -80E
• WRITE latency = READ latency - 1 tCK – 2.5ns @ CL = 6 (DDR2-800) -800
• Programmable burst lengths (BL): 4 or 8 – 3ns @ CL = 5 (DDR2-667) -667
• Adjustable data-output drive strength
Notes: 1. Contact Micron for industrial temperature
• 64ms, 8192-cycle refresh module offerings.
• On-die termination (ODT) 2. CL = CAS (READ) latency.
• Serial presence-detect (SPD) with EEPROM
• Halogen-free
• Gold edge contacts
• Single rank

Table 1: Key Timing Parameters

Speed Industry Data Rate (MT/s) tRCD tRP tRC

Grade Nomenclature CL = 7 CL = 6 CL = 5 CL = 4 CL = 3 (ns) (ns) (ns)

-1GA PC2-8500 1066 800 667 533 400 13.125 13.125 58.125
-80E PC2-6400 800 800 533 400 12.5 12.5 57.5
-800 PC2-6400 800 667 533 400 15 15 60
-667 PC2-5300 – 667 553 400 15 15 60
-53E PC2-4200 – – 553 400 15 15 55
-40E PC2-3200 – – 400 400 15 15 55

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Products and specifications discussed herein are subject to change by Micron without notice.
 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features

Table 2: Addressing

Parameter 512MB 1GB

Refresh count 8K 8K
Row address 8K A[12:0] 16K A[13:0]
Device bank address 8 BA[2:0] 8 BA[2:0]
Device configuration 1Gb (64 Meg x 16) 2Gb (128 Meg x16)
Column address 1K A[9:0] 1K A[9:0]
Module rank address 1 S0# 1 S0#

Table 3: Part Numbers and Timing Parameters – 512MB Modules

Base device: MT47H64M16,1 1Gb DDR2 SDRAM
Module Module Memory Clock/ Clock Cycles
Part Number2 Density Configuration Bandwidth Data Rate (CL-tRCD-tRP)
MT4HTF6464A(I)Z-1GA__ 512MB 64 Meg x 64 8.5 GB/s 1.875ns/1066 MT/s 7-7-7
MT4HTF6464A(I)Z-80E__ 512MB 64 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT4HTF6464A(I)Z-800__ 512MB 64 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT4HTF6464A(I)Z-667__ 512MB 64 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5

Table 4: Part Numbers and Timing Parameters – 512MB Modules

Base device: MT47H128M16,1 2Gb DDR2 SDRAM
Module Module Memory Clock/ Clock Cycles
Part Number2 Density Configuration Bandwidth Data Rate (CL-tRCD-tRP)
MT4HTF12864A(I)Z-1GA__ 1GB 128 Meg x 64 8.5 GB/s 1.875ns/1066 MT/s 7-7-7
MT4HTF12864A(I)Z-80E__ 1GB 128 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT4HTF12864A(I)Z-800__ 1GB 128 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT4HTF12864A(I)Z-667__ 1GB 128 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5

Notes: 1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT4HTF6464AZ-800M1.

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 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments

Pin Assignments

Table 5: Pin Assignments

240-Pin UDIMM Front 240-Pin UDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDDQ 211 DM5
2 VSS 32 VSS 62 VDDQ 92 DQS5# 122 DQ4 152 DQ28 182 A3 212 NC
3 DQ0 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 183 A1 213 VSS
4 DQ1 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VDD 214 DQ46
5 VSS 35 VSS 65 VSS 95 DQ42 125 DM0 155 DM3 185 CK0 215 DQ47
6 DQS0# 36 DQS3# 66 VSS 96 DQ43 126 NC 156 NC 186 CK0# 216 VSS
7 DQS0 37 DQS3 67 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52
8 VSS 38 VSS 68 NC 98 DQ48 128 DQ6 158 DQ30 188 A0 218 DQ53
9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 VSS
10 DQ3 40 DQ27 70 A10 100 VSS 130 VSS 160 VSS 190 BA1 220 CK2
11 VSS 41 VSS 71 BA0 101 SA2 131 DQ12 161 NC 191 VDDQ 221 CK2#
12 DQ8 42 NC 72 VDDQ 102 NC 132 DQ13 162 NC 192 RAS# 222 VSS
13 DQ9 43 NC 73 WE# 103 VSS 133 VSS 163 VSS 193 S0# 223 DM6
14 VSS 44 VSS 74 CAS# 104 DQS6# 134 DM1 164 NC 194 VDDQ 224 NC
15 DQS1# 45 NC 75 VDDQ 105 DQS6 135 NC 165 NC 195 ODT0 225 VSS
16 DQS1 46 NC 76 NC 106 VSS 136 VSS 166 VSS 196 NC/A131 226 DQ54
17 VSS 47 VSS 77 NC 107 DQ50 137 CK1 167 NC 197 VDD 227 DQ55
18 NC 48 NC 78 VDDQ 108 DQ51 138 CK1# 168 NC 198 VSS 228 VSS
19 NC 49 NC 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ36 229 DQ60
20 VSS 50 VSS 80 DQ32 110 DQ56 140 DQ14 170 VDDQ 200 DQ37 230 DQ61
21 DQ10 51 VDDQ 81 DQ33 111 DQ57 141 DQ15 171 NC 201 VSS 231 VSS
22 DQ11 52 CKE0 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4 232 DM7
23 VSS 53 VDD 83 DQS4# 113 DQS7# 143 DQ20 173 NC 203 NC 233 NC
24 DQ16 54 BA2 84 DQS4 114 DQS7 144 DQ21 174 NC 204 VSS 234 VSS
25 DQ17 55 NC 85 VSS 115 VSS 145 VSS 175 VDDQ 205 DQ38 235 DQ62
26 VSS 56 VDDQ 86 DQ34 116 DQ58 146 DM2 176 A12 206 DQ39 236 DQ63
27 DQS2# 57 A11 87 DQ35 117 DQ59 147 NC 177 A9 207 VSS 237 VSS
28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD
29 VSS 59 VDD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SA0
30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1

Note: 1. Pin 196 is NC for 512MB, or A13 for 1GB.

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 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Descriptions

Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.

Table 6: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
CKx, Input Clock: Differential clock inputs. All control, command, and address input signals are
CK#x sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
bus.
SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the
SPD EEPROM on the I2C bus.
CBx I/O Check bits. Used for system error detection and correction.
DQx I/O Data input/output: Bidirectional data bus.
DQSx, I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-
DQS#x troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.

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 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Descriptions

Table 6: Pin Descriptions (Continued)

Symbol Type Description

SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
the I2C bus.
RDQSx, Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
RDQS#x MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disa-
bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
Err_Out# Output Parity error output: Parity error found on the command and address bus.
(open drain)
VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-
ule VDD.
VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V.
VREF Supply Reference voltage: VDD/2.
VSS Supply Ground.
NC – No connect: These pins are not connected on the module.
NF – No function: These pins are connected within the module, but provide no functional-
ity.
NU – Not used: These pins are not used in specific module configurations/operations.
RFU – Reserved for future use.

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 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Functional Block Diagram

Functional Block Diagram

Figure 2: Functional Block Diagram

S0#
BA[2:0] BA[2:0]: DDR2 SDRAM
VSS CS# CS# A[13/12:0] A[13/12:0]: DDR2 SDRAM
DQS0 DQS# DQS4 DQS# RAS# RAS#: DDR2 SDRAM
DQS0# DQ DQS4# DQ
CAS# CAS#: DDR2 SDRAM
DM0 DM DM4 DM
DQ0 DQ DQ32 DQ WE# WE#: DDR2 SDRAM
DQ1 DQ DQ33 DQ CKE0 CKE0: DDR2 SDRAM
DQ2 DQ DQ34 DQ
Vss
DQ3 DQ DQ35 DQ
DQ4 DQ DQ36 DQ ODT0 ODT0: DDR2 SDRAM
DQ5 DQ DQ37 DQ
Vss
DQ6 DQ DQ38 DQ
DQ7 DQ
U1 DQ39 DQ U3
DQS1 DQS# DQS5 DQS#
DQS1# DQ DQS5# DQ
U5
DM1 DM DM5 DM SPD EEPROM
SCL SDA
DQ8 DQ DQ40 DQ
WP A0 A1 A2
DQ9 DQ DQ41 DQ
DQ10 DQ DQ42 DQ
VSS SA0 SA1 SA2
DQ11 DQ DQ43 DQ
DQ12 DQ DQ44 DQ
DQ13 DQ DQ45 DQ CK0
DQ14 DQ DQ46 DQ CK0#
DQ15 DQ DQ47 DQ

CK1
DDR SDRAM x 2
CS# CS# CK1#
DQS2 DQS# DQS6 DQS#
DQS2# DQ DQS6# DQ
DM2 DM DM6 DM CK2
DDR SDRAM x 2
DQ16 DQ DQ48 DQ CK2#
DQ17 DQ DQ49 DQ
DQ18 DQ DQ50 DQ
DQ19 DQ DQ51 DQ
DQ20 DQ DQ52 DQ VDDSPD SPD EEPROM
DQ21 DQ DQ53 DQ
DQ22 DQ DQ54 DQ VDD/VDDQ DDR2 SDRAM
DQ23 DQ U2 DQ55 DQ U4
DQS3 DQS# DQS7 DQS# VREF DDR2 SDRAM
DQS3# DQ DQS7# DQ
DM3 DM DM7 DM VSS DDR2 SDRAM
DQ24 DQ DQ56 DQ
DQ25 DQ DQ57 DQ
DQ26 DQ DQ58 DQ
DQ27 DQ DQ59 DQ
DQ28 DQ DQ60 DQ
DQ29 DQ DQ61 DQ
DQ30 DQ DQ62 DQ
DQ31 DQ DQ63 DQ

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 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
General Description

General Description
DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
essentially a 4n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data
transfers at the I/O pins.
DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is
transmitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.

Serial Presence-Detect EEPROM Operation

DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-
ule type and various SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
(WP) is connected to V SS, permanently disabling hardware write protection.

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 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications

Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in the device data sheet are not implied. Exposure to abso-
lute maximum rating conditions for extended periods may adversely affect reliability.

Table 7: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD/VDDQ VDD/VDDQ supply voltage relative to VSS –0.5 2.3 V
VIN, VOUT Voltage on any pin relative to VSS –0.5 2.3 V
II Input leakage current; Any input 0V ≤ VIN ≤ VDD; Address inputs, RAS#, –20 20 µA
VREF input 0V ≤ VIN ≤ 0.95V; (All other pins not CAS#, WE#, BA
under test = 0V) CK, CK# –10 10
DM –5 5
IOZ Output leakage current; 0V ≤ VOUT; DQ and ODT DQ, DQS, DQS# –5 5 µA
are disabled
IVREF VREF leakage current; VREF = valid VREF level –8 8 µA
TA Module ambient operating temperature Commercial 0 70 °C
Industrial –40 85 °C
TC 1 DDR2 SDRAM component operating tempera- Commercial 0 85 °C
ture2 Industrial –40 95 °C

Notes: 1. The refresh rate is required to double when TC exceeds 85°C.

2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-
able on Micron’s Web site.

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 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
DRAM Operating Conditions

DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron's Web site. Module speed grades cor-
relate with component speed grades.

Table 8: Module and Component Speed Grades

DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade Component Speed Grade
-1GA -187E
-80E -25E
-800 -25
-667 -3
-53E -37E
-40E -5E

Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Mi-
cron encourages designers to simulate the signal characteristics of the system's memo-
ry bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.

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 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications

IDD Specifications

Table 9: DDR2 IDD Specifications and Conditions (Die Revision G) – 512MB

Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Operating one bank active-precharge current: tCK = tCK (IDD), tRC IDD0 720 600 540 mA
= tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between val-
id commands; Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge current: IOUT = 0mA; IDD1 840 700 520 mA
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS
MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data pattern is same as
IDD4W
Precharge power-down current: All device banks idle; tCK = tCK IDD2P 28 28 28 mA
(IDD); CKE is LOW; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge quiet standby current: All device banks idle; tCK = tCK IDD2Q 360 300 260 mA
(IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are
stable; Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE IDD2N 380 320 280 mA
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current: All device banks open; Fast PDN exit IDD3P 200 160 120 mA
tCK = tCK (IDD); CKE is LOW; Other control and address MR[12] = 0
bus inputs are stable; Data bus inputs are floating Slow PDN exit 40 40 40
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = IDD3N 380 340 300 mA
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data
bus inputs are switching
Operating burst write current: All device banks open; Continuous IDD4W 1620 1260 800 mA
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous IDD4R 1680 1280 880 mA
burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (I ), tRP = tRP (I ); CKE is HIGH, S# is HIGH between
DD DD
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current: tCK = tCK (IDD); REFRESH command at every IDD5 1200 1120 1080 mA
tRFC (I ) interval; CKE is HIGH, S# is HIGH between valid commands;
DD
Other control and address bus inputs are switching; Data bus inputs
are switching

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 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications

Table 9: DDR2 IDD Specifications and Conditions (Die Revision G) – 512MB (Continued)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and IDD6 28 28 28 mA
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleav- IDD7 2080 1760 1400 mA
ing reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK
(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
puts are stable during deselects; Data bus inputs are switching

Table 10: DDR2 IDD Specifications and Conditions (Die Revision H) – 512MB
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Operating one bank active-precharge current: tCK = tCK (IDD), tRC IDD0 360 320 300 mA
= tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between val-
id commands; Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge current: IOUT = 0mA; IDD1 400 380 360 mA
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS
MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data pattern is same as
IDD4W
Precharge power-down current: All device banks idle; tCK = tCK IDD2P 28 28 28 mA
(IDD); CKE is LOW; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge quiet standby current: All device banks idle; tCK = tCK IDD2Q 160 104 104 mA
(IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are
stable; Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE IDD2N 144 120 104 mA
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current: All device banks open; Fast PDN exit IDD3P 92 80 60 mA
tCK = tCK (IDD); CKE is LOW; Other control and address MR[12] = 0
bus inputs are stable; Data bus inputs are floating Slow PDN exit 40 40 40
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = IDD3N 168 140 128 mA
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data
bus inputs are switching

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htf4c64_128x64az.pdf - Rev. D 4/14 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.
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 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications

Table 10: DDR2 IDD Specifications and Conditions (Die Revision H) – 512MB (Continued)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Operating burst write current: All device banks open; Continuous IDD4W 740 640 540 mA
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous IDD4R 720 600 500 mA
burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (I ), tRP = tRP (I ); CKE is HIGH, S# is HIGH between
DD DD
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current: tCK = tCK (IDD); REFRESH command at every IDD5 640 600 580 mA
tRFC (I ) interval; CKE is HIGH, S# is HIGH between valid commands;
DD
Other control and address bus inputs are switching; Data bus inputs
are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and IDD6 28 28 28 mA
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleav- IDD7 1080 1040 920 mA
ing reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK
(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
puts are stable during deselects; Data bus inputs are switching

Table 11: DDR2 IDD Specifications and Conditions (Die Revision M) – 512MB
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Operating one bank active-precharge current: tCK = tCK (IDD), tRC IDD0 360 320 300 mA
= tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between val-
id commands; Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge current: IOUT = 0mA; IDD1 400 380 360 mA
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS
MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data pattern is same as
IDD4W
Precharge power-down current: All device banks idle; tCK = tCK IDD2P 40 40 40 mA
(IDD); CKE is LOW; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge quiet standby current: All device banks idle; tCK = tCK IDD2Q 120 104 104 mA
(IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are
stable; Data bus inputs are floating

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htf4c64_128x64az.pdf - Rev. D 4/14 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications

Table 11: DDR2 IDD Specifications and Conditions (Die Revision M) – 512MB (Continued)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE IDD2N 144 120 104 mA
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current: All device banks open; Fast PDN exit IDD3P 128 120 104 mA
tCK = tCK (I ); CKE is LOW; Other control and address MR[12] = 0
DD
bus inputs are stable; Data bus inputs are floating Slow PDN exit 80 80 80
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = IDD3N 172 152 144 mA
tRAS MAX (I ), tRP = tRP (I ); CKE is HIGH, S# is HIGH between valid
DD DD
commands; Other control and address bus inputs are switching; Data
bus inputs are switching
Operating burst write current: All device banks open; Continuous IDD4W 740 640 540 mA
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous IDD4R 720 600 500 mA
burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (I ), tRP = tRP (I ); CKE is HIGH, S# is HIGH between
DD DD
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current: tCK = tCK (IDD); REFRESH command at every IDD5 680 640 620 mA
tRFC (I ) interval; CKE is HIGH, S# is HIGH between valid commands;
DD
Other control and address bus inputs are switching; Data bus inputs
are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and IDD6 28 28 28 mA
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleav- IDD7 1080 1040 920 mA
ing reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK
(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
puts are stable during deselects; Data bus inputs are switching

Table 12: DDR2 IDD Specifications and Conditions (Die Revision C) – 1GB
Values shown for MT47H128M16 DDR2 SDRAM only and are computed from values specified in the 2Gb (128 Meg x 16)
component data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Operating one bank active-precharge current: tCK = tCK (IDD), tRC IDD0 400 360 340 mA
= tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between val-
id commands; Address bus inputs are switching; Data bus inputs are
switching

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htf4c64_128x64az.pdf - Rev. D 4/14 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications

Table 12: DDR2 IDD Specifications and Conditions (Die Revision C) – 1GB (Continued)
Values shown for MT47H128M16 DDR2 SDRAM only and are computed from values specified in the 2Gb (128 Meg x 16)
component data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Operating one bank active-read-precharge current: IOUT = 0mA; IDD1 440 420 400 mA
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS
MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data pattern is same as
IDD4W
Precharge power-down current: All device banks idle; tCK = tCK IDD2P 48 48 48 mA
(IDD); CKE is LOW; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge quiet standby current: All device banks idle; tCK = tCK IDD2Q 200 180 160 mA
(IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are
stable; Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE IDD2N 220 200 180 mA
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current: All device banks open; Fast PDN exit IDD3P 100 100 100 mA
tCK = tCK (IDD); CKE is LOW; Other control and address MR[12] = 0
bus inputs are stable; Data bus inputs are floating Slow PDN exit 56 56 56
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = IDD3N 240 200 180 mA
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data
bus inputs are switching
Operating burst write current: All device banks open; Continuous IDD4W 840 760 680 mA
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous IDD4R 840 760 680 mA
burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (I ), tRP = tRP (I ); CKE is HIGH, S# is HIGH between
DD DD
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current: tCK = tCK (IDD); REFRESH command at every IDD5 700 680 660 mA
tRFC (I ) interval; CKE is HIGH, S# is HIGH between valid commands;
DD
Other control and address bus inputs are switching; Data bus inputs
are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and IDD6 48 48 48 mA
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleav- IDD7 1160 1120 1000 mA
ing reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK
(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
puts are stable during deselects; Data bus inputs are switching

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htf4c64_128x64az.pdf - Rev. D 4/14 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Serial Presence-Detect

Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.

Table 13: SPD EEPROM Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 1.7 3.6 V
Input high voltage: logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: logic 0; All inputs VIL –0.6 VDDSPD × 0.3 V
Output low voltage: IOUT = 3mA VOL – 0.4 V
Input leakage current: VIN = GND to VDD ILI 0.1 3 µA
Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA
Standby current ISB 1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA

Table 14: SPD EEPROM AC Operating Conditions

Parameter/Condition Symbol Min Max Units Notes

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1
Time bus must be free before a new transition can start tBUF 1.3 – µs
Data-out hold time tDH 200 – ns
SDA and SCL fall time tF – 300 ns 2
SDA and SCL rise time tR – 300 ns 2
Data-in hold time tHD:DAT 0 – µs
Start condition hold time tHD:STA 0.6 – µs
Clock HIGH period tHIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs tI – 50 ns
Clock LOW period tLOW 1.3 – µs
SCL clock frequency tSCL – 400 kHz
Data-in setup time tSU:DAT 100 – ns
Start condition setup time tSU:STA 0.6 – µs 3
Stop condition setup time tSU:STO 0.6 – µs
WRITE cycle time tWRC – 10 ms 4

Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to
pull-up resistance, and the EEPROM does not respond to its slave address.

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 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Module Dimensions

Module Dimensions

Figure 3: 240-Pin DDR2 UDIMM

Front view
2.7 (0.106)
133.5 (5.256) MAX
133.2 (5.244)

2.0 (0.079) R
(4X)

U1 U2 U3 U4 30.5 (1.2)
29.85 (1.175)
U5
2.5 (0.098) D 17.78 (0.7)
(2X) TYP

2.3 (0.091) TYP

Pin 1 0.76 (0.03) R 1.37 (0.054)
1.17 (0.046)
2.21 (0.087) TYP 1.0 (0.039) 0.8 (0.031) 10.0 (0.394)
TYP TYP TYP
1.0 (0.039) TYP
Pin 120
70.66 (2.782)
TYP

123.0 (4.840)
TYP

45° (4X) Back view

No components this side of module

Pin 240 Pin 121

3.04 (0.1197) 5.0 (0.197) TYP
TYP
55.0 (2.165) 63.0 (2.48)
TYP TYP

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for ad-
ditional design dimensions.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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htf4c64_128x64az.pdf - Rev. D 4/14 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.