512Mb: x4, x8, x16 DDR2 SDRAM

Features

DDR2 SDRAM
MT47H128M4 – 32 Meg x 4 x 4 banks
MT47H64M8 – 16 Meg x 8 x 4 banks
MT47H32M16 – 8 Meg x 16 x 4 banks

Features Options1 Marking

• Configuration
• VDD = 1.8V ±0.1V, V DDQ = 1.8V ±0.1V – 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4
• JEDEC-standard 1.8V I/O (SSTL_18-compatible) – 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8
• Differential data strobe (DQS, DQS#) option – 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16
• 4n-bit prefetch architecture • FBGA package (Pb-free) – x16
• Duplicate output strobe (RDQS) option for x8 – 84-ball FBGA (8mm x 12.5mm) Rev. G HR
– 84-ball FBGA (8mm x 12.5mm) Rev. H NF
• DLL to align DQ and DQS transitions with CK
• FBGA package (Pb-free) – x4, x8
• 4 internal banks for concurrent operation – 60-ball FBGA (8mm x 10mm) Rev. G CF
• Programmable CAS latency (CL) – 60-ball FBGA (8mm x 10mm) Rev. H SH
• Posted CAS additive latency (AL) • FBGA package (lead solder) – x16
• WRITE latency = READ latency - 1 tCK – 84-ball FBGA (8mm x 12.5mm) Rev. G HW
• Selectable burst lengths: 4 or 8 • FBGA package (lead solder) – x4, x8
– 60-ball FBGA (8mm x 10mm) Rev. G JN
• Adjustable data-output drive strength
• Timing – cycle time
• 64ms, 8192-cycle refresh – 1.875ns @ CL = 7 (DDR2-1066) -187E
• On-die termination (ODT) – 2.5ns @ CL = 5 (DDR2-800) -25E
• Industrial temperature (IT) option – 3.0ns @ CL = 5 (DDR2-667) -3
• RoHS-compliant • Self refresh
• Supports JEDEC clock jitter specification – Standard None
– Low-power L
• Operating temperature
– Commercial (0°C ื T C ื +85°C)2 None
– Industrial (–40°C ื T C ื +95°C; IT
–40°C ื T A ื +85°C)
• Revision :G/:H
Notes: 1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on www.micron.com for
product offerings and availability.
2. For extended CT operating temperature,
see Table 11 (page 30), Note 7.

Table 1: Key Timing Parameters

Data Rate (MT/s)

Speed Grade CL = 3 CL = 4 CL = 5 CL = 6 CL = 7 tRC (ns)
-187E 400 533 800 800 1066 54
-25E 400 533 800 800 n/a 55
-3 400 533 667 n/a n/a 55

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 512Mb: x4, x8, x16 DDR2 SDRAM
Features

Table 2: Addressing

Parameter 128 Meg x 4 64 Meg x 8 32 Meg x 16

Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks
Refresh count 8K 8K 8K
Row address A[13:0] (16K) A[13:0] (16K) A[12:0] (8K)
Bank address BA[1:0] (4) BA[1:0] (4) BA[1:0] (4)
Column address A[11, 9:0] (2K) A[9:0] (1K) A[9:0] (1K)

Figure 1: 512Mb DDR2 Part Numbers

Example Part Number: MT47H128M4SH-25E:H

- :
MT47H Configuration Package Speed Revision

^
Configuration :G/:H Revision
128 Meg x 4 128M4
64 Meg x 8 64M8 L Low power
32 Meg x 16 32M16 IT Industrial temperature

Package
Pb-free Speed Grade
84-ball 8mm x 12.5mm FBGA HR -3 tCK = 3ns, CL = 5
60-ball 8mm x 10.0mm FBGA CF -25E tCK = 2.5ns, CL = 5
84-ball 8mm x 12.5mm FBGA NF -187E tCK = 1.875ns, CL = 7
60-ball 8mm x 10.0mm FBGA SH
Lead solder
84-ball 8mm x 12.5mm FBGA HW
60-ball 8mm x 10mm FBGA JN

Note: 1. Not all speeds and configurations are available in all packages.

FBGA Part Number System

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Features

Contents
Important Notes and Warnings ......................................................................................................................... 8
State Diagram .................................................................................................................................................. 9
Functional Description ................................................................................................................................... 10
Industrial Temperature ............................................................................................................................... 10
General Notes ............................................................................................................................................ 11
Functional Block Diagrams ............................................................................................................................. 12
Ball Assignments and Descriptions ................................................................................................................. 14
Packaging ...................................................................................................................................................... 18
Package Dimensions ................................................................................................................................... 18
FBGA Package Capacitance ......................................................................................................................... 22
Electrical Specifications – Absolute Ratings ..................................................................................................... 23
Temperature and Thermal Impedance ........................................................................................................ 23
Electrical Specifications – IDD Parameters ........................................................................................................ 26
IDD Specifications and Conditions ............................................................................................................... 26
IDD7 Conditions .......................................................................................................................................... 26
AC Timing Operating Specifications ................................................................................................................ 33
AC and DC Operating Conditions .................................................................................................................... 45
ODT DC Electrical Characteristics ................................................................................................................... 46
Input Electrical Characteristics and Operating Conditions ............................................................................... 47
Output Electrical Characteristics and Operating Conditions ............................................................................. 50
Output Driver Characteristics ......................................................................................................................... 52
Power and Ground Clamp Characteristics ....................................................................................................... 56
AC Overshoot/Undershoot Specification ......................................................................................................... 57
Input Slew Rate Derating ................................................................................................................................ 59
Commands .................................................................................................................................................... 72
Truth Tables ............................................................................................................................................... 72
DESELECT ................................................................................................................................................. 76
NO OPERATION (NOP) ............................................................................................................................... 77
LOAD MODE (LM) ...................................................................................................................................... 77
ACTIVATE .................................................................................................................................................. 77
READ ......................................................................................................................................................... 77
WRITE ....................................................................................................................................................... 77
PRECHARGE .............................................................................................................................................. 78
REFRESH ................................................................................................................................................... 78
SELF REFRESH ........................................................................................................................................... 78
Mode Register (MR) ........................................................................................................................................ 78
Burst Length .............................................................................................................................................. 79
Burst Type .................................................................................................................................................. 80
Operating Mode ......................................................................................................................................... 80
DLL RESET ................................................................................................................................................. 80
Write Recovery ........................................................................................................................................... 81
Power-Down Mode ..................................................................................................................................... 81
CAS Latency (CL) ........................................................................................................................................ 82
Extended Mode Register (EMR) ....................................................................................................................... 83
DLL Enable/Disable ................................................................................................................................... 84
Output Drive Strength ................................................................................................................................ 84
DQS# Enable/Disable ................................................................................................................................. 84
RDQS Enable/Disable ................................................................................................................................. 84
Output Enable/Disable ............................................................................................................................... 84
On-Die Termination (ODT) ......................................................................................................................... 85

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 512Mb: x4, x8, x16 DDR2 SDRAM
Features

Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 85

Posted CAS Additive Latency (AL) ................................................................................................................ 85
Extended Mode Register 2 (EMR2) ................................................................................................................... 87
Extended Mode Register 3 (EMR3) ................................................................................................................... 88
Initialization .................................................................................................................................................. 89
ACTIVATE ...................................................................................................................................................... 92
READ ............................................................................................................................................................. 94
READ with Precharge .................................................................................................................................. 98
READ with Auto Precharge ......................................................................................................................... 100
WRITE .......................................................................................................................................................... 105
PRECHARGE ................................................................................................................................................. 115
REFRESH ...................................................................................................................................................... 116
SELF REFRESH .............................................................................................................................................. 117
Power-Down Mode ........................................................................................................................................ 119
Precharge Power-Down Clock Frequency Change ........................................................................................... 126
Reset ............................................................................................................................................................. 127
CKE Low Anytime ...................................................................................................................................... 127
ODT Timing .................................................................................................................................................. 129
MRS Command to ODT Update Delay ........................................................................................................ 131

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 512Mb: x4, x8, x16 DDR2 SDRAM
Features

List of Figures
Figure 1: 512Mb DDR2 Part Numbers ............................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 128 Meg x 4 Functional Block Diagram ............................................................................................. 12
Figure 4: 64 Meg x 8 Functional Block Diagram ............................................................................................... 13
Figure 5: 32 Meg x 16 Functional Block Diagram ............................................................................................. 13
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 14
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 15
Figure 8: 84-Ball FBGA (8mm x 12.5mm) – x16; Die Rev. :G .............................................................................. 18
Figure 9: 60-Ball FBGA (8mm x 10mm) – x4, x8; Die Rev. :G ............................................................................. 19
Figure 10: 84-Ball FBGA (8mm x 12.5mm) – x16; "NF" Die Rev. :H .................................................................... 20
Figure 11: 60-Ball FBGA (8mm x 10mm) – x4, x8; "SH" Die Rev. :H ................................................................... 21
Figure 12: Example Temperature Test Point Location ...................................................................................... 24
Figure 13: Single-Ended Input Signal Levels ................................................................................................... 47
Figure 14: Differential Input Signal Levels ...................................................................................................... 48
Figure 15: Differential Output Signal Levels .................................................................................................... 50
Figure 16: Output Slew Rate Load .................................................................................................................. 51
Figure 17: Full Strength Pull-Down Characteristics ......................................................................................... 52
Figure 18: Full Strength Pull-Up Characteristics .............................................................................................. 53
Figure 19: Reduced Strength Pull-Down Characteristics .................................................................................. 54
Figure 20: Reduced Strength Pull-Up Characteristics ...................................................................................... 55
Figure 21: Input Clamp Characteristics .......................................................................................................... 56
Figure 22: Overshoot ..................................................................................................................................... 57
Figure 23: Undershoot ................................................................................................................................... 57
Figure 24: Nominal Slew Rate for tIS ............................................................................................................... 62
Figure 25: Tangent Line for tIS ........................................................................................................................ 62
Figure 26: Nominal Slew Rate for tIH .............................................................................................................. 63
Figure 27: Tangent Line for tIH ....................................................................................................................... 63
Figure 28: Nominal Slew Rate for tDS ............................................................................................................. 68
Figure 29: Tangent Line for tDS ...................................................................................................................... 68
Figure 30: Nominal Slew Rate for tDH ............................................................................................................. 69
Figure 31: Tangent Line for tDH ..................................................................................................................... 69
Figure 32: AC Input Test Signal Waveform Command/Address Balls ................................................................ 70
Figure 33: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 70
Figure 34: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 71
Figure 35: AC Input Test Signal Waveform (Differential) .................................................................................. 71
Figure 36: MR Definition ............................................................................................................................... 79
Figure 37: CL ................................................................................................................................................. 82
Figure 38: EMR Definition ............................................................................................................................. 83
Figure 39: READ Latency ............................................................................................................................... 86
Figure 40: WRITE Latency .............................................................................................................................. 86
Figure 41: EMR2 Definition ........................................................................................................................... 87
Figure 42: EMR3 Definition ........................................................................................................................... 88
Figure 43: DDR2 Power-Up and Initialization ................................................................................................. 89
Figure 44: Example: Meeting tRRD (MIN) and tRCD (MIN) .............................................................................. 92
Figure 45: Multibank Activate Restriction ....................................................................................................... 93
Figure 46: READ Latency ............................................................................................................................... 95
Figure 47: Consecutive READ Bursts .............................................................................................................. 96
Figure 48: Nonconsecutive READ Bursts ........................................................................................................ 97
Figure 49: READ Interrupted by READ ............................................................................................................ 98
Figure 50: READ-to-WRITE ............................................................................................................................ 98

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 512Mb: x4, x8, x16 DDR2 SDRAM
Features

Figure 51: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 99

Figure 52: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 99
Figure 53: Bank Read – Without Auto Precharge ............................................................................................. 101
Figure 54: Bank Read – with Auto Precharge .................................................................................................. 102
Figure 55: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window .................................................. 103
Figure 56: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window ..................................................... 104
Figure 57: Data Output Timing – tAC and tDQSCK ......................................................................................... 105
Figure 58: Write Burst ................................................................................................................................... 107
Figure 59: Consecutive WRITE-to-WRITE ...................................................................................................... 108
Figure 60: Nonconsecutive WRITE-to-WRITE ................................................................................................ 108
Figure 61: WRITE Interrupted by WRITE ....................................................................................................... 109
Figure 62: WRITE-to-READ ........................................................................................................................... 110
Figure 63: WRITE-to-PRECHARGE ................................................................................................................ 111
Figure 64: Bank Write – Without Auto Precharge ............................................................................................ 112
Figure 65: Bank Write – with Auto Precharge .................................................................................................. 113
Figure 66: WRITE – DM Operation ................................................................................................................ 114
Figure 67: Data Input Timing ........................................................................................................................ 115
Figure 68: Refresh Mode ............................................................................................................................... 116
Figure 69: Self Refresh .................................................................................................................................. 118
Figure 70: Power-Down ................................................................................................................................ 120
Figure 71: READ-to-Power-Down or Self Refresh Entry .................................................................................. 122
Figure 72: READ with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................... 122
Figure 73: WRITE-to-Power-Down or Self Refresh Entry ................................................................................. 123
Figure 74: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 123
Figure 75: REFRESH Command-to-Power-Down Entry .................................................................................. 124
Figure 76: ACTIVATE Command-to-Power-Down Entry ................................................................................. 124
Figure 77: PRECHARGE Command-to-Power-Down Entry ............................................................................. 125
Figure 78: LOAD MODE Command-to-Power-Down Entry ............................................................................. 125
Figure 79: Input Clock Frequency Change During Precharge Power-Down Mode ............................................ 126
Figure 80: RESET Function ........................................................................................................................... 128
Figure 81: ODT Timing for Entering and Exiting Power-Down Mode ............................................................... 130
Figure 82: Timing for MRS Command to ODT Update Delay .......................................................................... 131
Figure 83: ODT Timing for Active or Fast-Exit Power-Down Mode .................................................................. 131
Figure 84: ODT Timing for Slow-Exit or Precharge Power-Down Modes .......................................................... 132
Figure 85: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 132
Figure 86: ODT Turn-On Timing When Entering Power-Down Mode .............................................................. 133
Figure 87: ODT Turn-Off Timing When Exiting Power-Down Mode ................................................................ 134
Figure 88: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................. 135

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 512Mb: x4, x8, x16 DDR2 SDRAM
Features

List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 16
Table 4: Input Capacitance ............................................................................................................................ 22
Table 5: Absolute Maximum DC Ratings ......................................................................................................... 23
Table 6: Temperature Limits .......................................................................................................................... 24
Table 7: Thermal Impedance ......................................................................................................................... 24
Table 8: General IDD Parameters ..................................................................................................................... 26
Table 9: IDD7 Timing Patterns (4-Bank Interleave READ Operation) ................................................................. 26
Table 10: DDR2 IDD Specifications and Conditions (Die Revision G) ................................................................ 27
Table 11: DDR2 IDD Specifications and Conditions (Die Revision H) ................................................................ 30
Table 12: AC Operating Specifications and Conditions .................................................................................... 33
Table 13: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 45
Table 14: ODT DC Electrical Characteristics ................................................................................................... 46
Table 15: Input DC Logic Levels ..................................................................................................................... 47
Table 16: Input AC Logic Levels ...................................................................................................................... 47
Table 17: Differential Input Logic Levels ......................................................................................................... 48
Table 18: Differential AC Output Parameters ................................................................................................... 50
Table 19: Output DC Current Drive ................................................................................................................ 50
Table 20: Output Characteristics .................................................................................................................... 51
Table 21: Full Strength Pull-Down Current (mA) ............................................................................................. 52
Table 22: Full Strength Pull-Up Current (mA) .................................................................................................. 53
Table 23: Reduced Strength Pull-Down Current (mA) ...................................................................................... 54
Table 24: Reduced Strength Pull-Up Current (mA) .......................................................................................... 55
Table 25: Input Clamp Characteristics ............................................................................................................ 56
Table 26: Address and Control Balls ................................................................................................................ 57
Table 27: Clock, Data, Strobe, and Mask Balls ................................................................................................. 57
Table 28: AC Input Test Conditions ................................................................................................................ 57
Table 29: DDR2-400/533 Setup and Hold Time Derating Values ( tIS and tIH) .................................................... 60
Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values ( tIS and tIH) ........................................... 61
Table 31: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe ...................................................... 64
Table 32: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe ............................................. 65
Table 33: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb ................................................... 66
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V REF) at DDR2-667 ...................................... 66
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V REF) at DDR2-533 ...................................... 67
Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V REF) at DDR2-400 ...................................... 67
Table 37: Truth Table – DDR2 Commands ...................................................................................................... 72
Table 38: Truth Table – Current State Bank n – Command to Bank n ................................................................ 73
Table 39: Truth Table – Current State Bank n – Command to Bank m ............................................................... 75
Table 40: Minimum Delay with Auto Precharge Enabled ................................................................................. 76
Table 41: Burst Definition .............................................................................................................................. 80
Table 42: READ Using Concurrent Auto Precharge ......................................................................................... 100
Table 43: WRITE Using Concurrent Auto Precharge ....................................................................................... 106
Table 44: Truth Table – CKE .......................................................................................................................... 121

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 512Mb: x4, x8, x16 DDR2 SDRAM
Important Notes and Warnings

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.

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 512Mb: x4, x8, x16 DDR2 SDRAM
State Diagram

State Diagram

Figure 2: Simplified State Diagram

CKE_L
Initialization
sequence
OCD Self
default refreshing

SR
PRE
H
CKE_
Setting Idle
MRS (E)MRS all banks REFRESH Refreshing
EMRS precharged

CK
E_ CK L
H E_ E_
L CK

Precharge
power-
down
CKE_L
Automatic Sequence
Command Sequence
ACT ACT = ACTIVATE
CKE_H = CKE HIGH, exit power-down or self refresh
CKE_L = CKE LOW, enter power-down
(E)MRS = (Extended) mode register set
CKE_L Activating PRE = PRECHARGE
_L PRE_A = PRECHARGE ALL
CKE READ = READ
Active
power- READ A = READ with auto precharge
down REFRESH = REFRESH
CK CKE_ SR = SELF REFRESH
E_L H WRITE = WRITE
WRITE A = WRITE with auto precharge
Bank
active

E RE
WRITE RIT AD READ
EA

W
RE
AD
RIT
W

Writing READ Reading

WRITE

REA A
DA ITE
WR READ A

WRITE A
PR
E,

A
PR

E_
E_

PR

Writing PRE, PRE_A Reading

A

with with
,
E
PR

auto auto
precharge precharge

Precharging

Note: 1. This diagram provides the basic command flow. It is not comprehensive and does not
identify all timing requirements or possible command restrictions such as multibank in-
teraction, power down, entry/exit, etc.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Functional Description

Functional Description
The DDR2 SDRAM uses a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture, with an
interface designed to transfer two data words per clock cycle at the I/O balls. A single
READ or WRITE operation for the DDR2 SDRAM effectively consists of a single 4n-bit-
wide, two-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. The x16 offering has two data
strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS,
UDQS#).
The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a se-
lected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The ad-
dress bits registered coincident with the READ or WRITE command are used to select
the bank and the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write burst lengths of four or
eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another
read or a burst write of eight with another write. An auto precharge function may be en-
abled to provide a self-timed row precharge that is initiated at the end of the burst ac-
cess.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM
enables concurrent operation, thereby providing high, effective bandwidth by hiding
row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength
outputs are SSTL_18-compatible.

Industrial Temperature
The industrial temperature (IT) option, if offered, has two simultaneous requirements:
ambient temperature surrounding the device cannot be less than –40°C or greater than
85°C, and the case temperature cannot be less than –40°C or greater than 95°C. JEDEC
specifications require the refresh rate to double when T C exceeds 85°C; this also requires
use of the high-temperature self refresh option. Additionally, ODT resistance, input/
output impedance and IDD values must be derated when T C is < 0°C or > 85°C.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Functional Description

General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated oth-
erwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte.
For the lower byte (DQ[7:0]), DM refers to LDM and DQS refers to LDQS. For the up-
per byte (DQ[15:8]), DM refers to UDM and DQS refers to UDQS.
• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be
used, use the lower byte for data transfers and terminate the upper byte as noted:
– Connect UDQS to ground via 1k˖* resistor
– Connect UDQS# to V DD via 1k˖* resistor
– Connect UDM to V DD via 1k˖* resistor
– Connect DQ[15:8] individually to either V SS or V DD via 1k˖* resistors, or float
DQ[15:8].
*If ODT is used, 1k˖ resistor should be changed to 4x that of the selected ODT.
• Complete functionality is described throughout the document, and any page or dia-
gram may have been simplified to convey a topic and may not be inclusive of all re-
quirements.
• Any specific requirement takes precedence over a general statement.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Functional Block Diagrams

Functional Block Diagrams

The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is inter-
nally configured as a multibank DRAM.

Figure 3: 128 Meg x 4 Functional Block Diagram

ODT

CKE Control
CK logic
CK#
Command

CS#
decode

Bank3 ODT control VddQ

RAS# sw1 sw2 sw3
CAS# Bank3 Bank2 COL0, COL1 CK, CK#
WE# Bank2
Bank1 Bank1 4
Refresh 14 Bank0 DLL
Mode Row- 14 Bank0 4 sw1 sw2 sw3
counter row- 16 Read 4
registers address 4 MUX R1 R2 R3
address 16,384 Memory latch DQ0–DQ3
16 MUX latch and Data DRVRS
array 4 R1 R2 R3
14 decoder
(16,384 x 512 x 16) 2
DQS
Sense amplifiers generator DQS, DQS#
8,192 Input
registers sw1 sw2 sw3
16
2 1 1 R1 R2 R3
I/O gating DQS, DQS#
A0–A13, Address Bank DM mask logic 4 1 1
Write 1 R1 R2 R3
BA0, BA1 16 register 2 control
512 FIFO Mask 1 1
logic and RCVRS
(x16) 16 1 1
drivers
Column internal 4 4
CK out
decoder CK, CK# 16 4 4 4 sw1 sw2 sw3
Column- 9 CK in
11 Data 4 4 R1 R2 R3
address DM
2
counter/ 4 4 R1 R2 R3
latch
COL0, COL1
2
VssQ

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 512Mb: x4, x8, x16 DDR2 SDRAM
Functional Block Diagrams

Figure 4: 64 Meg x 8 Functional Block Diagram

ODT

CKE Control
CK logic
CK#
Command

CS#
decode

RAS# Bank 3 ODT control VddQ

CAS# Bank 3 Bank 2 COL0, COL1 CK, CK# sw1 sw2 sw3
WE# Bank 2
Bank 1 Bank 1 8 DLL
Refresh 14 Bank 0 Bank 0 8
Mode counter Row- 14 sw1 sw2 sw3
row- 32 Read 8
registers address 8 MUX R1
address 16,384 Memory latch DRVRS R2 R3 DQ0–DQ7
16 MUX latch and Data
array 8
14 decoder R1 R2 R3
(16,384 x 256 x 32) 2
DQS
Sense amplifiers generator DQS, DQS#
8,192 Input
registers sw1 sw2 sw3
2 1 1 R1 R2 R3
I/O gating DQS, DQS#
32 1 1
A0–A13, Address Bank DM mask logic 4 1 R1 R2 R3
16 register Write RDQS#
BA0, BA1 2 control FIFO Mask 1 1
logic 256
(x32) 32 and 1 1 RCVRS
drivers
Column internal 8 8
CK out
decoder CK, CK# 32 8 8 8 sw1 sw2 sw3
Column- 8 CK in RDQS
10 address Data 8 8 R1 R2 R3
2 DM
counter/ 8 8 R1 R2 R3
latch
COL0, COL1

2 VssQ

Figure 5: 32 Meg x 16 Functional Block Diagram

ODT

CKE Control
CK Logic
CK#
Command
decode

CS#
CK, CK# ODT control VddQ
RAS# COL0, COL1 sw1 sw2 sw3
CAS# Bank 3 Bank 3
WE# Bank 2 Bank 2 16 DLL
Bank 1 Bank 1 64 16
Mode Refresh 13 Read 16 sw1 sw2 sw3
Bank 0 Bank 0
registers counter Row- 13 latch 16 MUX DRVRS
row- Data R1 R2 R3 DQ0–DQ15
address Address 8,192 16
15 Memory R1 R2 R3
13 MUX latch and array 4
decoder (8,192 x 256 x 64) DQS
generator UDQS, UDQS#
Sense amplifiers
Input LDQS, LDQS#
16,384 registers sw1 sw2 sw3
64 2 2
2 R1 R2 R3 UDQS, UDQS#
I/O gating 2 2 LDQS, LDQS#
A0–A12, Bank DM mask logic 8 2 R1 R2 R3
BA0, BA1 15 Address Write 2 2
register 2 control
FIFO Mask 2 2
logic 256 RCVRS
(x64) 64 and
drivers 16 16
Column Internal CK out 16 sw1 sw2 sw3
16
decoder CK, CK# 64 16
Column- 8 CK in 16 16 R1 R2 R3 UDM, LDM
10 address Data
2 16 16 R1 R2 R3
counter/
latch 4
COL0, COL1

VssQ

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 512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions

Ball Assignments and Descriptions

Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View)

1 2 3 4 5 6 7 8 9

A
VDD NF, RDQS#/NU VSS VSSQ DQS#/NU VDDQ

B
NF, DQ6 VSSQ DM, DM/RDQS DQS VSSQ NF, DQ7

C
VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ

D
NF, DQ4 VSSQ DQ3 DQ2 VSSQ NF, DQ5

E
VDDL VREF VSS VSSDL CK VDD

F
CKE WE# RAS# CK# ODT

G
RFU BA0 BA1 CAS# CS#

H
A10 A1 A2 A0 VDD

J
VSS A3 A5 A6 A4

K
A7 A9 A11 A8 VSS

L
VDD A12 RFU RFU A13

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 512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions

Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View)

1 2 3 4 5 6 7 8 9

A
VDD NC VSS VSSQ UDQS#/NU VDDQ

B
DQ14 VSSQ UDM UDQS VSSQ DQ15

C
VDDQ DQ9 VDDQ VDDQ DQ8 VDDQ

D
DQ12 VSSQ DQ11 DQ10 VSSQ DQ13

E
VDD NC VSS VSSQ LDQS#/NU VDDQ

F
DQ6 VSSQ LDM LDQS VSSQ DQ7

G
VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ

H
DQ4 VSSQ DQ3 DQ2 VSSQ DQ5

J
VDDL VREF VSS VSSDL CK VDD

K
CKE WE# RAS# CK# ODT

L
RFU BA0 BA1 CAS# CS#

M
A10 A1 A2 A0 VDD

N
VSS A3 A5 A6 A4

P
A7 A9 A11 A8 VSS

R
VDD A12 RFU RFU RFU

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 512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions

Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions

Symbol Type Description

A[12:0] (x16) Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-
A[13:0] (x4, x8) dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[1:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command.
BA0, BA1 Input Bank address inputs: BA[1:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[1:0] define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE pow-
er-down (row active in any bank). CKE is synchronous for power-down entry, power-
down exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF RE-
FRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an
SSTL_18 input but will detect a LVCMOS LOW level once VDD is applied during first pow-
er-up. After VREF has become stable during the power-on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH
operation, VREF must be maintained.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered high. CS# provides for exter-
nal bank selection on systems with multiple ranks. CS# is considered part of the com-
mand code.
LDM, UDM, DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on
both edges of DQS. Although DM balls are input-only, the DM loading is designed to
match that of DQ and DQS balls. LDM is DM for lower byte DQ[7:0] and UDM is DM for
upper byte DQ[15:8].
ODT Input On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls:
DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ[7:0], DQS, DQS#,
RDQS, RDQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input
will be ignored if disabled via the LOAD MODE command.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered.
DQ[15:0] (x16) I/O Data input/output: Bidirectional data bus for 32 Meg x 16.
DQ[3:0] (x4) Bidirectional data bus for 128 Meg x 4.
DQ[7:0] (x8) Bidirectional data bus for 64 Meg x 8.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions

Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions (Continued)

Symbol Type Description

DQS, DQS# I/O Data strobe: Output with read data, input with write data for source synchronous oper-
ation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
LDQS, LDQS# I/O Data strobe for lower byte: Output with read data, input with write data for source
synchronous operation. Edge-aligned with read data, center-aligned with write data.
LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
UDQS, UDQS# I/O Data strobe for upper byte: Output with read data, input with write data for source
synchronous operation. Edge-aligned with read data, center-aligned with write data.
UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
RDQS, RDQS# Output Redundant data strobe: For 64 Meg x 8 only. RDQS is enabled/disabled via the load
mode command to the extended mode register (EMR). When RDQS is enabled, RDQS is
output with read data only and is ignored during write data. When RDQS is disabled, ball
B3 becomes data mask (see DM ball). RDQS# is only used when RDQS is enabled and dif-
ferential data strobe mode is enabled.
VDD Supply Power supply: 1.8V ±0.1V.
VDDQ Supply DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity.
VDDL Supply DLL power supply: 1.8V ±0.1V.
VREF Supply SSTL_18 reference voltage (VDDQ/2).
VSS Supply Ground.
VSSDL Supply DLL ground: Isolated on the device from VSS and VSSQ.
VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.
NC – No connect: These balls should be left unconnected.
NF – No function: x8: these balls are used as DQ[7:4]; x4: they are no function.
NU – Not used: If EMR(E10) = 0: x16, A8 = UDQS# and E8 = LDQS#; x8, A2 = RDQS# and A8 =
DQS#; x4, A2 = NU and A8 = NU. If EMR(E10) = 1: x16, A8 = NU and E8 = NU; x8, A2 = NU
and A8 = NU; x4, A2 = NU and A8 = NU.
RFU – Reserved for future use: Bank address BA2, row address bits A13 (x16 only), A14, and
A15.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Packaging

Packaging
Package Dimensions

Figure 8: 84-Ball FBGA (8mm x 12.5mm) – x16; Die Rev. :G

0.8 ±0.05
0.155

Seating
plane
A 1.8 CTR
0.12 A
Nonconductive overmold
84X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-reflow 9 8 7 Ball A1 ID Ball A1 ID
3 2 1
on Ø0.35 SMD
ball pads. A
B
C
D
E
F
G
11.2 CTR H 12.5 ±0.1
J
K
L
M
N
P
0.8 TYP
R

0.8 1.2 MAX

TYP
0.25 MIN
6.4 CTR
8 ±0.1

Note: 1. All dimensions are in millimeters.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Packaging

Figure 9: 60-Ball FBGA (8mm x 10mm) – x4, x8; Die Rev. :G

0.8 ±0.05
0.155

Seating
Plane
A 1.8 CTR
0.12 A Nonconductive overmold

60X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to Ball A1 ID Ball A1 ID
solder balls post-reflow 9 8 7 3 2 1
on Ø0.35 SMD ball
pads. A
B
C
D
E
8 CTR F 10 ±0.1
G
H
J
K
0.8 TYP
L

0.8 TYP 1.2 MAX

6.4 CTR 0.25 MIN

8 ±0.1

Note: 1. All dimensions are in millimeters.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Packaging

Figure 10: 84-Ball FBGA (8mm x 12.5mm) – x16; "NF" Die Rev. :H

0.155

Seating plane

A 0.12 A
1.8 CTR
Nonconductive
overmold

84X Ø0.47
Dimensions apply
to solder balls Ball A1 ID Ball A1 ID
post-reflow on (covered by SR)
Ø0.42 SMD ball pads. 9 8 7 3 2 1
A
B
C
D
E
12.5 ±0.1 F
G
H
11.2 CTR J
K
L
M
N
P
0.8 TYP
R

0.8 TYP 1.1 ±0.1

6.4 CTR 0.28 MIN

8 ±0.1

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

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 512Mb: x4, x8, x16 DDR2 SDRAM
Packaging

Figure 11: 60-Ball FBGA (8mm x 10mm) – x4, x8; "SH" Die Rev. :H

0.155

Seating plane

1.8 CTR A 0.12 A

Nonconductive
overmold

60X Ø0.47
Dimensions
apply to solder Ball A1 ID Ball A1 ID
balls post-reflow (covered by SR)
on Ø0.42 SMD
ball pads. 9 8 7 3 2 1

A
B
C
10 ±0.1 D
8 CTR E
F
G
H
J
K
0.8 TYP L

0.8 TYP 1.1 ±0.1

6.4 CTR 0.28 MIN

8 ±0.1

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

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 512Mb: x4, x8, x16 DDR2 SDRAM
Packaging

FBGA Package Capacitance

Table 4: Input Capacitance

Parameter Symbol Min Max Units Notes

Input capacitance: CK, CK# CCK 1.0 2.0 pF 1
Delta input capacitance: CK, CK# CDCK – 0.25 pF 2, 3
Input capacitance: Address balls, bank address CI 1.0 2.0 pF 1, 4
balls, CS#, RAS#, CAS#, WE#, CKE, ODT
Delta input capacitance: Address balls, bank ad- CDI – 0.25 pF 2, 3
dress balls, CS#, RAS#, CAS#, WE#, CKE, ODT
Input/output capacitance: DQ, DQS, DM, NF CIO 2.5 4.0 pF 1, 5
Delta input/output capacitance: DQ, DQS, DM, NF CDIO – 0.5 pF 2, 3

Notes: 1. This parameter is sampled. VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V, VREF = VSS, f = 100 MHz,
TC = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.1V. DM input is grouped with I/O
balls, reflecting the fact that they are matched in loading.
2. The capacitance per ball group will not differ by more than this maximum amount for
any given device.
3. ˂C are not pass/fail parameters; they are targets.
4. Reduce MAX limit by 0.25pF for -25 and -25E speed devices.
5. Reduce MAX limit by 0.5pF for -3, -3E, -5E, -25, -25E, and -37E speed devices.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – Absolute Ratings

Electrical Specifications – Absolute Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions oustide those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

Table 5: Absolute Maximum DC Ratings

Parameter Symbol Min Max Units Notes

VDD supply voltage relative to VSS VDD –1.0 2.3 V 1
VDDQ supply voltage relative to VSSQ VDDQ –0.5 2.3 V 1, 2
VDDL supply voltage relative to VSSL VDDL –0.5 2.3 V 1
Voltage on any ball relative to VSS VIN, VOUT –0.5 2.3 V 3
Input leakage current; any input 0V ื VIN ื VDD; II –5 5 μA
all other balls not under test = 0V
Output leakage current; 0V ื VOUT ื VDDQ; DQ IOZ –5 5 μA
and ODT disabled
VREF leakage current; VREF = valid VREF level IVREF –2 2 μA

Notes: 1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times; this is not re-
quired when power is ramping down.
2. VREF ื 0.6 x VDDQ; however, VREF may be ุ VDDQ provided that VREF ื 300mV.
3. Voltage on any I/O may not exceed voltage on VDDQ.

Temperature and Thermal Impedance

It is imperative that the DDR2 SDRAM device’s temperature specifications, shown in
Table 6 (page 24), be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in main-
taining the proper junction temperature is using the device’s thermal impedances cor-
rectly. The thermal impedances are listed in Table 7 (page 24) for the applicable and
available die revision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications,” prior to using the thermal impedan-
ces listed in Table 7. For designs that are expected to last several years and require the
flexibility to use several DRAM die shrinks, consider using final target theta values (rath-
er than existing values) to account for increased thermal impedances from the die size
reduction.
The DDR2 SDRAM device’s safe junction temperature range can be maintained when
the T C specification is not exceeded. In applications where the device’s ambient tem-
perature is too high, use of forced air and/or heat sinks may be required in order to sat-
isfy the case temperature specifications.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – Absolute Ratings

Table 6: Temperature Limits

Parameter Symbol Min Max Units Notes

Storage temperature TSTG –55 150 °C 1
Operating temperature: commercial TC 0 85 °C 2, 3
Operating temperature: industrial TC –40 95 °C 2, 3 , 4
TA –40 85 °C 4, 5
Operating temperature: automotive TC –40 105 °C 2, 3, 4
TA –40 105 °C 4, 5

Notes: 1. MAX storage case temperature TSTG is measured in the center of the package, as shown
in Figure 12. This case temperature limit is allowed to be exceeded briefly during pack-
age reflow, as noted in Micron technical note TN-00-15, “Recommended Soldering Pa-
rameters.”
2. MAX operating case temperature TC is measured in the center of the package, as shown
in Figure 12.
3. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
4. Both temperature specifications must be satisfied.
5. Operating ambient temperature surrounding the package.

Figure 12: Example Temperature Test Point Location

Test point

Length (L)

0.5 (L)

0.5 (W)
Width (W)

Lmm x Wmm FBGA

Table 7: Thermal Impedance

ˆ JA (°C/W) ˆ JA (°C/W) ˆ JA (°C/W)

Die Revision Package Substrate Airflow = 0m/s Airflow = 1m/s Airflow = 2m/s ˆ JB (°C/W) ˆ JC (°C/W)
G1 60-ball 2-layer 94.2 76.5 70.1 57.3 6.1
4-layer 76.4 66.9 63.1 56.5
84-ball 2-layer 88.8 71.3 65.6 52.5 6.0
4-layer 71.4 62.1 58.7 52.0

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 512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – Absolute Ratings

Table 7: Thermal Impedance (Continued)

ˆ JA (°C/W) ˆ JA (°C/W) ˆ JA (°C/W)

Die Revision Package Substrate Airflow = 0m/s Airflow = 1m/s Airflow = 2m/s ˆ JB (°C/W) ˆ JC (°C/W)
H1 60-ball Low Conductivity 85.4 70.6 64.5
42.8 11.7
High Conductivity 63.2 56.1 52.8
84-ball Low Conductivity 80.8 67.0 61.6
44.7 11.7
High Conductivity 59.7 53.3 50.7

Note: 1. Thermal resistance data is based on a number of samples from multiple lots and should
be viewed as a typical number.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters

Electrical Specifications – IDD Parameters

IDD Specifications and Conditions

Table 8: General IDD Parameters

IDD Parameters -187E -25E -25 -3E -3 -37E Units

CL (IDD) 7 5 6 4 5 4 tCK

tRCD (IDD) 13.125 12.5 15 12 15 15 ns

tRC (IDD) 58.125 57.5 60 57 60 60 ns
tRRD (IDD) - x4/x8 (1KB) 7.5 7.5 7.5 7.5 7.5 7.5 ns
tRRD (IDD) - x16 (2KB) 10 10 10 10 10 10 ns
tCK (IDD) 1.875 2.5 2.5 3 3 3.75 ns
tRAS MIN (IDD) 45 45 45 45 45 45 ns
tRAS MAX (IDD) 70,000 70,000 70,000 70,000 70,000 70,000 ns
tRP (IDD) 13.125 12.5 15 12 15 15 ns
tRFC (IDD - 256Mb) 75 75 75 75 75 75 ns
tRFC (IDD - 512Mb) 105 105 105 105 105 105 ns
tRFC (IDD - 1Gb) 127.5 127.5 127.5 127.5 127.5 127.5 ns
tRFC (IDD - 2Gb) 197.5 197.5 197.5 197.5 197.5 197.5 ns
tFAW (IDD) - x4/x8 (1KB) Defined by pattern in Table 9 (page 26) ns
tFAW (IDD) - x16 (2KB) Defined by pattern in Table 9 (page 26) ns

IDD7 Conditions
The detailed timings are shown below for IDD7. Where general I DD parameters in the
General Parameters Table conflict with pattern requirements in the I DD7 Timing Pat-
terns Table, then the I DD7 timing patterns requirements take precedence.

Table 9: IDD7 Timing Patterns (4-Bank Interleave READ Operation)

Speed Grade IDD7 Timing Patterns

Timing patterns for 4-bank x4/x8/x16 devices
-5E A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
-37E A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-3 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
-3E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
-25 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
-25E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
-187E A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D

Notes: 1. A = active; RA = read auto precharge; D = deselect.

2. All banks are being interleaved at tRC (IDD) without violating tRRD (IDD) using a BL = 4.
3. Control and address bus inputs are stable during DESELECTs.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters

Table 10: DDR2 IDD Specifications and Conditions (Die Revision G)

Notes: 1–7 apply to the entire table
Parameter/Condition Symbol Configuration -187E -25E -3 -37E Units
Operating one bank active-precharge IDD0 x4, x8 75 65 60 55 mA
current: tCK = tCK (IDD), tRC = tRC (IDD), x16 90 80 75 70
tRAS = tRAS MIN (I ); CKE is HIGH, CS# is
DD
HIGH between valid commands; address bus
inputs are switching; Data bus inputs are
switching
Operating one bank active-read-pre- IDD1 x4, x8 85 75 70 65 mA
charge current: IOUT = 0mA; BL = 4, CL = CL x16 100 95 90 85
(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (I ), tRCD = tRCD (I );
DD DD
CKE is HIGH, CS# is HIGH between valid
commands; address bus inputs are switch-
ing; Data pattern is same as IDD4W
Precharge power-down current: All IDD2P x4, x8, x16 7 7 7 7 mA
banks idle; tCK = tCK (IDD); CKE is LOW; Oth-
er control and address bus inputs are stable;
Data bus inputs are floating
Precharge quiet standby current: All IDD2Q x4, x8 28 24 22 20 mA
banks idle; tCK = tCK (IDD); CKE is HIGH, CS# x16 30 26 24 22
is HIGH; Other control and address bus in-
puts are stable; Data bus inputs are floating
Precharge standby current: All banks IDD2N x4, x8 34 28 25 23 mA
idle; tCK = tCK (IDD); CKE is HIGH, CS# is x16 36 30 27 25
HIGH; Other control and address bus inputs
are switching; Data bus inputs are switching
Active power-down current: All banks IDD3Pf Fast PDN exit 23 18 15 14 mA
open; tCK = tCK (IDD); CKE is LOW; Other MR12 = 0
control and address bus inputs are stable; IDD3Ps Slow PDN exit 9 9 9 9
Data bus inputs are floating MR12 = 1
Active standby current: All banks open; IDD3N x4, x8 40 33 30 27 mA
tCK = tCK (I ), tRAS = tRAS MAX (I ), tRP =
DD DD x16 42 35 32 29
tRP (I ); CKE is HIGH, CS# is HIGH between
DD
valid commands; Other control and address
bus inputs are switching; Data bus inputs
are switching
Operating burst write current: All banks IDD4W x4, x8 145 125 115 99 mA
open, continuous burst writes; BL = 4, CL = x16 185 160 135 120
CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS#
is HIGH between valid commands; address
bus inputs are switching; Data bus inputs
are switching

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 512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters

Table 10: DDR2 IDD Specifications and Conditions (Die Revision G) (Continued)
Notes: 1–7 apply to the entire table
Parameter/Condition Symbol Configuration -187E -25E -3 -37E Units
Operating burst read current: All banks IDD4R x4, x8 140 120 110 95 mA
open, continuous burst reads, IOUT = 0mA; x16 180 150 125 110
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (I ), tRP = tRP (I ); CKE is
DD DD
HIGH, CS# is HIGH between valid com-
mands; address bus inputs are switching;
Data bus inputs are switching
Burst refresh current: tCK = tCK (IDD); re- IDD5 x4, x8 105 95 90 90 mA
fresh command at every tRFC (IDD) interval; x16 110 100 90 90
CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus
inputs are switching; Data bus inputs are
switching
Self refresh current: CK and CK# at 0V; IDD6 x4, x8, x16 7 7 7 7 mA
CKE ื 0.2V; Other control and address bus IDD6L 3 3 3 3
inputs are floating; Data bus inputs are
floating
Operating bank interleave read cur- IDD7 x4, x8 160 150 140 135 mA
rent: All bank interleaving reads, IOUT = x16 225 215 200 195
0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) -
1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD),
tRRD = tRRD (I ), tRCD = tRCD (I ); CKE is
DD DD
HIGH, CS# is HIGH between valid com-
mands; address bus inputs are stable during
deselects; Data bus inputs are switching;
See IDD7 Conditions (page 26) for details

Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C ื TC ื +85°C.
2. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
UDQS#. IDD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for IDD conditions:

LOW VIN ื VIL(AC)max

HIGH VIN ุ VIH(AC)min
Stable Inputs stable at a HIGH or LOW level
Floating Inputs at VREF = VDDQ/2
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Switching Inputs changing between HIGH and LOW every other data transfer (once
per clock) for DQ signals, not including masks or strobes
6. IDD1, IDD4R, and IDD7 require A12 in EMR1 to be enabled during testing.
7. The following IDD values must be derated (IDD limits increase) on IT- or AT-option devices
when operated outside of the range 0°C ื TC ื 85°C:

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 512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters

When IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD4W must be derat-
TC ื 0°C ed by 2%; and IDD6 and IDD7 must be derated by 7%
When IDD0 , IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5 must be derat-
TC ุ 85°C ed by 2%; IDD2P must be derated by 20%; IDD3P slow must be derated by
30%; and IDD6 must be derated by 80% (IDD6 will increase by this amount if
TC < 85°C and the 2X refresh option is still enabled)

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512MbDDR2.pdf - Rev. Z 09/18 EN 29 ‹ 2004 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters

Table 11: DDR2 IDD Specifications and Conditions (Die Revision H)

Notes: 1–7 apply to the entire table
Parameter/Condition Symbol Configuration -187E -25E -3 Units
Operating one bank active-precharge cur- IDD0 x4, x8 75 65 60 mA
rent: tCK = tCK (IDD), tRC = tRC (IDD), x16 90 80 75
tRAS = tRAS MIN (I ); CKE is HIGH, CS# is HIGH
DD
between valid commands; address bus inputs
are switching; Data bus inputs are switching
Operating one bank active-read-precharge IDD1 x4, x8 85 75 70 mA
current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = x16 100 95 90
0; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (I ), tRCD = tRCD (I ); CKE is
DD DD
HIGH, CS# is HIGH between valid commands;
address bus inputs are switching; Data pattern
is same as IDD4W
Precharge power-down current: All banks IDD2P x4, x8, x16 10 10 10 mA
idle; tCK = tCK (IDD); CKE is LOW; Other control
and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All banks IDD2Q x4, x8 28 24 22 mA
idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; x16 30 26 24
Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All banks idle; IDD2N x4, x8 34 28 25 mA
tCK = tCK (I ); CKE is HIGH, CS# is HIGH; Other
DD x16 36 30 27
control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current: All banks open; IDD3Pf Fast PDN exit 22 20 18 mA
tCK = tCK (I ); CKE is LOW; Other control and MR12 = 0
DD
address bus inputs are stable; Data bus inputs IDD3Ps Slow PDN exit 15 15 15
are floating MR12 = 1
Active standby current: All banks open; tCK IDD3N x4, x8 40 33 30 mA
= tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP x16 42 35 32
(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus in-
puts are switching; Data bus inputs are switch-
ing
Operating burst write current: All banks IDD4W x4, x8 145 125 115 mA
open, continuous burst writes; BL = 4, CL = CL x16 185 160 135
(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH
between valid commands; address bus inputs
are switching; Data bus inputs are switching

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512MbDDR2.pdf - Rev. Z 09/18 EN 30 ‹ 2004 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters

Table 11: DDR2 IDD Specifications and Conditions (Die Revision H) (Continued)
Notes: 1–7 apply to the entire table
Parameter/Condition Symbol Configuration -187E -25E -3 Units
Operating burst read current: All banks IDD4R x4, x8 140 120 110 mA
open, continuous burst reads, IOUT = 0mA; BL = x16 180 150 125
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (I ), tRP = tRP (I ); CKE is
DD DD
HIGH, CS# is HIGH between valid commands;
address bus inputs are switching; Data bus in-
puts are switching
Burst refresh current: tCK = tCK (IDD); refresh IDD5 x4, x8 105 95 90 mA
command at every tRFC (IDD) interval; CKE is x16 110 100 90
HIGH, CS# is HIGH between valid commands;
Other control and address bus inputs are
switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ื IDD6 x4, x8, x16 7 7 7 mA
0.2V; Other control and address bus inputs are
floating; Data bus inputs are floating
Operating bank interleave read current: All IDD7 x4, x8 160 150 140 mA
bank interleaving reads, IOUT = 0mA; BL = 4, CL x16 225 215 200
= CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK =
tCK (I ), tRC = tRC (I ), tRRD = tRRD (I ), tRCD
DD DD DD
= tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; address bus inputs are stable
during deselects; Data bus inputs are switching;
See IDD7 Conditions (page 26) for details

Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C ื TC ื +85°C.
2. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
UDQS#. IDD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for IDD conditions:

LOW VIN ื VIL(AC)max

HIGH VIN ุ VIH(AC)min
Stable Inputs stable at a HIGH or LOW level
Floating Inputs at VREF = VDDQ/2
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Switching Inputs changing between HIGH and LOW every other data transfer (once
per clock) for DQ signals, not including masks or strobes
6. IDD1, IDD4R, and IDD7 require A12 in EMR1 to be enabled during testing.
7. The following IDD values must be derated (IDD limits increase) on IT- or AT-option devices
when operated outside of the range 0°C ื TC ื 85°C:

When IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD4W must be derat-
TC ื 0°C ed by 2%; and IDD6 and IDD7 must be derated by 7%

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512MbDDR2.pdf - Rev. Z 09/18 EN 31 ‹ 2004 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters

When IDD0 , IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5 must be derat-
TC ุ 85°C ed by 2%; IDD2P must be derated by 20%; IDD3P slow must be derated by
30%; and IDD6 must be derated by 80% (IDD6 will increase by this amount if
TC < 85°C and the 2X refresh option is still enabled)

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512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657
AC Timing Operating Specifications

Table 12: AC Operating Specifications and Conditions

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes
Clock CL = 7 tCK (avg) 1.875 8.0 – – – – – – – – – – – – ns 6, 7, 8,
cycle time CL = 6 tCK (avg) 2.5 8.0 2.5 8.0 2.5 8.0 – – – – – – – – 9
CL = 5 tCK (avg) 2.5 8.0 2.5 8.0 3.0 8.0 3.0 8.0 3.0 8.0 – – – –
CL = 4 tCK (avg) 3.75 8.0 3.75 8.0 3.75 8.0 3.0 8.0 3.75 8.0 3.75 8.0 5.0 8.0
CL = 3 tCK (avg) 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0
CK high-level tCH (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK 10
width
Clock

CK low-level width tCL (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK

Half clock period tHP MIN = lesser oftCHand tCL ps 11

MAX = n/a
Absolute tCK tCK (abs) MIN = tCK (AVG) MIN + tJITper (MIN) ps
33

MAX = tCK (AVG) MAX + tJITper (MAX)

Absolute CK tCH (abs) MIN = tCK (AVG) MIN × tCH (AVG) MIN + tJITdty (MIN) ps
high-level width MAX = tCK (AVG) MAX × tCH (AVG) MAX + tJITdty (MAX)

AC Timing Operating Specifications

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Absolute CK tCL (abs) MIN = tCK (AVG) MIN × tCL (AVG) MIN + tJITdty (MIN) ps
low-level width MAX = tCK (AVG) MAX × tCL (AVG) MAX + tJITdty (MAX)

512Mb: x4, x8, x16 DDR2 SDRAM

‹ 2004 Micron Technology, Inc. All rights reserved.
512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes
Period jitter tJITper –90 90 –100 100 –100 100 –125 125 –125 125 –125 125 –125 125 ps 12
Half period tJITdty –75 75 –100 100 –100 100 –125 125 –125 125 –125 125 –150 150 ps 13
Cycle to cycle tJITcc 180 200 200 250 250 250 250 ps 14
Cumulative error, tERR –132 132 –150 150 –150 150 –175 175 –175 175 –175 175 –175 175 ps 15
2per
2 cycles
Cumulative error, tERR –157 157 –175 175 –175 175 –225 225 –225 225 –225 225 –225 225 ps 15
Clock Jitter

3per
3 cycles
Cumulative error, tERR –175 175 –200 200 –200 200 –250 250 –250 250 –250 250 –250 250 ps 15
4per
4 cycles
Cumulative error, tERR –188 188 –200 200 –200 200 –250 250 –250 250 –250 250 –250 250 ps 15, 16
5per
5 cycles
Cumulative error, tERR –250 250 –300 300 –300 300 –350 350 –350 350 –350 350 –350 350 ps 15, 16
6–
6–10 cycles 10per
34

Cumulative error, tERR –425 425 –450 450 –450 450 –450 450 –450 450 –450 450 –450 450 ps 15
11–
11–50 cycles 50per
DQS output access tDQSCK –300 300 –350 350 –350 350 –400 400 –400 400 –450 450 –500 500 ps 19

AC Timing Operating Specifications

Micron Technology, Inc. reserves the right to change products or specifications without notice.

time from CK/CK#

Data Strobe-Out

DQS read pream- tRPRE MIN = 0.9 × tCK tCK 17, 18,

512Mb: x4, x8, x16 DDR2 SDRAM

ble MAX = 1.1 × tCK 19
DQS read tRPST MIN = 0.4 × tCK tCK 17, 18,
postamble MAX = 0.6 × tCK 19, 20
CK/CK# to DQS tLZ MIN = tAC (MIN) ps 19, 21,
1
Low-Z MAX = tAC (MAX) 22
‹ 2004 Micron Technology, Inc. All rights reserved.
512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes
DQS rising edge to tDQSS MIN = –0.25 × tCK tCK 18
CK rising edge MAX = 0.25 × tCK
DQS input-high tDQSH MIN = 0.35 × tCK tCK 18
pulse width MAX = n/a
DQS input-low tDQSL MIN = 0.35 × tCK tCK 18
pulse width MAX = n/a
DQS falling to CK tDSS MIN = 0.2 × tCK tCK 18
rising: setup time MAX = n/a
Data Strobe-In

DQS falling from tDSH MIN = 0.2 × tCK tCK 18

CK rising: MAX = n/a
hold time
Write preamble tWPRES MIN = 0 ps 23, 24
setup time MAX = n/a
35

DQS write tWPRE MIN = 0.35 × tCK tCK 18

preamble MAX = n/a
DQS write tWPST MIN = 0.4 × tCK tCK 18, 25
postamble MAX = 0.6 × tCK

AC Timing Operating Specifications

Micron Technology, Inc. reserves the right to change products or specifications without notice.

WRITE command – MIN = WL - tDQSS tCK

512Mb: x4, x8, x16 DDR2 SDRAM

to first DQS MAX = WL + tDQSS
transition
‹ 2004 Micron Technology, Inc. All rights reserved.
512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes
DQ output access tAC –350 350 –400 400 –400 400 –450 450 –450 450 –500 500 –600 600 ps 19
time from CK/CK#
DQS–DQ skew, tDQSQ – 175 – 200 – 200 – 240 – 240 – 300 – 350 ps 26, 27
DQS to last DQ
valid, per group,
per access
DQ hold from next tQHS – 250 – 300 – 300 – 340 – 340 – 400 – 450 ps 28
Data-Out

DQS strobe
DQ–DQS hold, DQS tQH MIN = tHP - tQHS ps 26, 27,
to first DQ not val- MAX = n/a 28
id
CK/CK# to DQ, DQS tHZ MIN = n/a ps 19, 21,
High-Z MAX = tAC (MAX) 29
tLZ MIN = 2 × tAC (MIN)
36

CK/CK# to DQ 2 ps 19, 21,

Low-Z MAX = tAC (MAX) 22
Data valid output DVW MIN = tQH - tDQSQ ns 26, 27
window MAX = n/a

AC Timing Operating Specifications

Micron Technology, Inc. reserves the right to change products or specifications without notice.

DQ and DM input tDSb 0 – 50 – 50 – 100 – 100 – 100 – 150 – ps 26, 30,

512Mb: x4, x8, x16 DDR2 SDRAM

setup time to DQS 31
DQ and DM input tDHb 75 – 125 – 125 – 175 – 175 – 225 – 275 – ps 26, 30,
hold time to DQS 31
Data-In

DQ and DM input tDSa 200 – 250 – 250 – 300 – 300 – 350 – 400 – ps 26, 30,
setup time to DQS 31
DQ and DM input tDHa 200 – 250 – 250 – 300 – 300 – 350 – 400 – ps 26, 30,
hold time to DQS 31
‹ 2004 Micron Technology, Inc. All rights reserved.

DQ and DM input tDIPW MIN = 0.35 × tCK tCK 18, 32

pulse width MAX = n/a
512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes
Input setup time tISb 125 – 175 – 175 – 200 – 200 – 250 – 350 – ps 31, 33
Input hold time tIHb 200 – 250 – 250 – 275 – 275 – 375 – 475 – ps 31, 33
Input setup time tISa 325 – 375 – 375 – 400 – 400 – 500 – 600 – ps 31, 33
Input hold time tIHa 325 – 375 – 375 – 400 – 400 – 500 – 600 – ps 31, 33
Input pulse width tIPW 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – tCK 18, 32
ACTIVATE-to- tRC 54 – 55 – 55 – 54 – 55 – 55 – 55 – ns 18, 34,
ACTIVATE delay, 51
same bank
ACTIVATE-to-READ tRCD 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18
Command and Address

or WRITE delay
ACTIVATE-to- tRAS 40 70K 40 70K 40 70K 40 70K 40 70K 40 70K 40 70K ns 18, 34,
PRECHARGE delay 35
PRECHARGE period tRP 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18, 36
37

PRE- <1Gb tRPA 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18, 36

CHARGE ุ1Gb tRPA 15 – 15 – 17.5 15 18 18.75 20 ns 18, 36
ALL period

AC Timing Operating Specifications

Micron Technology, Inc. reserves the right to change products or specifications without notice.

ACTIVATE x4, x8 tRRD 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – ns 18, 37
-to-

512Mb: x4, x8, x16 DDR2 SDRAM

x16 tRRD 10 – 10 – 10 – 10 – 10 – 10 – 10 – ns 18, 37
ACTIVATE
delay
different
bank
4-bank x4, x8 tFAW 35 – 35 – 35 – 37.5 – 37.5 – 37.5 – 37.5 – ns 18, 38
activate x16 tFAW 45 – 45 – 45 – 50 – 50 – 50 – 50 – ns 18, 38
‹ 2004 Micron Technology, Inc. All rights reserved.

period
(ุ1Gb)
512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes
Internal READ-to- tRTP 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – ns 18, 37,
PRECHARGE delay 39
Command and Address

CAS#-to-CAS# tCCD 2 – 2 – 2 – 2 – 2 – 2 – 2 – tCK 18

delay
Write recovery tWR 15 – 15 – 15 – 15 – 15 – 15 – 15 – ns 18, 37
time
Write AP recovery tDAL tWR + – tWR + – tWR + – tWR + – tWR + – tWR + – tWR + – ns 40
+ precharge time tRP tRP tRP tRP tRP tRP tRP

Internal WRITE-to- tWTR 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 10 – ns 18, 37
READ delay
LOAD MODE cycle tMRD 2 – 2 – 2 – 2 – 2 – 2 – 2 – tCK 18
time
REFRESH- 256Mb tRFC 75 – 75 – 75 – 75 – 75 – 75 – 75 – ns 18, 41
38

to- 512Mb 105 – 105 – 105 – 105 – 105 – 105 – 105 –

ACTIVATE
1Gb 127.5 – 127.5 – 127.5 – 127.5 – 127.5 – 127.5 – 127.5 –
or to
-REFRESH 2Gb 195 – 195 – 195 – 195 – 195 – 195 – 195 –

AC Timing Operating Specifications

Micron Technology, Inc. reserves the right to change products or specifications without notice.

interval

512Mb: x4, x8, x16 DDR2 SDRAM

Average periodic tREFI – 7.8 – 7.8 – 7.8 – 7.8 – 7.8 – 7.8 – 7.8 μs 18, 41
refresh
Refresh

(commercial)
Average periodic tREFI – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 μs 18, 41
IT
refresh
(industrial)
Average periodic tREFI – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 μs 18, 41
AT
‹ 2004 Micron Technology, Inc. All rights reserved.

refresh
(automotive)
CKE LOW to CK, tDELAY MIN limit = tIS + tCK + tIH ns 42
CK# uncertainty MAX limit = n/a
512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes
Exit SELF REFRESH tXSNR MIN limit = tRFC (MIN) + 10 ns
to nonREAD MAX limit = n/a
Self Refresh

command
Exit SELF REFRESH tXSRD MIN limit = 200 tCK 18
to READ command MAX limit = n/a
Exit SELF REFRESH tISXR MIN limit = tIS ps 33, 43
timing reference MAX limit = n/a
Exit active MR12 tXARD 3 – 2 – 2 – 2 – 2 – 2 – 2 – tCK 18
power- =0
down to MR12 10 - – 8 - AL – 8 - AL – 7 - AL – 7 - AL – 6 - AL – 6 - AL – tCK 18
READ =1 AL
command
Power-Down

Exit precharge tXP 3 – 2 – 2 – 2 – 2 – 2 – 2 – tCK 18

power-down and
39

active power-down
to any
nonREAD

AC Timing Operating Specifications

Micron Technology, Inc. reserves the right to change products or specifications without notice.

command
CKE MIN tCKE MIN = 3 tCK 18, 44

512Mb: x4, x8, x16 DDR2 SDRAM

HIGH/LOW time MAX = n/a
‹ 2004 Micron Technology, Inc. All rights reserved.
512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes
ODT to power- tANPD 4 – 3 – 3 – 3 – 3 – 3 – 3 – tCK 18
down entry latency
ODT power-down tAXPD 11 – 8 – 8 – 8 – 8 – 8 – 8 – tCK 18
exit latency
ODT turn-on delay tAOND 2 tCK 18
ODT turn-off delay tAOFD 2.5 tCK 18, 45
ODT turn-on tAON tAC tAC MIN = tAC
(MIN) MIN = tAC
(MIN) MIN = tAC
(MIN) ps 19, 46
(MIN) (MAX) MAX = tAC (MAX) + 600 MAX = tAC (MAX) + 700 MAX = tAC (MAX) + 1000
+
2575
ODT turn-off tAOF MIN = tAC (MIN) ps 47, 48
ODT

MAX = tAC (MAX) + 600

ODT turn-on tAONPD tAC 2× MIN = tAC (MIN) + 2000 ps 49
40

(power-down (MIN) tCK+ MAX = 2 × tCK + tAC (MAX) + 1000

mode) + 2000 tAC
(MAX)
+

AC Timing Operating Specifications

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1000

512Mb: x4, x8, x16 DDR2 SDRAM

ODT turn-off tAOFPD MIN = tAC (MIN) + 2000 ps
(power-down MAX = 2.5 × tCK + tAC (MAX) + 1000
mode)
ODT enable from tMOD MIN = 12 ns 18, 50
MRS command MAX = n/a
‹ 2004 Micron Technology, Inc. All rights reserved.
512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657
Notes: 1. All voltages are referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply
voltage levels, but the related specifications and the operation of the device are warranted for the full voltage
range specified. ODT is disabled for all measurements that are not ODT-specific.
3. Outputs measured with equivalent load (see Figure 16 (page 51)).
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.0V in the test environment, and parameter specifica-
tions are guaranteed for the specified AC input levels under normal use conditions. The slew rate for the input
signals used to test the device is 1.0 V/ns for signals in the range between VIL(AC) and VIH(AC). Slew rates other than
1.0 V/ns may require the timing parameters to be derated as specified.
5. The AC and DC input level specifications are as defined in the SSTL_18 standard (that is, the receiver will effective-
ly switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal
does not ring back above [below] the DC input LOW [HIGH] level).
6. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).
7. Operating frequency is only allowed to change during self refresh mode (see Figure 79 (page 126)), precharge
power-down mode, or system reset condition (see Reset (page 127)). SSC allows for small deviations in operating
frequency, provided the SSC guidelines are satisfied.
8. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG) MIN is the smallest clock
rate allowed (except for a deviation due to allowed clock jitter). Input clock jitter is allowed provided it does not
exceed values specified. Also, the jitter must be of a random Gaussian distribution in nature.
9. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate
spread spectrum at a sweep rate in the range 8–60 kHz with an additional one percent tCK (AVG); however, the
spread spectrum may not use a clock rate below tCK (AVG) MIN or above tCK (AVG) MAX.
41

10. MIN (tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time driven to the
device. The clock’s half period must also be of a Gaussian distribution; tCH (AVG) and tCL (AVG) must be met with
or without clock jitter and with or without duty cycle jitter. tCH (AVG) and tCL (AVG) are the average of any 200
consecutive CK falling edges. tCH limits may be exceeded if the duty cycle jitter is small enough that the absolute

AC Timing Operating Specifications

Micron Technology, Inc. reserves the right to change products or specifications without notice.

half period limits (tCH [ABS], tCL [ABS]) are not violated.

512Mb: x4, x8, x16 DDR2 SDRAM

11. tHP (MIN) is the lesser of tCL and tCH actually applied to the device CK and CK# inputs; thus, tHP (MIN) ุ the lesser
of tCL (ABS) MIN and tCH (ABS) MIN.
12. The period jitter (tJITper) is the maximum deviation in the clock period from the average or nominal clock allowed
in either the positive or negative direction. JEDEC specifies tighter jitter numbers during DLL locking time. During
DLL lock time, the jitter values should be 20 percent less those than noted in the table (DLL locked).
13. The half-period jitter (tJITdty) applies to either the high pulse of clock or the low pulse of clock; however, the two
cumulatively can not exceed tJITper.
14. The cycle-to-cycle jitter (tJITcc) is the amount the clock period can deviate from one cycle to the next. JEDEC speci-
‹ 2004 Micron Technology, Inc. All rights reserved.

fies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter values should be 20 percent
less than those noted in the table (DLL locked).
15. The cumulative jitter error (tERRnper), where n is 2, 3, 4, 5, 6–10, or 11–50 is the amount of clock time allowed to
consecutively accumulate away from the average clock over any number of clock cycles.
16. JEDEC specifies using tERR6–10per when derating clock-related output timing (see notes 19 and 48). Micron requires
less derating by allowing tERR5per to be used.
17. This parameter is not referenced to a specific voltage level but is specified when the device output is no longer
driving (tRPST) or beginning to drive (tRPRE).
512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657
18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock that latches it in. Howev-
er, the input timing (in ns) references to the tCK (AVG) when determining the required number of clocks. The fol-
lowing input parameters are determined by taking the specified percentage times the tCK (AVG) rather than tCK:
tIPW, tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST, and tWPRE.

19. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by
the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. The
following parameters are required to be derated by subtracting tERR5per (MAX): tAC (MIN), tDQSCK (MIN), tLZDQS
(MIN), tLZDQ (MIN), tAON (MIN); while the following parameters are required to be derated by subtracting
tERR t t t t t t
5per (MIN): AC (MAX), DQSCK (MAX), HZ (MAX), LZDQS (MAX), LZDQ (MAX), AON (MAX). The parameter
tRPRE (MIN) is derated by subtracting tJITper (MAX), while tRPRE (MAX), is derated by subtracting tJITper (MIN).

The parameter tRPST (MIN) is derated by subtracting tJITdty (MAX), while tRPST (MAX), is derated by subtracting
tJITdty (MIN). Output timings that require tERR
5per derating can be observed to have offsets relative to the clock;
however, the total window will not degrade.
20. When DQS is used single-ended, the minimum limit is reduced by 100ps.
21. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (tHZ) or begins driv-
ing (tLZ).
22. LZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition.
t

23. This is not a device limit. The device will operate with a negative value, but system performance could be degra-
ded due to bus turnaround.
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS go-
ing from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous
WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS.
42

25. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-driven signal should either
be HIGH, LOW, or High-Z, and that any signal transition within the input switching region must follow valid input
requirements. That is, if DQS transitions HIGH (above VIH[DC]min), then it must not transition LOW (below VIH[DC])

AC Timing Operating Specifications

prior to tDQSH (MIN).
Micron Technology, Inc. reserves the right to change products or specifications without notice.

26. Referenced to each output group: x4 = DQS with DQ[3:0]; x8 = DQS with DQ[7:0]; x16 = LDQS with DQ[7:0]; and

512Mb: x4, x8, x16 DDR2 SDRAM

UDQS with DQ[15:8].
27. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS).
The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can
be derived.
28. tQH = tHP - tQHS; the worst case tQH would be the lesser of tCL (ABS) MAX or tCH (ABS) MAX times tCK (ABS) MIN
- tQHS. Minimizing the amount of tCH (AVG) offset and value of tJITdty will provide a larger tQH, which in turn
will provide a larger valid data out window.
‹ 2004 Micron Technology, Inc. All rights reserved.

29. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST
(MAX) condition.
30. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential slew rate of 2 V/ns (1 V/ns
for each signal). There are two sets of values listed: tDSa, tDHa and tDSb, tDHb. The tDSa, tDHa values (for reference
only) are equivalent to the baseline values of tDSb, tDHb at VREF when the slew rate is 2 V/ns, differentially. The
baseline values, tDSb, tDHb, are the JEDEC-defined values, referenced from the logic trip points. tDSb is referenced
from VIH(AC) for a rising signal and VIL(AC) for a falling signal, while tDHb is referenced from VIL(DC) for a rising sig-
nal and VIH(DC) for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values
must be derated by adding the values from Table 31 (page 64) and Table 32 (page 65). If the DQS differential
strobe feature is not enabled, then the DQS strobe is single-ended and the baseline values must be derated using
512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657
Table 33 (page 66). Single-ended DQS data timing is referenced at DQS crossing VREF. The correct timing values
for a single-ended DQS strobe are listed in Table 34 (page 66)–Table 36 (page 67) on Table 34 (page 66),
Table 35 (page 67), and Table 36 (page 67); listed values are already derated for slew rate variations and con-
verted from baseline values to VREF values.
31. VIL/VIH DDR2 overshoot/undershoot. See AC Overshoot/Undershoot Specification (page 57).
32. For each input signal—not the group collectively.
33. There are two sets of values listed for command/address: tISa, tIHa and tISb, tIHb. The tISa, tIHa values (for reference
only) are equivalent to the baseline values of tISb, tIHb at VREF when the slew rate is 1 V/ns. The baseline values,
tIS , tIH , are the JEDEC-defined values, referenced from the logic trip points. tIS is referenced from V
b b b IH(AC) for a
rising signal and VIL(AC) for a falling signal, while tIHb is referenced from VIL(DC) for a rising signal and VIH(DC) for a
falling signal. If the command/address slew rate is not equal to 1 V/ns, then the baseline values must be derated
by adding the values from Table 29 (page 60) and Table 30 (page 61).
34. This is applicable to READ cycles only. WRITE cycles generally require additional time due to tWR during auto pre-
charge.
35. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is satisfied because tRAS lock-
out feature is supported in DDR2 SDRAM.
36. When a single-bank PRECHARGE command is issued, tRP timing applies. tRPA timing applies when the PRE-
CHARGE (ALL) command is issued, regardless of the number of banks open. For 8-bank devices (ุ1Gb), tRPA (MIN)
= tRP (MIN) + tCK (AVG) (Table 12 (page 33) lists tRP [MIN] + tCK [AVG] MIN).
37. This parameter has a two clock minimum requirement at any tCK.
38. The tFAW (MIN) parameter applies to all 8-bank DDR2 devices. No more than four bank-ACTIVATE commands may
be issued in a given tFAW (MIN) period. tRRD (MIN) restriction still applies.
43

39. The minimum internal READ-to-PRECHARGE time. This is the time from which the last 4-bit prefetch begins to
when the PRECHARGE command can be issued. A 4-bit prefetch is when the READ command internally latches the
READ so that data will output CL later. This parameter is only applicable when tRTP/(2 × tCK) > 1, such as frequen-
cies faster than 533 MHz when tRTP = 7.5ns. If tRTP/(2 × tCK) ื 1, then equation AL + BL/2 applies. tRAS (MIN) has

AC Timing Operating Specifications

Micron Technology, Inc. reserves the right to change products or specifications without notice.

to be satisfied as well. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until tRAS
(MIN) has been satisfied.

512Mb: x4, x8, x16 DDR2 SDRAM

40. tDAL = (nWR) + (tRP/tCK). Each of these terms, if not already an integer, should be rounded up to the next integer.
tCK refers to the application clock period; nWR refers to the tWR parameter stored in the MR9–MR11. For exam-

ple, -37E at tCK = 3.75ns with tWR programmed to four clocks would have tDAL = 4 + (15ns/3.75ns) clocks = 4 + (4)
clocks = 8 clocks.
41. The refresh period is 64ms (commercial) or 32ms (industrial and automotive). This equates to an average refresh
rate of 7.8125μs (commercial) or 3.9607μs (industrial and automotive). To ensure all rows of all banks are properly
refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) or 32ms (industrial and automotive).
‹ 2004 Micron Technology, Inc. All rights reserved.

The JEDEC tRFC MAX of 70,000ns is not required as bursting of AUTO REFRESH commands is allowed.
42. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK# being re-

moved in a system RESET condition (see Reset (page 127)).

43. tISXR is equal to tIS and is used for CKE setup time during self refresh exit, as shown in Figure 69 (page 118).

44. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock edges. CKE must re-

main at the valid input level the entire time it takes to achieve the three clocks of registration. Thus, after any
CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 × tCK + tIH.
 45. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value must be derated by the
512MbDDR2.pdf - Rev. Z 09/18 EN
CCMTD-1725822587-9657

amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53, tAOFD would actually be 2.5 -
0.03, or 2.47, for tAOF (MIN) and 2.5 + 0.03, or 2.53, for tAOF (MAX).
46. ODT turn-on time tAON (MIN) is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-
on time tAON (MAX) is when the ODT resistance is fully on. Both are measured from tAOND.
47. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF (MAX)
is when the bus is in High-Z. Both are measured from tAOFD.
48. Half-clock output parameters must be derated by the actual tERR5per and tJITdty when input clock jitter is present;
this will result in each parameter becoming larger. The parameter tAOF (MIN) is required to be derated by sub-
tracting both tERR5per (MAX) and tJITdty (MAX). The parameter tAOF (MAX) is required to be derated by subtract-
ing both tERR5per (MIN) and tJITdty (MIN).
49. The -187E maximum limit is 2 × tCK + tAC (MAX) + 1000 but it will likely be 3 x tCK + tAC (MAX) + 1000 in the
future.
50. Should use 8 tCK for backward compatibility.
51. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row ad-
dress may result in reduction of the product lifetime.
44

AC Timing Operating Specifications

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

‹ 2004 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR2 SDRAM
AC and DC Operating Conditions

AC and DC Operating Conditions

Table 13: Recommended DC Operating Conditions (SSTL_18)

All voltages referenced to VSS
Parameter Symbol Min Nom Max Units Notes
Supply voltage VDD 1.7 1.8 1.9 V 1, 2
VDDL supply voltage VDDL 1.7 1.8 1.9 V 2, 3
I/O supply voltage VDDQ 1.7 1.8 1.9 V 2, 3
I/O reference voltage VREF(DC) 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 4
I/O termination voltage (system) VTT VREF(DC) - 40 VREF(DC) VREF(DC) + 40 mV 5

Notes: 1. VDD and VDDQ must track each other. VDDQ must be ื VDD.
2. VSSQ = VSSL = VSS.
3. VDDQ tracks with VDD; VDDL tracks with VDD.
4. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the
DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed
±1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent
of VREF(DC). This measurement is to be taken at the nearest VREF bypass capacitor.
5. VTT is not applied directly to the device. VTT is a system supply for signal termination re-
sistors, is expected to be set equal to VREF, and must track variations in the DC level of
VREF.

CCMTD-1725822587-9657 Micron Technology, Inc. reserves the right to change products or specifications without notice.
512MbDDR2.pdf - Rev. Z 09/18 EN 45 ‹ 2004 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR2 SDRAM
ODT DC Electrical Characteristics

ODT DC Electrical Characteristics

Table 14: ODT DC Electrical Characteristics

All voltages are referenced to VSS
Parameter Symbol Min Nom Max Units Notes
RTT effective impedance value for 75˖ setting RTT1(EFF) 60 75 90 ˖ 1, 2
EMR (A6, A2) = 0, 1
RTT effective impedance value for 150˖ setting RTT2(EFF) 120 150 180 ˖ 1, 2
EMR (A6, A2) = 1, 0
RTT effective impedance value for 50˖ setting RTT3(EFF) 40 50 60 ˖ 1, 2
EMR (A6, A2) = 1, 1
Deviation of VM with respect to VDDQ/2 ˂VM –6 – 6 % 3

Notes: 1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL(DC) to the ball
being tested, and then measuring current, I(VIH[AC]), and I(VIL[AC]), respectively.
VIH(AC) - VIL(AC)
RTT(EFF) =
I(VIH(AC)) - I(VIL(AC))

2. Minimum IT and AT device values are derated by six percent less when the devices oper-
ate between –40°C and 0°C (TC ).
3. Measure voltage (VM) at tested ball with no load.
2 × VM
ǻVM = - 1 × 100
VDDQ

CCMTD-1725822587-9657 Micron Technology, Inc. reserves the right to change products or specifications without notice.
512MbDDR2.pdf - Rev. Z 09/18 EN 46 ‹ 2004 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR2 SDRAM
Input Electrical Characteristics and Operating Conditions

Input Electrical Characteristics and Operating Conditions

Table 15: Input DC Logic Levels

All voltages are referenced to VSS
Parameter Symbol Min Max Units
Input high (logic 1) voltage VIH(DC) VREF(DC) + 125 VDDQ 1 mV
Input low (logic 0) voltage VIL(DC) –300 VREF(DC) - 125 mV

Note: 1. VDDQ + 300mV allowed provided 1.9V is not exceeded.

Table 16: Input AC Logic Levels

All voltages are referenced to VSS
Parameter Symbol Min Max Units
Input high (logic 1) voltage (-37E/-5E) VIH(AC) VREF(DC) + 250 VDDQ 1 mV
Input high (logic 1) voltage (-187E/-25E/-25/-3E/-3) VIH(AC) VREF(DC) + 200 VDDQ 1 mV
Input low (logic 0) voltage (-37E/-5E) VIL(AC) –300 VREF(DC) - 250 mV
Input low (logic 0) voltage (-187E/-25E/-25/-3E/-3) VIL(AC) –300 VREF(DC) - 200 mV

Note: 1. Refer to AC Overshoot/Undershoot Specification (page 57).

Figure 13: Single-Ended Input Signal Levels

1,150mV VIH(AC)

1,025mV VIH(DC)

936mV
VREF + AC noise
918mV
VREF + DC error
900mV
VREF - DC error
882mV
VREF - AC noise
864mV

775mV VIL(DC)

650mV VIL(AC)

Note: 1. Numbers in diagram reflect nominal DDR2-400/DDR2-533 values.

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512MbDDR2.pdf - Rev. Z 09/18 EN 47 ‹ 2004 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR2 SDRAM
Input Electrical Characteristics and Operating Conditions

Table 17: Differential Input Logic Levels

All voltages referenced to VSS
Parameter Symbol Min Max Units Notes
DC input signal voltage VIN(DC) –300 VDDQ mV 1, 6
DC differential input voltage VID(DC) 250 VDDQ mV 2, 6
AC differential input voltage VID(AC) 500 VDDQ mV 3, 6
AC differential cross-point voltage VIX(AC) 0.50 × VDDQ - 175 0.50 × VDDQ + 175 mV 4
Input midpoint voltage VMP(DC) 850 950 mV 5

Notes: 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK,
CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.
2. VID(DC) specifies the input differential voltage |VTR - VCP| required for switching, where
VTR is the true input (such as CK, DQS, LDQS, UDQS) level and VCP is the complementary
input (such as CK#, DQS#, LDQS#, UDQS#) level. The minimum value is equal to VIH(DC) -
VIL(DC). Differential input signal levels are shown in Figure 14.
3. VID(AC) specifies the input differential voltage |VTR - VCP| required for switching, where
VTR is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and VCP is the comple-
mentary input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#) level. The minimum value is
equal to VIH(AC) - VIL(AC), as shown in Table 16 (page 47).
4. The typical value of VIX(AC) is expected to be about 0.5 × VDDQ of the transmitting device
and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which
differential input signals must cross, as shown in Figure 14.
5. VMP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is
the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#). VMP(DC)
is expected to be approximately 0.5 × VDDQ.
6. VDDQ + 300mV allowed provided 1.9V is not exceeded.

Figure 14: Differential Input Signal Levels

2.1V VIN(DC)max1
VDDQ = 1.8V

CP2

1.075V X

0.9V VMP(DC)3 VIX(AC)4 VID(DC)5

VID(AC)6
0.725V X

TR2

–0.30V VIN(DC)min1

Notes: 1. TR and CP may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
2. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#,
RDQS#, LDQS#, and UDQS# signals.
3. This provides a minimum of 850mV to a maximum of 950mV and is expected to be
VDDQ/2.
4. TR and CP must cross in this region.
5. TR and CP must meet at least VID(DC)min when static and is centered around VMP(DC).
6. TR and CP must have a minimum 500mV peak-to-peak swing.

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Input Electrical Characteristics and Operating Conditions

7. Numbers in diagram reflect nominal values (VDDQ = 1.8V).

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Output Electrical Characteristics and Operating Conditions

Output Electrical Characteristics and Operating Conditions

Table 18: Differential AC Output Parameters

Parameter Symbol Min Max Units Notes

AC differential cross-point voltage VOX(AC) 0.50 × VDDQ - 125 0.50 × VDDQ + 125 mV 1

Note: 1. The typical value of VOX(AC) is expected to be about 0.5 × VDDQ of the transmitting de-
vice and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at
which differential output signals must cross.

Figure 15: Differential Output Signal Levels

VDDQ

VTR

Vswing Crossing point

VOX

VCP

VSSQ

Table 19: Output DC Current Drive

Parameter Symbol Value Units Notes

Output MIN source DC current IOH –13.4 mA 1, 2, 4
Output MIN sink DC current IOL 13.4 mA 2, 3, 4

Notes: 1. For IOH(DC); VDDQ = 1.7V, VOUT = 1,420mV. (VOUT - VDDQ)/IOH must be less than 21˖ for val-
ues of VOUT between VDDQ and VDDQ - 280mV.
2. For IOL(DC); VDDQ = 1.7V, VOUT = 280mV. VOUT/IOL must be less than 21˖ for values of VOUT
between 0V and 280mV.
3. The DC value of VREF applied to the receiving device is set to VTT.
4. The values of IOH(DC) and IOL(DC) are based on the conditions given in Notes 1 and 2. They
are used to test device drive current capability to ensure VIH,min plus a noise margin and
VIL,max minus a noise margin are delivered to an SSTL_18 receiver. The actual current val-
ues are derived by shifting the desired driver operating point (see output IV curves)
along a 21˖ load line to define a convenient driver current for measurement.

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Output Electrical Characteristics and Operating Conditions

Table 20: Output Characteristics

Parameter Min Nom Max Units Notes

Output impedance See Output Driver Characteristics (page 52) ˖ 1, 2
Pull-up and pull-down mismatch 0 – 4 ˖ 1, 2, 3
Output slew rate 1.5 – 5 V/ns 1, 4, 5, 6

Notes: 1. Absolute specifications: 0°C ื TC ื +85°C; VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V.
2. Impedance measurement conditions for output source DC current: VDDQ = 1.7V; VOUT =
1420mV; (VOUT - VDDQ)/IOH must be less than 23.4˖ for values of VOUT between VDDQ and
VDDQ - 280mV. The impedance measurement condition for output sink DC current: VDDQ
= 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4˖ for values of VOUT between 0V
and 280mV.
3. Mismatch is an absolute value between pull-up and pull-down; both are measured at
the same temperature and voltage.
4. Output slew rate for falling and rising edges is measured between VTT - 250mV and VTT
+ 250mV for single-ended signals. For differential signals (DQS, DQS#), output slew rate
is measured between DQS - DQS# = –500mV and DQS# - DQS = 500mV. Output slew rate
is guaranteed by design but is not necessarily tested on each device.
5. The absolute value of the slew rate as measured from VIL(DC)max to VIH(DC)min is equal to
or greater than the slew rate as measured from VIL(AC)max to VIH(AC)min. This is guaran-
teed by design and characterization.
6. IT and AT devices require an additional 0.4 V/ns in the MAX limit when TC is between –
40°C and 0°C.

Figure 16: Output Slew Rate Load

VTT = VDDQ/2
25ȍ
Output Reference
(VOUT) point

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Output Driver Characteristics

Output Driver Characteristics

Figure 17: Full Strength Pull-Down Characteristics
120

100

80
IOUT (mA)

60

40

20

0
0.0 0.5 1.0 1.5

VOUT (V)

Table 21: Full Strength Pull-Down Current (mA)

Voltage (V) Min Nom Max

0.0 0.00 0.00 0.00
0.1 4.30 5.63 7.95
0.2 8.60 11.30 15.90
0.3 12.90 16.52 23.85
0.4 16.90 22.19 31.80
0.5 20.40 27.59 39.75
0.6 23.28 32.39 47.70
0.7 25.44 36.45 55.55
0.8 26.79 40.38 62.95
0.9 27.67 44.01 69.55
1.0 28.38 47.01 75.35
1.1 28.96 49.63 80.35
1.2 29.46 51.71 84.55
1.3 29.90 53.32 87.95
1.4 30.29 54.9 90.70
1.5 30.65 56.03 93.00
1.6 30.98 57.07 95.05
1.7 31.31 58.16 97.05
1.8 31.64 59.27 99.05
1.9 31.96 60.35 101.05

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Output Driver Characteristics

Figure 18: Full Strength Pull-Up Characteristics

0

–20

–40
IOUT (mA)

–60

–80

–100

–120
0 0.5 1.0 1.5
VDDQ - VOUT (V)

Table 22: Full Strength Pull-Up Current (mA)

Voltage (V) Min Nom Max

0.0 0.00 0.00 0.00
0.1 –4.30 –5.63 –7.95
0.2 –8.60 –11.30 –15.90
0.3 –12.90 –16.52 –23.85
0.4 –16.90 –22.19 –31.80
0.5 –20.40 –27.59 –39.75
0.6 –23.28 –32.39 –47.70
0.7 –25.44 –36.45 –55.55
0.8 –26.79 –40.38 –62.95
0.9 –27.67 –44.01 –69.55
1.0 –28.38 –47.01 –75.35
1.1 –28.96 –49.63 –80.35
1.2 –29.46 –51.71 –84.55
1.3 –29.90 –53.32 –87.95
1.4 –30.29 –54.90 –90.70
1.5 –30.65 –56.03 –93.00
1.6 –30.98 –57.07 –95.05
1.7 –31.31 –58.16 –97.05
1.8 –31.64 –59.27 –99.05
1.9 –31.96 –60.35 –101.05

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Output Driver Characteristics

Figure 19: Reduced Strength Pull-Down Characteristics

70

60

50

40
IOUT (mV)

30

20

10

0
0.0 0.5 1.0 1.5

VOUT (V)

Table 23: Reduced Strength Pull-Down Current (mA)

Voltage (V) Min Nom Max

0.0 0.00 0.00 0.00
0.1 1.72 2.98 4.77
0.2 3.44 5.99 9.54
0.3 5.16 8.75 14.31
0.4 6.76 11.76 19.08
0.5 8.16 14.62 23.85
0.6 9.31 17.17 28.62
0.7 10.18 19.32 33.33
0.8 10.72 21.40 37.77
0.9 11.07 23.32 41.73
1.0 11.35 24.92 45.21
1.1 11.58 26.30 48.21
1.2 11.78 27.41 50.73
1.3 11.96 28.26 52.77
1.4 12.12 29.10 54.42
1.5 12.26 29.70 55.80
1.6 12.39 30.25 57.03
1.7 12.52 30.82 58.23
1.8 12.66 31.41 59.43
1.9 12.78 31.98 60.63

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Output Driver Characteristics

Figure 20: Reduced Strength Pull-Up Characteristics

0

–10

–20

IOUT (mV)
–30

–40

–50

–60

–70
0.0 0.5 1.0 1.5
VDDQ - VOUT (V)

Table 24: Reduced Strength Pull-Up Current (mA)

Voltage (V) Min Nom Max

0.0 0.00 0.00 0.00
0.1 –1.72 –2.98 –4.77
0.2 –3.44 –5.99 –9.54
0.3 –5.16 –8.75 –14.31
0.4 –6.76 –11.76 –19.08
0.5 –8.16 –14.62 –23.85
0.6 –9.31 –17.17 –28.62
0.7 –10.18 –19.32 –33.33
0.8 –10.72 –21.40 –37.77
0.9 –11.07 –23.32 –41.73
1.0 –11.35 –24.92 –45.21
1.1 –11.58 –26.30 –48.21
1.2 –11.78 –27.41 –50.73
1.3 –11.96 –28.26 –52.77
1.4 –12.12 –29.10 –54.42
1.5 –12.26 –29.69 –55.8
1.6 –12.39 –30.25 –57.03
1.7 –12.52 –30.82 –58.23
1.8 –12.66 –31.42 –59.43
1.9 –12.78 –31.98 –60.63

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Power and Ground Clamp Characteristics

Power and Ground Clamp Characteristics

Power and ground clamps are provided on the following input-only balls: Address balls,
bank address balls, CS#, RAS#, CAS#, WE#, ODT, and CKE.

Table 25: Input Clamp Characteristics

Minimum Power Clamp Current Minimum Ground Clamp Current

Voltage Across Clamp (V) (mA) (mA)
0.0 0.0 0.0
0.1 0.0 0.0
0.2 0.0 0.0
0.3 0.0 0.0
0.4 0.0 0.0
0.5 0.0 0.0
0.6 0.0 0.0
0.7 0.0 0.0
0.8 0.1 0.1
0.9 1.0 1.0
1.0 2.5 2.5
1.1 4.7 4.7
1.2 6.8 6.8
1.3 9.1 9.1
1.4 11.0 11.0
1.5 13.5 13.5
1.6 16.0 16.0
1.7 18.2 18.2
1.8 21.0 21.0

Figure 21: Input Clamp Characteristics

25
Minimum Clamp Current (mA)

20

15

10

0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Voltage Across Clamp (V)

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AC Overshoot/Undershoot Specification

AC Overshoot/Undershoot Specification

Table 26: Address and Control Balls

Applies to address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, and ODT
Specification
Parameter -187E -25/-25E -3/-3E -37E -5E
Maximum peak amplitude allowed for overshoot area
0.50V 0.50V 0.50V 0.50V 0.50V
(see Figure 22)
Maximum peak amplitude allowed for undershoot area
0.50V 0.50V 0.50V 0.50V 0.50V
(see Figure 23)
Maximum overshoot area above VDD (see Figure 22) 0.5 Vns 0.66 Vns 0.80 Vns 1.00 Vns 1.33 Vns
Maximum undershoot area below VSS (see Figure 23) 0.5 Vns 0.66 Vns 0.80 Vns 1.00 Vns 1.33 Vns

Table 27: Clock, Data, Strobe, and Mask Balls

Applies to DQ, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, and LDM
Specification
Parameter -187E -25/-25E -3/-3E -37E -5E
Maximum peak amplitude allowed for overshoot area 0.50V 0.50V 0.50V 0.50V 0.50V
(see Figure 22)
Maximum peak amplitude allowed for undershoot area 0.50V 0.50V 0.50V 0.50V 0.50V
(see Figure 23)
Maximum overshoot area above VDDQ (see Figure 22) 0.19 Vns 0.23 Vns 0.23 Vns 0.28 Vns 0.38 Vns
Maximum undershoot area below VSSQ (see Figure 23) 0.19 Vns 0.23 Vns 0.23 Vns 0.28 Vns 0.38 Vns

Figure 22: Overshoot

Maximum amplitude
Overshoot area
Volts (V)

VDD/VDDQ
VSS/VSSQ
Time (ns)

Figure 23: Undershoot

VSS/VSSQ
Volts (V)

Undershoot area
Maximum amplitude
Time (ns)

Table 28: AC Input Test Conditions

Parameter Symbol Min Max Units Notes

Input setup timing measurement reference level address VRS See Note 2 1, 2, 3, 4
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE

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AC Overshoot/Undershoot Specification

Table 28: AC Input Test Conditions (Continued)

Parameter Symbol Min Max Units Notes

Input hold timing measurement reference level address VRH See Note 5 1, 3, 4, 5
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE
Input timing measurement reference level (single-ended) VREF(DC) VDDQ × 0.49 VDDQ × 0.51 V 1, 3, 4, 6
DQS for x4, x8; UDQS, LDQS for x16
Input timing measurement reference level (differential) VRD VIX(AC) V 1, 3, 7, 8, 9
CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS,
RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16

Notes: 1. All voltages referenced to VSS.

2. Input waveform setup timing (tISb) is referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under
test, as shown in Figure 32 (page 70).
3. See Input Slew Rate Derating (page 59).
4. The slew rate for single-ended inputs is measured from DC level to AC level, VIL(DC) to
VIH(AC) on the rising edge and VIL(AC) to VIH(DC) on the falling edge. For signals referenced
to VREF, the valid intersection is where the “tangent” line intersects VREF, as shown in
Figure 25 (page 62), Figure 27 (page 63), Figure 29 (page 68), and Figure 31
(page 69).
5. Input waveform hold (tIHb) timing is referenced from the input signal crossing at the
VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under
test, as shown in Figure 32 (page 70).
6. Input waveform setup timing (tDS) and hold timing (tDH) for single-ended data strobe is
referenced from the crossing of DQS, UDQS, or LDQS through the Vref level applied to
the device under test, as shown in Figure 34 (page 71).
7. Input waveform setup timing (tDS) and hold timing (tDH) when differential data strobe
is enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/
LDQS#, as shown in Figure 33 (page 70).
8. Input waveform timing is referenced to the crossing point level (VIX) of two input signals
(VTR and VCP) applied to the device under test, where VTR is the true input signal and VCP
is the complementary input signal, as shown in Figure 35 (page 71).
9. The slew rate for differentially ended inputs is measured from twice the DC level to
twice the AC level: 2 × VIL(DC) to 2 × VIH(AC) on the rising edge and 2 × VIL(AC) to 2 ×
VIH(DC) on the falling edge. For example, the CK/CK# would be –250mV to 500mV for CK
rising edge and would be 250mV to –500mV for CK falling edge.

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Input Slew Rate Derating

Input Slew Rate Derating

For all input signals, the total tIS (setup time) and tIH (hold time) required is calculated
by adding the data sheet tIS (base) and tIH (base) value to the ˂tIS and ˂tIH derating
value, respectively. Example: tIS (total setup time) = tIS (base) + ˂tIS.
tIS, the nominal slew rate for a rising signal, is defined as the slew rate between the last
crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup nominal slew rate (tIS) for
a falling signal is defined as the slew rate between the last crossing of V REF(DC) and the
first crossing of V IL(AC)max.
If the actual signal is always earlier than the nominal slew rate line between shaded
“VREF(DC) to AC region,” use the nominal slew rate for the derating value (Figure 24
(page 62)).
If the actual signal is later than the nominal slew rate line anywhere between the shaded
“VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC
level to DC level is used for the derating value (see Figure 25 (page 62)).
tIH, the nominal slew rate for a rising signal, is defined as the slew rate between the last
crossing of V IL(DC)max and the first crossing of V REF(DC). tIH, nominal slew rate for a fall-
ing signal, is defined as the slew rate between the last crossing of V IH(DC)min and the first
crossing of V REF(DC).
If the actual signal is always later than the nominal slew rate line between shaded “DC
to V REF(DC) region,” use the nominal slew rate for the derating value (Figure 26
(page 63)).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded
“DC to V REF(DC) region,” the slew rate of a tangent line to the actual signal from the DC
level to V REF(DC) level is used for the derating value (Figure 27 (page 63)).
Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached V IH[AC]/VIL[AC] at the time of the rising clock transition), a valid in-
put signal is still required to complete the transition and reach V IH(AC)/VIL(AC).
For slew rates in between the values listed in Table 29 (page 60) and Table 30
(page 61), the derating values may obtained by linear interpolation.

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Input Slew Rate Derating

Table 29: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH)

CK, CK# Differential Slew Rate

2.0 V/ns 1.5 V/ns 1.0 V/ns
Command/Address Slew Rate (V/ns) ˂tIS ˂tIH ˂tIS ˂tIH ˂tIS ˂tIH Units
4.0 187 94 217 124 247 154 ps
3.5 179 89 209 119 239 149 ps
3.0 167 83 197 113 227 143 ps
2.5 150 75 180 105 210 135 ps
2.0 125 45 155 75 185 105 ps
1.5 83 21 113 51 143 81 ps
1.0 0 0 30 30 60 60 ps
0.9 –11 –14 19 16 49 46 ps
0.8 –25 –31 5 –1 35 29 ps
0.7 –43 –54 –13 –24 17 6 ps
0.6 –67 –83 –37 –53 –7 –23 ps
0.5 –110 –125 –80 –95 –50 –65 ps
0.4 –175 –188 –145 –158 –115 –128 ps
0.3 –285 –292 –255 –262 –225 –232 ps
0.25 –350 –375 –320 –345 –290 –315 ps
0.2 –525 –500 –495 –470 –465 –440 ps
0.15 –800 –708 –770 –678 –740 –648 ps
0.1 –1450 –1125 –1420 –1095 –1390 –1065 ps

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Input Slew Rate Derating

Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH)

Command/ CK, CK# Differential Slew Rate

Address Slew 2.0 V/ns 1.5 V/ns 1.0 V/ns
Rate (V/ns)
˂tIS ˂tIH ˂tIS ˂tIH ˂tIS ˂tIH Units
4.0 150 94 180 124 210 154 ps
3.5 143 89 173 119 203 149 ps
3.0 133 83 163 113 193 143 ps
2.5 120 75 150 105 180 135 ps
2.0 100 45 160 75 160 105 ps
1.5 67 21 97 51 127 81 ps
1.0 0 0 30 30 60 60 ps
0.9 –5 –14 25 16 55 46 ps
0.8 –13 –31 17 –1 47 29 ps
0.7 –22 –54 8 –24 38 6 ps
0.6 –34 –83 –4 –53 36 –23 ps
0.5 –60 –125 –30 –95 0 –65 ps
0.4 –100 –188 –70 –158 –40 –128 ps
0.3 –168 –292 –138 –262 –108 –232 ps
0.25 –200 –375 –170 –345 –140 –315 ps
0.2 –325 –500 –295 –470 –265 –440 ps
0.15 –517 –708 –487 –678 –457 –648 ps
0.1 –1000 –1125 –970 –1095 –940 –1065 ps

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Input Slew Rate Derating

Figure 24: Nominal Slew Rate for tIS

CK

CK#

tIS tIH tIS tIH

VDDQ

VIH(AC)min

VREF to AC
region

VIH(DC)min

Nominal
slew rate
VREF(DC)

Nominal
slew rate

VIL(DC)max

VREF to AC
region
VIL(AC)max

VSS
ǻTF ǻTR
Setup slew rate VREF(DC) - VIL(AC)max Setup slew rate VIH(AC)min - VREF(DC)
= rising signal =
falling signal ǻTF ǻTR

Figure 25: Tangent Line for tIS

CK

CK#

tIS tIH tIS tIH

VDDQ

VIH(AC)min
VREF to AC
region Nominal
line

VIH(DC)min
Tangent
line

VREF(DC)

Tangent
line

VIL(DC)max
Nominal VREF to AC
line region
VIL(AC)max
ǻTF ǻTR
VSS
Setup slew rate Tangent line (VIH[AC]min - VREF[DC])
rising signal =
ǻTR

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Input Slew Rate Derating

Figure 26: Nominal Slew Rate for tIH

CK

CK#

tIS tIH tIS tIH

VDDQ

VIH(AC)min

VIH(DC)min
DC to VREF
region
Nominal
slew rate

VREF(DC)

Nominal
slew rate DC to VREF
region
VIL(DC)max

VIL(AC)max

VSS

ǻTR ǻTF

Figure 27: Tangent Line for tIH

CK

CK#
tIS tIH tIS tIH
VDDQ

VIH(AC)min
Nominal
line
VIH(DC)min
DC to VREF
region
Tangent
line

VREF(DC)

Tangent
line
Nominal DC to VREF
line region
VIL(DC)max

VIL(AC)max

VSS

ǻTR ǻTF

Hold slew rate Tangent line (VREF[DC] - VIL[DC]max) Hold slew rate Tangent line (VIH[DC]min - VREF[DC])
= =
rising signal ǻTR falling signal ǻTF

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Input Slew Rate Derating

Table 31: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe
All units are shown in picoseconds
DQS, DQS# Differential Slew Rate
DQ
Slew 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
Rate ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂
(V/ns) tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 125 45 125 45 125 45 – – – – – – – – – – – –

1.5 83 21 83 21 83 21 95 33 – – – – – – – – – –
1.0 0 0 0 0 0 0 12 12 24 24 – – – – – – – –
0.9 – – –11 –14 –11 –14 1 –2 13 10 25 22 – – – – – –
0.8 – – – – –25 –31 –13 –19 –1 –7 11 5 23 17 – – – –
0.7 – – – – – – –31 –42 –19 –30 –7 –18 5 –6 17 6 – –
0.6 – – – – – – – – –43 –59 –31 –47 –19 –35 –7 –23 5 –11
0.5 – – – – – – – – – – –74 –89 –62 –77 –50 –65 –38 –53
0.4 – – – – – – – – – – – – –127 –140 –115 –128 –103 –116

Notes: 1. For all input signals, the total tDS and tDH required is calculated by adding the data
sheet value to the derating value listed in Table 31.
2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC)min. tDS nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VREF(DC) and the first cross-
ing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line be-
tween the shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating
value (see Figure 28 (page 68)). If the actual signal is later than the nominal slew rate
line anywhere between the shaded “VREF(DC) to AC region,” the slew rate of a tangent
line to the actual signal from the AC level to DC level is used for the derating value (see
Figure 29 (page 68)).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VIL(DC)max and the first crossing of VREF(DC). tDH nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VIH(DC)min and the first
crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line
between the shaded “DC level to VREF(DC) region,” use the nominal slew rate for the de-
rating value (see Figure 30 (page 69)). If the actual signal is earlier than the nominal
slew rate line anywhere between shaded “DC to VREF(DC) region,” the slew rate of a tan-
gent line to the actual signal from the DC level to VREF(DC) level is used for the derating
value (see Figure 31 (page 69)).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid in-
put signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
5. For slew rates between the values listed in this table, the derating values may be ob-
tained by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 33 (page 66) are the
DQS single-ended slew rate derating with DQS referenced at VREF and DQ referenced at
the logic levels tDSb and tDHb. Converting the derated base values from DQ referenced
to the AC/DC trip points to DQ referenced to VREF is listed in Table 35 (page 67) and
Table 36 (page 67). Table 35 provides the VREF-based fully derated values for the DQ
(tDSa and tDHa) for DDR2-533. Table 36 provides the VREF-based fully derated values for
the DQ (tDSa and tDHa) for DDR2-400.

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Input Slew Rate Derating

Table 32: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe
All units are shown in picoseconds
DQS, DQS# Differential Slew Rate
DQ
Slew 2.8 V/ns 2.4 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
Rate ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂ ˂
(V/ns) tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 100 63 100 63 100 63 112 75 124 87 136 99 148 111 160 123 172 135
1.5 67 42 67 42 67 42 79 54 91 66 103 78 115 90 127 102 139 114
1.0 0 0 0 0 0 0 12 12 24 24 36 36 48 48 60 60 72 72
0.9 –5 –14 –5 –14 –5 –14 7 –2 19 10 31 22 43 34 55 46 67 58
0.8 –13 –31 –13 –31 –13 –31 –1 –19 11 –7 23 5 35 17 47 29 59 41
0.7 –22 –54 –22 –54 –22 –54 –10 –42 2 –30 14 –18 26 –6 38 6 50 18
0.6 –34 –83 –34 –83 –34 –83 –22 –71 –10 –59 2 –47 14 –35 26 –23 38 –11
0.5 –60 –125 –60 –125 –60 –125 –48 –113 –36 –101 –24 –89 –12 –77 0 –65 12 –53
0.4 –100 –188 –100 –188 –100 –188 –88 –176 –76 –164 –64 –152 –52 –140 –40 –128 –28 –116

Notes: 1. For all input signals the total tDS and tDH required is calculated by adding the data
sheet value to the derating value listed in Table 32.
2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC)min. tDS nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VREF(DC) and the first cross-
ing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line be-
tween the shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating
value (see Figure 28 (page 68)). If the actual signal is later than the nominal slew rate
line anywhere between shaded “VREF(DC) to AC region,” the slew rate of a tangent line
to the actual signal from the AC level to DC level is used for the derating value (see Fig-
ure 29 (page 68)).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VIL(DC)max and the first crossing of VREF(DC). tDH nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VIH(DC)min and the first
crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line
between the shaded “DC level to VREF(DC) region,” use the nominal slew rate for the de-
rating value (see Figure 30 (page 69)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded “DC to VREF(DC) region,” the slew rate of a
tangent line to the actual signal from the DC level to VREF(DC) level is used for the derat-
ing value (see Figure 31 (page 69)).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid in-
put signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
5. For slew rates between the values listed in this table, the derating values may be ob-
tained by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 33 (page 66) are the
DQS single-ended slew rate derating with DQS referenced at VREF and DQ referenced at
the logic levels tDSb and tDHb. Converting the derated base values from DQ referenced
to the AC/DC trip points to DQ referenced to VREF is listed in Table 34 (page 66). Ta-
ble 34 provides the VREF-based fully derated values for the DQ (tDSa and tDHa) for

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Input Slew Rate Derating

DDR2-667. It is not advised to operate DDR2-800 and DDR2-1066 devices with single-
ended DQS; however, Table 33 would be used with the base values.

Table 33: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb
Reference points indicated in bold; Derating values are to be used with base tDSb- and tDHb--specified values
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns
DQ (V/ns) tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 130 53 130 53 130 53 130 53 130 53 145 48 155 45 165 41 175 38
1.5 97 32 97 32 97 32 97 32 97 32 112 27 122 24 132 20 142 17
1.0 30 –10 30 –10 30 –10 30 –10 30 –10 45 –15 55 –18 65 –22 75 –25
0.9 25 –24 25 –24 25 –24 25 –24 25 –24 40 –29 50 –32 60 –36 70 –39
0.8 17 –41 17 –41 17 –41 17 –41 17 –41 32 –46 42 –49 52 –53 61 –56
0.7 5 –64 5 –64 5 –64 5 –64 5 –64 20 –69 30 –72 40 –75 50 –79
0.6 –7 –93 –7 –93 –7 –93 –7 –93 –7 –93 8 –98 18 –102 28 –105 38 –108
0.5 –28 –135 –28 –135 –28 –135 –28 –135 –28 –135 –13 –140 –3 –143 7 –147 17 –150
0.4 –78 –198 –78 –198 –78 –198 –78 –198 –78 –198 –63 –203 –53 –206 –43 –210 –33 –213

Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667
Reference points indicated in bold
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns
DQ (V/ns) tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 330 291 330 291 330 291 330 291 330 291 345 286 355 282 365 29 375 276
1.5 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 279 375 275
1.0 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 278 375 275
0.9 347 290 347 290 347 290 347 290 347 290 362 285 372 282 382 278 392 275
0.8 367 290 367 290 367 290 367 290 367 290 382 285 392 282 402 278 412 275
0.7 391 290 391 290 391 290 391 290 391 290 406 285 416 281 426 278 436 275
0.6 426 290 426 290 426 290 426 290 426 290 441 285 451 282 461 278 471 275
0.5 472 290 472 290 472 290 472 290 472 290 487 285 497 282 507 278 517 275
0.4 522 289 522 289 522 289 522 289 522 289 537 284 547 281 557 278 567 274

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Input Slew Rate Derating

Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533
Reference points indicated in bold
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns
DQ (V/ns) tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 355 341 355 341 355 341 355 341 355 341 370 336 380 332 390 329 400 326
1.5 364 340 364 340 364 340 364 340 364 340 379 335 389 332 399 329 409 325
1.0 380 340 380 340 380 340 380 340 380 340 395 335 405 332 415 328 425 325
0.9 402 340 402 340 402 340 402 340 402 340 417 335 427 332 437 328 447 325
0.8 429 340 429 340 429 340 429 340 429 340 444 335 454 332 464 328 474 325
0.7 463 340 463 340 463 340 463 340 463 340 478 335 488 331 498 328 508 325
0.6 510 340 510 340 510 340 510 340 510 340 525 335 535 332 545 328 555 325
0.5 572 340 572 340 572 340 572 340 572 340 587 335 597 332 607 328 617 325
0.4 647 339 647 339 647 339 647 339 647 339 662 334 672 331 682 328 692 324

Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400
Reference points indicated in bold
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns
DQ (V/ns) tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 405 391 405 391 405 391 405 391 405 391 420 386 430 382 440 379 450 376
1.5 414 390 414 390 414 390 414 390 414 390 429 385 439 382 449 379 459 375
1.0 430 390 430 390 430 390 430 390 430 390 445 385 455 382 465 378 475 375
0.9 452 390 452 390 452 390 452 390 452 390 467 385 477 382 487 378 497 375
0.8 479 390 479 390 479 390 479 390 479 390 494 385 504 382 514 378 524 375
0.7 513 390 513 390 513 390 513 390 513 390 528 385 538 381 548 378 558 375
0.6 560 390 560 390 560 390 560 390 560 390 575 385 585 382 595 378 605 375
0.5 622 390 622 390 622 390 622 390 622 390 637 385 647 382 657 378 667 375
0.4 697 389 697 389 697 389 697 389 697 389 712 384 722 381 732 378 742 374

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Input Slew Rate Derating

Figure 28: Nominal Slew Rate for tDS

DQS1

DQS#1

tDS tDH tDS tDH

VDDQ

VIH(AC)min
VREF to AC
region

VIH(DC)min
Nominal
slew rate

VREF(DC)
Nominal
slew rate

VIL(DC)max

VREF to AC
region

VIL(AC)max

VSS
ǻTF ǻTR

Setup slew rate VREF(DC) - VIL(AC)max Setup slew rate VIH(AC)min - VREF(DC)
= =
falling signal ǻTF rising signal ǻTR

Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.

Figure 29: Tangent Line for tDS

DQS1

DQS#1

t t t t
DS DH DS DH
VDDQ

VIH(AC)min
Nominal
VREF to AC
line
region

VIH(DC)min
Tangent line

VREF(DC)

Tangent line

VIL(DC)max
Nominal line
VREF to AC
region

VIL(AC)max

ǻTF ǻTR

VSS

Tangent line (V REF[DC] - VIL[AC]max) Tangent line (VIH[AC]min - VREF[DC])

Setup slew rate Setup slew rate
= =
falling signal ǻTF rising signal ǻTR

Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.

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Input Slew Rate Derating

Figure 30: Nominal Slew Rate for tDH

DQS1

DQS#1

tIS tIH tIS tIH

VDDQ

VIH(AC)min

VIH(DC)min
DC to VREF
region
Nominal
slew rate

VREF(DC)

Nominal
slew rate DC to VREF
region
VIL(DC)max

VIL(AC)max

VSS

ǻTR ǻTF
Hold slew rate VREF(DC) - VIL(DC)max Hold slew rate VIH(DC)min - VREF(DC)
= =
rising signal ǻTR falling signal ǻTF

Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.

Figure 31: Tangent Line for tDH

DQS1

DQS#1
tIS tIH tIS tIH
VDDQ

VIH(AC)min
Nominal
line
VIH(DC)min
DC to VREF
region
Tangent
line

VREF(DC)

Tangent
line DC to VREF
Nominal region
line
VIL(DC)max

VIL(AC)max

VSS
ǻTR ǻTF
Tangent line (VREF[DC] - VIL[DC]max)
Hold slew rate Hold slew rate Tangent line (VIH[DC]min - VREF[DC])
= =
rising signal ǻTR falling signal ǻTF

Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.

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Input Slew Rate Derating

Figure 32: AC Input Test Signal Waveform Command/Address Balls

CK#

CK
tIS tIH tIS tIH
b b b b
Logic levels

VDDQ

VIH(AC)min
Vswing (MAX)

VIH(DC)min

VREF(DC)
VIL(DC)min

VIL(AC)min

VSSQ
VREF levels tIS tIH tIS tIH
a a a a

Figure 33: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential)
DQS#

DQS

tDS tDH tDS tDH

b b b b

Logic levels

VDDQ

VIH(AC)min
Vswing (MAX)

VIH(DC)min

VREF(DC)

VIL(DC)max

VIL(AC)max

VSSQ

VREF levels tDS tDH tDS tDH

a a a a

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Input Slew Rate Derating

Figure 34: AC Input Test Signal Waveform for Data with DQS (Single-Ended)

VREF

DQS

tDS tDH tDS tDH

b b b b
Logic levels

VDDQ

VIH(AC)min
Vswing (MAX)

VIH(DC)min

VREF(DC)

VIL(DC)max

VIL(AC)max

VSSQ

VREF levels
tDS tDH tDS tDH
a a a a

Figure 35: AC Input Test Signal Waveform (Differential)

VDDQ

VTR

Vswing Crossing point

VIX

VCP

VSSQ

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 512Mb: x4, x8, x16 DDR2 SDRAM
Commands

Commands
Truth Tables
The following tables provide a quick reference of available DDR2 SDRAM commands,
including CKE power-down modes and bank-to-bank commands.

Table 37: Truth Table – DDR2 Commands

Notes: 1–3 apply to the entire table
CKE
Previous Current BA2–
Function Cycle Cycle CS# RAS# CAS# WE# BA0 An–A11 A10 A9–A0 Notes
LOAD MODE H H L L L L BA OP code 4, 6
REFRESH H H L L L H X X X X
SELF REFRESH entry H L L L L H X X X X
SELF REFRESH exit L H H X X X X X X X 4, 7
L H H H
Single bank H H L L H L BA X L X 6
PRECHARGE
All banks PRECHARGE H H L L H L X X H X
Bank ACTIVATE H H L L H H BA Row address 4
WRITE H H L H L L BA Column L Column 4, 5, 6,
address address 8
WRITE with auto H H L H L L BA Column H Column 4, 5, 6,
precharge address address 8
READ H H L H L H BA Column L Column 4, 5, 6,
address address 8
READ with auto H H L H L H BA Column H Column 4, 5, 6,
precharge address address 8
NO OPERATION H X L H H H X X X X
Device DESELECT H X H X X X X X X X
Power-down entry H L H X X X X X X X 9
L H H H
Power-down exit L H H X X X X X X X 9
L H H H

Notes: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at
the rising edge of the clock.
2. The state of ODT does not affect the states described in this table. The ODT function is
not available during self refresh. See ODT Timing (page 129) for details.
3. “X” means “H or L” (but a defined logic level) for valid IDD measurements.
4. BA2 is only applicable for densities ุ1Gb.
5. An n is the most significant address bit for a given density and configuration. Some larg-
er address bits may be “Don’t Care” during column addressing, depending on density
and configuration.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Commands

6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD
MODE command selects which mode register is programmed.
7. SELF REFRESH exit is asynchronous.
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 49
(page 98) and Figure 61 (page 109) for other restrictions and details.
9. The power-down mode does not perform any REFRESH operations. The duration of
power-down is limited by the refresh requirements outlined in the AC parametric sec-
tion.

Table 38: Truth Table – Current State Bank n – Command to Bank n

Notes: 1–6 apply to the entire table
Current
State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X DESELECT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle L L H H ACTIVATE (select and activate row)
L L L H REFRESH 7
L L L L LOAD MODE 7
Row active L H L H READ (select column and start READ burst) 8
L H L L WRITE (select column and start WRITE burst) 8
L L H L PRECHARGE (deactivate row in bank or banks) 9
Read (auto L H L H READ (select column and start new READ burst) 8
precharge L H L L WRITE (select column and start WRITE burst) 8, 10
disabled)
L L H L PRECHARGE (start PRECHARGE) 9
Write L H L H READ (select column and start READ burst) 8
(auto pre- L H L L WRITE (select column and start new WRITE burst) 8
charge disa-
L L H L PRECHARGE (start PRECHARGE) 9
bled)

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that
state). Exceptions are covered in the notes below.
3. Current state definitions:

The bank has been precharged, tRP has been met, and any READ burst is com-
Idle:
plete.
Row A row in the bank has been activated, and tRCD has been met. No data bursts/
active: accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled and has not yet
terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and has not yet
terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Issue DESELECT or NOP commands, or allowable commands to the other bank, on any
clock edge occurring during these states. Allowable commands to the other bank are
determined by its current state and this table, and according to Table 39 (page 75).

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Commands

Precharge: Starts with registration of a PRECHARGE command and ends when

tRP
is met. After tRP is met, the bank will be in the idle state.
Read with auto Starts with registration of a READ command with auto precharge
precharge enabled and ends when tRP has been met. After tRP is met, the
enabled: bank will be in the idle state.
Row activate: Starts with registration of an ACTIVATE command and ends when
tRCD is met. After tRCD is met, the bank will be in the row active

state.
Write with auto Starts with registration of a WRITE command with auto precharge
precharge enabled and ends when tRP has been met. After tRP is met, the
enabled: bank will be in the idle state.
5. The following states must not be interrupted by any executable command (DESELECT or
NOP commands must be applied on each positive clock edge during these states):

Refresh: Starts with registration of a REFRESH command and ends when tRFC is
met. After tRFC is met, the DDR2 SDRAM will be in the all banks idle
state.
Accessing Starts with registration of the LOAD MODE command and ends when
mode tMRD has been met. After tMRD is met, the DDR2 SDRAM will be in the

register: all banks idle state.

Precharge Starts with registration of a PRECHARGE ALL command and ends when
all: tRP is met. After tRP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle and bursts are not in progress.
8. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
9. May or may not be bank-specific; if multiple banks are to be precharged, each must be
in a valid state for precharging.
10. A WRITE command may be applied after the completion of the READ burst.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Commands

Table 39: Truth Table – Current State Bank n – Command to Bank m

Notes: 1–6 apply to the entire table
Current State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X DESELECT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle X X X X Any command otherwise allowed to bank m
Row L L H H ACTIVATE (select and activate row)
active, active, L H L H READ (select column and start READ burst) 7
or precharge
L H L L WRITE (select column and start WRITE burst) 7
L L H L PRECHARGE
Read (auto L L H H ACTIVATE (select and activate row)
precharge L H L H READ (select column and start new READ burst) 7
disabled)
L H L L WRITE (select column and start WRITE burst) 7, 8
L L H L PRECHARGE
Write (auto L L H H ACTIVATE (select and activate row)
precharge L H L H READ (select column and start READ burst) 7, 9, 10
disabled)
L H L L WRITE (select column and start new WRITE burst) 7
L L H L PRECHARGE
Read (with L L H H ACTIVATE (select and activate row)
auto L H L H READ (select column and start new READ burst) 7
precharge)
L H L L WRITE (select column and start WRITE burst) 7, 8
L L H L PRECHARGE
Write (with L L H H ACTIVATE (select and activate row)
auto L H L H READ (select column and start READ burst) 7, 10
precharge)
L H L L WRITE (select column and start new WRITE burst) 7
L L H L PRECHARGE

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been
met (if the previous state was self refresh).
2. This table describes an alternate bank operation, except where noted (the current state
is for bank n and the commands shown are those allowed to be issued to bank m, as-
suming that bank m is in such a state that the given command is allowable). Exceptions
are covered in the notes below.
3. Current state definitions:

Idle: The bank has been precharged, tRP has been met, and any READ
burst is complete.
Row active: A row in the bank has been activated and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated with auto precharge disabled
and has not yet terminated.
Write: A WRITE burst has been initiated with auto precharge disabled
and has not yet terminated.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Commands

READ with auto The READ with auto precharge enabled or WRITE with auto pre-
precharge enabled/ charge enabled states can each be broken into two parts: the ac-
WRITE with auto cess period and the precharge period. For READ with auto pre-
precharge enabled: charge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with
the earliest possible PRECHARGE command that still accesses all
of the data in the burst. For WRITE with auto precharge, the pre-
charge period begins when tWR ends, with tWR measured as if
auto precharge was disabled. The access period starts with regis-
tration of the command and ends where the precharge period
(or tRP) begins. This device supports concurrent auto precharge
such that when a READ with auto precharge is enabled or a
WRITE with auto precharge is enabled, any command to other
banks is allowed, as long as that command does not interrupt
the read or write data transfer already in process. In either case,
all other related limitations apply (contention between read da-
ta and write data must be avoided).
The minimum delay from a READ or WRITE command with auto precharge enabled to
a command to a different bank is summarized in Table 40 (page 76).
4. REFRESH and LOAD MODE commands may only be issued when all banks are idle.
5. Not used.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. A WRITE command may be applied after the completion of the READ burst.
9. Requires appropriate DM.
10. The number of clock cycles required to meet tWTR is either two or tWTR/tCK, whichever
is greater.

Table 40: Minimum Delay with Auto Precharge Enabled

Minimum Delay
From Command (Bank n) To Command (Bank m) (with Concurrent Auto Precharge) Units
WRITE with auto precharge READ or READ with auto precharge (CL - 1) + (BL/2) + tWTR tCK

WRITE or WRITE with auto precharge (BL/2) tCK

PRECHARGE or ACTIVATE 1 tCK

READ with auto precharge READ or READ with auto precharge (BL/2) tCK

WRITE or WRITE with auto precharge (BL/2) + 2 tCK

PRECHARGE or ACTIVATE 1 tCK

DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in
progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Commands

NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to
perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted
commands from being registered during idle or wait states. Operations already in pro-
gress are not affected.

LOAD MODE (LM)

The mode registers are loaded via bank address and address inputs. The bank address
balls determine which mode register will be programmed. See Mode Register (MR)
(page 78). The LM command can only be issued when all banks are idle, and a subse-
quent executable command cannot be issued until tMRD is met.

ACTIVATE
The ACTIVATE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the bank address inputs determines the bank, and the
address inputs select the row. This row remains active (or open) for accesses until a pre-
charge command is issued to that bank. A precharge command must be issued before
opening a different row in the same bank.

READ
The READ command is used to initiate a burst read access to an active row. The value
on the bank address inputs determine the bank, and the address provided on address
inputs A0–Ai (where Ai is the most significant column address bit for a given configura-
tion) selects the starting column location. The value on input A10 determines whether
or not auto precharge is used. If auto precharge is selected, the row being accessed will
be precharged at the end of the read burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command
to be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE
command to the internal device by AL clock cycles.

WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the bank select inputs selects the bank, and the address provided on inputs A0–Ai
(where Ai is the most significant column address bit for a given configuration) selects
the starting column location. The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be pre-
charged at the end of the WRITE burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command
to be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE
command to the internal device by AL clock cycles.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW,
the corresponding data will be written to memory; if the DM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE will not be executed to that
byte/column location (see Figure 66 (page 114)).

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 512Mb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)

PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row activation
a specified time (tRP) after the PRECHARGE command is issued, except in the case of
concurrent auto precharge, where a READ or WRITE command to a different bank is al-
lowed as long as it does not interrupt the data transfer in the current bank and does not
violate any other timing parameters. After a bank has been precharged, it is in the idle
state and must be activated prior to any READ or WRITE commands being issued to
that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle
state) or if the previously open row is already in the process of precharging. However,
the precharge period will be determined by the last PRECHARGE command issued to
the bank.

REFRESH
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to
CAS#-before-RAS# (CBR) REFRESH. All banks must be in the idle mode prior to issuing
a REFRESH command. This command is nonpersistent, so it must be issued each time
a refresh is required. The addressing is generated by the internal refresh controller. This
makes the address bits a “Don’t Care” during a REFRESH command.

SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if
the rest of the system is powered down. When in the self refresh mode, the DDR2
SDRAM retains data without external clocking. All power supply inputs (including Vref)
must be maintained at valid levels upon entry/exit and during SELF REFRESH opera-
tion.
The SELF REFRESH command is initiated like a REFRESH command except CKE is
LOW. The DLL is automatically disabled upon entering self refresh and is automatically
enabled upon exiting self refresh.

Mode Register (MR)

The mode register is used to define the specific mode of operation of the DDR2 SDRAM.
This definition includes the selection of a burst length, burst type, CAS latency, operat-
ing mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 36
(page 79). Contents of the mode register can be altered by re-executing the LOAD
MODE (LM) command. If the user chooses to modify only a subset of the MR variables,
all variables must be programmed when the command is issued.
The MR is programmed via the LM command and will retain the stored information un-
til it is programmed again or until the device loses power (except for bit M8, which is
self-clearing). Reprogramming the mode register will not alter the contents of the mem-
ory array, provided it is performed correctly.
The LM command can only be issued (or reissued) when all banks are in the precharged
state (idle state) and no bursts are in progress. The controller must wait the specified
time tMRD before initiating any subsequent operations such as an ACTIVATE com-
mand. Violating either of these requirements will result in an unspecified operation.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)

Burst Length
Burst length is defined by bits M0–M2, as shown in Figure 36. Read and write accesses
to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to
either four or eight. The burst length determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most
significant column address bit for a given configuration). The remaining (least signifi-
cant) address bit(s) is (are) used to select the starting location within the block. The pro-
grammed burst length applies to both read and write bursts.

Figure 36: MR Definition

1 2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

16 15 14 n 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register (Mx)

0 MR 0 PD WR DLL TM CAS# Latency BT Burst Length

M12 PD Mode M7 Mode M2 M1 M0 Burst Length

0 Fast exit 0 Normal 0 0 0 Reserved
(normal) 0 0 1 Reserved
1 Test
1 Slow exit 0 1 0 4
(low power)
M8 DLL Reset 0 1 1 8
0 No 1 0 0 Reserved
1 Yes 1 0 1 Reserved
1 1 0 Reserved
M11 M10 M9 Write Recovery 1 1 1 Reserved
0 0 0 Reserved
0 0 1 2 M3 Burst Type
0 1 0 3 0 Sequential
0 1 1 4 1 Interleaved
1 0 0 5
1 0 1 6 CAS Latency (CL)
M6 M5 M4
1 1 0 7 Reserved
0 0 0
1 1 1 8 Reserved
0 0 1
0 1 0 Reserved
M15 M14 Mode Register Definition
0 1 1 3
0 0 Mode register (MR)
1 0 0 4
0 1 Extended mode register (EMR)
1 0 1 5
1 0 Extended mode register (EMR2)
1 1 0 6
1 1 Extended mode register (EMR3)
1 1 1 7

Notes: 1. M16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be
programmed to “0.”
2. Mode bits (Mn) with corresponding address balls (An) greater than M12 (A12) are re-
served for future use and must be programmed to “0.”
3. Not all listed WR and CL options are supported in any individual speed grade.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)

Burst Type
Accesses within a given burst may be programmed to be either sequential or inter-
leaved. The burst type is selected via bit M3, as shown in Figure 36. The ordering of ac-
cesses within a burst is determined by the burst length, the burst type, and the starting
column address, as shown in Table 41. DDR2 SDRAM supports 4-bit burst mode and 8-
bit burst mode only. For 8-bit burst mode, full interleaved address ordering is suppor-
ted; however, sequential address ordering is nibble-based.

Table 41: Burst Definition

Burst Length Starting Column Address Order of Accesses Within a Burst

(A2, A1, A0) Burst Type = Sequential Burst Type = Interleaved
4 000 0, 1, 2, 3 0, 1, 2, 3
001 1, 2, 3, 0 1, 0, 3, 2
010 2, 3, 0, 1 2, 3, 0, 1
011 3, 0, 1, 2 3, 2, 1, 0
8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5
011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1
111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

Operating Mode
The normal operating mode is selected by issuing a command with bit M7 set to “0,”
and all other bits set to the desired values, as shown in Figure 36 (page 79). When bit M7
is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1”
places the DDR2 SDRAM into a test mode that is only used by the manufacturer and
should not be used. No operation or functionality is guaranteed if M7 bit is “1.”

DLL RESET
DLL RESET is defined by bit M8, as shown in Figure 36. Programming bit M8 to “1” will
activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a
value of “0” after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ
command can be issued to allow time for the internal clock to be synchronized with the
external clock. Failing to wait for synchronization to occur may result in a violation of
the tAC or tDQSCK parameters.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)

Write Recovery
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 36 (page 79).
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-
tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter-
nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last
data burst. An example of WRITE with auto precharge is shown in Figure 65 (page 113).
WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The
user is required to program the value of WR, which is calculated by dividing tWR (in
nanoseconds) by tCK (in nanoseconds) and rounding up a noninteger value to the next
integer; WR (cycles) = tWR (ns)/tCK (ns). Reserved states should not be used as an un-
known operation or incompatibility with future versions may result.

Power-Down Mode
Active power-down (PD) mode is defined by bit M12, as shown in Figure 36. PD mode
enables the user to determine the active power-down mode, which determines per-
formance versus power savings. PD mode bit M12 does not apply to precharge PD
mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is en-
abled. The tXARDS parameter is used for slow-exit active PD exit timing. The DLL can
be enabled but “frozen” during active PD mode because the exit-to-READ command
timing is relaxed. The power difference expected between I DD3P normal and IDD3P low-
power mode is defined in the DDR2 IDD Specifications and Conditions table.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)

CAS Latency (CL)

The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 36 (page 79). CL is
the delay, in clock cycles, between the registration of a READ command and the availa-
bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may re-
sult.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-
ture allows the READ command to be issued prior to tRCD (MIN) by delaying the inter-
nal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further
detail in Posted CAS Additive Latency (AL) (page 85).
Examples of CL = 3 and CL = 4 are shown in Figure 37; both assume AL = 0. If a READ
command is registered at clock edge n, and the CL is m clocks, the data will be available
nominally coincident with clock edge n + m (this assumes AL = 0).

Figure 37: CL
T0 T1 T2 T3 T4 T5 T6
CK#

CK

Command READ NOP NOP NOP NOP NOP NOP

DQS, DQS#

DQ DO DO DO DO
n n+1 n+2 n+3
CL = 3 (AL = 0)

T0 T1 T2 T3 T4 T5 T6
CK#

CK

Command READ NOP NOP NOP NOP NOP NOP

DQS, DQS#

DQ DO DO DO DO
n n+1 n+2 n+3
CL = 4 (AL = 0)

Transitioning data Don’t care

Notes: 1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)

Extended Mode Register (EMR)

The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, output drive strength, on-
die termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#
enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These func-
tions are controlled via the bits shown in Figure 38. The EMR is programmed via the LM
command and will retain the stored information until it is programmed again or the de-
vice loses power. Reprogramming the EMR will not alter the contents of the memory ar-
ray, provided it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent opera-
tion. Violating either of these requirements could result in an unspecified operation.

Figure 38: EMR Definition

1 2
BA2 BA1 BA0 An A12 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus

Extended mode
16 15 14 n 12 11 10 9 8 7 6 5 4 3 2 1 0
0 MRS 0 Out RDQS DQS# OCD Program RTT Posted CAS# RTT ODS DLL register (Ex)

E12 Outputs E0 DLL Enable

0 Enabled E6 E2 RTT (Nominal) 0 Enable (normal)
1 Disabled 0 0 RTT disabled 1 Disable (test/debug)
0 1 75Ÿ
E11 RDQS Enable 1 0 150Ÿ E1 Output Drive Strength
0 No 1 1 50Ÿ 0 Full
1 Yes 1 Reduced

E10 DQS# Enable 3

E5 E4 E3 Posted CAS# Additive Latency (AL)
0 Enable 0 0 0 0
1 Disable 0 0 1 1
4 0 1 0 2
E9 E8 E7 OCD Operation
0 1 1 3
0 0 0 OCD exit
1 0 0 4
0 0 1 Reserved
1 0 1 5
0 1 0 Reserved
1 1 0 6
1 0 0 Reserved
1 1 1 Reserved
1 1 1 Enable OCD defaults

E15 E14 Mode Register Set

0 0 Mode register (MR)
0 1 Extended mode register (EMR)
1 0 Extended mode register (EMR2)
1 1 Extended mode register (EMR3)

Notes: 1. E16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be pro-
grammed to 0.
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-
served for future use and must be programmed to 0.
3. Not all listed AL options are supported in any individual speed grade.
4. As detailed in the Initialization section notes, during initialization of the OCD operation,
all three bits must be set to 1 for the OCD default state, then set to 0 before initializa-
tion is finished.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)

DLL Enable/Disable
The DLL may be enabled or disabled by programming bit E0 during the LM command,
as shown in Figure 38 (page 83). These specifications are applicable when the DLL is en-
abled for normal operation. DLL enable is required during power-up initialization and
upon returning to normal operation after having disabled the DLL for the purpose of
debugging or evaluation. Enabling the DLL should always be followed by resetting the
DLL using the LM command.
The DLL is automatically disabled when entering SELF REFRESH operation and is auto-
matically re-enabled and reset upon exit of SELF REFRESH operation.
Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur be-
fore a READ command can be issued to allow time for the internal clock to synchronize
with the external clock. Failing to wait for synchronization to occur may result in a vio-
lation of the tAC or tDQSCK parameters.
Anytime the DLL is disabled and the device is operated below 25 MHz, any AUTO RE-
FRESH command should be followed by a PRECHARGE ALL command.

Output Drive Strength

The output drive strength is defined by bit E1, as shown in Figure 38. The normal drive
strength for all outputs is specified to be SSTL_18. Programming bit E1 = 0 selects nor-
mal (full strength) drive strength for all outputs. Selecting a reduced drive strength op-
tion (E1 = 1) will reduce all outputs to approximately 45 to 60 percent of the SSTL_18
drive strength. This option is intended for the support of lighter load and/or point-to-
point environments.

DQS# Enable/Disable
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the dif-
ferential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a single-
ended mode and the DQS# ball is disabled. When disabled, DQS# should be left float-
ing; however, it may be tied to ground via a 20˖ to 10k˖ resistor. This function is also
used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 =
0), then both DQS# and RDQS# will be enabled.

RDQS Enable/Disable
The RDQS ball is enabled by bit E11, as shown in Figure 38. This feature is only applica-
ble to the x8 configuration. When enabled (E11 = 1), RDQS is identical in function and
timing to data strobe DQS during a READ. During a WRITE operation, RDQS is ignored
by the DDR2 SDRAM.

Output Enable/Disable
The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 38. When ena-
bled (E12 = 0), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) function normally. When
disabled (E12 = 1), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) are disabled, thus re-
moving output buffer current. The output disable feature is intended to be used during
IDD characterization of read current.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)

On-Die Termination (ODT)

ODT effective resistance, RTT(EFF), is defined by bits E2 and E6 of the EMR, as shown in
Figure 38 (page 83). The ODT feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM controller to independently turn on/off
ODT for any or all devices. RTT effective resistance values of 50˖˖, and 150˖ are se-
lectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/
LDQS#, DM, and UDM/LDM signal. Bits (E6, E2) determine what ODT resistance is en-
abled by turning on/off sw1, sw2, or sw3. The ODT effective resistance value is selected
by enabling switch sw1, which enables all R1 values that are 150˖ each, enabling an ef-
fective resistance of 75˖(RTT2 [EFF] = R2/2). Similarly, if sw2 is enabled, all R2 values that
are 300˖ each, enable an effective ODT resistance of 150˖(RTT2[EFF] = R2/2). Switch sw3
enables R1 values of 100˖, enabling effective resistance of 50˖. Reserved states should
not be used, as an unknown operation or incompatibility with future versions may re-
sult.
The ODT control ball is used to determine when RTT(EFF) is turned on and off, assuming
ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input
ball are only used during active, active power-down (both fast-exit and slow-exit
modes), and precharge power-down modes of operation.
ODT must be turned off prior to entering self refresh mode. During power-up and initi-
alization of the DDR2 SDRAM, ODT should be disabled until the EMR command is is-
sued. This will enable the ODT feature, at which point the ODT ball will determine the
RTT(EFF) value. Anytime the EMR enables the ODT function, ODT may not be driven
HIGH until eight clocks after the EMR has been enabled (see Figure 81 (page 130) for
ODT timing diagrams).

Off-Chip Driver (OCD) Impedance Calibration

The OFF-CHIP DRIVER function is an optional DDR2 JEDEC feature not supported by
Micron and thereby must be set to the default state. Enabling OCD beyond the default
settings will alter the I/O drive characteristics and the timing and output I/O specifica-
tions will no longer be valid (see Initialization section for proper setting of OCD de-
faults).

Posted CAS Additive Latency (AL)

Posted CAS additive latency (AL) is supported to make the command and data bus effi-
cient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as
shown in Figure 38. Bits E3–E5 allow the user to program the DDR2 SDRAM with an AL
of 0, 1, 2, 3, 4, 5, or 6 clocks. Reserved states should not be used as an unknown opera-
tion or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued
prior to tRCD (MIN) with the requirement that AL ื tRCD (MIN). A typical application
using this feature would set AL = tRCD (MIN) - 1 × tCK. The READ or WRITE command
is held for the time of the AL before it is issued internally to the DDR2 SDRAM device.
RL is controlled by the sum of AL and CL; RL = AL + CL. WRITE latency (WL) is equal to
RL minus one clock; WL = AL + CL - 1 × tCK. An example of RL is shown in Figure 39
(page 86). An example of a WL is shown in Figure 40 (page 86).

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 512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)

Figure 39: READ Latency

T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK

Command ACTIVE n READ n NOP NOP NOP NOP NOP NOP NOP

DQS, DQS#
tRCD (MIN)

DQ DO DO DO DO
n n+1 n+2 n+3
AL = 2 CL = 3
RL = 5

Transitioning Data Don’t Care

Notes: 1. BL = 4.
2. Shown with nominal tAC, tDQSCK, and tDQSQ.
3. RL = AL + CL = 5.

Figure 40: WRITE Latency

T0 T1 T2 T3 T4 T5 T6 T7
CK#
CK

Command ACTIVE n WRITE n NOP NOP NOP NOP NOP NOP

tRCD (MIN)

DQS, DQS#

AL = 2 CL - 1 = 2

DQ DI DI DI DI
n n+1 n+2 n+3
WL = AL + CL - 1 = 4

Transitioning Data Don’t Care

Notes: 1. BL = 4.
2. CL = 3.
3. WL = AL + CL - 1 = 4.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register 2 (EMR2)

Extended Mode Register 2 (EMR2)

The extended mode register 2 (EMR2) controls functions beyond those controlled by
the mode register. Currently all bits in EMR2 are reserved, except for E7, which is used
in commercial or high-temperature operations, as shown in Figure 41. The EMR2 is pro-
grammed via the LM command and will retain the stored information until it is pro-
grammed again or until the device loses power. Reprogramming the EMR will not alter
the contents of the memory array, provided it is performed correctly.
Bit E7 (A7) must be programmed as 1 to provide a faster refresh rate on IT and AT devi-
ces if T C exceeds 85°C.
EMR2 must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent opera-
tion. Violating either of these requirements could result in an unspecified operation.

Figure 41: EMR2 Definition

1 2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus

Extended mode
16 15 14 n 12 11 10 9 8 7 6 5 4 3 2 1 0
0 MRS 0 0 0 0 0 0 SRT 0 0 0 0 0 0 0 register (Ex)

E15 E14 Mode Register Set E7 SRT Enable

0 0 Mode register (MR) 0 1X refresh rate (0°C to 85°C)
0 1 Extended mode register (EMR) 1 2X refresh rate (>85°C)
1 0 Extended mode register (EMR2)
1 1 Extended mode register (EMR3)

Notes: 1. E16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be pro-
grammed to 0.
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-
served for future use and must be programmed to 0.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register 3 (EMR3)

Extended Mode Register 3 (EMR3)

The extended mode register 3 (EMR3) controls functions beyond those controlled by
the mode register. Currently all bits in EMR3 are reserved, as shown in Figure 42. The
EMR3 is programmed via the LM command and will retain the stored information until
it is programmed again or until the device loses power. Reprogramming the EMR will
not alter the contents of the memory array, provided it is performed correctly.
EMR3 must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent opera-
tion. Violating either of these requirements could result in an unspecified operation.

Figure 42: EMR3 Definition

1 2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus

Extended mode
16 15 14 n 12 11 10 9 8 7 6 5 4 3 2 1 0
0 register (Ex)
0 MRS 0 0 0 0 0 0 0 0 0 0 0 0 0

E15 E14 Mode Register Set

0 0 Mode register (MR)
0 1 Extended mode register (EMR)
1 0 Extended mode register (EMR2)
1 1 Extended mode register (EMR3)

Notes: 1. E16 (BA2) is only applicable for densities ุ1Gb, is reserved for future use, and must be
programmed to 0.
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-
served for future use and must be programmed to 0.

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 Initialization

Figure 43: DDR2 Power-Up and Initialization

CCMTD-1725822587-9657
DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in unde-
fined operation. Figure 43 illustrates, and the notes outline, the sequence required for power-up and initialization.

512MbDDR2.pdf - Rev. Z 09/18 EN

VDD

VDDL

VDDQ tVTD1

VTT1

VREF

T0 Ta0 Tb0 Tc0 Td0 Te0 Tf0 Tg0 Th0 Ti0 Tj0 Tk0 Tl0 Tm0
tCK
CK#
CK
tCL tCL

LVCMOS SSTL_18 2
CKE low level2 low level

ODT

Command NOP3 PRE LM5 LM6 LM7 LM8 PRE9 REF10 REF10 LM11 LM12 LM13 Valid14

89
15
DM

16
Address A10 = 1 Code Code Code Code A10 = 1 Code Code Code Valid

15 High-Z
DQS
15 High-Z
DQ

Rtt High-Z

T = 200μs (MIN)3 T = 400ns (MIN)4 tRPA tMRD tMRD tMRD tMRD tRPA tRFC tRFC tMRD tMRD tMRD

6HHQR WH
Power-up: EMR(2) EMR(3) EMR
VDD and stable
clock (CK, CK#) MR without EMR with EMR with
DLL RESET OCD default OCD exit
200 cycles of CK are required before a READ command can be issued
Normal
MR with operation
DLL RESET
Indicates a Break in
Don’t care
Time Scale

‹ 2004 Micron Technology, Inc. All rights reserved.

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Initialization
512Mb: x4, x8, x16 DDR2 SDRAM
 512Mb: x4, x8, x16 DDR2 SDRAM
Initialization

Notes: 1. Applying power; if CKE is maintained below 0.2 × VDDQ, outputs remain disabled. To
guarantee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied
to the ODT ball (all other inputs may be undefined; I/Os and outputs must be less than
VDDQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). VTT is not ap-
plied directly to the device; however, tVTD should be ุ0 to avoid device latch-up. At
least one of the following two sets of conditions (A or B) must be met to obtain a stable
supply state (stable supply defined as VDD, VDDL, VDDQ, VREF, and VTT are between their
minimum and maximum values as stated in Table 13 (page 45)):
A. Single power source: The VDD voltage ramp from 300mV to VDD,min must take no lon-
ger than 200ms; during the VDD voltage ramp, |VDD - VDDQ| ื 0.3V. Once supply voltage
ramping is complete (when VDDQ crosses VDD,min), Table 13 specifications apply.
• VDD, VDDL, and VDDQ are driven from a single power converter output
• VTT is limited to 0.95V MAX
• VREF tracks VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during supply
ramp time; does not need to be satisfied when ramping power down
• VDDQ ุ VREF at all times
B. Multiple power sources: VDD ุ VDDL ุ VDDQ must be maintained during supply voltage
ramping, for both AC and DC levels, until supply voltage ramping completes (VDDQ
crosses VDD,min). Once supply voltage ramping is complete, Table 13 specifications apply.
• Apply VDD and VDDL before or at the same time as VDDQ; VDD/VDDL voltage ramp time
must be ื 200ms from when VDD ramps from 300mV to VDD,min
• Apply VDDQ before or at the same time as VTT; the VDDQ voltage ramp time from when
VDD,min is achieved to when VDDQ,min is achieved must be ื 500ms; while VDD is ramp-
ing, current can be supplied from VDD through the device to VDDQ
• VREF must track VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during sup-
ply ramp time; VDDQ ุ VREF must be met at all times; does not need to be satisfied
when ramping power down
• Apply VTT; the VTT voltage ramp time from when VDDQ,min is achieved to when VTT,min
is achieved must be no greater than 500ms
2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during de-
vice power-up prior to VREF being stable. After state T0, CKE is required to have SSTL_18
input levels. Once CKE transitions to a high level, it must stay HIGH for the duration of
the initialization sequence.
3. For a minimum of 200μs after stable power and clock (CK, CK#), apply NOP or DESELECT
commands, then take CKE HIGH.
4. Wait a minimum of 400ns then issue a PRECHARGE ALL command.
5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide
LOW to BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropri-
ate self refresh rate; remaining EMR(2) bits must be “0” (see Extended Mode Register 2
(EMR2) (page 87) for all EMR(2) requirements).
6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide
HIGH to BA0 and BA1; remaining EMR(3) bits must be “0.” Extended Mode Register 3
(EMR3) for all EMR(3) requirements.
7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE com-
mand, provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set
to “0” or “1;” Micron recommends setting them to “0;” remaining EMR bits must be
“0.” Extended Mode Register (EMR) (page 83) for all EMR requirements.
8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is re-
quired to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to
BA1 and BA0; CKE must be HIGH the entire time the DLL is resetting; remaining MR bits
must be “0.” Mode Register (MR) (page 78) for all MR requirements.
9. Issue PRECHARGE ALL command.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Initialization

10. Issue two or more REFRESH commands.

11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation
(that is, to program operating parameters without resetting the DLL). To access the MR,
set BA0 and BA1 LOW; remaining MR bits must be set to desired settings. Mode Register
(MR) (page 78) for all MR requirements.
12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8,
and E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0
HIGH and BA1 LOW (see Extended Mode Register (EMR) (page 83) for all EMR require-
ments.
13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and
E9 to “0,” and then setting all other desired parameters. To access the extended mode
registers, EMR, set BA0 HIGH and BA1 LOW for all EMR requirements.
14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles af-
ter the DLL RESET at Tf0.
15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configura-
tion; DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the ap-
propriate configuration (x4, x8, x16); DQ represents DQ[3:0] for x4, DQ[7:0] for x8 and
DQ[15:0] for x16.
16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are
required to be decoded).

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 512Mb: x4, x8, x16 DDR2 SDRAM
ACTIVATE

ACTIVATE
Before any READ or WRITE commands can be issued to a bank within the DDR2
SDRAM, a row in that bank must be opened (activated), even when additive latency is
used. This is accomplished via the ACTIVATE command, which selects both the bank
and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may
be issued to that row subject to the tRCD specification. tRCD (MIN) should be divided
by the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVATE command on which a READ or WRITE command can be
entered. The same procedure is used to convert other specification limits from time
units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz
clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is shown in Figure 44,
which covers any case where 5 < tRCD (MIN)/tCK ื 6. Figure 44 also shows the case for
tRRD where 2 < tRRD (MIN)/tCK ื 3.

Figure 44: Example: Meeting tRRD (MIN) and tRCD (MIN)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CK#

CK

Command ACT NOP NOP ACT NOP NOP NOP NOP NOP RD/WR

Address Row Row Row Col

Bank address Bank x Bank y Bank z Bank y

tRRD tRRD
tRCD

Don’t Care

A subsequent ACTIVATE command to a different row in the same bank can only be is-
sued after the previous active row has been closed (precharged). The minimum time in-
terval between successive ACTIVATE commands to the same bank is defined by tRC.
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVATE commands to different banks is de-
fined by tRRD.
DDR2 devices with 8 banks (1Gb or larger) have an additional requirement: tFAW. This
requires no more than four ACTIVATE commands may be issued in any given tFAW
(MIN) period, as shown in Figure 45 (page 93).

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 512Mb: x4, x8, x16 DDR2 SDRAM
ACTIVATE

Figure 45: Multibank Activate Restriction

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK

Command ACT READ ACT READ ACT READ ACT READ NOP NOP ACT

Address Row Col Row Col Row Col Row Col Row

Bank address Bank a Bank a Bank b Bank b Bank c Bank c Bank d Bank d Bank e
tRRD (MIN)
tFAW (MIN)

Don’t Care

Note: 1. DDR2-533 (-37E, x4 or x8), tCK = 3.75ns, BL = 4, AL = 3, CL = 4, tRRD (MIN) = 7.5ns, tFAW
(MIN) = 37.5ns.

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 512Mb: x4, x8, x16 DDR2 SDRAM
READ

READ
READ bursts are initiated with a READ command. The starting column and bank ad-
dresses are provided with the READ command, and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address will
be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL: RL =
AL + CL. The value for AL and CL are programmable via the MR and EMR commands,
respectively. Each subsequent data-out element will be valid nominally at the next posi-
tive or negative clock edge (at the next crossing of CK and CK#). Figure 46 (page 95)
shows examples of RL based on different AL and CL settings.
DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state
on DQS and the HIGH state on DQS# are known as the read preamble (tRPRE). The
LOW state on DQS and the HIGH state on DQS# coincident with the last data-out ele-
ment are known as the read postamble (tRPST).
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out
window hold), and the valid data window are depicted in Figure 55 (page 103) and Fig-
ure 56 (page 104). A detailed explanation of tDQSCK (DQS transition skew to CK) and
tAC (data-out transition skew to CK) is shown in Figure 57 (page 105).

Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued x cycles after the first READ command, where x equals BL/2 cycles (see Figure 47
(page 96)).
Nonconsecutive read data is illustrated in Figure 48 (page 97). Full-speed random read
accesses within a page (or pages) can be performed. DDR2 SDRAM supports the use of
concurrent auto precharge timing (see Table 42 (page 100)).
DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4
operations. Once the BL = 4 READ command is registered, it must be allowed to com-
plete the entire READ burst. However, a READ (with auto precharge disabled) using BL =
8 operation may be interrupted and truncated only by another READ burst as long as
the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of
DDR2 SDRAM. As shown in Figure 49 (page 98), READ burst BL = 8 operations may
not be interrupted or truncated with any other command except another READ com-
mand.
Data from any READ burst must be completed before a subsequent WRITE burst is al-
lowed. An example of a READ burst followed by a WRITE burst is shown in Figure 50
(page 98). The tDQSS (NOM) case is shown (tDQSS [MIN] and tDQSS [MAX] are de-
fined in Figure 58 (page 107)).

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 512Mb: x4, x8, x16 DDR2 SDRAM
READ

Figure 46: READ Latency

T0 T1 T2 T3 T3n T4 T4n T5
CK#
CK

Command READ NOP NOP NOP NOP NOP

Address Bank a,
Col n
RL = 3 (AL = 0, CL = 3)

DQS, DQS#

DQ DO
n

T0 T1 T2 T3 T4 T4n T5 T5n
CK#
CK

Command READ NOP NOP NOP NOP NOP

Address Bank a,
Col n
AL = 1 CL = 3
RL = 4 (AL = 1 + CL = 3)

DQS, DQS#

DQ DO
n

T0 T1 T2 T3 T3n T4 T4n T5
CK#
CK

Command READ NOP NOP NOP NOP NOP

Address Bank a,
Col n
RL = 4 (AL = 0, CL = 4)

DQS, DQS#

DQ DO
n

Transitioning Data Don’t Care

Notes: 1. DO n = data-out from column n.

2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following
DO n.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.

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 512Mb: x4, x8, x16 DDR2 SDRAM
READ

Figure 47: Consecutive READ Bursts

T0 T1 T2 T3 T3n T4 T4n T5 T5n T6 T6n
CK#
CK
Command READ NOP READ NOP NOP NOP NOP

Address Bank, Bank,

Col n Col b
tCCD

RL = 3
DQS, DQS#

DO DO
DQ n b

T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n T6 T6n

CK#
CK
Command READ NOP READ NOP NOP NOP NOP

Address Bank, Bank,

Col n Col b
tCCD

RL = 4

DQS, DQS#

DO DO
DQ n b

Transitioning Data Don’t Care

Notes: 1. DO n (or b) = data-out from column n (or column b).

2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following
DO n.
4. Three subsequent elements of data-out appear in the programmed order following
DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. Example applies only when READ commands are issued to same device.

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 512Mb: x4, x8, x16 DDR2 SDRAM
READ

Figure 48: Nonconsecutive READ Bursts

T0 T1 T2 T3 T3n T4 T4n T5 T6 T6n T7 T7n T8
CK#
CK
Command READ NOP NOP READ NOP NOP NOP NOP NOP

Address Bank, Bank,

Col n Col b

CL = 3

DQS, DQS#

DQ DO DO
n b
T0 T1 T2 T3 T4 T4n T5 T5n T6 T7 T7n T8
CK#
CK
Command READ NOP NOP READ NOP NOP NOP NOP NOP

Address Bank, Bank,

Col n Col b

CL = 4

DQS, DQS#

DQ DO DO
n b

Transitioning Data Don’t Care

Notes: 1. DO n (or b) = data-out from column n (or column b).

2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following
DO n.
4. Three subsequent elements of data-out appear in the programmed order following
DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. Example applies when READ commands are issued to different devices or nonconsecu-
tive READs.

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 512Mb: x4, x8, x16 DDR2 SDRAM
READ

Figure 49: READ Interrupted by READ

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CK#
CK
Command READ1 NOP2 READ3 NOP2 Valid Valid Valid Valid Valid Valid

Address Valid4 Valid4

A10 Valid5

DQS, DQS#

DQ DO DO DO DO DO DO DO DO DO DO DO DO

CL = 3 (AL = 0)
tCCD CL = 3 (AL = 0)

Transitioning Data Don’t Care

Notes: 1. BL = 8 required; auto precharge must be disabled (A10 = LOW).

2. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be is-
sued to banks used for READs at T0 and T2.
3. Interrupting READ command must be issued exactly 2 × tCK from previous READ.
4. READ command can be issued to any valid bank and row address (READ command at T0
and T2 can be either same bank or different bank).
5. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the in-
terrupting READ command.
6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal tAC, tDQSCK, and
tDQSQ.

Figure 50: READ-to-WRITE

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
Command ACT n READ n NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP

DQS, DQS#
tRCD = 3 WL = RL - 1 = 4
DQ DO DO DO DO DI DI DI DI
n n+1 n+2 n+3 n n+1 n+2 n+3
AL = 2 CL = 3

RL = 5

Transitioning Data Don’t Care

Notes: 1. BL = 4; CL = 3; AL = 2.
2. Shown with nominal tAC, tDQSCK, and tDQSQ.

READ with Precharge

A READ burst may be followed by a PRECHARGE command to the same bank, provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-
ing to the same bank has two requirements that must be satisfied: AL + BL/2 clocks and
tRTP. tRTP is the minimum time from the rising clock edge that initiates the last 4-bit

prefetch of a READ command to the PRECHARGE command. For BL = 4, this is the time
from the actual READ (AL after the READ command) to PRECHARGE command. For BL
= 8, this is the time from AL + 2 × CK after the READ-to-PRECHARGE command. Follow-

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 512Mb: x4, x8, x16 DDR2 SDRAM
READ

ing the PRECHARGE command, a subsequent command to the same bank cannot be
issued until tRP is met. However, part of the row precharge time is hidden during the
access of the last data elements.
Examples of READ-to-PRECHARGE for BL = 4 are shown in Figure 51 and in Figure 52
for BL = 8. The delay from READ-to-PRECHARGE period to the same bank is AL + BL/2 -
2CK + MAX (tRTP/tCK or 2 × CK) where MAX means the larger of the two.

Figure 51: READ-to-PRECHARGE – BL = 4

4-bit
prefetch
T0 T1 T2 T3 T4 T5 T6 T7
CK#
CK
Command READ NOP NOP PRE NOP NOP ACT NOP
AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)

Address Bank a Bank a Bank a

A10 Valid Valid

AL = 1 CL = 3

DQS, DQS#
•tRTP (MIN)
DQ DO DO DO DO
•tRAS (MIN) •tRP (MIN)

•tRC (MIN)

Transitioning Data Don’t Care

Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 4.

2. tRTP ุ 2 clocks.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.

Figure 52: READ-to-PRECHARGE – BL = 8

First 4-bit Second 4-bit
prefetch prefetch
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
Command READ NOP NOP NOP NOP PRE NOP NOP ACT
AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)
Address Bank a Bank a Bank a

A10 Valid Valid

AL = 1 CL = 3

DQS, DQS#

DQ DO DO DO DO DO DO DO DO
•tRTP (MIN) •tRP (MIN)

•tRAS (MIN)

•tRC (MIN)

Transitioning Data Don’t Care

Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 8.

2. tRTP ุ 2 clocks.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.

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 512Mb: x4, x8, x16 DDR2 SDRAM
READ

READ with Auto Precharge

If A10 is high when a READ command is issued, the READ with auto precharge function
is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock
edge that is AL + (BL/2) cycles later than the read with auto precharge command provi-
ded tRAS (MIN) and tRTP are satisfied. If tRAS (MIN) is not satisfied at this rising clock
edge, the start point of the auto precharge operation will be delayed until tRAS (MIN) is
satisfied. If tRTP (MIN) is not satisfied at this rising clock edge, the start point of the au-
to precharge operation will be delayed until tRTP (MIN) is satisfied. When the internal
precharge is pushed out by tRTP, tRP starts at the point where the internal precharge
happens (not at the next rising clock edge after this event).
When BL = 4, the minimum time from READ with auto precharge to the next ACTIVATE
command is AL + (tRTP + tRP)/tCK. When BL = 8, the minimum time from READ with
auto precharge to the next ACTIVATE command is AL + 2 clocks + (tRTP + tRP)/tCK. The
term (tRTP + tRP)/tCK is always rounded up to the next integer. A general purpose equa-
tion can also be used: AL + BL/2 - 2CK + (tRTP + tRP)/tCK. In any event, the internal pre-
charge does not start earlier than two clocks after the last 4-bit prefetch.
READ with auto precharge command may be applied to one bank while another bank is
operational. This is referred to as concurrent auto precharge operation, as noted in Ta-
ble 42. Examples of READ with precharge and READ with auto precharge with applica-
ble timing requirements are shown in Figure 53 (page 101) and Figure 54 (page 102),
respectively.

Table 42: READ Using Concurrent Auto Precharge

Minimum Delay
From Command (Bank n) To Command (Bank m) (with Concurrent Auto Precharge) Units
READ with auto precharge READ or READ with auto precharge BL/2 tCK

WRITE or WRITE with auto precharge (BL/2) + 2 tCK

PRECHARGE or ACTIVATE 1 tCK

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 512Mb: x4, x8, x16 DDR2 SDRAM
READ

Figure 53: Bank Read – Without Auto Precharge

T0 T1 T2 T3 T4 T5 T6 T7 T7n T8 T8n T9
CK#
CK
tCK tCH tCL

CKE

Command NOP1 ACT NOP1 NOP1 READ2 NOP1 PRE3 NOP1 NOP1 ACT
tRTP4

Address RA Col n RA

All banks
A10 RA 5 RA
One bank

Bank address Bank x Bank x Bank x6 Bank x

tRCD CL = 3
tRAS3 tRP

tRC

DM

tDQSCK (MIN)
Case 1: tAC (MIN) and tDQSCK (MIN) tRPRE tRPST
7 7
DQS, DQS#
tLZ (MIN)

DQ8 DO
n
tLZ (MIN) tAC (MIN) tHZ (MIN)

tDQSCK (MAX)
Case 2: tAC (MAX) and tDQSCK (MAX) tRPRE tRPST
7 7
DQS, DQS#
tLZ (MAX)

DQ8 DO
n

tLZ (MIN) tAC (MAX) tHZ (MAX)

Transitioning Data Don’t Care

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 and AL = 0 in the case shown.
3. The PRECHARGE command can only be applied at T6 if tRAS (MIN) is met.
4. READ-to-PRECHARGE = AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK).
5. Disable auto precharge.
6. “Don’t Care” if A10 is HIGH at T5.
7. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
8. DO n = data-out from column n; subsequent elements are applied in the programmed
order.

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 512Mb: x4, x8, x16 DDR2 SDRAM
READ

Figure 54: Bank Read – with Auto Precharge

T0 T1 T2 T3 T4 T5 T6 T7 T7n T8 T8n
CK#
CK
tCK tCH tCL

CKE

Command1 NOP1 ACT NOP1 READ2,3 NOP1 NOP1 NOP1 NOP1 NOP1 ACT

Address RA Col n RA

4
A10 RA RA

Bank address Bank x Bank x Bank x

AL = 1 CL = 3

tRCD tRTP
tRAS tRP

tRC

DM

tDQSCK (MIN)
Case 1: tAC (MIN) and tDQSCK (MIN) tRPRE
tRPST
5 5
DQS, DQS#
tLZ (MIN)

DQ6 DO
n

tLZ (MIN) tAC (MIN) tHZ (MIN)

tDQSCK (MAX)
Case 2: tAC (MAX) and tDQSCK (MAX) tRPRE tRPST
5 5

DQS, DQS#
tLZ (MAX)

DQ6 DO
n

t tAC (MAX) tHZ (MAX)

4-bit Internal LZ (MAX)
prefetch precharge

Transitioning Data Don’t Care

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.
3. The DDR2 SDRAM internally delays auto precharge until both tRAS (MIN) and tRTP (MIN)
have been satisfied.
4. Enable auto precharge.
5. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
6. DO n = data-out from column n; subsequent elements are applied in the programmed
order.

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 512Mb: x4, x8, x16 DDR2 SDRAM
READ

Figure 55: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window

T1 T2 T2n T3 T3n T4
CK#
CK
tHP1 tHP1 tHP1 tHP1 tHP1 tHP1

tDQSQ2 tDQSQ2 tDQSQ2 tDQSQ2

DQS#
DQS3

DQ (last data valid)

DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ (first data no longer valid)

tQH5 tQH5 tQH5 tQH5

tQHS tQHS tQHS tQHS

DQ (last data valid) T2 T2n T3 T3n

DQ (first data no longer valid) T2 T2n T3 T3n

All DQs and DQS collectively6 T2 T2n T3 T3n

Earliest signal transition
Latest signal transition
Data Data Data Data
valid valid valid valid
window window window window

Notes: 1. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.
2. tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
3. DQ transitioning after the DQS transition defines the tDQSQ window. DQS transitions at
T2 and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”
4. DQ0, DQ1, DQ2, DQ3 for x4 or DQ[7:0] for x8.
5. tQH is derived from tHP: tQH = tHP - tQHS.
6. The data valid window is derived for each DQS transition and is defined as tQH - tDQSQ.

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 512Mb: x4, x8, x16 DDR2 SDRAM
READ

Figure 56: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window

T1 T2 T2n T3 T3n T4
CK#
CK
tHP1 tHP1 tHP1 tHP1 tHP1 tHP1

tDQSQ2 tDQSQ2 tDQSQ2 tDQSQ2

LDSQ#
LDQS3

DQ (last data valid)4

DQ4
DQ4
DQ4
DQ4
DQ4

Lower Byte
DQ4
DQ (first data no longer valid)4

tQH5 tQH5 tQH5 tQH5

tQHS tQHS tQHS tQHS

DQ (last data valid)4 T2 T2n T3 T3n

DQ (first data no longer valid)4 T2 T2n T3 T3n

DQ0–DQ7 and LDQS collectively6 T2 T2n T3 T3n

Data valid Data valid Data valid Data valid

window window window window
tDQSQ2 tDQSQ2 tDQSQ2 tDQSQ2

UDQS#
UDQS3

DQ (last data valid)7

DQ7
DQ7
DQ7
DQ7

Upper Byte
DQ7
DQ7
DQ (first data no longer valid)7

tQH5 tQH5 tQH5 tQH5

tQHS tQHS tQHS tQHS

DQ (last data valid)7 T2 T2n T3 T3n

DQ (first data no longer valid)7 T2 T2n T3 T3n

DQ8–DQ15 and UDQS collectively6 T2 T2n T3 T3n

Data valid Data valid Data valid Data valid

window window window window

Notes: 1. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.
2. tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
3. DQ transitioning after the DQS transitions define the tDQSQ window. LDQS defines the
lower byte, and UDQS defines the upper byte.
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.

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 512Mb: x4, x8, x16 DDR2 SDRAM
WRITE

5. tQH is derived from tHP: tQH = tHP - tQHS.

6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

Figure 57: Data Output Timing – tAC and tDQSCK

T01 T1 T2 T3 T3n T4 T4n T5 T5n T6 T6n T7

CK#
CK
tHZ (MAX)
tLZ (MIN) tDQSCK2 (MIN) tDQSCK2 (MAX)
tRPRE tRPST

DQS#/DQS or
LDQS#/LDQS/UDQ#/UDQS3

DQ (last data valid) T3 T3n T4 T4n T5 T5n T6 T6n

DQ (first data valid) T3 T3n T4 T4n T5 T5n T6 T6n

All DQs collectively4 T3 T3n T4 T4n T5 T5n T6 T6n

tLZ (MIN) tAC5 (MIN) tAC5 (MAX) tHZ (MAX)

Notes: 1. READ command with CL = 3, AL = 0 issued at T0.

2. tDQSCK is the DQS output window relative to CK and is the long-term component of
DQS skew.
3. DQ transitioning after DQS transitions define tDQSQ window.
4. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
5. tAC is the DQ output window relative to CK and is the “long term” component of DQ
skew.
6. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.
7. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.
8. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.

WRITE
WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL
minus one clock cycle (WL = RL - 1CK) (see READ (page 77)). The starting column and
bank addresses are provided with the WRITE command, and auto precharge is either
enabled or disabled for that access. If auto precharge is enabled, the row being accessed
is precharged at the completion of the burst.
Note: For the WRITE commands used in the following illustrations, auto precharge is
disabled.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be reg-
istered on successive edges of DQS. The LOW state on DQS between the WRITE com-
mand and the first rising edge is known as the write preamble; the LOW state on DQS
following the last data-in element is known as the write postamble.
The time between the WRITE command and the first rising DQS edge is WL ± tDQSS.
Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as
±tDQSS. tDQSS is specified with a relatively wide range (25% of one clock cycle). All of

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 512Mb: x4, x8, x16 DDR2 SDRAM
WRITE

the WRITE diagrams show the nominal case, and where the two extreme cases ( tDQSS
[MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Figure 58
(page 107) shows the nominal case and the extremes of tDQSS for BL = 4. Upon com-
pletion of a burst, assuming no other commands have been initiated, the DQ will re-
main High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide continuous flow of input data. The first data element from the new burst is ap-
plied after the last element of a completed burst. The new WRITE command should be
issued x cycles after the first WRITE command, where x equals BL/2.
Figure 59 (page 108) shows concatenated bursts of BL = 4 and how full-speed random
write accesses within a page or pages can be performed. An example of nonconsecutive
WRITEs is shown in Figure 60 (page 108). DDR2 SDRAM supports concurrent auto pre-
charge options, as shown in Table 43.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4
operation. Once the BL = 4 WRITE command is registered, it must be allowed to com-
plete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto pre-
charge disabled) might be interrupted and truncated only by another WRITE burst as
long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture
of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated
with any command except another WRITE command, as shown in Figure 61
(page 109).
Data for any WRITE burst may be followed by a subsequent READ command. To follow
a WRITE, tWTR should be met, as shown in Figure 62 (page 110). The number of clock
cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any
WRITE burst may be followed by a subsequent PRECHARGE command. tWR must be
met, as shown in Figure 63 (page 111). tWR starts at the end of the data burst, regardless
of the data mask condition.

Table 43: WRITE Using Concurrent Auto Precharge

From Command To Command Minimum Delay

(Bank n) (Bank m) (with Concurrent Auto Precharge) Units
WRITE with auto precharge READ or READ with auto precharge (CL - 1) + (BL/2) + tWTR tCK

WRITE or WRITE with auto precharge (BL/2) tCK

PRECHARGE or ACTIVATE 1 tCK

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 512Mb: x4, x8, x16 DDR2 SDRAM
WRITE

Figure 58: Write Burst

T0 T1 T2 T2n T3 T3n T4
CK#
CK

Command WRITE NOP NOP NOP NOP

Address Bank a,
Col b

t DQSS (NOM) WL ± tDQSS

5
DQS, DQS#

DI
DQ b

DM

t DQSS (MIN) WL - tDQSS tDQSS5

DQS, DQS#

DI
DQ b

DM

t DQSS (MAX) WL + tDQSS tDQSS5

DQS, DQS#
DI
DQ b

DM

Transitioning Data Don’t Care

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.
2. DI b = data-in for column b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI b.
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. A10 is LOW with the WRITE command (auto precharge is disabled).

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WRITE

Figure 59: Consecutive WRITE-to-WRITE

T0 T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n T6
CK#
CK

Command WRITE NOP WRITE NOP NOP NOP NOP

tCCD

WL = 2 WL = 2

Address Bank, Bank,

Col b Col n

tDQSS (NOM) WL ± tDQSS

1 1 1
DQS, DQS#

DQ DI DI
b n

DM

Transitioning Data Don’t Care

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.
2. DI b, etc. = data-in for column b, etc.
3. Three subsequent elements of data-in are applied in the programmed order following
DI b.
4. Three subsequent elements of data-in are applied in the programmed order following
DI n.
5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
6. Each WRITE command may be to any bank.

Figure 60: Nonconsecutive WRITE-to-WRITE

T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n T6 T6n
CK#
CK

Command WRITE NOP NOP WRITE NOP NOP NOP

WL = 2 WL = 2

Address Bank, Bank,

Col b Col n

tDQSS (NOM) WL ± tDQSS

1 1 1
DQS, DQS#

DQ DI DI
b n

DM

Transitioning Data Don’t Care

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.
2. DI b (or n), etc. = data-in for column b (or column n).
3. Three subsequent elements of data-in are applied in the programmed order following
DI b.
4. Three subsequent elements of data-in are applied in the programmed order following
DI n.
5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
6. Each WRITE command may be to any bank.

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 512Mb: x4, x8, x16 DDR2 SDRAM
WRITE

Figure 61: WRITE Interrupted by WRITE

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CK#
CK
Command WRITE1 a NOP2 WRITE3 b NOP2 NOP2 NOP2 NOP2 Valid4 Valid4 Valid4

Address Valid5 Valid5

A10 Valid6
7 7 7 7 7
DQS, DQS#

DQ DI DI DI DI DI DI DI DI DI DI DI DI
a a+1 a+2 a+3 b b+1 b+2 b+3 b+4 b+5 b+6 b+7
WL = 3
2-clock requirement WL = 3
Transitioning Data Don’t Care

Notes: 1. BL = 8 required and auto precharge must be disabled (A10 = LOW).

2. The NOP or COMMAND INHIBIT commands are valid. The PRECHARGE command cannot
be issued to banks used for WRITEs at T0 and T2.
3. The interrupting WRITE command must be issued exactly 2 × tCK from previous WRITE.
4. The earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 + tWR where tWR
starts with T7 and not T5 (because BL = 8 from MR and not the truncated length).
5. The WRITE command can be issued to any valid bank and row address (WRITE command
at T0 and T2 can be either same bank or different bank).
6. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the in-
terrupting WRITE command.
7. Subsequent rising DQS signals must align to the clock within tDQSS.
8. Example shown uses AL = 0; CL = 4, BL = 8.

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WRITE

Figure 62: WRITE-to-READ

T0 T1 T2 T2n T3 T3n T4 T5 T6 T7 T8 T9 T9n

CK#
CK
Command WRITE NOP NOP NOP NOP NOP READ NOP NOP NOP
tWTR1
Address Bank a, Bank a,
Col b Col n

t DQSS (NOM) WL ± tDQSS CL = 3

2
DQS, DQS#

DI DI
DQ b

DM

t DQSS (MIN) WL - tDQSS CL = 3

2
DQS, DQS#

DI DI
DQ b

DM

t DQSS (MAX) WL + tDQSS CL = 3

2
DQS, DQS#

DI
DQ b DI

DM

Transitioning Data Don’t Care

Notes: 1. tWTR is required for any READ following a WRITE to the same device, but it is not re-
quired between module ranks.
2. Subsequent rising DQS signals must align to the clock within tDQSS.
3. DI b = data-in for column b; DO n = data-out from column n.
4. BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. One subsequent element of data-in is applied in the programmed order following DI b.
6. tWTR is referenced from the first positive CK edge after the last data-in pair.
7. A10 is LOW with the WRITE command (auto precharge is disabled).
8. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is
greater.

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WRITE

Figure 63: WRITE-to-PRECHARGE

T0 T1 T2 T2n T3 T3n T4 T5 T6 T7
CK#
CK

Command WRITE NOP NOP NOP NOP NOP NOP PRE

tWR tRP

Address Bank a, Bank,

Col b (a or all)

t DQSS (NOM) WL + tDQSS 1

DQS#
DQS

DI
DQ b

DM

t DQSS (MIN) WL - tDQSS

1
DQS#
DQS
DI
DQ b

DM

t DQSS (MAX) WL + tDQSS

1
DQS#
DQS

DI
DQ b

DM

Transitioning Data Don’t Care

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.
2. DI b = data-in for column b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI b.
4. BL = 4, CL = 3, AL = 0; thus, WL = 2.
5. tWR is referenced from the first positive CK edge after the last data-in pair.
6. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE
and WRITE commands may be to different banks, in which case tWR is not required and
the PRECHARGE command could be applied earlier.
7. A10 is LOW with the WRITE command (auto precharge is disabled).

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 512Mb: x4, x8, x16 DDR2 SDRAM
WRITE

Figure 64: Bank Write – Without Auto Precharge

T0 T1 T2 T3 T4 T5 T5n T6 T6n T7 T8 T9
CK#
CK
tCK tCH tCL

CKE

Command NOP1 ACT NOP1 WRITE2 NOP1 NOP1 NOP1 NOP1 NOP1 PRE

Address RA Col n

All banks
A10 RA 3
One bank

Bank select Bank x Bank x Bank x4

tRCD WL = 2 tWR

tRAS tRP

WL ±tDQSS (NOM)
5
DQS, DQS#

tWPRE tDQSL tDQSH tWPST

DQ6 DI
n

DM

Transitioning Data Don’t Care

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 and AL = 0 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T9.
5. Subsequent rising DQS signals must align to the clock within tDQSS.
6. DI n = data-in for column n; subsequent elements are applied in the programmed order.
7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.

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 512Mb: x4, x8, x16 DDR2 SDRAM
WRITE

Figure 65: Bank Write – with Auto Precharge

T0 T1 T2 T3 T4 T5 T5n T6 T6n T7 T8 T9
CK#
CK
tCK tCH tCL

CKE

Command NOP1 ACT NOP1 WRITE2 NOP1 NOP1 NOP1 NOP1 NOP1 NOP1

Address RA Col n

3
A10 RA

Bank select Bank x Bank x

tRCD WL = 2 WR4
tRAS tRP

WL ±tDQSS (NOM)
5
DQS, DQS#
tWPRE tDQSL tDQSH tWPST

DQ6 DI
n

DM

Transitioning Data Don’t Care

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 and AL = 0 in the case shown.
3. Enable auto precharge.
4. WR is programmed via MR9–MR11 and is calculated by dividing tWR (in ns) by tCK and
rounding up to the next integer value.
5. Subsequent rising DQS signals must align to the clock within tDQSS.
6. DI n = data-in from column n; subsequent elements are applied in the programmed or-
der.
7. DSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
t

8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.

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 512Mb: x4, x8, x16 DDR2 SDRAM
WRITE

Figure 66: WRITE – DM Operation

T0 T1 T2 T3 T4 T5 T6 T6n T7 T7n T8 T9 T10 T11

CK#
CK
tCK tCH tCL

CKE

Command NOP1 ACT NOP1 WRITE2 NOP1 NOP1 NOP1 NOP1 NOP1 NOP1 NOP1 PRE
AL = 1 WL = 2
Address RA Col n

All banks
A10 RA 3
One bank

Bank select Bank x Bank x Bank x4

tRCD tWR5
tRAS tRPA
WL ±tDQSS (NOM)
6
DQS, DQS#
tWPRE tDQSL tDQSH tWPST

DQ7 DI
n

DM

Transitioning Data Don’t Care

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4, AL = 1, and WL = 2 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T11.
5. tWR starts at the end of the data burst regardless of the data mask condition.
6. Subsequent rising DQS signals must align to the clock within tDQSS.
7. DI n = data-in for column n; subsequent elements are applied in the programmed order.
8. tDSH is applicable during tDQSS (MIN) and is referenced from CK T6 or T7.
9. tDSS is applicable during tDQSS (MAX) and is referenced from CK T7 or T8.

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 512Mb: x4, x8, x16 DDR2 SDRAM
PRECHARGE

Figure 67: Data Input Timing

T0 T1 T1n T2 T2n T3 T3n T4
CK#

CK

WL - tDQSS (NOM) t DSH 1 t DSS 2 t DSH 1 t DSS 2

3
DQS
DQS#
t DQSL t DQSH t WPST
t WPRE

DQ DI

DM

Transitioning Data Don’t Care

1. tDSH (MIN) generally occurs during tDQSS (MIN).

Notes:
2. tDSS (MIN) generally occurs during tDQSS (MAX).
3. Subsequent rising DQS signals must align to the clock within tDQSS.
4. WRITE command issued at T0.
5. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
6. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.

PRECHARGE
Precharge can be initiated by either a manual PRECHARGE command or by an autopre-
charge in conjunction with either a READ or WRITE command. Precharge will deacti-
vate the open row in a particular bank or the open row in all banks. The PRECHARGE
operation is shown in the previous READ and WRITE operation sections.
During a manual PRECHARGE command, the A10 input determines whether one or all
banks are to be precharged. In the case where only one bank is to be precharged, bank
address inputs determine the bank to be precharged. When all banks are to be pre-
charged, the bank address inputs are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and must be activated prior to
any READ or WRITE commands being issued to that bank. When a single-bank PRE-
CHARGE command is issued, tRP timing applies. When the PRECHARGE (ALL) com-
mand is issued, tRPA timing applies, regardless of the number of banks opened.

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 512Mb: x4, x8, x16 DDR2 SDRAM
REFRESH

REFRESH
The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in-
terval of 7.8125μs (MAX) and all rows in all banks must be refreshed at least once every
64ms. The refresh period begins when the REFRESH command is registered and ends
tRFC (MIN) later. The average interval must be reduced to 3.9μs (MAX) when T exceeds
C
85°C.

Figure 68: Refresh Mode

T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2

CK#
CK
tCK tCH tCL

CKE

Command NOP1 PRE NOP1 NOP1 REF NOP1 REF2 NOP1 NOP1 ACT

Address RA

All banks
A10 RA
One bank

Bank Bank(s)3 BA

DQS, DQS#4

DQ4

DM4
tRP tRFC (MIN) tRFC2

Indicates a break in
Don’t Care
time scale

Notes: 1. NOP commands are shown for ease of illustration; other valid commands may be possi-
ble at these times. CKE must be active during clock positive transitions.
2. The second REFRESH is not required and is only shown as an example of two back-to-
back REFRESH commands.
3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is
active (must precharge all active banks).
4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.

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 512Mb: x4, x8, x16 DDR2 SDRAM
SELF REFRESH

SELF REFRESH
The SELF REFRESH command is initiated when CKE is LOW. The differential clock
should remain stable and meet tCKE specifications at least 1 × tCK after entering self re-
fresh mode. The procedure for exiting self refresh requires a sequence of commands.
First, the differential clock must be stable and meet tCK specifications at least 1 × tCK
prior to CKE going back to HIGH. Once CKE is HIGH (tCKE [MIN] has been satisfied
with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-
mands issued for tXSNR. A simple algorithm for meeting both refresh and DLL require-
ments is used to apply NOP or DESELECT commands for 200 clock cycles before apply-
ing any other command.

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 512Mb: x4, x8, x16 DDR2 SDRAM
SELF REFRESH

Figure 69: Self Refresh

T0 T1 T2 Ta0 Ta1 Ta2 Tb0 Tc0 Td0

CK#
CK1
tCH tCL tCK1 tCK1 tISXR2 tCKE3 W ,+

CKE1

Command NOP REF NOP4 NOP4 Valid 5 Valid5

W ,+

ODT6
tAOFD/tAOFPD6

Address Valid Valid7

DQS#, DQS

DQ

DM

tCKE (MIN)9 tXSNR2, 5, 10

tRP8
tXSRD2, 7
Enter self refresh Exit self refresh
mode (synchronous) mode (asynchronous)
Indicates a break in Don’t Care
time scale

Notes: 1. Clock must be stable and meeting tCK specifications at least 1 × tCK after entering self
refresh mode and at least 1 × tCK prior to exiting self refresh mode.
2. Self refresh exit is asynchronous; however, tXSNR and tXSRD timing starts at the first ris-
ing clock edge where CKE HIGH satisfies tISXR.
3. CKE must stay HIGH until tXSRD is met; however, if self refresh is being re-entered, CKE
may go back LOW after tXSNR is satisfied.
4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0,
which allows any nonREAD command.
5. tXSNR is required before any nonREAD command can be applied.
6. ODT must be disabled and RTT off (tAOFD and tAOFPD have been satisfied) prior to en-
tering self refresh at state T1.
7. tXSRD (200 cycles of CK) is required before a READ command can be applied at state
Td0.
8. Device must be in the all banks idle state prior to entering self refresh mode.
9. After self refresh has been entered, tCKE (MIN) must be satisfied prior to exiting self re-
fresh.
10. Upon exiting SELF REFRESH, ODT must remain LOW until tXSRD is satisfied.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode

Power-Down Mode
DDR2 SDRAM supports multiple power-down modes that allow significant power sav-
ings over normal operating modes. CKE is used to enter and exit different power-down
modes. Power-down entry and exit timings are shown in Figure 70 (page 120). Detailed
power-down entry conditions are shown in Figure 71 (page 122)–Figure 78 (page 125).
Table 44 (page 121) is the CKE Truth Table.
DDR2 SDRAM requires CKE to be registered HIGH (active) at all times that an access is
in progress—from the issuing of a READ or WRITE command until completion of the
burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined
when the read postamble is satisfied; for WRITEs, a burst completion is defined when
the write postamble and tWR (WRITE-to-PRECHARGE command) or tWTR (WRITE-to-
READ command) are satisfied, as shown in Figure 73 (page 123) and Figure 74
(page 123) on Figure 74 (page 123). The number of clock cycles required to meet tWTR
is either two or tWTR/tCK, whichever is greater.
Power-down mode (see Figure 70 (page 120)) is entered when CKE is registered low co-
incident with an NOP or DESELECT command. CKE is not allowed to go LOW during a
mode register or extended mode register command time, or while a READ or WRITE op-
eration is in progress. If power-down occurs when all banks are idle, this mode is refer-
red to as precharge power-down. If power-down occurs when there is a row active in
any bank, this mode is referred to as active power-down. Entering power-down deacti-
vates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum
power savings, the DLL is frozen during precharge power-down. Exiting active power-
down requires the device to be at the same voltage and frequency as when it entered
power-down. Exiting precharge power-down requires the device to be at the same volt-
age as when it entered power-down; however, the clock frequency is allowed to change
(see Precharge Power-Down Clock Frequency Change (page 126)).
The maximum duration for either active or precharge power-down is limited by the re-
fresh requirements of the device tRFC (MAX). The minimum duration for power-down
entry and exit is limited by the tCKE (MIN) parameter. The following must be main-
tained while in power-down mode: CKE LOW, a stable clock signal, and stable power
supply signals at the inputs of the DDR2 SDRAM. All other input signals are “Don’t
Care” except ODT. Detailed ODT timing diagrams for different power-down modes are
shown in Figure 83 (page 131)–Figure 88 (page 135).
The power-down state is synchronously exited when CKE is registered HIGH (in con-
junction with a NOP or DESELECT command), as shown in Figure 70 (page 120).

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 512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode

Figure 70: Power-Down

T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
tCK tCH tCL

Command Valid1 NOP NOP NOP Valid Valid

tCKE (MIN)2

tIH
CKE
tIH
tCKE (MIN)2
tIS

Address Valid Valid Valid

tXP3, tXARD4

tXARDS5

DQS, DQS#

DQ

DM

Enter Exit
power-down power-down
Don’t Care
mode6 mode

Notes: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVATE
(or if at least one row is already active), then the power-down mode shown is active
power-down.
2. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive
clock edges. CKE must remain at the valid input level the entire time it takes to achieve
the three clocks of registration. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of tIS + 2 × tCK + tIH. CKE must not transition
during its tIS and tIH window.
3. tXP timing is used for exit precharge power-down and active power-down to any non-
READ command.
4. tXARD timing is used for exit active power-down to READ command if fast exit is selec-
ted via MR (bit 12 = 0).
5. tXARDS timing is used for exit active power-down to READ command if slow exit is se-
lected via MR (bit 12 = 1).
6. No column accesses are allowed to be in progress at the time power-down is entered. If
the DLL was not in a locked state when CKE went LOW, the DLL must be reset after exit-
ing power-down mode for proper READ operation.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode

Table 44: Truth Table – CKE

Notes 1–4 apply to the entire table
CKE Command (n)
Previous Cycle Current CS#, RAS#, CAS#,
Current State (n - 1) Cycle (n) WE# Action (n) Notes
Power-down L L X Maintain power-down 5, 6
L H DESELECT or NOP Power-down exit 7, 8
Self refresh L L X Maintain self refresh 6
L H DESELECT or NOP Self refresh exit 7, 9, 10
Bank(s) active H L DESELECT or NOP Active power-down en- 7, 8, 11, 12
try
All banks idle H L DESELECT or NOP Precharge power-down 7, 8, 11
entry
H L Refresh Self refresh entry 10, 12, 13
H H Shown in Table 37 (page 72) 14

Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the
previous clock edge.
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.
3. Command (n) is the command registered at clock edge n, and action (n) is a result of
command (n).
4. The state of ODT does not affect the states described in this table. The ODT function is
not available during self refresh (see ODT Timing (page 129) for more details and spe-
cific restrictions).
5. Power-down modes do not perform any REFRESH operations. The duration of power-
down mode is therefore limited by the refresh requirements.
6. “X” means “Don’t Care” (including floating around VREF) in self refresh and power-
down. However, ODT must be driven high or low in power-down if the ODT function is
enabled via EMR.
7. All states and sequences not shown are illegal or reserved unless explicitly described
elsewhere in this document.
8. Valid commands for power-down entry and exit are NOP and DESELECT only.
9. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge oc-
curring during the tXSNR period. READ commands may be issued only after tXSRD (200
clocks) is satisfied.
10. Valid commands for self refresh exit are NOP and DESELECT only.
11. Power-down and self refresh can not be entered while READ or WRITE operations,
LOAD MODE operations, or PRECHARGE operations are in progress. See SELF REFRESH
(page 117) and SELF REFRESH (page 78) for a list of detailed restrictions.
12. Minimum CKE high time is tCKE = 3 × tCK. Minimum CKE LOW time is tCKE = 3 × tCK.
This requires a minimum of 3 clock cycles of registration.
13. Self refresh mode can only be entered from the all banks idle state.
14. Must be a legal command, as defined in Table 37 (page 72).

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 512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode

Figure 71: READ-to-Power-Down or Self Refresh Entry

T0 T1 T2 T3 T4 T5 T6 T7
CK#
CK

Command READ NOP NOP NOP Valid Valid NOP1

tCKE (MIN)

CKE

Address Valid

A10

DQS, DQS#

DQ DO DO DO DO
RL = 3

Power-down2 or
self refresh entry

Transitioning Data Don’t Care

Notes: 1. In the example shown, READ burst completes at T5; earliest power-down or self refresh
entry is at T6.
2. Power-down or self refresh entry may occur after the READ burst completes.

Figure 72: READ with Auto Precharge-to-Power-Down or Self Refresh Entry

T0 T1 T2 T3 T4 T5 T6 T7
CK#
CK

Command READ NOP NOP NOP Valid Valid NOP1

tCKE (MIN)

CKE

Address Valid

A10

DQS, DQS#

DQ DO DO DO DO
RL = 3

Power-down or
self refresh2 entry

Transitioning Data Don’t Care

Notes: 1. In the example shown, READ burst completes at T5; earliest power-down or self refresh
entry is at T6.
2. Power-down or self refresh entry may occur after the READ burst completes.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode

Figure 73: WRITE-to-Power-Down or Self Refresh Entry

T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
Command WRITE NOP NOP NOP Valid Valid Valid NOP1
tCKE (MIN)

CKE

Address Valid

A10

DQS, DQS#

DQ DO DO DO DO
WL = 3 tWTR

Power-down or
self refresh entry1

Transitioning Data Don’t Care

Note: 1. Power-down or self refresh entry may occur after the WRITE burst completes.

Figure 74: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry

T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2

CK#
CK
Command WRITE NOP NOP NOP Valid Valid Valid1 NOP
tCKE (MIN)

CKE

Address Valid

A10

DQS, DQS#

DQ DO DO DO DO
WL = 3 WR2
Power-down or
self refresh entry

Indicates a break in Transitioning Data Don’t Care

time scale

Notes: 1. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may oc-
cur 1 x tCK later at Ta1, prior to tRP being satisfied.
2. WR is programmed through MR9–MR11 and represents (tWR [MIN] ns/tCK) rounded up
to next integer tCK.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode

Figure 75: REFRESH Command-to-Power-Down Entry

T0 T1 T2 T3
CK#

CK

Command Valid REFRESH NOP

tCKE (MIN)

CKE

1 x tCK

Power-down1
entry

Don’t Care

Note: 1. The earliest precharge power-down entry may occur is at T2, which is 1 × tCK after the
REFRESH command. Precharge power-down entry occurs prior to tRFC (MIN) being satis-
fied.

Figure 76: ACTIVATE Command-to-Power-Down Entry

T0 T1 T2 T3
CK#

CK

Command Valid ACT NOP

Address VALID

tCKE (MIN)

CKE

1 tCK

Power-down1
entry

Don’t Care

Note: 1. The earliest active power-down entry may occur is at T2, which is 1 × tCK after the ACTI-
VATE command. Active power-down entry occurs prior to tRCD (MIN) being satisfied.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode

Figure 77: PRECHARGE Command-to-Power-Down Entry

T0 T1 T2 T3
CK#
CK

Command Valid PRE NOP

Address Valid

All banks
A10 vs
Single bank

tCKE (MIN)

CKE

1 x tCK

Power-down1
entry
Don’t Care

Note: 1. The earliest precharge power-down entry may occur is at T2, which is 1 × tCK after the
PRECHARGE command. Precharge power-down entry occurs prior to tRP (MIN) being sat-
isfied.

Figure 78: LOAD MODE Command-to-Power-Down Entry

T0 T1 T2 T3 T4
CK#
CK

Command Valid LM NOP NOP

Address Valid1

tCKE (MIN)

CKE

tRP2 tMRD
Power-down3
entry

Don’t Care

Notes: 1. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.
2. All banks must be in the precharged state and tRP met prior to issuing LM command.
3. The earliest precharge power-down entry is at T3, which is after tMRD is satisfied.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Precharge Power-Down Clock Frequency Change

Precharge Power-Down Clock Frequency Change

When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off
and CKE must be at a logic LOW level. A minimum of two differential clock cycles must
pass after CKE goes LOW before clock frequency may change. The device input clock
frequency is allowed to change only within minimum and maximum operating fre-
quencies specified for the particular speed grade. During input clock frequency change,
ODT and CKE must be held at stable LOW levels. When the input clock frequency is
changed, new stable clocks must be provided to the device before precharge power-
down may be exited, and DLL must be reset via MR after precharge power-down exit.
Depending on the new clock frequency, additional LM commands might be required to
adjust the CL, WR, AL, and so forth. Depending on the new clock frequency, an addi-
tional LM command might be required to appropriately set the WR MR9, MR10, MR11.
During the DLL relock period of 200 cycles, ODT must remain off. After the DLL lock
time, the DRAM is ready to operate with a new clock frequency.

Figure 79: Input Clock Frequency Change During Precharge Power-Down Mode

Previous clock frequency New clock frequency

T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0
CK#
CK
tCH tCL tCH tCL
tCK tCK

2 x tCK (MIN)1 1 x tCK (MIN)2

tCKE (MIN)3

CKE tCKE (MIN)3

Command Valid4 NOP NOP NOP LM NOP Valid

Address Valid DLL RESET Valid

tXP

ODT

High-Z
DQS, DQS#

High-Z
DQ

DM

Enter precharge Frequency Exit precharge

power-down mode change 200 x tCK
power-down mode

Indicates a break in
Don’t Care
time scale

Notes: 1. A minimum of 2 × tCK is required after entering precharge power-down prior to chang-
ing clock frequencies.
2. When the new clock frequency has changed and is stable, a minimum of 1 × tCK is re-
quired prior to exiting precharge power-down.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Reset

3. Minimum CKE high time is tCKE = 3 × tCK. Minimum CKE LOW time is tCKE = 3 × tCK.
This requires a minimum of three clock cycles of registration.
4. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down, which is required prior to the clock
frequency change.

Reset
CKE Low Anytime
DDR2 SDRAM applications may go into a reset state anytime during normal operation.
If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM de-
vice resumes normal operation after reinitializing. All data will be lost during a reset
condition; however, the DDR2 SDRAM device will continue to operate properly if the
following conditions outlined in this section are satisfied.
The reset condition defined here assumes all supply voltages (VDD, V DDQ, V DDL, and
VREF) are stable and meet all DC specifications prior to, during, and after the RESET op-
eration. All other input balls of the DDR2 SDRAM device are a “Don’t Care” during RE-
SET with the exception of CKE.
If CKE asynchronously drops LOW during any valid operation (including a READ or
WRITE burst), the memory controller must satisfy the timing parameter tDELAY before
turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM be-
fore CKE is raised HIGH, at which time the normal initialization sequence must occur
(see Initialization). The DDR2 SDRAM device is now ready for normal operation after
the initialization sequence. Figure 80 (page 128) shows the proper sequence for a RE-
SET operation.

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 512Mb: x4, x8, x16 DDR2 SDRAM
Reset

Figure 80: RESET Function

T0 T1 T2 T3 T4 T5 Ta0 Tb0
tCK
CK#
CK
tCL tCL tCKE (MIN)
tDELAY
1
CKE

ODT

Command READ NOP2 READ NOP2 NOP2 NOP2 PRE

DM3

Address Col n Col n

All banks
A10

Bank address Bank a Bank b

High-Z High-Z 
DQS3
High-Z High-Z
DQ3 DO DO DO
High-Z
RTT

System T = 400ns (MIN) tRPA

RESET

Start of normal5
initialization
sequence

Indicates a break in Unknown RTT On Transitioning Data Don’t Care

time scale

Notes: 1. VDD, VDDL, VDDQ, VTT, and VREF must be valid at all times.
2. Either NOP or DESELECT command may be applied.
3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS
represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri-
ate configuration (x4, x8, x16).
4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the
completion of the burst.
5. Initialization timing is shown in Figure 43 (page 89).

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 512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing

ODT Timing
Once a 12ns delay (tMOD) has been satisfied, and after the ODT function has been ena-
bled via the EMR LOAD MODE command, ODT can be accessed under two timing cate-
gories. ODT will operate either in synchronous mode or asynchronous mode, depend-
ing on the state of CKE. ODT can switch anytime except during self refresh mode and a
few clocks after being enabled via EMR, as shown in Figure 81 (page 130).
There are two timing categories for ODT—turn-on and turn-off. During active mode
(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,
MR[12 = 0]), tAOND, tAON, tAOFD, and tAOF timing parameters are applied, as shown in
Figure 83 (page 131).
During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)
and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),
tAONPD and tAOFPD timing parameters are applied, as shown in Figure 84 (page 132).

ODT turn-off timing, prior to entering any power-down mode, is determined by the pa-
rameter tANPD (MIN), as shown in Figure 85 (page 132). At state T2, the ODT HIGH sig-
nal satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD
(MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 85 (page 132) also
shows the example where tANPD (MIN) is not satisfied because ODT HIGH does not oc-
cur until state T3. When tANPD (MIN) is not satisfied, tAOFPD timing parameters apply.
ODT turn-on timing prior to entering any power-down mode is determined by the pa-
rameter tANPD, as shown in Figure 86 (page 133). At state T2, the ODT HIGH signal sat-
isfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is
satisfied, tAOND and tAON timing parameters apply. Figure 86 (page 133) also shows
the example where tANPD (MIN) is not satisfied because ODT HIGH does not occur un-
til state T3. When tANPD (MIN) is not satisfied, tAONPD timing parameters apply.
ODT turn-off timing after exiting any power-down mode is determined by the parame-
ter tAXPD (MIN), as shown in Figure 87 (page 134). At state Ta1, the ODT LOW signal
satisfies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is
satisfied, tAOFD and tAOF timing parameters apply. Figure 87 (page 134) also shows the
example where tAXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0.
When tAXPD (MIN) is not satisfied, tAOFPD timing parameters apply.
ODT turn-on timing after exiting either slow-exit power-down mode or precharge pow-
er-down mode is determined by the parameter tAXPD (MIN), as shown in Figure 88
(page 135). At state Ta1, the ODT HIGH signal satisfies tAXPD (MIN) after exiting pow-
er-down mode at state T1. When tAXPD (MIN) is satisfied, tAOND and tAON timing pa-
rameters apply. Figure 88 (page 135) also shows the example where tAXPD (MIN) is not
satisfied because ODT HIGH occurs at state Ta0. When tAXPD (MIN) is not satisfied,
tAONPD timing parameters apply.

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 512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing

Figure 81: ODT Timing for Entering and Exiting Power-Down Mode

Synchronous Synchronous or Synchronous

Asynchronous

tANPD (3 tCKs) tAXPD (8 tCKs)

First CKE latched LOW First CKE latched HIGH

CKE

Any mode except Any mode except

self refresh mode Active power-down fast (synchronous) self refresh mode

Active power-down slow (asynchronous)

Precharge power-down (asynchronous)
Applicable modes

tAOND/tAOFD tAOND/tAOFD (synchronous) tAOND/tAOFD

tAONPD/tAOFPD (asynchronous)
Applicable timing parameters

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 512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing

MRS Command to ODT Update Delay

During normal operation, the value of the effective termination resistance can be
changed with an EMRS set command. tMOD (MAX) updates the RTT setting.

Figure 82: Timing for MRS Command to ODT Update Delay

T0 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5

Command EMRS1 NOP NOP NOP NOP NOP

CK#
CK

ODT2 2
tAOFD tMOD
tIS

0ns
Internal
RTT setting Old setting Undefined New setting

Indicates a break in
time scale

Notes: 1. The LM command is directed to the mode register, which updates the information in
EMR (A6, A2), that is, RTT (nominal).
2. To prevent any impedance glitch on the channel, the following conditions must be met:
tAOFD must be met before issuing the LM command; ODT must remain LOW for the en-

tire duration of the tMOD window until tMOD is met.

Figure 83: ODT Timing for Active or Fast-Exit Power-Down Mode

T0 T1 T2 T3 T4 T5 T6
CK#

CK
tCK tCH tCL

Command Valid Valid Valid Valid Valid Valid Valid

Address Valid Valid Valid Valid Valid Valid Valid

CKE

tAOND

ODT

tAOFD

RTT
tAON (MIN) tAOF (MAX)

tAON (MAX) tAOF (MIN)

RTT Unknown RTT On Don’t Care

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 512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing

Figure 84: ODT Timing for Slow-Exit or Precharge Power-Down Modes

T0 T1 T2 T3 T4 T5 T6 T7
CK#
CK
tCK tCH tCL

Command Valid Valid Valid Valid Valid Valid Valid Valid

Address Valid Valid Valid Valid Valid Valid Valid Valid

CKE

ODT

tAONPD (MAX)

tAONPD (MIN)

RTT
tAOFPD (MIN)
tAOFPD (MAX)

Transitioning RTT RTT Unknown RTT On Don’t Care

Figure 85: ODT Turn-Off Timings When Entering Power-Down Mode

T0 T1 T2 T3 T4 T5 T6
CK#

CK

Command NOP NOP NOP NOP NOP NOP NOP

tANPD (MIN)

CKE

tAOFD

ODT

tAOF (MAX)

RTT

tAOF (MIN)

tAOFPD (MAX)

ODT

RTT

tAOFPD (MIN)

Transitioning RTT RTT Unknown RTT ON Don’t Care

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 512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing

Figure 86: ODT Turn-On Timing When Entering Power-Down Mode

T0 T1 T2 T3 T4 T5 T6
CK#

CK

Command NOP NOP NOP NOP NOP NOP NOP

tANPD (MIN)

CKE

ODT

tAOND

tAON (MAX)

RTT
tAON (MIN)

ODT
tAONPD (MAX)

RTT
tAONPD (MIN)

Transitioning RTT RTT Unknown RTT On Don’t Care

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 512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing

Figure 87: ODT Turn-Off Timing When Exiting Power-Down Mode

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5

CK#
CK

Command NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP

tAXPD (MIN)

CKE

tCKE (MIN)

tAOFD

ODT
tAOF (MAX)
RTT
tAOF (MIN)

tAOFPD (MAX)
ODT

RTT
tAOFPD (MIN)

Indicates a break in
RTT Unknown RTT On Transitioning RTT Don’t Care
time scale

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 512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing

Figure 88: ODT Turn-On Timing When Exiting Power-Down Mode

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5

CK#
CK

Command NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP

tAXPD (MIN)

CKE
tCKE (MIN)

ODT

tAOND

tAON (MAX)
RTT
tAON (MIN)

ODT
tAONPD (MAX)

RTT
tAONPD (MIN)

Indicates a break in
RTT Unknown RTT On Transitioning RTT Don’t Care
time scale

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www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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