0% found this document useful (0 votes)

10 views61 pages

AAADoc 3

The document details specifications for 256Mb SDRAM, including various configurations (x4, x8, x16) and part numbers. It highlights features such as synchronous operation, programmable burst lengths, and auto-refresh modes. The SDRAM is designed for high-speed operation with a 3.3V power supply and includes options for different package types.

Uploaded by

Rober

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

10 views61 pages

AAADoc 3

Uploaded by

Rober

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 61

256Mb: x4, x8, x16

SDRAM

SYNCHRONOUS MT48LC64M4A2 – 16 Meg x 4 x 4 banks

MT48LC32M8A2 – 8 Meg x 8 x 4 banks

DRAM MT48LC16M16A2 – 4 Meg x 16 x 4 banks

For the latest data sheet, please refer to the Micron Web site:
www.micron.com/dramds

Features
• PC66-, PC100-, and PC133-compliant Figure 1: Pin Assignment (Top View)
• Fully synchronous; all signals registered on 54-Pin TSOP
positive edge of system clock x4 x8 x16 x16 x8 x4
• Internal pipelined operation; column address can - - - -
VDD 1 54 Vss
be changed every clock cycle NC DQ0 DQ0 2 53 DQ15 DQ7 NC
• Internal banks for hiding row access/precharge - - VDDQ 3 52 VssQ - -
NC NC DQ1 4 51 DQ14 NC NC
• Programmable burst lengths: 1, 2, 4, 8, or full page DQ0 DQ1 DQ2 5 50 DQ13 DQ6 DQ3
• Auto Precharge, includes CONCURRENT AUTO - - VssQ 6 49 VDDQ - -
NC NC DQ3 7 48 DQ12 NC NC
PRECHARGE, and Auto Refresh Modes NC DQ2 DQ4 8 47 DQ11 DQ5 NC
• Self Refresh Mode - - VDDQ 9 46 VssQ - -
NC NC DQ5 10 45 DQ10 NC NC
• 64ms, 8,192-cycle refresh DQ1 DQ3 DQ6 11 44 DQ9 DQ4 DQ2
• LVTTL-compatible inputs and outputs - - VssQ 12 43 VDDQ - -
NC NC DQ7 13 42 DQ8 NC NC
• Single +3.3V ±0.3V power supply - - VDD 14 41 Vss - -
NC NC DQML 15 40 NC - -
Options Marking - - WE# 16 39 DQMH DQM DQM
- - CAS# 17 38 CLK - -
• Configurations - - RAS# 18 37 CKE - -
- - CS# 19 36 A12 - -
64 Meg x 4 (16 Meg x 4 x 4 banks) 64M4 - - BA0 20 35 A11 - -
32 Meg x 8 ( 8 Meg x 8 x 4 banks) 32M8 - - BA1 21 34 A9 - -
- - A10 22 33 A8 - -
16 Meg x 16 ( 4 Meg x 16 x 4 banks) 16M16 - - A0 23 32 A7 - -
• WRITE Recovery (tWR) - - A1 24 31 A6 - -
- - A2 25 30 A5 - -
t
WR = “2 CLK”1 A2 - - A3 26 29 A4 - -
- - VDD 27 28 Vss - -
• Package/Pinout
Note: The # symbol indicates signal is active LOW. A dash (–)
54-pin TSOP II OCPL2 (400 mil) (standard) TG
indicates x8 and x4 pin function is same as x16 pin function.
54-pin TSOP II OCPL2 (400 mil) (lead-free) P
60-ball FBGA (x4, x8) FB4, 5
54-ball VFBGA (x16) FG3
Table 1: Address Table
64 Meg x 4 32 Meg x 8 16 Meg x 16
60-ball FBGA (x4, x8) (lead-free) BB4, 5
Configuration 16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
54-ball VFBGA (x16) (lead-free) BG3
Refresh Count 8K 8K 8K
• Timing (Cycle Time) Row Addressing 8K (A0–A12) 8K (A0–A12) 8K (A0–A12)
7.5ns @ CL = 2 (PC133) -7E Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
7.5ns @ CL = 3 (PC133) -75 Column Addressing 2K (A0–A9, A11) 1K (A0–A9) 512 (A0–A8)

• Die Revision :D
• Self Refresh Table 2: Key Timing Parameters
Standard None
Low power L3 SPEED CLOCK ACCESS TIME SETUP HOLD
GRADE FREQUENCY CL = 2* CL = 3* TIME TIME
• Operating Temperature
-7E 143 MHz – 5.4ns 1.5ns 0.8ns
Commercial (0oC to +70oC) None
-75 133 MHz – 5.4ns 1.5ns 0.8ns
Industrial (-40oC to +85oC) IT3
-7E 133 MHz 5.4ns – 1.5ns 0.8ns
NOTE: 1. Refer to Micron Technical Note TN-48-05. -75 100 MHz 6ns – 1.5ns 0.8ns
2. Off-center parting line.
3. Consult Micron for availability. *CL = CAS (READ) latency
4. Not available in x16 configuration.
5. Actual FBGA part marking shown on page 60.
Part Number Example:
MT48LC16M16A2TG-75
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MSDRAM.pmd – Rev. H; Pub. 2/05 1 ©2003 Micron Technology, Inc. All rights reserved.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
256Mb: x4, x8, x16
SDRAM

Figure 2: 60-Ball FBGA Assignment (Top View)

64 Meg x 4 SDRAM 32 Meg x 8 SDRAM

8mm x 16mm “FB” 8mm x 16mm “FB”

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

A NC Vss VDD NC A DQ7 Vss VDD DQ0

B NC VssQ VDDQ NC B NC VssQ VDDQ NC

C VDDQ DQ3 DQ0 VssQ C VDDQ DQ6 DQ1 VssQ

D NC NC NC NC D DQ5 NC NC DQ2

E NC VssQ VDDQ NC E NC VssQ VDDQ NC

F VDDQ DQ2 DQ1 VssQ F VDDQ DQ4 DQ3 VssQ

G NC NC NC NC G NC NC NC NC

H NC Vss VDD NC H NC Vss VDD NC

J NC DQM WE# CAS# J NC DQM WE# CAS#

K NC CK RAS# NC K NC CK RAS# NC

L A12 CKE NC CS# L A12 CKE NC CS#

M A11 A9 BA1 BA0 M A11 A9 BA1 BA0

N A8 A7 A0 A10 N A8 A7 A0 A10

P A6 A5 A2 A1 P A6 A5 A2 A1

R A4 Vss VDD A3 R A4 Vss VDD A3

Depopulated Balls Depopulated Balls

NOTE: FBGA pin Symbol, Type, and Descriptions are identical to the listing of the 54-pin TSOP table on page 9.

Figure 3: 54-Ball FBGA Assignment (Top View)

16 Meg x 16 SDRAM
8mm x 14mm “FG”

1 2 3 4 5 6 7 8 9

A Vss DQ15 VSSQ VDDQ DQ0 VDD

B DQ14 DQ13 VDDQ VssQ DQ2 DQ1

C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3

D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5

E DQ8 NC Vss VDD LDQM DQ7

F UDQM CLK CKE CAS# RAS# WE#

G A12 A11 A9 BA0 BA1 CS#

H A8 A7 A6 A0 A1 A10

J Vss A5 A4 A3 A2 VDD

Depopulated Balls

Table 3: 256 Mb SDRAM Part Numbers tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
PART NUMBER ARCHITECTURE PACKAGE tered coincident with the ACTIVE command are used
MT48LC64M4A2TG 64 Meg x 4 54-pin TSOP II to select the bank and row to be accessed (BA0, BA1
MT48LC64M4A2P 64 Meg x 4 54-pin TSOP II select the bank; A0–A12 select the row). The address
MT48LC64M4A2FB* 64 Meg x 4 60-ball FBGA bits registered coincident with the READ or WRITE com-
MT48LC64M4A2BB* 64 Meg x 4 60-ball FBGA mand are used to select the starting column location
MT48LC32M8A2TG 32 Meg x 8 54-pin TSOP II for the burst access.
MT48LC32M8A2P 32 Meg x 8 54-pin TSOP II The SDRAM provides for programmable READ or
MT48LC32M8A2FB* 32 Meg x 8 60-ball FBGA WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
MT48LC32M8A2BB* 32 Meg x 8 60-ball FBGA
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
MT48LC16M16A2TG 16 Meg x 16 54-pin TSOP II
precharge that is initiated at the end of the burst se-
MT48LC16M16A2P 16 Meg x 16 54-pin TSOP II
quence.
MT48LC16M16A2FG 16 Meg x 16 54-ball FBGA
The 256Mb SDRAM uses an internal pipelined ar-
MT48LC16M16A2BG 16 Meg x 16 54-ball FBGA
chitecture to achieve high-speed operation. This ar-
*Actual FBGA part marking shown on pages 60 and chitecture is compatible with the 2n rule of prefetch
61. architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
General Description speed, fully random access. Precharging one bank
The 256Mb SDRAM is a high-speed CMOS, while accessing one of the other three banks will hide
dynamic random-access memory containing the precharge cycles and provide seamless, high-
268,435,456 bits. It is internally configured as a quad- speed, random-access operation.
bank DRAM with a synchronous interface (all signals The 256Mb SDRAM is designed to operate in 3.3V
are registered on the positive edge of the clock signal, memory systems. An auto refresh mode is provided,
CLK). Each of the x4’s 67,108,864-bit banks is orga- along with a power-saving, power-down mode. All in-
nized as 8,192 rows by 2,048 columns by puts and outputs are LVTTL-compatible.
4 bits. Each of the x8’s 67,108,864-bit banks is orga- SDRAMs offer substantial advances in DRAM oper-
nized as 8,192 rows by 1,024 columns by 8 bits. Each of ating performance, including the ability to synchro-
the x16’s 67,108,864-bit banks is organized as 8,192 nously burst data at a high data rate with automatic
rows by 512 columns by 16 bits. column-address generation, the ability to interleave
Read and write accesses to the SDRAM are burst between internal banks to hide precharge time and
oriented; accesses start at a selected location and the capability to randomly change column addresses
continue for a programmed number of locations in a on each clock cycle during a burst access.
programmed sequence. Accesses begin with the regis-

Table of Contents
Functional Block Diagram – 64 Meg x 4 .................... 6 Concurrent Auto Precharge ................................. 29
Functional Block Diagram – 32 Meg x 8 .................... 7 Truth Table 2 (CKE) ...................................................... 31
Functional Block Diagram – 16 Meg x 16 .................. 8 Truth Table 3 (Current State, Same Bank) ........................ 32
Pin Descriptions .......................................................... 10 Truth Table 4 (Current State, Different Bank) .................. 34
Ball Descriptions .......................................................... 10 Absolute Maximum Ratings ....................................... 36
Functional Description ............................................... 12 DC Electrical Characteristics
Initialization ........................................................... 12 and Operating Conditions ....................................... 36
Register Definition ................................................ 12 IDD Specifications and Conditions ............................. 36
Mode Register ................................................... 12 Capacitance .................................................................. 37
Burst Length ................................................ 12 Electrical Characteristics
Burst Type ................................................... 13 and Recommended AC Operating Conditions ....... 37
CAS Latency ................................................ 14 AC Electrical Characteristics (Timing Table) ......... 38
Operating Mode .......................................... 14
Timing Waveforms
Write Burst Mode ........................................ 14
Initialize and Load mode register ........................ 40
Commands ................................................................... 15
Power-Down Mode ................................................ 41
Truth Table 1 (Commands and DQM Operation) .............. 15
Clock Suspend Mode ............................................ 42
Command Inhibit .................................................. 16
Auto Refresh Mode ................................................ 43
No Operation (NOP) .............................................. 16
Self Refresh Mode .................................................. 44
Load mode register ................................................ 16
Reads
Active ....................................................................... 16
Read – Without Auto Precharge ..................... 45
Read ....................................................................... 16
Read – With Auto Precharge ........................... 46
Write ....................................................................... 16
Single Read – Without Auto Precharge ......... 47
Precharge ................................................................ 16
Single Read – With Auto Precharge ............... 48
Auto Precharge ....................................................... 16
Alternating Bank Read Accesses .................... 49
Burst Terminate ..................................................... 17
Read – Full-Page Burst .................................... 50
Auto Refresh ........................................................... 17
Read – DQM Operation ................................... 51
Self Refresh ............................................................. 17
Writes
Operation ..................................................................... 18
Write – Without Auto Precharge ..................... 52
Bank/Row Activation ............................................. 18
Write – With Auto Precharge ........................... 53
Reads ....................................................................... 19
Single Write - Without Auto Precharge ......... 54
Writes ....................................................................... 25
Single Write - With Auto Precharge ................ 55
Precharge ................................................................ 27
Alternating Bank Write Accesses ................... 56
Power-Down ........................................................... 27
Write – Full-Page Burst .................................... 57
Clock Suspend ........................................................ 28
Write – DQM Operation ................................... 58
Burst Read/Single Write ....................................... 28

Figure 4: Functional Block Diagram

64 Meg x 4 SDRAM

CKE
CLK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
RAS# BANK1

REFRESH 13
MODE REGISTER COUNTER
ROW- 13 BANK0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 1 1
12 8192
LATCH ARRAY DQM
13 & (8,192 x 2,048 x 4)
DECODER

SENSE AMPLIFIERS DATA

4 OUTPUT
8192 REGISTER

2 I/O GATING 4 DQ0-

DQM MASK LOGIC DQ3
BANK READ DATA LATCH
A0-A12, ADDRESS CONTROL WRITE DRIVERS
BA0, BA1 15
REGISTER LOGIC DATA
2 4 INPUT
2048 REGISTER
(x4)

COLUMN
DECODER
COLUMN-
ADDRESS 11
11 COUNTER/
LATCH

Figure 5: Functional Block Diagram

32 Meg x 8 SDRAM

CKE
CLK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
RAS# BANK1

REFRESH 13
MODE REGISTER COUNTER
ROW- 13 BANK0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 1 1
12 8192
LATCH ARRAY DQM
13 & (8,192 x 1,024 x 8)
DECODER

SENSE AMPLIFIERS DATA

8 OUTPUT
8192 REGISTER

2 I/O GATING 8 DQ0-

DQM MASK LOGIC DQ7
BANK READ DATA LATCH
A0-A12, ADDRESS CONTROL WRITE DRIVERS
BA0, BA1 15
REGISTER LOGIC DATA
2 8 INPUT
1024 REGISTER
(x8)

COLUMN
DECODER
COLUMN-
ADDRESS 10
10 COUNTER/
LATCH

Figure 6: Functional Block Diagram

16 Meg x 16 SDRAM

CKE
CLK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
RAS# BANK1

REFRESH 13
MODE REGISTER COUNTER
ROW- 13 BANK0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 2 2
12 8192
LATCH ARRAY DQML,
13 & (8,192 x 512 x 16) DQMH
DECODER

SENSE AMPLIFIERS DATA

16 OUTPUT
8192 REGISTER

2 I/O GATING 16 DQ0-

DQM MASK LOGIC DQ15
BANK READ DATA LATCH
A0-A12, ADDRESS CONTROL WRITE DRIVERS
BA0, BA1 15
REGISTER LOGIC DATA
2 16 INPUT
512 REGISTER
(x16)

COLUMN
DECODER
COLUMN-
ADDRESS 9
9 COUNTER/
LATCH

Table 4: Pin Descriptions (54-pin TSOP)

54-PIN TSOP SYMBOL TYPE DESCRIPTION
38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
19 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
16, 17, 18 WE#, CAS#, Input Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the
RAS# command being entered.
39 x4, x8: DQM Input Input/Output Mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
15, 39 x16: DQML, DQM is sampled HIGH during a WRITE cycle. The output buffers are
DQMU placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a
NC and DQMH is DQM. On the x16, DQML corresponds to DQ0-
DQ7 and DQMH corresponds to DQ8-DQ15. DQML and DQMH are
considered same state when referenced as DQM.
20, 21 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
23-26, 29-34, 22, 35, 36 A0-A12 Input Address Inputs: A0-A12 are sampled during the ACTIVE command (row-
address A0-A12) and READ/WRITE command (column-address A0-A9, A11
[x4]; A0-A9 [x8]; A0-A8 [x16]; with A10 defining auto precharge) to select
one location out of the memory array in the respective bank. A10 is
sampled during a PRECHARGE command to determine if all banks are to
be precharged (A10 [HIGH]) or bank selected by (A10 [LOW]). The
address inputs also provide the op-code during a LOAD MODE
REGISTER command.
2, 4, 5, 7, 8, 10, 11, 13, 42, DQ0-DQ15 x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51
44, 45, 47, 48, 50, 51, 53 are NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs
for x4).
2, 5, 8, 11, 44, 47, 50, 53 DQ0-DQ7 x8: I/O Data Input/Output: Data bus for x8 (2, 8, 47, 53 are NCs for x4).
5, 11, 44, 50 DQ0-DQ3 x4: I/O Data Input/Output: Data bus for x4.
40 NC – No Connect: This pin should be left unconnected.
3, 9, 43, 49 V DD Q Supply DQ Power: DQ power to the die for improved noise immunity.
6, 12, 46, 52 VSSQ Supply DQ Ground: DQ ground to the die for improved noise immunity.
1, 14, 27 VDD Supply Power Supply: +3.3V ±0.3V.
28, 41, 54 VSS Supply Ground.

Table 5: Ball Descriptions (54-Ball FBGA)

54-BALL FBGA SYMBOL TYPE DESCRIPTION
F2 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter
and controls the output registers.
F3 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
G9 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
F7, F8, F9 CAS#, RAS#, Input Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the
WE# command being entered.
E8, F1 LDQM, Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
UDQM write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z state
(two-clock latency) when during a READ cycle. LDQM corresponds to DQ0–DQ7,
UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered same
state when referenced as DQM.
G7, G8 BA0, BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. These pins also provide the
op-code during a LOAD MODE REGISTER command
H7, H8, J8, J7, J3, J2, A0–A12 Input Address Inputs: A0–A12 are sampled during the ACTIVE command (row-
H3, H2, H1, G3, H9, G2, G1 address A0–A11) and READ/WRITE command (column-address A0–A8; with A10
defining auto precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW).
The address inputs also provide the op-code during a LOAD MODE REGISTER
command.
A8, B9, B8, C9, C8, D9, DQ0–DQ15 I/O Data Input/Output: Data bus
D8, E9, E1, D2, D1, C2,
C1, B2, B1, A2
E2 NC – No Connect: These pins should be left unconnected.
A7, B3, C7, D3 VDDQ Supply DQ Power: DQ power to the die for improved noise immunity.
A3, B7, C3, D7 V SS Q Supply DQ Ground: DQ ground to the die for improved noise immunity.
A9, E7, J9 VDD Supply Power Supply: Voltage dependant on option.
A1, E3, J1 VSS Supply Ground.

Table 6: Ball Descriptions (60-ball FBGA)

60-BALL FBGA SYMBOL TYPE DESCRIPTION
K2 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter
and controls the output registers.
L2 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
L8 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
J8, K7, J7 CAS#, RAS#, Input Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the
WE# command being entered.
J2 DQM, Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z state
(two-clock latency) when during a READ cycle.
M8, M7 BA0, BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. These pins also provide the
op-code during a LOAD MODE REGISTER command
N7, P8, P7, R8, R1, P2, P1, A0–A12 Input Address Inputs: A0–A11 are sampled during the ACTIVE command (row-
N2, N1, M2, N8, M1, L1 address A0–A11) and READ/WRITE command (column-address A0–A8; with A10
defining auto precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW).
The address inputs also provide the op-code during a LOAD MODE REGISTER
command.
C7, F7, F2, C2 DQ0–DQ3 (x4) I/O Data Input/Output: Data bus
A8, C7, D8, F7, F2, D1, C2, DQ0–DQ7 (x8) I/O Data Input/Output: Data bus
A1
A1, A8, B1, B8, D1, D2, D7, NC x4 No Connect: These pins should be left unconnected.
D8, E1, E8, G1, G2, G7, G1 is a no connect for this part but may be used as A12 in future designs.
G8, H1, H8, J1, K1, K8, L7
B1, B8, D2, D7, E1, E8, G1, NC x8 No Connect: These pins should be left unconnected.
G2, G7, G8, H1, H8, J1, K1, G1 is a no connect for this part but may be used as A12 in future designs.
K8, L7
B7, C1, E7, F1 VDDQ Supply DQ Power: Isolated power to DQs for improved noise immunity.
B2, C8, E2, F8 V SS Q Supply DQ Ground: Isolated ground to DQs for improved noise immunity.
A7, R7 VDD Supply Power Supply: Voltage dependant on option.
A2, H2, R2 VSS Supply Ground.

Functional Description Register Definition

In general, the 256Mb SDRAMs (16 Meg x 4 x 4 banks, Mode Register
8 Meg x 8 x 4 banks and 4 Meg x 16 x 4 banks) are quad- The mode register is used to define the specific mode
bank DRAMs that operate at 3.3V and include a syn- of operation of the SDRAM. This definition includes
chronous interface (all signals are registered on the the selection of a burst length, a burst type, a CAS
positive edge of the clock signal, CLK). Each of the x4’s latency, an operating mode and a write burst mode, as
67,108,864-bit banks is organized as 8,192 rows by 2,048 shown in Figure 7. The mode register is programmed
columns by 4 bits. Each of the x8’s 67,108,864-bit banks via the LOAD MODE REGISTER command and will re-
is organized as 8,192 rows by 1,024 columns by 8 bits. tain the stored information until it is programmed again
Each of the x16’s 67,108,864-bit banks is organized as or the device loses power.
8,192 rows by 512 columns by 16 bits. Mode register bits M0–M2 specify the burst length,
Read and write accesses to the SDRAM are burst M3 specifies the type of burst (sequential or inter-
oriented; accesses start at a selected location and con- leaved), M4–M6 specify the CAS latency, M7 and M8
tinue for a programmed number of locations in a pro- specify the operating mode, M9 specifies the write burst
grammed sequence. Accesses begin with the registra- mode, and M10 and M11 are reserved for future use.
tion of an ACTIVE command, which is then followed by Address A12 (M12) is undefined but should be driven
a READ or WRITE command. The address bits regis- LOW during loading of the mode register.
tered coincident with the ACTIVE command are used The mode register must be loaded when all banks
to select the bank and row to be accessed (BA0 and BA1 are idle, and the controller must wait the specified time
select the bank, A0–A12 select the row). The address before initiating the subsequent operation. Violating
bits (x4: A0–A9, A11; x8: A0–A9; x16: A0–A8) registered either of these requirements will result in unspecified
coincident with the READ or WRITE command are used operation.
to select the starting column location for the burst ac-
cess.
Burst Length
Prior to normal operation, the SDRAM must be ini-
Read and write accesses to the SDRAM are burst
tialized. The following sections provide detailed infor-
oriented, with the burst length being programmable,
mation covering device initialization, register defini-
as shown in Figure 1. The burst length determines the
tion, command descriptions and device operation.
maximum number of column locations that can be ac-
cessed for a given READ or WRITE command. Burst
Initialization lengths of 1, 2, 4 or 8 locations are available for both the
SDRAMs must be powered up and initialized in a sequential and the interleaved burst types, and a full-
predefined manner. Operational procedures other page burst is available for the sequential type. The
than those specified may result in undefined opera- full-page burst is used in conjunction with the BURST
tion. Once power is applied to VDD and VDDQ (simulta- TERMINATE command to generate arbitrary burst
neously) and the clock is stable (stable clock is defined lengths.
as a signal cycling within timing constraints specified Reserved states should not be used, as unknown
for the clock pin), the SDRAM requires a 100µs delay operation or incompatibility with future versions may
prior to issuing any command other than a result.
COMMAND INHIBIT or NOP. Starting at some point When a READ or WRITE command is issued, a block
during this 100µs period and continuing at least of columns equal to the burst length is effectively se-
through the end of this period, COMMAND INHIBIT or lected. All accesses for that burst take place within this
NOP commands should be applied. block, meaning that the burst will wrap within the block
Once the 100µs delay has been satisfied with at if a boundary is reached. The block is uniquely se-
least one COMMAND INHIBIT or NOP command hav- lected by A1–A9, A11 (x4), A1–A9 (x8) or A1–A8 (x16)
ing been applied, a PRECHARGE command should be when the burst length is set to two; by A2–A9, A11 (x4),
applied. All banks must then be precharged, thereby A2–A9 (x8) or A2–A8 (x16) when the burst length is set
placing the device in the all banks idle state. to four; and by A3–A9, A11 (x4), A3–A9 (x8) or A3–A8
Once in the idle state, two AUTO REFRESH cycles (x16) when the burst length is set to eight. The remain-
must be performed. After the AUTO REFRESH cycles ing (least significant) address bit(s) is (are) used to
are complete, the SDRAM is ready for mode register select the starting location within the block. Full-page
programming. Because the mode register will power bursts wrap within the page if the boundary is reached.
up in an unknown state, it should be loaded prior to
applying any operational command.

Burst Type Table 7: Burst Definition

Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to Burst Starting Column Order of Accesses Within a Burst
as the burst type and is selected via bit M3. Length Address Type = Sequential Type = Interleaved
The ordering of accesses within a burst is deter- A0
mined by the burst length, the burst type and the start- 2
0 0-1 0-1
ing column address, as shown in Table 7. 1 1-0 1-0
A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
Figure 7: Mode Register Definition 4
1 0 2-3-0-1 2-3-0-1
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 1 1 3-0-1-2 3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
12 11 10 9 8 7 6 5 4 3 2 1 0
Mode Register (Mx) 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
Reserved* WB Op Mode CAS Latency BT Burst Length
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
8
*Should program
M12, M11, M10 = “0, 0, 0”
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
to ensure compatibility Burst Length
with future devices. 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
M2 M1 M0 M3 = 0 M3 = 1
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
0 0 0 1 1

0 0 1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
2 2
Cn, Cn + 1, Cn + 2
0 1 0 4 4
Full n = A0-A11/9/8
0 1 1 8 8 Cn + 3, Cn + 4...
Page Not Supported
1 0 0 Reserved Reserved …Cn - 1,
1 0 1
(y) (location 0-y)
Reserved Reserved
Cn…
1 1 0 Reserved Reserved

1 1 1 Full Page Reserved

NOTE: 1. For full-page accesses: y = 2,048 (x4); y = 1,024
(x8); y = 512 (x16).
2. For a burst length of two, A1-A9, A11 (x4); A1-A9
M3 Burst Type
(x8); or A1-A8 (x16) select the block-of-two burst;
0 Sequential
A0 selects the starting column within the block.
1 Interleaved
3. For a burst length of four, A2-A9, A11 (x4); A2-A9
M6 M5 M4 CAS Latency
(x8); or A2-A8 (x16) select the block-of-four burst;
0 0 0 Reserved
A0-A1 select the starting column within the block.
0 0 1 Reserved
4. For a burst length of eight, A3-A9, A11 (x4); A3-A9
0 1 0 2
(x8); or A3-A8 (x16) select the block-of-eight burst;
0 1 1 3
A0-A2 select the starting column within the block.
1 0 0 Reserved
5. For a full-page burst, the full row is selected and
1 0 1 Reserved
A0-A9, A11 (x4); A0-A9 (x8); or A0-A8 (x16) select
Reserved
the starting column.
1 1 0

Reserved
6. Whenever a boundary of the block is reached
1 1 1
within a given sequence above, the following
access wraps within the block.
M8 M7 M6-M0 Operating Mode 7. For a burst length of one, A0-A9, A11 (x4); A0-A9
0 0 Defined Standard Operation (x8); or A0-A8 (x16) select the unique column to be
- - - All other states reserved accessed, and mode register bit M3 is ignored.

M9 Write Burst Mode

0 Programmed Burst Length

1 Single Location Access

CAS Latency Operating Mode

The CAS latency is the delay, in clock cycles, be- The normal operating mode is selected by setting
tween the registration of a READ command and the M7 and M8 to zero; the other combinations of values for
availability of the first piece of output data. The la- M7 and M8 are reserved for future use and/or test
tency can be set to two or three clocks. modes. The programmed burst length applies to both
If a READ command is registered at clock edge n, READ and WRITE bursts.
and the latency is m clocks, the data will be available by Test modes and reserved states should not be used
clock edge n + m. The DQs will start driving as a result of because unknown operation or incompatibility with
the clock edge one cycle earlier (n + m - 1), and provided future versions may result.
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that Write Burst Mode
the clock cycle time is such that all relevant access times When M9 = 0, the burst length programmed via
are met, if a READ command is registered at T0 and the M0-M2 applies to both READ and WRITE bursts; when
latency is programmed to two clocks, the DQs will start M9 = 1, the programmed burst length applies to READ
driving after T1 and the data will be valid by T2, as bursts, but write accesses are single-location (nonburst)
shown in Figure 8. Table 8 indicates the operating fre- accesses.
quencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result. Table 8: CAS Latency
ALLOWABLE OPERATING
FREQUENCY (MHz)
Figure 8: CAS Latency
CAS CAS
T0 T1 T2 T3 SPEED LATENCY = 2 LATENCY = 3
CLK
-7E ≤ 133 ≤ 143
COMMAND
-75 ≤ 100 ≤ 133
READ NOP NOP
tLZ tOH

DQ DOUT
tAC

CAS Latency = 2

T0 T1 T2 T3 T4
CLK

COMMAND READ NOP NOP NOP

tLZ tOH

DQ DOUT
tAC

CAS Latency = 3

DON’T CARE

UNDEFINED

Commands
Truth Table 1 provides a quick reference of Truth Tables appear following the Operation section;
available commands. This is followed by a written de- these tables provide current state/next state
scription of each command. Three additional information.

Table 9: Truth Table 1 – Commands and DQM Operation

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES
COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3
READ (Select bank and column, and start READ burst) L H L H L/H8 Bank/Col X 4
WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 Bank/Col Valid 4
BURST TERMINATE L H H L X X Active
PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5
AUTO REFRESH or SELF REFRESH L L L H X X X 6, 7
(Enter self refresh mode)
LOAD MODE REGISTER L L L L X Op-Code X 2
Write Enable/Output Enable – – – – L – Active 8
Write Inhibit/Output High-Z – – – – H – High-Z 8

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register, and A12 should be driven LOW.
3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A9, A11 (x4); A0-A9 (x8); or A0-A8 (x16) provide column address; A10 HIGH enables the auto precharge feature
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from
or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

COMMAND INHIBIT
inputs A0-A9; A11 (x4); A0-A9 (x8); or A0-A8 (x16) se-
The COMMAND INHIBIT function prevents new
lects the starting column location. The value on input
commands from being executed by the SDRAM, re-
A10 determines whether or not auto precharge is used.
gardless of whether the CLK signal is enabled. The
If auto precharge is selected, the row being accessed
SDRAM is effectively deselected. Operations already
will be precharged at the end of the WRITE burst; if
in progress are not affected.
auto precharge is not selected, the row will remain open
for subsequent accesses. Input data appearing on the
NO OPERATION (NOP) DQs is written to the memory array subject to the DQM
The NO OPERATION (NOP) command is used to input logic level appearing coincident with the data. If
perform a NOP to an SDRAM which is selected (CS# is a given DQM signal is registered LOW, the correspond-
LOW). This prevents unwanted commands from being ing data will be written to memory; if the DQM signal is
registered during idle or wait states. Operations already registered HIGH, the corresponding data inputs will
in progress are not affected. be ignored, and a WRITE will not be executed to that
byte/column location.
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A11 (A12 PRECHARGE
should be driven LOW.) See mode register heading in The PRECHARGE command is used to deactivate
the Register Definition section. The LOAD MODE REG- the open row in a particular bank or the open row in all
ISTER command can only be issued when all banks are banks. The bank(s) will be available for a subsequent
idle, and a subsequent executable command cannot row access a specified time (tRP) after the PRECHARGE
be issued until tMRD is met. command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
ACTIVE where only one bank is to be precharged, inputs BA0,
The ACTIVE command is used to open (or activate) BA1 select the bank. Otherwise BA0, BA1 are treated as
a row in a particular bank for a subsequent access. The “Don’t Care.” Once a bank has been precharged, it is in
value on the BA0, BA1 inputs selects the bank, and the the idle state and must be activated prior to any READ
address provided on inputs A0-A12 selects the row. or WRITE commands being issued to that bank.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A AUTO PRECHARGE
PRECHARGE command must be issued before open- Auto precharge is a feature which performs the
ing a different row in the same bank. same individual-bank PRECHARGE function de-
scribed above, without requiring an explicit command.
READ This is accomplished by using A10 to enable auto
The READ command is used to initiate a burst read precharge in conjunction with a specific READ or WRITE
access to an active row. The value on the BA0, BA1 command. A PRECHARGE of the bank/row that is ad-
inputs selects the bank, and the address provided on dressed with the READ or WRITE command is auto-
inputs A0-A9, A11 (x4), A0-A9 (x8), or A0-A8 (x16) se- matically performed upon completion of the READ or
lects the starting column location. The value on input WRITE burst, except in the full-page burst mode, where
A10 determines whether or not auto precharge is used. AUTO PRECHARGE does not apply. Auto precharge is
If auto precharge is selected, the row being accessed nonpersistent in that it is either enabled or disabled for
will be precharged at the end of the READ burst; if auto each individual READ or WRITE command.
precharge is not selected, the row will remain open for Auto precharge ensures that the precharge is initi-
subsequent accesses. Read data appears on the DQs ated at the earliest valid stage within a burst. The user
subject to the logic level on the DQM inputs two clocks must not issue another command to the same bank
earlier. If a given DQM signal was registered HIGH, the until the precharge time (tRP) is completed. This is
corresponding DQs will be High-Z two clocks later; if determined as if an explicit PRECHARGE command
the DQM signal was registered LOW, the DQs will pro- was issued at the earliest possible time, as described
vide valid data. for each burst type in the Operation section of this data
sheet.
WRITE
The WRITE command is used to initiate a burst write BURST TERMINATE
access to an active row. The value on the BA0, BA1 The BURST TERMINATE command is used to trun-
inputs selects the bank, and the address provided on cate either fixed-length or full-page bursts. The most

PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MSDRAM.pmd – Rev. H; Pub. 2/05 16 ©2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16
SDRAM
recently registered READ or WRITE command prior to SELF REFRESH
the BURST TERMINATE command will be truncated, The SELF REFRESH command can be used to retain
as shown in the Operation section of this data sheet. data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
AUTO REFRESH SDRAM retains data without external clocking.
AUTO REFRESH is used during normal operation of The SELF REFRESH command is initiated like an AUTO
the SDRAM and is analogous to CAS#-BEFORE-RAS# REFRESH command except CKE is disabled (LOW).
(CBR) REFRESH in conventional DRAMs. This Once the SELF REFRESH command is registered, all
command is nonpersistent, so it must be issued each the inputs to the SDRAM become “Don’t Care” with
time a refresh is required. All active banks must be the exception of CKE, which must remain LOW.
precharged prior to issuing an AUTO REFRESH com- Once self refresh mode is engaged, the SDRAM pro-
mand. The AUTO REFRESH command should not be vides its own internal clocking, causing it to perform its
issued until the minimum tRP has been met after the own AUTO REFRESH cycles. The SDRAM must remain
PRECHARGE command as shown in the operations sec- in self refresh mode for a minimum period equal to
tion. tRAS and may remain in self refresh mode for an indefi-
The addressing is generated by the internal refresh nite period beyond that.
controller. This makes the address bits “Don’t Care” The procedure for exiting self refresh requires a se-
during an AUTO REFRESH command. The 256Mb quence of commands. First, CLK must be stable (stable
SDRAM requires 8,192 AUTO REFRESH cycles every clock is defined as a signal cycling within timing con-
64ms (tREF), regardless of width option. Providing a straints specified for the clock pin) prior to CKE going
distributed AUTO REFRESH command every 7.81µs back HIGH. Once CKE is HIGH, the SDRAM must have
will meet the refresh requirement and ensure that each NOP commands issued (a minimum of two clocks) for
row is refreshed. Alternatively, 8,192 AUTO REFRESH tXSR because time is required for the completion of any
commands can be issued in a burst at the minimum internal refresh in progress.
cycle rate (tRFC), once every 64ms. Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued every 7.81µs or less as both
SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.

Operation Figure 9: Activating a Specific Row in a

Bank/Row Activation Specific Bank
Before any READ or WRITE commands can be is-
sued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the AC-
TIVE command, which selects both the bank and the CLK
row to be activated (see Figure 9).
After opening a row (issuing an ACTIVE command), CKE HIGH
a READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should
be divided by the clock period and rounded up to the CS#
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a tRCD specifi- RAS#
cation of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks, rounded to 3. This is reflected in Figure 10,
which covers any case where 2 < tRCD (MIN)/tCK ≤ 3. CAS#
(The same procedure is used to convert other specifi-
cation limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row WE#
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com- ROW
A0-A12
mands to the same bank is defined by tRC. ADDRESS
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over- BANK
head. The minimum time interval between successive BA0, BA1 ADDRESS
ACTIVE commands to different banks is defined by
t RRD.

Figure 10: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3
T0 T1 T2 T3 T4

CLK

COMMAND READ or
ACTIVE NOP NOP
WRITE

tRCD

DON’T CARE

READs
READ bursts are initiated with a READ command, each possible CAS latency setting.
as shown in Figure 11. Upon completion of a burst, assuming no other com-
The starting column and bank addresses are pro- mands have been initiated, the DQs will go High-Z. A
vided with the READ command, and auto precharge is full-page burst will continue until terminated. (At the
either enabled or disabled for that burst access. If auto end of the page, it will wrap to the start address and
precharge is enabled, the row being accessed is continue.)
precharged at the completion of the burst. For the ge- Data from any READ burst may be truncated with a
neric READ commands used in the following illustra- subsequent READ command, and data from a fixed-
tions, auto precharge is disabled. length READ burst may be immediately followed by
During READ bursts, the valid data-out element data from a READ command. In either case, a continu-
from the starting column address will be available fol- ous flow of data can be maintained. The first data ele-
lowing the CAS latency after the READ command. Each ment from the new burst follows either the last ele-
subsequent data-out element will be valid by the next ment of a completed burst or the last desired data ele-
positive clock edge. Figure 12 shows general timing for ment of a longer burst that is being truncated. The new
READ command should be issued x cycles before the
clock edge at which the last desired data element is

Figure 11: READ Command

Figure 12: CAS Latency

CLK
T0 T1 T2 T3
CLK
CKE HIGH
COMMAND READ NOP NOP
CS# tLZ tOH

DQ DOUT
tAC
RAS#
CAS Latency = 2

CAS#
T0 T1 T2 T3 T4

WE# CLK

COMMAND READ NOP NOP NOP

A0–A9, A11: x4 COLUMN tLZ tOH
A0–A9: x8 ADDRESS
A0–A8: x16
DQ DOUT
A12: x4 tAC
A11, A12: x8
A9, A11, A12: x16 CAS Latency = 3

ENABLE AUTO PRECHARGE DON’T CARE

A10 UNDEFINED
DISABLE AUTO PRECHARGE

BA0,1 BANK
ADDRESS

DON’T CARE

Figure 13: Consecutive READ Bursts

T0 T1 T2 T3 T4 T5 T6

CLK

COMMAND READ NOP NOP NOP READ NOP NOP

X = 1 cycle

BANK, BANK,
ADDRESS COL n COL b

DOUT DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3 b

CAS Latency = 2

T0 T1 T2 T3 T4 T5 T6 T7

CLK

COMMAND READ NOP NOP NOP READ NOP NOP NOP

X = 2 cycles

BANK, BANK,
ADDRESS COL n COL b

DOUT DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3 b

CAS Latency = 3

TRANSITIONING DATA DON’T CARE

NOTE: Each READ command may be to any bank. DQM is LOW.

Figure 14: Random READ Accesses

T0 T1 T2 T3 T4 T5

CLK

COMMAND READ READ READ READ NOP NOP

BANK, BANK, BANK, BANK,

ADDRESS COL n COL a COL x COL m

DOUT DOUT DOUT DOUT

DQ n a x m

CAS Latency = 2

T0 T1 T2 T3 T4 T5 T6

CLK

COMMAND READ READ READ READ NOP NOP NOP

BANK, BANK, BANK, BANK,

ADDRESS COL n COL a COL x COL m

DOUT DOUT DOUT DOUT

DQ n a x m

CAS Latency = 3

TRANSITIONING DATA DON’T CARE

NOTE: Each READ command may be to any bank. DQM is LOW.

PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MSDRAM.pmd – Rev. H; Pub. 2/05 21 ©2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16
SDRAM
Data from any READ burst may be truncated with a buffers) to suppress data-out from the READ. Once the
subsequent WRITE command, and data from a fixed- WRITE command is registered, the DQs will go High-Z
length READ burst may be immediately followed by (or remain High-Z), regardless of the state of the DQM
data from a WRITE command (subject to bus turn- signal; provided the DQM was active on the clock just
around limitations). The WRITE burst may be initiated prior to the WRITE command that truncated the READ
on the clock edge immediately following the last (or last command. If not, the second WRITE will be an invalid
desired) data element from the READ burst, provided WRITE. For example, if DQM was LOW during T4 in
that I/O contention can be avoided. In a given system Figure 10, then the WRITEs at T5 and T7 would be
design, there may be a possibility that the device driv- valid, while the WRITE at T6 would be invalid.
ing the input data will go Low-Z before the SDRAM DQs The DQM signal must be de-asserted prior to the
go High-Z. In this case, at least a single-cycle delay WRITE command (DQM latency is zero clocks for input
should occur between the last read data and the WRITE buffers) to ensure that the written data is not masked.
command. Figure 9 shows the case where the clock frequency al-
The DQM input is used to avoid I/O contention, as lows for bus contention to be avoided without adding a
shown in Figures 15 and 16. The DQM signal must be NOP cycle, and Figure 16 shows the case where the
asserted (HIGH) at least two clocks prior to the WRITE additional NOP is needed.
command (DQM latency is two clocks for output

Figure 15: READ to WRITE Figure 16: READ to WRITE with Extra
Clock Cycle
T0 T1 T2 T3 T4 T0 T1 T2 T3 T4 T5

CLK CLK

DQM DQM

COMMAND READ NOP NOP NOP WRITE COMMAND READ NOP NOP NOP NOP WRITE

BANK, BANK,
ADDRESS
BANK, BANK, ADDRESS COL n COL b
COL n COL b
tCK tHZ
tHZ DQ DOUT n DIN b

tDS
DQ DOUT n DIN b

tDS
TRANSITIONING DATA DON’T CARE
TRANSITIONING DATA DON’T CARE
NOTE: A CAS latency of three is used for illustration. The READ command
NOTE: A CAS latency of three is used for illustration. The READ may be to any bank, and the WRITE command may be to any bank.
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.

PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MSDRAM.pmd – Rev. H; Pub. 2/05 22 ©2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16
SDRAM
A fixed-length READ burst may be followed by, or four or the last desired of a longer burst. Following the
truncated with, a PRECHARGE command to the same PRECHARGE command, a subsequent command to
bank (provided that auto precharge was not acti- the same bank cannot be issued until tRP is met. Note
vated), and a full-page burst may be truncated with a that part of the row precharge time is hidden during
PRECHARGE command to the same bank. The the access of the last data element(s).
PRECHARGE command should be issued x cycles be- In the case of a fixed-length burst being executed to
fore the clock edge at which the last desired data ele- completion, a PRECHARGE command issued at the
ment is valid, where x equals the CAS latency minus optimum time (as described above) provides the same
one. This is shown in Figure 17 for each possible CAS operation that would result from the same fixed-length
latency; data element n + 3 is either the last of a burst of burst with auto precharge. The disadvantage of the

Figure 17: READ to PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7

CLK

t RP

COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE

X = 1 cycle
BANK a, BANK BANK a,
ADDRESS COL n (a or all) ROW

DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3

CAS Latency = 2

T0 T1 T2 T3 T4 T5 T6 T7

CLK

t RP

COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE

X = 2 cycles
BANK a, BANK BANK a,
ADDRESS COL n (a or all) ROW

DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3

CAS Latency = 3

TRANSITIONING DATA DON’T CARE

NOTE: DQM is LOW.

PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MSDRAM.pmd – Rev. H; Pub. 2/05 23 ©2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16
SDRAM
PRECHARGE command is that it requires that the com- command, provided that auto precharge was not acti-
mand and address buses be available at the appropri- vated. The BURST TERMINATE command should be
ate time to issue the command; the advantage of the issued x cycles before the clock edge at which the last
PRECHARGE command is that it can be used to trun- desired data element is valid, where x equals the CAS
cate fixed-length or full-page bursts. latency minus one. This is shown in Figure 18 for each
Full-page READ bursts can be truncated with the possible CAS latency; data element n + 3 is the last
BURST TERMINATE command, and fixed-length READ desired data element of a longer burst.
bursts may be truncated with a BURST TERMINATE

Figure 18: Terminating a READ Burst

T0 T1 T2 T3 T4 T5 T6

CLK

BURST
COMMAND READ NOP NOP NOP
TERMINATE
NOP NOP

X = 1 cycle
BANK,
ADDRESS COL n

DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3

CAS Latency = 2

T0 T1 T2 T3 T4 T5 T6 T7

CLK

BURST
COMMAND READ NOP NOP NOP
TERMINATE
NOP NOP NOP

X = 2 cycles
BANK,
ADDRESS COL n

DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3

CAS Latency = 3
TRANSITIONING DATA DON’T CARE

NOTE: DQM is LOW.

WRITEs
WRITE bursts are initiated with a WRITE command, new command applies to the new command. An ex-
as shown in Figure 19. ample is shown in Figure 21. Data n + 1 is either the last
The starting column and bank addresses are pro- of a burst of two or the last desired of a longer burst. The
vided with the WRITE command, and auto precharge 256Mb SDRAM uses a pipelined architecture and there-
is either enabled or disabled for that access. If auto fore does not require the 2n rule associated with a
precharge is enabled, the row being accessed is prefetch architecture. A WRITE command can be initi-
precharged at the completion of the burst. For the ge- ated on any clock cycle following a previous WRITE
neric WRITE commands used in the following illustra- command. Full-speed random write accesses within a
tions, auto precharge is disabled. page can be performed to the same bank, as shown in
During WRITE bursts, the first valid data-in ele- Figure 22, or each subsequent WRITE may be per-
ment will be registered coincident with the WRITE com- formed to a different bank.
mand. Subsequent data elements will be registered on Data for any WRITE burst may be truncated with a
each successive positive clock edge. Upon completion subsequent READ command, and data for a fixed-
of a fixed-length burst, assuming no other commands length WRITE burst may be immediately followed by a
have been initiated, the DQs will remain High-Z and READ command. Once the READ command is regis-
any additional input data will be ignored (see Figure
20). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to the start address
and continue.)
Figure 20: WRITE Burst
Data for any WRITE burst may be truncated with a T0 T1 T2 T3
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by CLK
data for a WRITE command. The new WRITE command
can be issued on any clock following the previous WRITE
COMMAND WRITE NOP NOP NOP
command, and the data provided coincident with the
BANK,
ADDRESS COL n
Figure 19: WRITE Command
DIN DIN
DQ n n+1
CLK

TRANSITIONING DATA DON’T CARE

CKE HIGH
NOTE: Burst length = 2. DQM is LOW.
CS#

RAS#
Figure 21: WRITE to WRITE
CAS# T0 T1 T2

CLK
WE#

A0-A9, A11: x4 COLUMN

A0-A9: x8 ADDRESS COMMAND WRITE NOP WRITE
A0-A8: x16
A12: x4
A11, A12: x8
A9, A11, A12: x16 BANK, BANK,
ADDRESS COL n COL b
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE DIN DIN DIN
DQ n n+1 b

BA0,1 BANK
ADDRESS TRANSITIONING DATA DON’T CARE

NOTE: DQM is LOW. Each WRITE command may

DON’T CARE be to any bank.

CLK

COMMAND WRITE WRITE WRITE WRITE

Figure 24: WRITE To PRECHARGE

BANK, BANK, BANK, BANK,
ADDRESS COL n COL a COL x COL m
T0 T1 T2 T3 T4 T5 T6

CLK
DIN DIN DIN DIN
DQ n a x m
tWR @ tCLK ≥ 15ns

DQM
TRANSITIONING DATA DON’T CARE
t RP

COMMAND WRITE NOP PRECHARGE NOP NOP ACTIVE NOP

BANK a, BANK BANK a,

ADDRESS COL n (a or all) ROW

t WR

Figure 23: WRITE To READ DQ

DIN DIN
n n+1

T0 T1 T2 T3 T4 T5
tWR = tCLK < 15ns
CLK
DQM

t RP
COMMAND WRITE NOP READ NOP NOP NOP
COMMAND WRITE NOP NOP PRECHARGE NOP NOP ACTIVE

BANK a, BANK BANK a,

BANK, BANK, ADDRESS COL n (a or all) ROW
ADDRESS COL n COL b
t WR

DIN DIN
DQ n n+1
DIN DIN DOUT DOUT
DQ n n+1 b b+1

TRANSITIONING DATA DON’T CARE

TRANSITIONING DATA DON’T CARE
NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MSDRAM.pmd – Rev. H; Pub. 2/05 26 ©2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16
SDRAM
ignored. The last data written (provided that DQM is open row in all banks. The bank(s) will be available for
LOW at that time) will be the input data applied one a subsequent row access some specified time (tRP) af-
clock previous to the BURST TERMINATE command. ter the PRECHARGE command is issued. Input A10
This is shown in Figure 25, where data n is the last determines whether one or all banks are to be
desired data element of a longer burst. precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. When
PRECHARGE all banks are to be precharged, inputs BA0, BA1 are
The PRECHARGE command (see Figure 26) is used treated as “Don’t Care.” Once a bank has been
to deactivate the open row in a particular bank or the precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
Figure 25: Terminating a WRITE Burst
Power-Down
T0 T1 T2
Power-down occurs if CKE is registered LOW coinci-
dent with a NOP or COMMAND INHIBIT when no ac-
CLK cesses are in progress. If power-down occurs when all
banks are idle, this mode is referred to as precharge
COMMAND WRITE
BURST
TERMINATE
NEXT
COMMAND
power-down; if power-down occurs when there is a row
active in any bank, this mode is referred to as active
BANK, (ADDRESS)
power-down. Entering power-down deactivates the in-
ADDRESS COL n
put and output buffers, excluding CKE, for maximum
DIN
power savings while in standby. The device may not
DQ (DATA)
n remain in the power-down state longer than the re-
fresh period (64ms) since no refresh operations are
TRANSITIONING DATA DON’T CARE performed in this mode.
The power-down state is exited by registering a NOP
NOTE: DQMs are LOW.
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting tCKS). See Figure 27.

Figure 26: PRECHARGE Command

CLK
Figure 27: Power-Down
((
CKE HIGH CLK
))
((
))
tCKS > tCKS
CS#
CKE ((
))

((
))
RAS# COMMAND NOP NOP ACTIVE
((
))
All banks idle tRCD
Input buffers gated off tRAS
CAS#
tRC
Enter power-down mode. Exit power-down mode.

WE# DON’T CARE

A0-A9, A11, A12

All Banks
A10
Bank Selected

BA0, BA1 BANK

ADDRESS

CLOCK SUSPEND
The clock suspend mode occurs when a column ac- Clock suspend mode is exited by registering CKE
cess/burst is in progress and CKE is registered LOW. In HIGH; the internal clock and related operation will re-
the clock suspend mode, the internal clock is deacti- sume on the subsequent positive clock edge.
vated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is BURST READ/SINGLE WRITE
sampled LOW, the next internal positive clock edge is The burst read/single write mode is entered by pro-
suspended. Any command or data present on the in- gramming the write burst mode bit (M9) in the mode
put pins at the time of a suspended internal clock edge register to a logic 1. In this mode, all WRITE commands
is ignored; any data present on the DQ pins remains result in the access of a single column location (burst of
driven; and burst counters are not incremented, as one), regardless of the programmed burst length. READ
long as the clock is suspended. (See examples in Fig- commands access columns according to the pro-
ures 28and 29.) grammed burst length and sequence, just as in the
normal mode of operation (M9 = 0).

Figure 28: Clock Suspend During Figure 29: Clock Suspend During READ
WRITE Burst Burst
T0 T1 T2 T3 T4 T5 T0 T1 T2 T3 T4 T5 T6

CLK CLK

CKE CKE

INTERNAL INTERNAL
CLOCK CLOCK

COMMAND NOP WRITE NOP NOP

COMMAND READ NOP NOP NOP NOP NOP

BANK,
ADDRESS COL n ADDRESS
BANK,
COL n

DIN DIN DIN DOUT DOUT DOUT DOUT

DIN n n+1 n+2 DQ n n+1 n+2 n+3

TRANSITIONING DATA DON’T CARE

NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.

CONCURRENT AUTO PRECHARGE

An access command (READ or WRITE) to another on bank n, CAS latency later. The PRECHARGE to
bank while an access command with auto precharge bank n will begin when the READ to bank m is regis-
enabled is executing is not allowed by SDRAMs, tered (Figure 30).
unless the SDRAM supports CONCURRENT AUTO 2. Interrupted by a WRITE (with or without auto
PRECHARGE. Micron SDRAMs support CONCURRENT precharge): A WRITE to bank m will interrupt a READ
AUTO PRECHARGE. Four cases where CONCURRENT on bank n when registered. DQM should be used
AUTO PRECHARGE occurs are defined below. two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will
READ with Auto Precharge begin when the WRITE to bank m is registered (Fig-
1. Interrupted by a READ (with or without auto ure 31).
precharge): A READ to bank m will interrupt a READ

Figure 30: READ With Auto Precharge Interrupted by a READ

T0 T1 T2 T3 T4 T5 T6 T7

CLK

READ - AP READ - AP
COMMAND NOP
BANK n
NOP
BANK m
NOP NOP NOP NOP

BANK n Page Active READ with Burst of 4 Interrupt Burst, Precharge Idle

Internal t RP - BANK n tRP - BANK m

States Page Active READ with Burst of 4 Precharge

BANK m

BANK n, BANK m,
ADDRESS COL a COL d

DOUT DOUT DOUT DOUT

DQ a a+1 d d+1

CAS Latency = 3 (BANK n)

NOTE: DQM is LOW. CAS Latency = 3 (BANK m)

TRANSITIONING DATA DON’T CARE

Figure 31: READ With Auto Precharge Interrupted by a WRITE

T0 T1 T2 T3 T4 T5 T6 T7

CLK

READ - AP WRITE - AP
COMMAND BANK n
NOP NOP NOP
BANK m
NOP NOP NOP

Page
BANK n Active
READ with Burst of 4 Interrupt Burst, Precharge Idle

Internal tRP - BANK n t WR - BANK m

States Page Active WRITE with Burst of 4 Write-Back

BANK m

BANK n, BANK m,
ADDRESS COL a COL d

1
DQM

DOUT DIN DIN DIN DIN

DQ a d d+1 d+2 d+3

CAS Latency = 3 (BANK n)

TRANSITIONING DATA DON’T CARE

NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.

PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MSDRAM.pmd – Rev. H; Pub. 2/05 29 ©2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16
SDRAM
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto 4. Interrupted by a WRITE (with or without auto
precharge): A READ to bank m will interrupt a WRITE precharge): A WRITE to bank m will interrupt a
on bank n when registered, with the data-out ap- WRITE on bank n when registered. The
pearing CAS latency later. The PRECHARGE to bank PRECHARGE to bank n will begin after tWR is met,
n will begin after tWR is met, where tWR begins when where tWR begins when the WRITE to bank m is
the READ to bank m is registered. The last valid registered. The last valid data WRITE to bank n will
WRITE to bank n will be data-in registered one clock be data registered one clock prior to a WRITE to
prior to the READ to bank m (Figure 32). bank m (Figure 33).

Figure 32: WRITE With Auto Precharge Interrupted by a READ

T0 T1 T2 T3 T4 T5 T6 T7

CLK

WRITE - AP READ - AP
COMMAND NOP
BANK n
NOP
BANK m
NOP NOP NOP NOP

BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
tRP - BANK n
Internal tWR - BANK n
tRP - BANK m
States Page Active READ with Burst of 4
BANK m

BANK n, BANK m,
ADDRESS COL a COL d

DIN DIN DOUT DOUT

DQ a a+1 d d+1

CAS Latency = 3 (BANK m)

TRANSITIONING DATA DON’T CARE

NOTE: 1. DQM is LOW.

Figure 33: WRITE With Auto Precharge Interrupted by a WRITE

T0 T1 T2 T3 T4 T5 T6 T7

CLK

WRITE - AP WRITE - AP
COMMAND NOP
BANK n
NOP NOP
BANK m
NOP NOP NOP

BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
tRP - BANK n
Internal tWR - BANK n
t WR - BANK m
States Page Active WRITE with Burst of 4 Write-Back
BANK m

BANK n, BANK m,
ADDRESS COL a COL d

DIN DIN DIN DIN DIN DIN DIN

DQ a a+1 a+2 d d+1 d+2 d+3

TRANSITIONING DATA DON’T CARE

NOTE: 1. DQM is LOW.

Table 10: Truth Table 2 – CKE

(Notes: 1-4)
CKEn-1 CKEn CURRENT STATE COMMANDn ACTIONn NOTES
L L Power-Down X Maintain Power-Down
Self Refresh X Maintain Self Refresh
Clock Suspend X Maintain Clock Suspend
L H Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5
Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6
Clock Suspend X Exit Clock Suspend 7
H L All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry
All Banks Idle AUTO REFRESH Self Refresh Entry
Reading or Writing VALID Clock Suspend Entry
H H See Truth Table 3

NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT
or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP
commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
edge n + 1.

Table 11: Truth Table 3 – Current State Bank n, Command to Bank n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)
L H H H NO OPERATION (NOP/Continue previous operation)
L L H H ACTIVE (Select and activate row)
Idle L L L H AUTO REFRESH 7
L L L L LOAD MODE REGISTER 7
L L H L PRECHARGE 11
L H L H READ (Select column and start READ burst) 10
Row Active L H L L WRITE (Select column and start WRITE burst) 10
L L H L PRECHARGE (Deactivate row in bank or banks) 8
Read L H L H READ (Select column and start new READ burst) 10
(Auto L H L L WRITE (Select column and start WRITE burst) 10
Precharge L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) 8
Disabled) L H H L BURST TERMINATE 9
Write L H L H READ (Select column and start READ burst) 10
(Auto L H L L WRITE (Select column and start new WRITE burst) 10
Precharge L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8
Disabled) L H H L BURST TERMINATE 9

NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or
been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth
Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met,
the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met,
the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.

Table 12: Truth Table 4 – Current State Bank n, Command to Bank m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)
L H H H NO OPERATION (NOP/Continue previous operation)
Idle X X X X Any Command Otherwise Allowed to Bank m
Row L L H H ACTIVE (Select and activate row)
Activating, L H L H READ (Select column and start READ burst) 7
Active, or L H L L WRITE (Select column and start WRITE burst) 7
Precharging L L H L PRECHARGE
Read L L H H ACTIVE (Select and activate row)
(Auto L H L H READ (Select column and start new READ burst) 7, 10
Precharge L H L L WRITE (Select column and start WRITE burst) 7, 11
Disabled) L L H L PRECHARGE 9
Write L L H H ACTIVE (Select and activate row)
(Auto L H L H READ (Select column and start READ burst) 7, 12
Precharge L H L L WRITE (Select column and start new WRITE burst) 7, 13
Disabled) L L H L PRECHARGE 9
Read L L H H ACTIVE (Select and activate row)
(With Auto L H L H READ (Select column and start new READ burst) 7, 8, 14
Precharge) L H L L WRITE (Select column and start WRITE burst) 7, 8, 15
L L H L PRECHARGE 9
Write L L H H ACTIVE (Select and activate row)
(With Auto L H L H READ (Select column and start READ burst) 7, 8, 16
Precharge) L H L L WRITE (Select column and start new WRITE burst) 7, 8, 17
L L H L PRECHARGE 9

NOTE: 1. This table applies when CKE n-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the
previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or
been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.

PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MSDRAM.pmd – Rev. H; Pub. 2/05 34 ©2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16
SDRAM
NOTE (continued):
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted
by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last
valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 24).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m (Figure 26).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior
to the WRITE to bank m (Figure 27).

Absolute Maximum Ratings

Stresses greater than those listed may cause per- Voltage on VDD, VDDQ Supply
manent damage to the device. This is a stress rating Relative to VSS ....................................... -1V to +4.6V
only, and functional operation of the device at these or Voltage on Inputs, NC or I/O Pins
any other conditions above those indicated in the op- Relative to VSS ....................................... -1V to +4.6V
erational sections of this specification is not implied. Operating Temperature,
Exposure to absolute maximum rating conditions for TA (commercial) ....................................... 0°C to +70°C
extended periods may affect reliability. Operating Temperature,
TA (industrial “IT”) ............................. -40°C to +85°C
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ........................................................ 1W

Table 13: DC Electrical Characteristics and Operating Conditions

(Notes: 1, 5, 6; notes appear on page 39); (VDD, VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD, VDDQ 3 3.6 V
Input High Voltage: Logic 1; All inputs VIH 2 VDD + 0.3 V 22
Input Low Voltage: Logic 0; All inputs VIL -0.3 0.8 V 22
Input Leakage Current: Any input 0V ≤ VIN ≤ VDD II -5 5 µA
(All other pins not under test = 0V)
Output Leakage Current: DQs are disabled; IOZ -5 5 µA
0V ≤ VOUT ≤ VDDQ
Output Levels:
Output High Voltage (IOUT = -4mA) VOH 2.4 – V
Output Low Voltage (IOUT = 4mA) VOL – 0.4 V

Table 14: IDD Specifications and Conditions

(Notes: 1, 5, 6, 11, 13; notes appear on page 39); (VDD, VDDQ = +3.3V ±0.3V)
MAX
PARAMETER/CONDITION SYMBOL -7E -75 UNITS NOTES
Operating Current: Active Mode; IDD1 135 125 mA 3, 18,
Burst = 2; READ or WRITE; tRC = tRC (MIN) 19, 32
Standby Current: Power-Down Mode; IDD2 2 2 mA 32
All banks idle; CKE = LOW
Standby Current: Active Mode; IDD3 40 40 mA 3, 12,
CKE = HIGH; CS# = HIGH; All banks active after tRCD met; 19, 32
No accesses in progress
Operating Current: Burst Mode; Page burst; IDD4 135 135 mA 3, 18,
READ or WRITE; All banks active 19, 32
Auto Refresh Current tRFC = tRFC (MIN) IDD5 285 270 mA 3, 12,
CS# = HIGH; CKE = HIGH tRFC = 7.81 µs IDD6 3.5 3.5 mA 18, 19,
32, 33
SELF REFRESH CURRENT: CKE ≤ 0.2V Standard IDD7 2.5 2.5 mA 4
Low power (L) IDD7 1.5 1.5 mA

Table 15: Capacitance

(Note: 2; notes appear on page 39)

PARAMETER - TSOP “TG” Package SYMBOL MIN MAX UNITS NOTES

Input Capacitance: CLK CI1 2.5 3.5 pF 29
Input Capacitance: All other input-only pins CI2 2.5 3.8 pF 30
Input/Output Capacitance: DQs CIO 4.0 6.0 pF 31

PARAMETER - FBGA “FB” and “FG” Package SYMBOL MIN MAX UNITS NOTES
Input Capacitance: CLK CI1 1.5 3.5 pF 34
Input Capacitance: All other input-only pins CI2 1.5 3.8 pF 35
Input/Output Capacitance: DQs CIO 3.0 6.0 pF 36

Table 16: Electrical Characteristics and Recommended AC Operating Conditions

(Notes: 5, 6, 8, 9, 11; notes appear on page 39)

AC CHARACTERISTICS -7E -75

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Access time from CL = 3 tAC(3) 5.4 5.4 ns 27
CLK (pos. edge) CL = 2 tAC(2) 5.4 6 ns
Address hold time tAH 0.8 0.8 ns
Address setup time tAS 1.5 1.5 ns
CLK high-level width tCH 2.5 2.5 ns
CLK low-level width tCL 2.5 2.5 ns
Clock cycle time CL = 3 tCK(3) 7 7.5 ns 23
CL = 2 tCK(2) 7.5 10 ns 23
CKE hold time tCKH 0.8 0.8 ns
CKE setup time tCKS 1.5 1.5 ns 37
CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 ns
CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 ns
Data-in hold time tDH 0.8 0.8 ns
Data-in setup time tDS 1.5 1.5 ns
Data-out high-impedance CL = 3 tHZ(3) 5.4 5.4 ns 10
time CL = 2 tHZ(2) 5.4 6 ns 10
Data-out low-impedance time t LZ 1 1 ns
Data-out hold time (load) tOH 3 3 ns
Data-out hold time (no load) tOH 1.8 1.8 ns 28
N
ACTIVE to PRECHARGE command tRAS 37 120,000 44 120,000 ns
ACTIVE to ACTIVE command period tRC 60 66 ns
ACTIVE to READ or WRITE delay tRCD 15 20 ns
Refresh period (8,192 rows) tREF 64 64 ms
AUTO REFRESH period tRFC 66 66 ns
PRECHARGE command period tRP 15 20 ns
ACTIVE bank a to ACTIVE bank b command tRRD 14 15 ns
Transition time tT 0.3 1.2 0.3 1.2 ns 7
WRITE recovery time tWR 1 CLK+ 1 CLK+ ns 24
7ns 7.5ns
14 15 ns 25
Exit SELF REFRESH to ACTIVE command tXSR 67 75 ns 20

Table 17: AC Functional Characteristics

(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 39)

PARAMETER SYMBOL -7E -75 UNITS NOTES

READ/WRITE command to READ/WRITE command tCCD 1 1 tCK 17
CKE to clock disable or power-down entry mode tCKED 1 1 tCK 14
CKE to clock enable or power-down exit setup mode tPED 1 1 tCK 14
DQM to input data delay tDQD 0 0 tCK 17
DQM to data mask during WRITEs tDQM 0 0 tCK 17
DQM to data high-impedance during READs tDQZ 2 2 tCK 17
WRITE command to input data delay tDWD 0 0 tCK 17
Data-in to ACTIVE command tDAL 4 5 tCK 15, 21
Data-in to PRECHARGE command tDPL 2 2 tCK 16, 21
Last data-in to burst STOP command tBDL 1 1 tCK 17
Last data-in to new READ/WRITE command tCDL 1 1 tCK 17
Last data-in to PRECHARGE command tRDL 2 2 tCK 16, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 tCK 26
Data-out to high-impedance from PRECHARGE command CL = 3 tROH(3) 3 3 tCK 17
CL = 2 tROH(2) 2 2 tCK 17

Notes
1. All voltages referenced to VSS. 14. Timing actually specified by tCKS; clock(s) speci-
2. This parameter is sampled. VDD , V DDQ = +3.3V; fied as a reference only at minimum cycle rate.
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V. 15. Timing actually specified by tWR plus tRP; clock(s)
3. IDD is dependent on output loading and cycle rates. specified as a reference only at minimum cycle rate.
Specified values are obtained with minimum cycle 16. Timing actually specified by tWR.
time and the outputs open. 17. Required clocks are specified by JEDEC function-
4. Enables on-chip refresh and address counters. ality and are not dependent on any timing param-
5. The minimum specifications are used only to eter.
indicate cycle time at which proper operation over 18. The IDD current will increase or decrease propor-
the full temperature range is ensured; (0°C ≤ TA ≤ tionally according to the amount of frequency al-
+70°C for commercial) and (-40°C ≤ TA ≤ +85°C teration for the test condition.
for IT). 19. Address transitions average one transition every
6. An initial pause of 100µs is required after power- two clocks.
up, followed by two AUTO REFRESH commands, 20. CLK must be toggled a minimum of two times dur-
before proper device operation is ensured. (VDD ing this period.
and VDDQ must be powered up simultaneously. VSS 21.Based on tCK = 7.5ns for -75 and -7E.
and VSSQ must be at same potential.) The two AUTO 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
REFRESH command wake-ups should be repeated width ≤ 3ns, and the pulse width cannot be
any time the tREF refresh requirement is exceeded. greater than one third of the cycle rate. VIL under-
7. AC characteristics assume tT = 1ns. shoot: VIL (MIN) = -2V for a pulse width ≤ 3ns.
8. In addition to meeting the transition rate specifi- 23. The clock frequency must remain constant (stable
cation, the clock and CKE must transit between VIH clock is defined as a signal cycling within timing
and VIL (or between VIL and VIH) in a monotonic constraints specified for the clock pin) during ac-
manner. cess or precharge states (READ, WRITE, including
9. Outputs measured at 1.5V with equivalent load: tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
Q 24. Auto precharge mode only. The precharge timing
50pF budget (tRP) begins 7ns for -7E and 7.5ns for -75
after the first clock delay, after the last WRITE is
executed.
25. Precharge mode only.
10. tHZ defines the time at which the output achieves 26. JEDEC and PC100 specify three clocks.
the open circuit condition; it is not a reference to 27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is
VOH or VOL. The last valid data element will meet guaranteed by design.
tOH before going High-Z. 28. Parameter guaranteed by design.
11. AC operating and IDD test conditions have VIL = 0V 29. PC100 specifies a maximum of 4pF.
and VIH = 3.0V using a measurement reference level 30. PC100 specifies a maximum of 5pF.
of 1.5V. If the input transition time is longer than 31. PC100 specifies a maximum of 6.5pF.
1ns, then the timing is measured from VIL (MAX) 32. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and
and VIH (MIN) and no longer from the 1.5V mid- tCK = 7.5ns.
point. CLK should always be 1.5V referenced to 33. CKE is HIGH during refresh command period
crossover. Refer to Micron Technical Note TN-48- tRFC (MIN) else CKE is LOW. The IDD6 limit is actu-
09. ally a nominal value and does not result in a fail
12. Other input signals are allowed to transition no value.
more than once every two clocks and are otherwise 34. PC133 specifies a minimum of 2.5pF.
at valid VIH or VIL levels. 35. PC133 specifies a minimum of 2.5pF.
13. IDD specifications are tested after the device is prop- 36. PC133 specifies a minimum of 3.0pF.
erly initialized. 37. For operating frequencies ≤ 45 MHz tCKS = 3.0ns.

Figure 34: Initialize and Load Mode Register 2

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3
tCK (( (( tCL ((
CK )) )) ))
(( (( tCH (( ((
)) )) )) ))
tCKS tCKH
(( (( (( ((
)) )) )) ))
CKE
(( ((
)) ))
tCMS tCMH
(( (( (( ((
)) )) AUTO )) AUTO )) LOAD MODE
COMMAND NOP PRECHARGE NOP NOP NOP NOP NOP ACTIVE
(( (( REFRESH (( REFRESH (( REGISTER
)) )) )) ))

(( (( (( ((
)) )) )) ))
DQM/ ((
(( (( ((
DQML, DQMU )) )) )) ))

tAS tAH 5
(( (( (( ((
)) )) )) ))
A0-A9, A11, A12 (( (( CODE ROW
(( ((
)) )) )) ))

tAS tAH
(( ALL BANKS (( (( ((
)) )) )) ))
A10 (( (( CODE ROW
(( ((
)) )) )) ))
SINGLE BANK

(( (( (( ((
)) ALL )) )) ))
BA0, BA1 (( BANK
(( BANKS (( ((
)) )) )) ))

(( High-Z ((
DQ
)) ))
T = 100µs
MIN tRP tRFC tRFC tMRD

Power-up:
VDD and Precharge AUTO REFRESH AUTO REFRESH Program Mode Register 1, 3, 4
CLK stable all banks
DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -7E -75

SYMBOL* MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns tCKS 1.5 1.5 ns
tAS 1.5 1.5 ns tCMH 0.8 0.8 ns
tCH 2.5 2.5 ns tCMS 1.5 1.5 ns
tCL 2.5 2.5 ns tMRD3 2 2 tCK
tCK (3) 7 7.5 ns tRFC 66 66 ns
tCK (2) 7.5 10 ns tRP 15 20 ns
tCKH 0.8 0.8 ns

*CAS latency indicated in parentheses.

NOTE: 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock HIGH time, all commands applied are NOP.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at tP + 1.

Figure35: Power-Down Mode 1

T0 T1 T2 ((
Tn + 1 Tn + 2
((
tCK tCL )) ))
CLK
tCH (( ((
)) ))
tCKS tCKS

CKE (( ((
)) ))
tCKS tCKH

tCMS tCMH
(( ((
)) ))
COMMAND PRECHARGE NOP NOP NOP ACTIVE
(( ((
)) ))

(( ((
DQM/ )) ))
DQML, DQMU (( ((
)) ))

(( ((
)) ))
A0-A9, A11, A12 ROW
(( ((
)) ))

ALL BANKS (( ((
)) ))
A10 ROW
(( ((
SINGLE BANK )) ))

tAS tAH
(( ((
)) ))
BA0, BA1 BANK(S) BANK
(( ((
)) ))

High-Z
(( ((
DQ )) ))
Two clock cycles Input buffers gated off while in
power-down mode
Precharge all All banks idle, enter All banks idle
active banks power-down mode Exit power-down mode

DON’T CARE

TIMING PARAMETERS

-7E -75 -7E -75

SYMBOL* MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns tCK (2) 7.5 10 ns
tAS 1.5 1.5 ns tCKH 0.8 0.8 ns
tCH 2.5 2.5 ns tCKS 1.5 1.5 ns
tCL 2.5 2.5 ns tCMH 0.8 0.8 ns
tCK (3) 7 7.5 ns tCMS 1.5 1.5 ns

*CAS latency indicated in parentheses.

NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.

Figure 36: Clock Suspend Mode1

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCKS tCKH

tCMS tCMH

COMMAND READ NOP NOP NOP NOP NOP WRITE NOP

tCMS tCMH
DQM/
DQML, DQMU
tAS tAH

2
A0-A9, A11, A12 COLUMN m COLUMN e 2

tAS tAH

A10
tAS tAH

BA0, BA1 BANK BANK

tAC
tAC tOH tHZ tDS tDH

DQ DOUT m DOUT m + 1 DIN e DIN + 1

tLZ

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -7E -75

SYMBOL* MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns tCKS 1.5 1.5 ns
tAC (2) 5.4 6 ns tCMH 0.8 0.8 ns
tAH 0.8 0.8 ns tCMS 1.5 1.5 ns
tAS 1.5 1.5 ns tDH 0.8 0.8 ns
tCH 2.5 2.5 ns tDS 1.5 1.5 ns
tCL 2.5 2.5 ns tHZ (3) 5.4 5.4 ns
tCK (3) 7 7.5 ns tHZ (2) 5.4 6 ns
tCK (2) 7.5 10 ns tLZ 1 1 ns
tCKH 0.8 0.8 ns tOH 3 3 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
2. x16: A9, A11 and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”

Figure 37: Auto Refresh Mode

T0 T1 T2 Tn + 1 To + 1
(( tCL ((
CLK )) ))
tCK tCH (( ((
)) ))
(( ((
)) ))
CKE

tCKS tCKH

tCMS tCMH
(( ((
AUTO )) AUTO ))
COMMAND PRECHARGE NOP NOP
REFRESH ( ( NOP REFRESH
NOP
( ( NOP ACTIVE
)) ))

(( ((
DQM / )) ))
DQML, DQMU (( ((
)) ))

(( ((
)) ))
A0-A9, A11, A12 ROW
(( ((
)) ))

ALL BANKS (( ((
)) ))
A10 ROW
(( ((
SINGLE BANK )) ))

tAS tAH
(( ((
)) ))
BA0, BA1 BANK(S) BANK
(( ((
)) ))

DQ High-Z (( ((
)) ))
tRP tRFC tRFC

Precharge all DON’T CARE

active banks

TIMING PARAMETERS

-7E -75 -7E -75

SYMBOL* MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns tCKH 0.8 0.8 ns
tAS 1.5 1.5 ns tCKS 1.5 1.5 ns
tCH 2.5 2.5 ns tCMH 0.8 0.8 ns
tCL 2.5 2.5 ns tCMS 1.5 1.5 ns
tCK (3) 7 7.5 ns tRFC 66 66 ns
tCK (2) 7.5 10 ns tRP 15 20 ns

*CAS latency indicated in parentheses.

Figure 38: Self Refresh Mode

T0 T1 T2 ((
Tn + 1 ((
To + 1 To + 2
tCL )) ))
CLK
tCK tCH (( ((
)) ))
tCKS
≥ tRAS(MIN)1
((
))
CKE (( ((
)) ))
tCKS tCKH

tCMS tCMH
(( ((
AUTO )) ) ) or COMMAND AUTO
COMMAND PRECHARGE NOP NOP ( (
REFRESH (( INHIBIT REFRESH
)) ))

(( ((
DQM/ )) ))
DQML, DQMU (( ((
)) ))

(( ((
)) ))
A0-A9, A11,A12
(( ((
)) ))
ALL BANKS (( ((
)) ))
A10
(( ((
SINGLE BANK )) ))

tAS tAH
(( ((
)) ))
BA0, BA1 BANK(S) (( ((
)) ))

High-Z (( ((
DQ )) ))
tRP tXSR2

Precharge all Enter self refresh mode Exit self refresh mode
active banks
(Restart refresh time base)
CLK stable prior to exiting DON’T CARE
self refresh mode
TIMING PARAMETERS

-7E -75 -7E -75

SYMBOL* MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns tCKS 1.5 1.5 ns
tAS 1.5 1.5 ns tCMH 0.8 0.8 ns
tCH 2.5 2.5 ns tCMS 1.5 1.5 ns
tCL 2.5 2.5 ns tRAS 37 120,000 44 120,000 ns
tCK (3) 7 7.5 ns tRP 15 20 ns
tCK (2) 7.5 10 ns tXSR 67 75 ns
tCKH 0.8 0.8 ns *CAS latency indicated in parentheses.

NOTES: 1. No maximum time limit for Self Refresh. tRAS(MAX) applies to non-Self Refresh mode.
2. tXSR requires minimum of two clocks regardless of frequency or timing.
3. As a general rule, any time Self Refresh is exited, the DRAM may not reenter the Self Refresh mode until all rows have
been refreshed by the Auto Refresh command at the distributed refresh rate, tREF, or faster. However, the following
exceptions are allowed
a. The DRAM has been in Self Refresh mode for a minimum of 64mS prior to exiting.
b. TXSR is not violated
c.. At least two Auto Refresh commands are preformed during each 7.81mS interval while the DRAM remains
out of the Self Refresh mode.

Figure 39: Read – Without Auto Precharge1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCMS tCMH

COMMAND ACTIVE NOP READ NOP NOP NOP PRECHARGE NOP ACTIVE

tCMS tCMH
DQM/
DQML, DQMU
tAS tAH

A0-A9, A11, A12 ROW COLUMN m 2 ROW

tAS tAH
ALL BANKS
A10 ROW ROW
SINGLE BANK
tAS tAH DISABLE AUTO PRECHARGE

BA0, BA1 BANK BANK BANK BANK

tAC tAC tAC

tAC tOH tOH tOH tOH

DQ tLZ
DOUT m DOUT m + 1 DOUT m + 2 DOUT m + 3

tHZ
tRCD CAS Latency tRP
tRAS
tRC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -7E -75

SYMBOL* MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns tCMH 0.8 0.8 ns
tAC (2) 5.4 6 ns tCMS 1.5 1.5 ns
tAH 0.8 0.8 ns tHZ (3) 5.4 5.4 ns
tAS 1.5 1.5 ns tHZ (2) 5.4 6 ns
tCH 2.5 2.5 ns tLZ 1 1 ns
tCL 2.5 2.5 ns tOH 3 3 ns
tCK (3) 7 7.5 ns tRAS 37 120,000 44 120,000 ns
tCK (2) 7.5 10 ns tRC 60 66 ns
tCKH 0.8 0.8 ns tRCD 20 20 ns
tCKS 1.5 1.5 ns tRP 15 20 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”

Figure 40: Read – With Auto Precharge1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE

tCMS tCMH
DQM/
DQML, DQMU
tAS tAH

A0-A9, A11, A12 ROW COLUMN m 2 ROW

tAS tAH ENABLE AUTO PRECHARGE

A10 ROW ROW

tAS tAH

BA0, BA1 BANK BANK BANK

tAC tAC tAC

tAC tOH tOH tOH tOH

DQ DOUT m DOUT m + 1 DOUT m + 2 DOUT m + 3

tLZ
tHZ
tRCD CAS Latency tRP
tRAS
tRC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -7E -75

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”

Figure 41: Single Read – Without Autor Precharge1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCMS tCMH

COMMAND ACTIVE NOP READ NOP 2 NOP 2 PRECHARGE NOP ACTIVE NOP

tCMS tCMH
DQM /
DQML, DQMU
tAS tAH

A0-A9, A11,A12 ROW COLUMN m3 ROW

tAS tAH
ALL BANKS
A10 ROW ROW

tAS tAH DISABLE AUTO PRECHARGE SINGLE BANKS

BA0, BA1 BANK BANK BANK(S) BANK

tAC tOH

DQ DOUT m
tLZ
tHZ
tRCD CAS Latency tRP
tRAS
tRC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -7E -75

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. PRECHARGE command not allowed else tRAS would be violated.
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”

Figure 42: Single Read – With Auto Precharge1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP NOP2 NOP2 READ NOP NOP ACTIVE NOP

tCMS tCMH
DQM /
DQML, DQMU
tAS tAH

A0-A9, A11 ROW COLUMN m3 ROW

tAS tAH ENABLE AUTO PRECHARGE

A10 ROW ROW

tAS tAH

BA0, BA1 BANK BANK BANK

tAC
t OH

DQ DOUT m
tRCD CAS Latency tHZ

tRAS tRP
tRC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -7E -75

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.
2. PRECHARGE command not allowed else tRAS would be violated.
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”

Figure 43: Alternating Bank Read Accesses1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP READ NOP ACTIVE NOP READ NOP ACTIVE

tCMS tCMH
DQM/
DQML, DQMU
tAS tAH

A0-A9, A11, A12 ROW COLUMN m 2 ROW COLUMN b 2 ROW

tAS tAH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE

A10 ROW ROW ROW

tAS tAH

BA0, BA1 BANK 0 BANK 0 BANK 3 BANK 3 BANK 0

tAC tAC tAC tAC tAC

tAC tOH tOH tOH tOH tOH

DQ DOUT m DOUT m + 1 DOUT m + 2 DOUT m + 3 DOUT b

tLZ

tRCD - BANK 0 CAS Latency - BANK 0 tRP - BANK 0 tRCD - BANK 0

tRAS - BANK 0
tRC - BANK 0
tRRD tRCD - BANK 3 CAS Latency - BANK 3

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -7E -75

SYMBOL* MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns tCMH 0.8 0.8 ns
tAC (2) 5.4 6 ns tCMS 1.5 1.5 ns
tAH 0.8 0.8 ns tLZ 1 1 ns
tAS 1.5 1.5 ns tOH 3 3 ns
tCH 2.5 2.5 ns tRAS 37 120,000 44 120,000 ns
tCL 2.5 2.5 ns tRC 60 66 ns
tCK (3) 7 7.5 ns tRCD 15 20 ns
tCK (2) 7.5 10 ns tRP 15 20 ns
tCKH 0.8 0.8 ns tRRD 14 15 ns
tCKS 1.5 1.5 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”

Figure 44: Read – Full-Page Burst1

T0 T1 T2 T3 T4 T5 T6 ((
Tn + 1 Tn + 2 Tn + 3 Tn + 4
tCL tCK ))
CLK
tCH ((
))

tCKS tCKH
((
CKE ))
((
))
tCMS tCMH
((
))
COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP BURST TERM NOP NOP
((
))

tCMS tCMH ((
DQM/ ))
DQML, DQMU ((
))

tAS tAH
((
))
A0-A9, A11, A12 ROW COLUMN m 2 ((
))

tAS tAH
((
))
A10 ROW ((
))

tAS tAH
((
))
BA0, BA1 BANK BANK
((
))

tAC tAC tAC ( ( tAC tAC

tAC tOH tOH tOH ) ) tOH tOH tOH
((
))
DQ DOUT m DOUT m+1 DOUT m+2 DOUT m-1 Dout m DOUT m+1
((
tLZ ))
tHZ
512 (x16) locations within same row
1,024 (x8) locations within same row
tRCD CAS Latency 2,048 (x4) locations within same row

Full page completed DON’T CARE

Full-page burst does not self-terminate.
3 UNDEFINED
Can use BURST TERMINATE command.

TIMING PARAMETERS

-7E -75 -7E -75

SYMBOL* MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 ns tCKS 1.5 1.5 ns
tAC (2) 5.4 6 ns tCMH 0.8 0.8 ns
tAH 0.8 0.8 ns tCMS 1.5 1.5 ns
tAS 1.5 1.5 ns tHZ (3) 5.4 5.4 ns
tCH 2.5 2.5 ns tHZ (2) 5.4 6 ns
tCL 2.5 2.5 ns tLZ 1 1 ns
tCK (3) 7 7.5 ns tOH 3 3 ns
tCK (2) 7.5 10 ns tRCD 15 20 ns
tCKH 0.8 0.8 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the CAS latency = 2.

2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
3. Page left open; no tRP.

Figure 45: Read – DQM Operation1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE
tCMS tCMH

COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP NOP

tCMS tCMH

DQM/
DQML, DQMU
tAS tAH

A0-A9, A11, A12 ROW COLUMN m 2

tAS tAH
ENABLE AUTO PRECHARGE
A10 ROW
DISABLE AUTO PRECHARGE
tAS tAH

BA0, BA1 BANK BANK

tAC
tAC tOH tAC tOH tOH

DQ DOUT m DOUT m + 2 DOUT m + 3

tLZ
tHZ tLZ tHZ

tRCD CAS Latency

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -7E -75

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”

Figure 46: Write – Without Auto Precharge1

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP PRECHARGE NOP ACTIVE

tCMS tCMH

DQM/
DQML, DQMU
tAS tAH

A0-A9, A11, A12 ROW COLUMN m 2 ROW

tAS tAH
ALL BANKs

A10 ROW ROW

DISABLE AUTO PRECHARGE SINGLE BANK
tAS tAH

BA0, BA1 BANK BANK BANK BANK

tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3

tRCD t WR 3 tRP
tRAS
tRC

DON’T CARE

TIMING PARAMETERS

-7E -75 -7E -75

SYMBOL* MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns tCMS 1.5 1.5 ns
tAS 1.5 1.5 ns tDH 0.8 0.8 ns
tCH 2.5 2.5 ns tDS 1.5 1.5 ns
tCL 2.5 2.5 ns tRAS 37 120,000 44 120,000 ns
tCK (3) 7 7.5 ns tRC 60 66 ns
tCK (2) 7.5 10 ns tRCD 15 20 ns
tCKH 0.8 0.8 ns tRP 15 20 ns
tCKS 1.5 1.5 ns tWR 14 15 ns
tCMH 0.8 0.8 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m+3> and the PRECHARGE command, regardless of frequency.
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”

Figure 47: Write – With Auto Precharge1

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE

tCMS tCMH
DQM/
DQML, DQMU
tAS tAH

A0-A9, A11, A12 ROW COLUMN m 2 ROW

tAS tAH
ENABLE AUTO PRECHARGE

A10 ROW ROW

tAS tAH

BA0, BA1 BANK BANK BANK

tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3

tRCD tWR tRP
tRAS
tRC

DON’T CARE

TIMING PARAMETERS

-7E -75 -7E -75

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”

Figure 48: Single Write – Without Auto Precharge1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP 2 NOP 2 PRECHARGE NOP ACTIVE NOP

tCMS tCMH

DQM /
DQML, DQMU
tAS tAH

A0-A9, A11 ROW COLUMN m 3

tAS tAH
ALL BANKS

A10 ROW ROW

DISABLE AUTO PRECHARGE SINGLE BANK
tAS tAH

BA0, BA1 BANK BANK BANK BANK

tDS tDH

DQ DIN m
tRCD t WR 4 tRP
tRAS
tRC

DON’T CARE

TIMING PARAMETERS

-7E -75 -7E -75

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency. With a single write
tWR has been increased to meet minimum tRAS requirement.
3. x16: A8, A9, and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
4. PRECHARGE command not allowed else tRAS would be violated.

Figure 49: Single Write – With Auto Precharge1

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP2 NOP2 NOP2 WRITE NOP NOP NOP ACTIVE NOP

tCMS tCMH
DQM/
DQML, DQMU
tAS tAH

A0-A9, A11, A12 ROW COLUMN m 3 ROW

tAS tAH
ENABLE AUTO PRECHARGE

A10 ROW ROW

tAS tAH

BA0, BA1 BANK BANK BANK

tDS tDH

DQ DIN m
tRCD tWR4 tRP
tRAS
tRC

DON’T CARE

TIMING PARAMETERS

-7E -75 -7E -75

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1.

2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
4. WRITE command not allowed else tRAS would be violated.

Figure 50: Alternating Bank Write Accesses1

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE

tCMS tCMH
DQM/
DQML, DQMU
tAS tAH

A0-A9, A11, A12 ROW COLUMN m 3 ROW COLUMN b 3 ROW

tAS tAH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE

A10 ROW ROW ROW

tAS tAH

BA0, BA1 BANK 0 BANK 0 BANK 1 BANK 1 BANK 0

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3 DIN b DIN b + 1 DIN b + 2 DIN b + 3

tRCD - BANK 0 tWR - BANK 0 tRP - BANK 0 tRCD - BANK 0

tRAS - BANK 0
tRC - BANK 0
tRRD tRCD - BANK 1 tWR - BANK 1

DON’T CARE

TIMING PARAMETERS

-7E -75 -7E -75

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. Requires one clock plus time (7ns or 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”

Figure 51: Write – Full-Page Burst

T0 T1 T2 T3 T4 T5 ((
Tn + 1 Tn + 2 Tn + 3
tCL tCK ))
CLK
tCH ((
))

tCKS tCKH
((
))
CKE
((
))
tCMS tCMH
((
))
COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP
((
))

tCMS tCMH
((
DQM/ ))
DQML, DQMU ((
))

tAS tAH
((
))
A0-A9, A11, A12 ROW COLUMN m 1
((
))

tAS tAH
((
))
A10 ROW ((
))

tAS tAH
((
))
BA0, BA1 BANK BANK
((
))

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
((
))
DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3 (( DIN m - 1
))
tRCD
Full-page burst does
512 (x16) locations within same row not self-terminate.
1,024 (x8) locations within same row Can use BURST TERMINATE
2,048 (x4) locations within same row command to stop.2, 3

Full page completed

DON’T CARE

TIMING PARAMETERS

-7E -75 -7E -75

SYMBOL* MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX UNITS
tAH 0.8 0.8 ns tCKS 1.5 1.5 ns
tAS 1.5 1.5 ns tCMH 0.8 0.8 ns
tCH 2.5 2.5 ns tCMS 1.5 1.5 ns
tCL 2.5 2.5 ns tDH 0.8 0.8 ns
tCK (3) 7 7.5 ns tDS 1.5 1.5 ns
tCK (2) 7.5 10 ns tRCD 15 20 ns
tCKH 0.8 0.8 ns

*CAS latency indicated in parentheses.

NOTE: 1. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
2. tWR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.

Figure 52: Write – DQM Operation1

T0 T1 T2 T3 T4 T5 T6 T7
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP

tCMS tCMH
DQM/
DQML, DQMU
tAS tAH

A0-A9, A11, A12 ROW COLUMN m 2

tAS tAH
ENABLE AUTO PRECHARGE
A10 ROW
tAS tAH DISABLE AUTO PRECHARGE

BA0, BA1 BANK BANK

tDS tDH tDS tDH tDS tDH

DQ DIN m DIN m + 2 DIN m + 3

tRCD
DON’T CARE

TIMING PARAMETERS

-7E -75 -7E -75

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”

Figure 53: 54-PIN PLASTIC TSOP (400 mil)

SEE DETAIL A
22.22 ±.08
.71
.80 TYP
2X 0.10

.375 ±.075 TYP

2.80

11.76 ±0.20

10.16 ±0.08

R 2X 0.75
+0.03 GAGE PLANE
PIN #1 ID 0.15
-0.02
R 2X 1.00 0.25

+0.10
0.10
-0.05
0.10 0.50 ±0.10
PLATED LEAD FINISH: 90% Sn, 10% Pb OR 100%Sn 1.2 MAX
PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC 0.80
PACKAGE WIDTH AND LENGTH DO NOT TYP
INCLUDE MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DETAIL A

NOTE: 1. All dimensions in millimeters .

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

Figure 54: FBGA “FB” Package, 60-Ball, 8mm x 16mm

x4, x8
.205 MAX
.850 ±.075
.10 A

SEATING PLANE

SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag

A SOLDER BALL PAD: Ø 0.33mm
SUBSTRATE: PLASTIC LAMINATE
8.00 ±.10
ENCAPSULATION MATERIAL: EPOXY NOVOLAC
5.60 PIN #1 ID
.80
60X Ø .45 TYP PIN #1 ID

BALL A1
BALL A8

8.00 ±.05 .80

TYP
16.00 ±.10

11.20
5.60 ±.05

2.40 ±.05
CTR
2.80 ±.05
1.20 MAX

4.00 ±.05

(Bottom View)

NOTE: 1. All dimensions in millimeters.

2. Recommended Pad size for PCB is 0.33mm±0.025mm.
3. Top side part marking decode can be found at:
http://www.micron.com/products/fbga/FBGA.asp

Figure 55: VFBGA “FG” Package, 54-ball, 8mm x 14mm

x16
0.65 ±0.05

SEATING PLANE

C
0.10 C

6.40 1.00 MAX

54X Ø0.45 0.80 TYP BALL A1 ID
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE- BALL A1 ID
REFLOW DIAMETER IS Ø0.42
BALL A9 BALL A1

0.80 TYP

6.40 CL 14.00 ±0.10

3.20 ±0.05

7.00 ±0.05

CL
3.20 ±0.05
4.00 ±0.05 MOLD COMPOUND: EPOXY NOVOLAC
8.00 ±0.10 SUBSTRATE MATERIAL: PLASTIC LAMINATE
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR
96.5% Sn, 3%Ag, 0.5% Cu
SOLDER MASK DEFINED BALL PADS: Ø 0.40

(Bottom View)

NOTE: 1. All dimensions in millimeters.

2. Recommended Pad size for PCB is 0.4mm±0.065mm.
3. Top side part marking decode can be found at:
http://www.micron.com/products/fbga/FBGA.asp

DATA SHEET DESIGNATION

Production: This data sheet contains minimum and maximum limits specified over the complete power supply
and temperature range for production devices. Although considered final, these specifications are
subject to change, as further product development and data characterization sometimes occur.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

MT48LC64M4A2
No ratings yet
MT48LC64M4A2
62 pages
Synchronous Dram: Pin Assignment (Top View) 54-Pin TSOP Features
No ratings yet
Synchronous Dram: Pin Assignment (Top View) 54-Pin TSOP Features
55 pages
Synchronous Dram: Pin Assignment (Top View) 54-Pin TSOP Features
No ratings yet
Synchronous Dram: Pin Assignment (Top View) 54-Pin TSOP Features
59 pages
MT48LC 4m16a2,8m8a2,16m4a2
No ratings yet
MT48LC 4m16a2,8m8a2,16m4a2
55 pages
48LC8M16A2
No ratings yet
48LC8M16A2
59 pages
Double Data Rate (DDR) SDRAM
No ratings yet
Double Data Rate (DDR) SDRAM
83 pages
46V16M16
No ratings yet
46V16M16
83 pages
2Gb DDR2
No ratings yet
2Gb DDR2
140 pages
Synchronous DRAM
No ratings yet
Synchronous DRAM
77 pages
MT48LC64M4A2
No ratings yet
MT48LC64M4A2
86 pages
SDRAM
No ratings yet
SDRAM
86 pages
512Mb DDR2 SDRAM Specs & Features
No ratings yet
512Mb DDR2 SDRAM Specs & Features
133 pages
Microddr 2 Sram
No ratings yet
Microddr 2 Sram
132 pages
Samsung SDRAM Product Guide 2007
No ratings yet
Samsung SDRAM Product Guide 2007
8 pages
256Mb SDR
No ratings yet
256Mb SDR
86 pages
Samsung K4H641638N LCCC Datasheet
No ratings yet
Samsung K4H641638N LCCC Datasheet
26 pages
MT48LC64M4A2
No ratings yet
MT48LC64M4A2
86 pages
512 MB DDR2
No ratings yet
512 MB DDR2
133 pages
MT46V64M8
No ratings yet
MT46V64M8
93 pages
2Gb DDR2
No ratings yet
2Gb DDR2
135 pages
Double Data Rate (DDR) SDRAM
No ratings yet
Double Data Rate (DDR) SDRAM
93 pages
512Mb DDR2 SDRAM Specifications
No ratings yet
512Mb DDR2 SDRAM Specifications
135 pages
Double Data Rate (DDR) SDRAM
No ratings yet
Double Data Rate (DDR) SDRAM
93 pages
64Mb SDRAM Features & Specs
No ratings yet
64Mb SDRAM Features & Specs
84 pages
Synchronous Dram: Pin Assignment (Top View) 50-Pin TSOP Features
No ratings yet
Synchronous Dram: Pin Assignment (Top View) 50-Pin TSOP Features
52 pages
Micron's Product Range
No ratings yet
Micron's Product Range
101 pages
DDR SDRAM Module Specs
No ratings yet
DDR SDRAM Module Specs
16 pages
512Mb SDR
No ratings yet
512Mb SDR
78 pages
64mb x32 Sdram PDF
No ratings yet
64mb x32 Sdram PDF
81 pages
SDR Product Guide July - '02
No ratings yet
SDR Product Guide July - '02
11 pages
256Mb E-Die SDRAM Specification: Revision 1.5 May 2004
No ratings yet
256Mb E-Die SDRAM Specification: Revision 1.5 May 2004
14 pages
256Mb E-Die SDRAM Specification: Revision 1.5 May 2004
No ratings yet
256Mb E-Die SDRAM Specification: Revision 1.5 May 2004
14 pages
8gb gddr5 Sgram Brief
No ratings yet
8gb gddr5 Sgram Brief
7 pages
Double Data Rate (DDR) Sdram
No ratings yet
Double Data Rate (DDR) Sdram
8 pages
Double Data Rate (DDR) Sdram
No ratings yet
Double Data Rate (DDR) Sdram
8 pages
IS42R86400D
No ratings yet
IS42R86400D
66 pages
1Gb DDR2 Addendum PDF
No ratings yet
1Gb DDR2 Addendum PDF
3 pages
Sb5101 Samsung Upgrade
No ratings yet
Sb5101 Samsung Upgrade
14 pages
256mb x8x16 at DDR T66a PDF
No ratings yet
256mb x8x16 at DDR T66a PDF
91 pages
256 MB DDR2
No ratings yet
256 MB DDR2
128 pages
MT48LC16M16A2 MicronTechnology
No ratings yet
MT48LC16M16A2 MicronTechnology
87 pages
Samsung 256Mb E-die SDRAM Specs
No ratings yet
Samsung 256Mb E-die SDRAM Specs
15 pages
HP Laser Jet 2015 RAM
No ratings yet
HP Laser Jet 2015 RAM
22 pages
MT48LC1M16A1
No ratings yet
MT48LC1M16A1
51 pages
FM25F02A Ds Eng
No ratings yet
FM25F02A Ds Eng
43 pages
1gb Ddr2 Aut U88b Addendum-3179150
No ratings yet
1gb Ddr2 Aut U88b Addendum-3179150
151 pages
FM25Q16A Ds Eng
No ratings yet
FM25Q16A Ds Eng
79 pages
AllianceMemory AS4C64M16D2A-25BIN-25BCN v.1.1 October2017
No ratings yet
AllianceMemory AS4C64M16D2A-25BIN-25BCN v.1.1 October2017
62 pages
64mb Ait Aat SDR
No ratings yet
64mb Ait Aat SDR
84 pages
DDR1 Sdram 2.5V - 200P - Sodimm
No ratings yet
DDR1 Sdram 2.5V - 200P - Sodimm
13 pages
MT 48lc2m32b2 - 64mb x32 Sdram
No ratings yet
MT 48lc2m32b2 - 64mb x32 Sdram
53 pages
8gb gddr5x Sgram Brief PDF
No ratings yet
8gb gddr5x Sgram Brief PDF
23 pages
Archive: Datasheet
No ratings yet
Archive: Datasheet
22 pages
Eeprom Flash
No ratings yet
Eeprom Flash
12 pages
M29F200BB
No ratings yet
M29F200BB
23 pages
M 29 F 200 BB
No ratings yet
M 29 F 200 BB
22 pages
Mdoc 4
No ratings yet
Mdoc 4
9 pages
cc3 Developer Reference Guide
No ratings yet
cc3 Developer Reference Guide
30 pages
Products Datasheet: GNSS Antenna H483D
No ratings yet
Products Datasheet: GNSS Antenna H483D
3 pages
2
No ratings yet
2
54 pages
Electronics Schematic Reference
No ratings yet
Electronics Schematic Reference
1 page
Philips ARM LPC Microcontroller Family: Rev. 02 - 25 October 2004 Application Note
No ratings yet
Philips ARM LPC Microcontroller Family: Rev. 02 - 25 October 2004 Application Note
18 pages
Fujitsu Lifebook S Series SH760 560
No ratings yet
Fujitsu Lifebook S Series SH760 560
3 pages
IGCSE O-Level Computer Coursebook: Chapter 2: Communications and Internet Technologies
No ratings yet
IGCSE O-Level Computer Coursebook: Chapter 2: Communications and Internet Technologies
2 pages
MGC Network Firmware Update Guide
No ratings yet
MGC Network Firmware Update Guide
2 pages
Securifire 1000-Extracted
No ratings yet
Securifire 1000-Extracted
2 pages
Storage Technology Foundations
No ratings yet
Storage Technology Foundations
4 pages
Intel Core 2 Duo E7500
No ratings yet
Intel Core 2 Duo E7500
4 pages
HP g4 g6 Dar18dmb6d0 Schematic (ComunidadeTecnica - Com.br)
100% (1)
HP g4 g6 Dar18dmb6d0 Schematic (ComunidadeTecnica - Com.br)
42 pages
Principles of Computer Hardware - PDF Room
No ratings yet
Principles of Computer Hardware - PDF Room
705 pages
Husky IVO 700R - Specification Sheet
No ratings yet
Husky IVO 700R - Specification Sheet
2 pages
iBMC Intelligent Management System White Paper
No ratings yet
iBMC Intelligent Management System White Paper
114 pages
New Hivision Price Excel
No ratings yet
New Hivision Price Excel
15 pages
ReadMe MotopilotMP v1.0
No ratings yet
ReadMe MotopilotMP v1.0
3 pages
Computer Parts
No ratings yet
Computer Parts
9 pages
Communications For The 4000 Series Controllers Manual
No ratings yet
Communications For The 4000 Series Controllers Manual
2 pages
ES Module 2 Notes
No ratings yet
ES Module 2 Notes
39 pages
CH4 Geography Pract. Use of Computers in Data Processing & Mapping Chapter-4 Practical
No ratings yet
CH4 Geography Pract. Use of Computers in Data Processing & Mapping Chapter-4 Practical
6 pages
Hand Book
No ratings yet
Hand Book
35 pages
2.3 Output Devices and Their Uses
No ratings yet
2.3 Output Devices and Their Uses
8 pages
CAT25256 EEPROM Serial 256-Kb SPI: Description
No ratings yet
CAT25256 EEPROM Serial 256-Kb SPI: Description
22 pages
STVEP - (Internet and Computing Fundamentals) : Activity Sheet Quarter 1 - LO 4
100% (2)
STVEP - (Internet and Computing Fundamentals) : Activity Sheet Quarter 1 - LO 4
8 pages
Netburstdetail
No ratings yet
Netburstdetail
17 pages
Operating Systems Concepts Chapter 1 Questions
No ratings yet
Operating Systems Concepts Chapter 1 Questions
7 pages
Hefei Yifei Mac Fix: LAST - MODIFICATION Fri Dec 20 23:04:51 2019
No ratings yet
Hefei Yifei Mac Fix: LAST - MODIFICATION Fri Dec 20 23:04:51 2019
109 pages
Zeppelin Manual
No ratings yet
Zeppelin Manual
18 pages
Safak Yilmaz CV 2023 New Last
No ratings yet
Safak Yilmaz CV 2023 New Last
4 pages
DOPSoft UM EN 20181101-1-100
No ratings yet
DOPSoft UM EN 20181101-1-100
101 pages
Humidity and Temperature Datalogger Kits: Features Features
No ratings yet
Humidity and Temperature Datalogger Kits: Features Features
1 page
Adobe Scan 28 Apr 2024
No ratings yet
Adobe Scan 28 Apr 2024
4 pages
Makalah CPU Dan Storage
No ratings yet
Makalah CPU Dan Storage
9 pages
Computer Literacy Exam
88% (8)
Computer Literacy Exam
3 pages