256Mb: x4, x8, x16 SDRAM

Features

SDR SDRAM
MT48LC64M4A2 16 Meg x 4 x 4 banks
MT48LC32M8A2 8 Meg x 8 x 4 banks
MT48LC16M16A2 4 Meg x 16 x 4 banks

Features Options Marking

60-ball TFBGA (x4, x8) (8mm x FB
PC100- and PC133-compliant 16mm)
Fully synchronous; all signals registered on positive 60-ball TFBGA (x4, x8) (8mm x BB
edge of system clock 16mm) Pb-free
Internal, pipelined operation; column address can 54-ball VFBGA (x16) (8mm x 14 mm) FG2
be changed every clock cycle 54-ball VFBGA (x16) (8mm x 14 mm) BG2
Internal banks for hiding row access/precharge Pb-free
Programmable burst lengths: 1, 2, 4, 8, or full page 54-ball VFBGA (x16) (8mm x 8 mm) F43
Auto precharge, includes concurrent auto precharge 54-ball VFBGA (x16) (8mm x 8 mm) B43
and auto refresh modes Pb-free
Self refresh mode (not available on AT devices) Timing cycle time
Auto refresh 6ns @ CL = 3 (x8, x16 only) -6A
64ms, 8192-cycle refresh (commercial and 7.5ns @ CL = 3 (PC133) -752
industrial) 7.5ns @ CL = 2 (PC133) -7E
16ms, 8192-cycle refresh (automotive) Self refresh
LVTTL-compatible inputs and outputs Standard None
Single 3.3V 0.3V power supply Low power L2, 4
Options Marking Operating temperature range
Configurations Commercial (0C to +70C) None
64 Meg x 4 (16 Meg x 4 x 4 banks) 64M4 Industrial (40C to +85C) IT
32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8 Automotive (40C to +105C) AT4
16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16 Revision :D/:G
Write recovery (tWR) Notes: 1. Off-center parting line.
tWR = 2 CLK A2 2. Only available on Revision D.
Plastic package OCPL1 3. Only available on Revision G.
54-pin TSOP II OCPL 1 (400 mil) TG 4. Contact Micron for availability.
(standard)
54-pin TSOP II OCPL 1 (400 mil) P
Pb-free

Table 1: Key Timing Parameters

CL = CAS (READ) latency
Clock
Speed Grade Frequency (MHz) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-6A 167 3-3-3 18 18 18
-75 133 3-3-3 20 20 20
-7E 133 2-2-2 15 15 15

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 256Mb: x4, x8, x16 SDRAM
Features

Table 2: Address Table

Parameter 64 Meg x 4 32 Meg x 8 16 Meg x 16

Configuration 16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
Refresh count 8K 8K 8K
Row addressing 8K A[12:0] 8K A[12:0] 8K A[12:0]
Bank addressing 4 BA[1:0] 4 BA[1:0] 4 BA[1:0]
Column addressing 2K A[9:0], A11 1K A[9:0] 512 A[8:0]

Table 3: 256Mb SDR Part Numbering

Part Numbers Architecture Package

MT48LC64M4A2TG 64 Meg x 4 54-pin TSOP II
MT48LC64M4A2P 64 Meg x 4 54-pin TSOP II
MT48LC64M4A2FB1 64 Meg x 4 60-ball FBGA
MT48LC64M4A2BB1 64 Meg x 4 60-ball FBGA
MT48LC32M8A2TG 32 Meg x 8 54-pin TSOP II
MT48LC32M8A2P 32 Meg x 8 54-pin TSOP II
MT48LC32M8A2FB1 32 Meg x 8 60-ball FBGA
MT48LC32M8A2BB1 32 Meg x 8 60-ball FBGA
MT48LC16M16A2TG 16 Meg x 16 54-pin TSOP II
MT48LC16M16A2P 16 Meg x 16 54-pin TSOP II
MT48LC16M16A2FG 16 Meg x 16 54-ball FBGA
MT48LC16M16A2BG 16 Meg x 16 54-ball FBGA

Note: 1. FBGA Device Decoder: www.micron.com/decoder.

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 256Mb: x4, x8, x16 SDRAM
Features

Contents
General Description ......................................................................................................................................... 7
Automotive Temperature .............................................................................................................................. 7
Functional Block Diagrams ............................................................................................................................... 8
Pin and Ball Assignments and Descriptions ..................................................................................................... 11
Package Dimensions ....................................................................................................................................... 15
Temperature and Thermal Impedance ............................................................................................................ 19
Electrical Specifications .................................................................................................................................. 23
Electrical Specifications IDD Parameters ........................................................................................................ 25
Electrical Specifications AC Operating Conditions ......................................................................................... 27
Functional Description ................................................................................................................................... 30
Commands .................................................................................................................................................... 31
COMMAND INHIBIT .................................................................................................................................. 31
NO OPERATION (NOP) ............................................................................................................................... 32
LOAD MODE REGISTER (LMR) ................................................................................................................... 32
ACTIVE ...................................................................................................................................................... 32
READ ......................................................................................................................................................... 33
WRITE ....................................................................................................................................................... 34
PRECHARGE .............................................................................................................................................. 35
BURST TERMINATE ................................................................................................................................... 35
REFRESH ................................................................................................................................................... 36
AUTO REFRESH ..................................................................................................................................... 36
SELF REFRESH ....................................................................................................................................... 36
Truth Tables ................................................................................................................................................... 37
Initialization .................................................................................................................................................. 42
Mode Register ................................................................................................................................................ 44
Burst Length .............................................................................................................................................. 46
Burst Type .................................................................................................................................................. 46
CAS Latency ............................................................................................................................................... 48
Operating Mode ......................................................................................................................................... 48
Write Burst Mode ....................................................................................................................................... 48
Bank/Row Activation ...................................................................................................................................... 49
READ Operation ............................................................................................................................................. 50
WRITE Operation ........................................................................................................................................... 59
Burst Read/Single Write .............................................................................................................................. 66
PRECHARGE Operation .................................................................................................................................. 67
Auto Precharge ........................................................................................................................................... 67
AUTO REFRESH Operation ............................................................................................................................. 79
SELF REFRESH Operation ............................................................................................................................... 81
Power-Down .................................................................................................................................................. 83
Clock Suspend ............................................................................................................................................... 84

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 256Mb: x4, x8, x16 SDRAM
Features

List of Figures
Figure 1: 64 Meg x 4 Functional Block Diagram ................................................................................................. 8
Figure 2: 32 Meg x 8 Functional Block Diagram ................................................................................................. 9
Figure 3: 16 Meg x 16 Functional Block Diagram ............................................................................................. 10
Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11
Figure 5: 60-Ball FBGA (Top View) ................................................................................................................. 12
Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 13
Figure 7: 54-Pin Plastic TSOP "TG/P" (400 mil) ............................................................................................... 15
Figure 8: 60-Ball TFBGA "BB/FB" (8mm x 16mm) (x4, x8) ............................................................................... 16
Figure 9: 54-Ball VFBGA "BG/FG" (8mm x 14mm) (x16) .................................................................................. 17
Figure 10: 54-Ball VFBGA "B4/F4" (8mm x 8mm) (x16) ................................................................................... 18
Figure 11: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 21
Figure 12: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 21
Figure 13: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 22
Figure 14: ACTIVE Command ........................................................................................................................ 32
Figure 15: READ Command ........................................................................................................................... 33
Figure 16: WRITE Command ......................................................................................................................... 34
Figure 17: PRECHARGE Command ................................................................................................................ 35
Figure 18: Initialize and Load Mode Register .................................................................................................. 43
Figure 19: Mode Register Definition ............................................................................................................... 45
Figure 20: CAS Latency .................................................................................................................................. 48
Figure 21: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 49
Figure 22: Consecutive READ Bursts .............................................................................................................. 51
Figure 23: Random READ Accesses ................................................................................................................ 52
Figure 24: READ-to-WRITE ............................................................................................................................ 53
Figure 25: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 54
Figure 26: READ-to-PRECHARGE .................................................................................................................. 54
Figure 27: Terminating a READ Burst ............................................................................................................. 55
Figure 28: Alternating Bank Read Accesses ..................................................................................................... 56
Figure 29: READ Continuous Page Burst ......................................................................................................... 57
Figure 30: READ DQM Operation ................................................................................................................ 58
Figure 31: WRITE Burst ................................................................................................................................. 59
Figure 32: WRITE-to-WRITE .......................................................................................................................... 60
Figure 33: Random WRITE Cycles .................................................................................................................. 61
Figure 34: WRITE-to-READ ............................................................................................................................ 61
Figure 35: WRITE-to-PRECHARGE ................................................................................................................. 62
Figure 36: Terminating a WRITE Burst ............................................................................................................ 63
Figure 37: Alternating Bank Write Accesses ..................................................................................................... 64
Figure 38: WRITE Continuous Page Burst ..................................................................................................... 65
Figure 39: WRITE DQM Operation ............................................................................................................... 66
Figure 40: READ With Auto Precharge Interrupted by a READ ......................................................................... 68
Figure 41: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 69
Figure 42: READ With Auto Precharge ............................................................................................................ 70
Figure 43: READ Without Auto Precharge ....................................................................................................... 71
Figure 44: Single READ With Auto Precharge .................................................................................................. 72
Figure 45: Single READ Without Auto Precharge ............................................................................................. 73
Figure 46: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 74
Figure 47: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 74
Figure 48: WRITE With Auto Precharge ........................................................................................................... 75
Figure 49: WRITE Without Auto Precharge ..................................................................................................... 76
Figure 50: Single WRITE With Auto Precharge ................................................................................................. 77

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 256Mb: x4, x8, x16 SDRAM
Features

Figure 51: Single WRITE Without Auto Precharge ............................................................................................ 78

Figure 52: Auto Refresh Mode ........................................................................................................................ 80
Figure 53: Self Refresh Mode .......................................................................................................................... 82
Figure 54: Power-Down Mode ........................................................................................................................ 83
Figure 55: Clock Suspend During WRITE Burst ............................................................................................... 84
Figure 56: Clock Suspend During READ Burst ................................................................................................. 85
Figure 57: Clock Suspend Mode ..................................................................................................................... 86

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 256Mb: x4, x8, x16 SDRAM
Features

List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Address Table ..................................................................................................................................... 2
Table 3: 256Mb SDR Part Numbering ............................................................................................................... 2
Table 4: Pin and Ball Descriptions .................................................................................................................. 14
Table 5: Temperature Limits .......................................................................................................................... 19
Table 6: Thermal Impedance Simulated Values ............................................................................................... 20
Table 7: Absolute Maximum Ratings .............................................................................................................. 23
Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 23
Table 9: Capacitance ..................................................................................................................................... 24
Table 10: IDD Specifications and Conditions (x4, x8, x16) Revision D ................................................................ 25
Table 11: IDD Specifications and Conditions (x4, x8, x16) Revision G ................................................................ 25
Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 27
Table 13: AC Functional Characteristics ......................................................................................................... 28
Table 14: Truth Table Commands and DQM Operation ................................................................................. 31
Table 15: Truth Table Current State Bank n, Command to Bank n .................................................................. 37
Table 16: Truth Table Current State Bank n, Command to Bank m ................................................................. 39
Table 17: Truth Table CKE ........................................................................................................................... 41
Table 18: Burst Definition Table ..................................................................................................................... 47

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 256Mb: x4, x8, x16 SDRAM
General Description

General Description
The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory contain-
ing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchro-
nous interface (all signals are registered on the positive edge of the clock signal, CLK).
Each of the x4s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4
bits. Each of the x8s 67,108,864-bit banks is organized as 8192 rows by 1024 columns by
8 bits. Each of the x16s 67,108,864-bit banks is organized as 8192 rows by 512 columns
by 16 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the
bank; A[12:0] select the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper-
ation. This architecture is compatible with the 2n rule of prefetch architectures, but it
also allows the column address to be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank while accessing one of the other
three banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran-
dom-access operation.
The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh
mode is provided, along with a power-saving, power-down mode. All inputs and out-
puts are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks to hide precharge time, and
the capability to randomly change column addresses on each clock cycle during a burst
access.

Automotive Temperature
The automotive temperature (AT) option adheres to the following specifications:
16ms refresh rate
Self refresh not supported
Ambient and case temperature cannot be less than 40C or greater than +105C

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 256Mb: x4, x8, x16 SDRAM
Functional Block Diagrams

Functional Block Diagrams

Figure 1: 64 Meg x 4 Functional Block Diagram

CKE
CLK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
BANK1
RAS#

REFRESH 13
MODE REGISTER COUNTER
ROW- 13 BANK0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 1 1
12 8192
LATCH ARRAY DQM
13 & (8192 x 2048 x 4)
DECODER

SENSE AMPLIFIERS DATA

4 OUTPUT
8192 REGISTER

2 I/O GATING 4 DQ[3:0]

DQM MASK LOGIC
BANK READ DATA LATCH
A[12:0] ADDRESS CONTROL WRITE DRIVERS
15
BA[1:0] REGISTER LOGIC DATA
2 4 INPUT
2048 REGISTER
(x4)

COLUMN
DECODER
COLUMN-
ADDRESS 11
11 COUNTER/
LATCH

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 256Mb: x4, x8, x16 SDRAM
Functional Block Diagrams

Figure 2: 32 Meg x 8 Functional Block Diagram

CKE
CLK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
BANK1
RAS#

REFRESH 13
MODE REGISTER COUNTER
ROW- 13 BANK0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 1 1
12 8192
LATCH ARRAY DQM
13 & (8192 x 1024 x 8)
DECODER

SENSE AMPLIFIERS DATA

8 OUTPUT
8192 REGISTER

2 I/O GATING 8 DQ[7:0]

DQM MASK LOGIC
BANK READ DATA LATCH
A[12:0] ADDRESS CONTROL WRITE DRIVERS
BA[1:0] 15
REGISTER LOGIC DATA
2 8 INPUT
1024 REGISTER
(x8)

COLUMN
DECODER
COLUMN-
ADDRESS 10
10 COUNTER/
LATCH

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 256Mb: x4, x8, x16 SDRAM
Functional Block Diagrams

Figure 3: 16 Meg x 16 Functional Block Diagram

CKE
CLK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
BANK1
RAS#

REFRESH 13
MODE REGISTER COUNTER
ROW- 13 BANK0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 2 2
12 8192 DQML,
LATCH ARRAY
13 & DQMH
(8192 x 512 x 16)
DECODER

SENSE AMPLIFIERS DATA

16 OUTPUT
8192 REGISTER

2 I/O GATING 16 DQ[15:0]

DQM MASK LOGIC
BANK READ DATA LATCH
A[12:0] ADDRESS CONTROL WRITE DRIVERS
15
BA[1:0] REGISTER LOGIC DATA
2 16 INPUT
512 REGISTER
(x16)

COLUMN
DECODER
COLUMN-
ADDRESS 9
9 COUNTER/
LATCH

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 256Mb: x4, x8, x16 SDRAM
Pin and Ball Assignments and Descriptions

Pin and Ball Assignments and Descriptions

Figure 4: 54-Pin TSOP (Top View)

x4 x8 x16 x16 x8 x4
- - VDD 1 54 VSS - -
NC DQ0 DQ0 2 53 DQ15 DQ7 NC
- - VDDQ 3 52 VSSQ - -
NC NC DQ1 4 51 DQ14 NC NC
DQ0 DQ1 DQ2 5 50 DQ13 DQ6 DQ3
- - VSSQ 6 49 VDDQ - -
NC NC DQ3 7 48 DQ12 NC NC
NC DQ2 DQ4 8 47 DQ11 DQ5 NC
- - VDDQ 9 46 VSSQ - -
NC NC DQ5 10 45 DQ10 NC NC
DQ1 DQ3 DQ6 11 44 DQ9 DQ4 DQ2
- - VSSQ 12 43 VDDQ - -
NC NC DQ7 13 42 DQ8 NC NC
- - VDD 14 41 VSS - -
NC NC DQML 15 40 NC - -
- - WE# 16 39 DQMH DQM DQM
- - CAS# 17 38 CLK - -
- - RAS# 18 37 CKE - -
- - CS# 19 36 A12 - -
- - BA0 20 35 A11 - -
- - BA1 21 34 A9 - -
- - A10 22 33 A8 - -
- - A0 23 32 A7 - -
- - A1 24 31 A6 - -
- - A2 25 30 A5 - -
- - A3 26 29 A4 - -
- - VDD 27 28 VSS - -

Notes: 1. The # symbol indicates that the signal is active LOW. A dash (-) indicates that the x8 and
x4 pin function is the same as the x16 pin function.
2. Package may or may not be assembled with a location notch.

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 256Mb: x4, x8, x16 SDRAM
Pin and Ball Assignments and Descriptions

Figure 5: 60-Ball FBGA (Top View)

64 Meg x 4 SDRAM 32 Meg x 8 SDRAM

8mm x 16mm FB 8mm x 16mm FB

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

A NC VSS VDD NC A DQ7 VSS VDD DQ0

B NC VSSQ VDDQ NC B NC VSSQ VDDQ NC

C VDDQ DQ3 DQ0 VSSQ C VDDQ DQ6 DQ1 VSSQ

D NC NC NC NC D DQ5 NC NC DQ2

E NC VSSQ VDDQ NC E NC VSSQ VDDQ NC

F VDDQ DQ2 DQ1 VSSQ F VDDQ DQ4 DQ3 VSSQ

G NC NC NC NC G NC NC NC NC

H NC VSS VDD NC H NC VSS VDD NC

J NC DQM WE# CAS# J NC DQM WE# CAS#

K NC CK RAS# NC K NC CK RAS# NC

L A12 CKE NC CS# L A12 CKE NC CS#

M A11 A9 BA1 BA0 M A11 A9 BA1 BA0

N A8 A7 A0 A10 N A8 A7 A0 A10

P A6 A5 A2 A1 P A6 A5 A2 A1

R A4 VSS VDD A3 R A4 VSS VDD A3

Depopulated Balls Depopulated Balls

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 256Mb: x4, x8, x16 SDRAM
Pin and Ball Assignments and Descriptions

Figure 6: 54-Ball VFBGA (Top View)

1 2 3 4 5 6 7 8 9

A VSS DQ15 VSSQ VDDQ DQ0 VDD

B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1

C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3

D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5

E DQ8 NC VSS VDD LDQM DQ7

F UDQM CLK CKE CAS# RAS# WE#

G A12 A11 A9 BA0 BA1 CS#

H A8 A7 A6 A0 A1 A10

J VSS A5 A4 A3 A2 VDD

Depopulated Balls
Note: 1. The balls at A4, A5, and A6 are absent from the physical package. They are included to
illustrate that rows 4, 5, and 6 exist, but contain no solder balls.

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 256Mb: x4, x8, x16 SDRAM
Pin and Ball Assignments and Descriptions

Table 4: Pin and Ball Descriptions

Symbol Type Description

CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides precharge power-down and SELF REFRESH operation (all banks idle), active
power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in pro-
gress). CKE is synchronous except after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same mode. The input buffers, in-
cluding CLK, are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decod-
er. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in
progress will continue, and DQM operation will retain its DQ mask capability while CS# is
HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-
ered part of the command code.
CAS#, RAS#, Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.
WE#
x4, x8: Input Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and
DQM an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are High-Z (two-clock latency) during a READ cycle. LDQM corresponds to
x16:
DQ[7:0], and UDQM corresponds to DQ[15:8]. LDQM and UDQM are considered same-state
DQML, DQMH
when referenced as DQM.
LDQM, UDQM
(54-ball)
BA[1:0] Input Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRECHARGE
command is being applied.
A[12:0] Input Address inputs: A[12:0] are sampled during the ACTIVE command (row address A[12:0]) and
READ or WRITE command (column address A[9:0] and A11 for x4; A[9:0] for x8; A[8:0] for x16;
with A10 defining auto precharge) to select one location out of the memory array in the re-
spective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to
be precharged (A10 HIGH) or bank selected by BA[1:0] (LOW). The address inputs also provide
the op-code during a LOAD MODE REGISTER command.
x16: I/O Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 42, 45, 48, and 51 are NC for x8; and
DQ[15:0] pins 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NC for x4).
x8: I/O Data input/output: Data bus for x8 (pins 2, 8, 47, 53 are NC for x4).
DQ[7:0]
x4: I/O Data input/output: Data bus for x4.
DQ[3:0]
VDDQ Supply DQ power: DQ power to the die for improved noise immunity.
VSSQ Supply DQ ground: DQ ground to the die for improved noise immunity.
VDD Supply Power supply: +3.3V 0.3V.
VSS Supply Ground.
NC These should be left unconnected. For x4 and x8 parts, G1 is a no connect, but may be used as
A12 in future designs.

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 256Mb: x4, x8, x16 SDRAM
Package Dimensions

Package Dimensions

Figure 7: 54-Pin Plastic TSOP "TG/P" (400 mil)

0.10
2X 2.28
Pin #1 ID
1.2 MAX

0.375 0.075 TYP

2X R 0.75
0.80 TYP
2X R 1.00 (for reference
22.22 0.08
22.42 only)

Package may
or may not be
assembled with
a location notch.

0.71

Plated lead finish: 90% Sn, 10% Pb or 100%Sn

Plastic package material: epoxy novolac
Package width and length do not
10.16 0.08 include mold protrusion. Allowable
protrusion is 0.25 per side.
11.76 0.20
Gage plane
Package may or may not be 0.25
assembled with a location notch. +0.10
+0.03 0.10
0.15 -0.05
-0.02

0.50 0.10
See detail A 0.80
Detail A

Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
3. 2X means the notch is present in two locations (both ends of the device).
4. Package may or may not be assembled with a location notch.

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 256Mb: x4, x8, x16 SDRAM
Package Dimensions

Figure 8: 60-Ball TFBGA "BB/FB" (8mm x 16mm) (x4, x8)

Seating
plane
A 0.12 A

60X 0.45
Dimensions apply
to solder balls
post-reflow on 0.33 Ball A1 ID Ball A1 ID
NSMD ball pads.
8 7 2 1

A
B
C
D
E
F
16 0.1 G
H
11.2 CTR J
K
L
M
N
P
0.8 TYP
R

0.8 TYP 1.1 0.1

5.6 CTR 0.25 MIN

8 0.1

Notes: 1. All dimensions are in millimeters.

2. Recommended pad size for PCB is 0.33mm 0.025mm.
3. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or 62% Sn, 2% Ag, 36% Pb.
4. Topside part-marking decoder is available at www.micron.com/decoder.

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 256Mb: x4, x8, x16 SDRAM
Package Dimensions

Figure 9: 54-Ball VFBGA "BG/FG" (8mm x 14mm) (x16)

0.65 0.05

SEATING PLANE

C
0.12 C

6.40 1.00 MAX

54X 0.45 0.80 TYP BALL A1 ID
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE- BALL A1 ID
REFLOW DIAMETER IS 0.42
BALL A9 BALL A1

0.80 TYP

6.40 CL 14.00 0.10

3.20 0.05

7.00 0.05

CL
3.20 0.05
4.00 0.05 MOLD COMPOUND: EPOXY NOVOLAC
8.00 0.10 SUBSTRATE MATERIAL: PLASTIC LAMINATE
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR
96.5% Sn, 3%Ag, 0.5% Cu
SOLDER MASK DEFINED BALL PADS: 0.40

Notes: 1. All dimensions are in millimeters.

2. Recommended pad size for PCB is 0.4mm 0.065mm.
3. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or 62% Sn, 2% Ag, 36% Pb.
4. Topside part-marking decoder is available at www.micron.com/decoder.

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 256Mb: x4, x8, x16 SDRAM
Package Dimensions

Figure 10: 54-Ball VFBGA "B4/F4" (8mm x 8mm) (x16)

Seating plane

A 0.12 A

54X 0.45
Dimensions apply
to solder balls post- Ball A1 ID Ball A1 ID
reflow on0.40 SMD (covered by SR)
ball pads. 9 8 7 3 2 1

A
B
C
D
6.4 CTR
E
8 0.1
F
G
H
0.8 TYP
J

0.8 TYP 0.9 0.1

6.4 CTR 0.25 MIN

8 0.1

Notes: 1. All dimensions are in millimeters.

2. Recommended pad size for PCB is 0.4mm 0.065mm.
3. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or 62% Sn, 2% Ag, 36% Pb.
4. Topside part-marking decoder is available at www.micron.com/decoder.

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 256Mb: x4, x8, x16 SDRAM
Temperature and Thermal Impedance

Temperature and Thermal Impedance

It is imperative that the SDRAM devices temperature specifications, shown in Table 5
(page 19), be maintained to ensure the junction temperature is in the proper operat-
ing range to meet data sheet specifications. An important step in maintaining the prop-
er junction temperature is using the devices thermal impedances correctly. The ther-
mal impedances are listed in Table 6 (page 20) for the applicable die revision and
packages being made available. These thermal impedance values vary according to the
density, package, and particular design used for each device.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, Thermal Applications prior to using the thermal impedan-
ces listed in Table 6 (page 20). To ensure the compatibility of current and future de-
signs, contact Micron Applications Engineering to confirm thermal impedance values.
The SDRAM devices safe junction temperature range can be maintained when the T C
specification is not exceeded. In applications where the devices ambient temperature
is too high, use of forced air and/or heat sinks may be required to satisfy the case tem-
perature specifications.

Table 5: Temperature Limits

Parameter Symbol Min Max Unit Notes

Operating case temperature Commercial TC 0 80 C 1, 2, 3, 4
Industrial 40 90
Automotive 40 105
Junction temperature Commercial TJ 0 85 C 3
Industrial 40 95
Automotive 40 110
Ambient temperature Commercial TA 0 70 C 3, 5
Industrial 40 85
Automotive 40 105
Peak reflow temperature TPEAK 260 C

Notes: 1. MAX operating case temperature, TC, is measured in the center of the package on the
top side of the device, as shown in Figure 11 (page 21), Figure 12 (page 21), and Fig-
ure 13 (page 22).
2. Device functionality is not guaranteed if the device exceeds maximum TC during opera-
tion.
3. All temperature specifications must be satisfied.
4. The case temperature should be measured by gluing a thermocouple to the top-center
of the component. This should be done with a 1mm bead of conductive epoxy, as de-
fined by the JEDEC EIA/JESD51 standards. Take care to ensure that the thermocouple
bead is touching the case.
5. Operating ambient temperature surrounding the package.

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 256Mb: x4, x8, x16 SDRAM
Temperature and Thermal Impedance

Table 6: Thermal Impedance Simulated Values

JA (C/W) JA (C/W) JA (C/W)

Die Airflow = Airflow = Airflow =
Revision Package Substrate 0m/s 1m/s 2m/s JB (C/W) JC (C/W)
D 54-pin TSOP Low Con- 81 63.8 57.6 45.3 10.3
(TG, P) ductivity
High Con- 55 47.3 44.5 39.1
ductivity
54-ball VFBGA Low Con- 64.9 50.8 44.8 31.4 3.2
(BG, FG) ductivity
High Con- 51.5 41.6 38.1 31.4
ductivity
60-ball FBGA Low Con- 67 51.2 47.8 19.7 6.7
(BB, FB) ductivity
High Con- 40.9 35.1 32.2 18.6
ductivity
G 54-pin TSOP Low Con- 122.3 105.6 98.1 89.5 20.7
(TG, P) ductivity
High Con- 101.9 93.5 88.8 87.6
ductivity
54-ball VFBGA Low Con- 96.9 81.9 81.9 69.5 11.5
(B4, F4) ductivity
High Con- 74.0 66.3 62.7 60.7
ductivity
60-ball FBGA Low Con- 68.8 55.9 51.1 42.1 10.9
(BB, FB) ductivity
High Con- 47.9 42.0 39.9 34.9
ductivity

Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications
Engineering to confirm thermal impedance values.
2. Thermal resistance data is sampled from multiple lots, and the values should be viewed
as typical.
3. These are estimates; actual results may vary.

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Temperature and Thermal Impedance

Figure 11: Example: Temperature Test Point Location, 54-Pin TSOP (Top View)

22.22mm

11.11mm
Test point

10.16mm

5.08mm

Note: 1. Package may or may not be assembled with a location notch.

Figure 12: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View)

8.00mm

4.00mm

Test point

14.00mm

7.00mm

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 256Mb: x4, x8, x16 SDRAM
Temperature and Thermal Impedance

Figure 13: Example: Temperature Test Point Location, 60-Ball FBGA (Top View)

8.00mm

4.00mm

Test point

16.00mm

8.00mm

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 256Mb: x4, x8, x16 SDRAM
Electrical Specifications

Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

Table 7: Absolute Maximum Ratings

Voltage/Temperature Symbol Min Max Unit Notes

Voltage on VDD/VDDQ supply relative to VSS VDD/VDDQ 1 4.6 V 1
Voltage on inputs, NC, or I/O balls relative to VSS VIN 1 4.6
Storage temperature (plastic) TSTG 55 150 C
Power dissipation 1 W

Note: 1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed
VDD.

Table 8: DC Electrical Characteristics and Operating Conditions

Notes 13 apply to all parameters and conditions; VDD/VDDQ = 3.3V 0.3V
Parameter/Condition Symbol Min Max Unit Notes
Supply voltage VDD, VDDQ 3 3.6 V
Input high voltage: Logic 1; All inputs VIH 2 VDD + 0.3 V 4
Input low voltage: Logic 0; All inputs VIL 0.3 0.8 V 4
Output high voltage: IOUT = 4mA VOH 2.4 V
Output low voltage: IOUT = 4mA VOL 0.4 V
Input leakage current: Any input 0V VIN VDD (All IL 5 5 A
other balls not under test = 0V)
Output leakage current: DQ are disabled; 0V VOUT IOZ 5 5 A
VDDQ
Operating temperature: Commercial TA 0 70 C
Industrial TA 40 85 C
Automotive TA 40 105 C

Notes: 1. All voltages referenced to VSS.

2. The minimum specifications are used only to indicate cycle time at which proper opera-
tion over the full temperature range is ensured; (0C TA +70C (commercial), 40C
TA +85C (industrial), and 40C TA +105C (automotive)).
3. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh requirement is excee-
ded.
4. VIH overshoot: VIH,max = VDDQ + 2V for a pulse width 3ns, and the pulse width cannot
be greater than one-third of the cycle rate. VIL undershoot: VIL,min = 2V for a pulse
width 3ns.

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 256Mb: x4, x8, x16 SDRAM
Electrical Specifications

Table 9: Capacitance
Note 1 applies to all parameters and conditions
Package Parameter Symbol Min Max Unit Notes
TSOP package Input capacitance: CLK CL1 2.5 3.5 pF 2
Input capacitance: All other input-only CL2 2.5 3.8 pF 3
balls
Input/output capacitance: DQ CL0 4 6 pF 4
FBGA package Input capacitance: CLK CL1 1.5 3.5 pF 5
Input capacitance: All other input-only CL2 1.5 3.8 pF 6
balls
Input/output capacitance: DQ CL0 3 6 pF 7

Notes: 1. This parameter is sampled. VDD, VDDQ = 3.3V; f = 1 MHz, TA = 25C; pin under test biased
at 1.4V.
2. PC100 specifies a maximum of 4pF.
3. PC100 specifies a maximum of 5pF.
4. PC100 specifies a maximum of 6.5pF.
5. PC133 specifies a minimum of 2.5pF.
6. PC133 specifies a minimum of 2.5pF.
7. PC133 specifies a minimum of 3.0pF.

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 256Mb: x4, x8, x16 SDRAM
Electrical Specifications IDD Parameters

Electrical Specifications IDD Parameters

Table 10: IDD Specifications and Conditions (x4, x8, x16) Revision D
Notes 15 apply to all parameters and conditions; VDD/VDDQ = +3.3V 0.3V
Max
Parameter/Condition Symbol -6A -7E -75 Unit Notes
Operating current: Active mode; Burst = 2; READ or WRITE; tRC IDD1 135 135 125 mA 6, 7, 8,
= tRC (MIN) 9
Standby current: Power-down mode; All banks idle; CKE = IDD2 2 2 2 mA 9
LOW
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All IDD3 40 40 40 mA 6, 8, 9,
banks active after tRCD met; No accesses in progress 10
Operating current: Burst mode; Page burst; READ or WRITE; IDD4 135 135 135 mA 6, 7, 8,
All banks active 9
Auto refresh current: CKE = HIGH; CS# = tRFC = tRFC (MIN) IDD5 285 285 270 mA 6, 7, 8,
HIGH tRFC = 7.813s IDD6 3.5 3.5 3.5 mA 9, 10,
tRFC 11
= 1.953s (AT) IDD6 8 8 8 mA
Self refresh current: CKE 0.2V Standard IDD7 2.5 2.5 2.5 mA
Low power (L) IDD7 1.5 1.5 mA 12

Table 11: IDD Specifications and Conditions (x4, x8, x16) Revision G
Notes 15 apply to all parameters and conditions; VDD/VDDQ = +3.3V 0.3V
Max
Parameter/Condition Symbol -6A -7E Unit Notes
Operating current: Active mode; Burst = 2; READ or WRITE; tRC = tRC IDD1 100 100 mA 6, 7, 8,
(MIN) 9
Standby current: Power-down mode; All banks idle; CKE = LOW IDD2 2.5 2.5 mA 9
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks ac- IDD3 35 35 mA 6, 8, 9,
tive after tRCD met; No accesses in progress 10
Operating current: Burst mode; Page burst; READ or WRITE; All IDD4 100 100 mA 6, 7, 8,
banks active 9
Auto refresh current: CKE = HIGH; CS# = HIGH tRFC = tRFC (MIN) IDD5 150 150 mA 6, 7, 8,
tRFC = 7.813s IDD6 4 4 mA 9, 10,
tRFC 11
= 1.953s (AT) IDD6 8 8 mA
Self refresh current: CKE 0.2V Standard IDD7 3 3 mA
Low power (L) IDD7 1.5 1.5 mA 12

Notes: 1. All voltages referenced to VSS.

2. The minimum specifications are used only to indicate cycle time at which proper opera-
tion over the full temperature range is ensured; (0C TA +70C (commercial), 40C
TA +85C (industrial), and 40C TA +105C (automotive)).
3. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH

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 256Mb: x4, x8, x16 SDRAM
Electrical Specifications IDD Parameters

command wake-ups should be repeated any time the tREF refresh requirement is excee-
ded.
4. AC operating and IDD test conditions have VIL = 0V and VIH = 3.0V using a measurement
reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is
measured from VIL, max and VIH,min and no longer from the 1.5V midpoint. CLK should
always be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09.
5. IDD specifications are tested after the device is properly initialized.
6. IDD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time and the outputs open.
7. The IDD current will increase or decrease proportionally according to the amount of fre-
quency alteration for the test condition.
8. Address transitions average one transition every two clocks.
9. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns.
10. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
11. CKE is HIGH during REFRESH command period tRFC (MIN) else CKE is LOW. The IDD6 limit
is actually a nominal value and does not result in a fail value.
12. Enables on-chip refresh and address counters.
13. PC100 specifies a maximum of 4pF.
14. PC100 specifies a maximum of 5pF.

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 256Mb: x4, x8, x16 SDRAM
Electrical Specifications AC Operating Conditions

Electrical Specifications AC Operating Conditions

Table 12: Electrical Characteristics and Recommended AC Operating Conditions

Notes 15 apply to all parameters and conditions
-6A -7E -75
Parameter Symbol Min Max Min Max Min Max Unit Notes
Access time from CLK CL = 3 tAC(3) 5.4 5.4 5.4 ns 7
(positive edge) CL = 2 tAC(2) 7.56 5.4 6 ns 7
CL = 1 tAC(1) 176 ns 7
Address hold time tAH 0.8 0.8 0.8 ns
Address setup time tAS 1.5 1.5 1.5 ns
CLK high-level width tCH 2.5 2.5 2.5 ns
CLK low-level width tCL 2.5 2.5 2.5 ns
Clock cycle time CL = 3 tCK(3) 6 7 7.5 ns 8
CL = 2 tCK(2) 106 7.5 10 ns 8
CL = 1 tCK(1) 206 ns 8
CKE hold time tCKH 0.8 0.8 0.8 ns
CKE setup time tCKS 1.5 1.5 1.5 ns
CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 0.8 ns
CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 1.5 ns
Data-in hold time tDH 0.8 0.8 0.8 ns
Data-in setup time tDS 1.5 1.5 1.5 ns
Data-out High-Z time CL = 3 tHZ(3) 5.4 5.4 5.4 ns 9
CL = 2 tHZ(2) 7.56 5.4 6 ns 9
CL = 1 tHZ(1) 176 ns 9
Data-out Low-Z time tLZ 1 1 1 ns
Data-out hold time (load) tOH 3 3 3 ns
Data-out hold time (no load) tOHn 1.8 1.8 1.8 ns 10
ACTIVE-to-PRECHARGE command tRAS 42 120,000 37 120,000 44 120,000 ns
ACTIVE-to-ACTIVE command period tRC 60 60 66 ns 11
ACTIVE-to-READ or WRITE delay tRCD 18 15 20 ns
Refresh period (8192 rows) tREF 64 64 64 ms
Refresh period automotive (8192 rows) tREF 16 16 16 ms
AT
AUTO REFRESH period tRFC 60 66 66 ns
PRECHARGE command period tRP 18 15 20 ns
ACTIVE bank a to ACTIVE bank b com- tRRD 12 14 15 ns
mand
Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 ns 12
WRITE recovery time tWR 1 CLK + 1 CLK + 1 CLK + ns 13
6ns 7ns 7.5ns
12 14 15 ns 14

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 256Mb: x4, x8, x16 SDRAM
Electrical Specifications AC Operating Conditions

Table 12: Electrical Characteristics and Recommended AC Operating Conditions (Continued)

Notes 15 apply to all parameters and conditions
-6A -7E -75
Parameter Symbol Min Max Min Max Min Max Unit Notes
Exit SELF REFRESH-to-ACTIVE command tXSR 67 67 75 ns 15

Table 13: AC Functional Characteristics

Notes 25 apply to all parameters and conditions
Parameter Symbol -6A -7E -75 Unit Notes
Last data-in to burst STOP command tBDL 1 1 1 tCK 16
READ/WRITE command to READ/WRITE command tCCD 1 1 1 tCK 16
Last data-in to new READ/WRITE command tCDL 1 1 1 tCK 16
CKE to clock disable or power-down entry mode tCKED 1 1 1 tCK 17
Data-in to ACTIVE command tDAL 5 4 5 tCK 18, 19
Data-in to PRECHARGE command tDPL 2 2 2 tCK 19, 20
DQM to input data delay tDQD 0 0 0 tCK 16
DQM to data mask during WRITEs tDQM 0 0 0 tCK 16
DQM to data High-Z during READs tDQZ 2 2 2 tCK 16
WRITE command to input data delay tDWD 0 0 0 tCK 16
LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 2 tCK 21
CKE to clock enable or power-down exit setup mode tPED 1 1 1 tCK 17
Last data-in to PRECHARGE command tRDL 2 2 2 tCK 19, 20
Data-out High-Z from PRECHARGE command CL = 3 tROH(3) 3 3 3 tCK 16
CL = 2 tROH(2) 2 2 2 tCK 16
CL = 1 tROH(1) 1 tCK 16

Notes: 1. Minimum specifications are used only to indicate the cycle time at which proper opera-
tion over the full temperature range is ensured:
0C TA +70C (commercial)
-40C TA +85C (industrial)
-40C TA +105C (automotive)
2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh requirement is excee-
ded.
3. In addition to meeting the transition rate specification, the clock and CKE must transit
between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. Outputs measured at 1.5V with equivalent load:
Q
50pF

5. AC operating and IDD test conditions have VIL = 0V and VIH = 3.0V using a measurement
reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is

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 256Mb: x4, x8, x16 SDRAM
Electrical Specifications AC Operating Conditions

measured from VIL,max and VIH,min and no longer from the 1.5V midpoint. CLK should al-
ways be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09.
6. Not applicable for Revision D.
7. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.

8. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge states
(READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce
the data rate.
9. tHZ defines the time at which the output achieves the open circuit condition; it is not a

reference to VOH or VOL. The last valid data element will meet tOH before going High-Z.
10. Parameter guaranteed by design.
11. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in reduction of the product lifetime.
12. AC characteristics assume tT = 1ns.
13. Auto precharge mode only. The precharge timing budget (tRP) begins at 6ns for -6A, 7ns
for -7E, and 7.5ns for -75 after the first clock delay, after the last WRITE is executed.
14. Precharge mode only.
15. CLK must be toggled a minimum of two times during this period.
16. Required clocks are specified by JEDEC functionality and are not dependent on any tim-
ing parameter.
17. Timing is specified by tCKS. Clock(s) specified as a reference only at minimum cycle rate.
18. Timing is specified by tWR plus tRP. Clock(s) specified as a reference only at minimum cy-
cle rate.
19. Based on tCK = 7.5ns for -75 and -7E, 6ns for -6A.
20. Timing is specified by tWR.
21. JEDEC and PC100 specify three clocks.

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 256Mb: x4, x8, x16 SDRAM
Functional Description

Functional Description
In general, 256Mb SDRAM devices (16 Meg x 4 x 4 banks, 8 Meg x 8 x 4 banks, and 4 Meg
x 16 x 4 banks) are quad-bank DRAM that operate at 3.3V and include a synchronous
interface. All signals are registered on the positive edge of the clock signal, CLK. Each of
the x4s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Each
of the x8s 67,108,864-bit banks is organized as 8192 rows by 1024 columns by 8 bits.
Each of the x16s 67,108,864-bit banks is organized as 8192 rows by 512 columns by 16
bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE
command are used to select the bank and row to be accessed (BA0 and BA1 select the
bank, A[12:0] select the row). The address bits (x4: A[9:0], A11; x8: A[9:0]; x16: A[8:0]) reg-
istered coincident with the READ or WRITE command are used to select the starting
column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections pro-
vide detailed information covering device initialization, register definition, command
descriptions, and device operation.

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 256Mb: x4, x8, x16 SDRAM
Commands

Commands
The following table provides a quick reference of available commands, followed by a
written description of each command. Additional Truth Tables (Table 15 (page 37), Ta-
ble 16 (page 39), and Table 17 (page 41)) provide current state/next state informa-
tion.

Table 14: Truth Table Commands and DQM Operation

Note 1 applies to all parameters and conditions
Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ Notes
COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (select bank and activate row) L L H H X Bank/row X 2
READ (select bank and column, and start READ burst) L H L H L/H Bank/col X 3
WRITE (select bank and column, and start WRITE burst) L H L L L/H Bank/col Valid 3
BURST TERMINATE L H H L X X Active 4
PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5
AUTO REFRESH or SELF REFRESH (enter self refresh mode) L L L H X X X 6, 7
LOAD MODE REGISTER L L L L X Op-code X 8
Write enable/output enable X X X X L X Active 9
Write inhibit/output High-Z X X X X H X High-Z 9

Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1
determine which bank is made active.
3. A[0:i] provide column address (where i = the most significant column address for a given
device configuration). A10 HIGH enables the auto precharge feature (nonpersistent),
while A10 LOW disables the auto precharge feature. BA0 and BA1 determine which
bank is being read from or written to.
4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the com-
mand could coincide with data on the bus. However, the DQ column reads a Dont
Care state to illustrate that the BURST TERMINATE command can occur when there is
no data present.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks pre-
charged and BA0, BA1 are Dont Care.
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are Dont Care ex-
cept for CKE.
8. A[11:0] define the op-code written to the mode register.
9. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
delay).

COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by
the device, regardless of whether the CLK signal is enabled. The device is effectively de-
selected. Operations already in progress are not affected.

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 256Mb: x4, x8, x16 SDRAM
Commands

NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to the selected device
(CS# is LOW). This prevents unwanted commands from being registered during idle or
wait states. Operations already in progress are not affected.

LOAD MODE REGISTER (LMR)

The mode registers are loaded via inputs A[n:0] (where An is the most significant ad-
dress term), BA0, and BA1(see Mode Register (page 44)). The LOAD MODE REGISTER
command can only be issued when all banks are idle and a subsequent executable com-
mand cannot be issued until tMRD is met.

ACTIVE
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The value on the BA0, BA1 inputs selects the bank, and the address provided se-
lects the row. This row remains active for accesses until a PRECHARGE command is is-
sued to that bank. A PRECHARGE command must be issued before opening a different
row in the same bank.

Figure 14: ACTIVE Command

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

Address Row address

BA0, BA1 Bank address

Dont Care

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 256Mb: x4, x8, x16 SDRAM
Commands

READ
The READ command is used to initiate a burst read access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-
umn location. The value on input A10 determines whether auto precharge is used. If au-
to precharge is selected, the row being accessed is precharged at the end of the READ
burst; if auto precharge is not selected, the row remains open for subsequent accesses.
Read data appears on the DQ subject to the logic level on the DQM inputs two clocks
earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-
Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data.

Figure 15: READ Command

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

Address Column address

EN AP
A101
DIS AP

BA0, BA1 Bank address

Dont Care

Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

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 256Mb: x4, x8, x16 SDRAM
Commands

WRITE
The WRITE command is used to initiate a burst write access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-
umn location. The value on input A10 determines whether auto precharge is used. If au-
to precharge is selected, the row being accessed is precharged at the end of the write
burst; if auto precharge is not selected, the row remains open for subsequent accesses.
Input data appearing on the DQ is written to the memory array, subject to the DQM in-
put logic level appearing coincident with the data. If a given DQM signal is registered
LOW, the corresponding data is written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that
byte/column location.

Figure 16: WRITE Command

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

Address Column address

EN AP
A101
DIS AP

BA0, BA1 Bank address

Valid address Dont Care

Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

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 256Mb: x4, x8, x16 SDRAM
Commands

PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only one bank is
precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as
Dont Care. After a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands are issued to that bank.

Figure 17: PRECHARGE Command

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

Address

All banks
A10
Bank selected

BA0, BA1 Bank address

Valid address Dont Care

BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or continu-
ous page bursts. The most recently registered READ or WRITE command prior to the
BURST TERMINATE command is truncated.

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 256Mb: x4, x8, x16 SDRAM
Commands

REFRESH
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All active banks must be pre-
charged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command
should not be issued until the minimum tRP has been met after the PRECHARGE com-
mand, as shown in Bank/Row Activation (page 49).
The addressing is generated by the internal refresh controller. This makes the address
bits a Dont Care during an AUTO REFRESH command. Regardless of device width,
the 256Mb SDRAM requires 8192 AUTO REFRESH cycles every 64ms (commercial and
industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command
every 7.813s (commercial and industrial) or 1.953s (automotive) will meet the refresh
requirement and ensure that each row is refreshed. Alternatively, 8192 AUTO REFRESH
commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms
(commercial and industrial) or 16ms (automotive).

SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered-down. When in the self refresh mode, the SDRAM retains data
without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except
CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs
to the SDRAM become a Dont Care with the exception of CKE, which must remain
LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking, caus-
ing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self re-
fresh mode for a minimum period equal to tRAS and may remain in self refresh mode
for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK
must be stable (stable clock is defined as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the
SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because
time is required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued at the
specified intervals, as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Self refresh is not supported on automotive temperature devices.

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 256Mb: x4, x8, x16 SDRAM
Truth Tables

Truth Tables

Table 15: Truth Table Current State Bank n, Command to Bank n

Notes 16 apply to all parameters and conditions
Current State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X COMMAND INHIBIT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle L L H H ACTIVE (select and activate row)
L L L H AUTO REFRESH 7
L L L L LOAD MODE REGISTER 7
L L H L PRECHARGE 8
Row active L H L H READ (select column and start READ burst) 9
L H L L WRITE (select column and start WRITE burst) 9
L L H L PRECHARGE (deactivate row in bank or banks) 10
Read L H L H READ (select column and start new READ burst) 9
(auto precharge disabled) L H L L WRITE (select column and start WRITE burst) 9
L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 10
L H H L BURST TERMINATE 11
Write L H L H READ (select column and start READ burst) 9
(auto precharge disabled) L H L L WRITE (select column and start new WRITE burst) 9
L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) 10
L H H L BURST TERMINATE 11

Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 17 (page 41))
and after tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (for example, the current state is for a
specific bank and the commands shown can be issued to that bank when in that state).
Exceptions are covered below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
COMMAND INHIBIT or NOP commands, or supported commands to the other bank
should be issued on any clock edge occurring during these states. Supported commands
to any other bank are determined by the banks current state and the conditions descri-
bed in this and the following table.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is
met. After tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. After tRCD is met, the bank will be in the row active state.

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 256Mb: x4, x8, x16 SDRAM
Truth Tables

Read with auto precharge enabled: Starts with registration of a READ command
with auto precharge enabled and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
Write with auto precharge enabled: Starts with registration of a WRITE command
with auto precharge enabled and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these
states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
tRFC is met. After tRFC is met, the device will be in the all banks idle state.

Accessing mode register: Starts with registration of a LOAD MODE REGISTER com-
mand and ends when tMRD has been met. After tMRD is met, the device will be in the
all banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends
when tRP is met. After tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank specific; requires that all banks are idle.
8. Does not affect the state of the bank and acts as a NOP to that bank.
9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
10. May or may not be bank specific; if all banks need to be precharged, each must be in a
valid state for precharging.
11. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, re-
gardless of bank.

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 256Mb: x4, x8, x16 SDRAM
Truth Tables

Table 16: Truth Table Current State Bank n, Command to Bank m

Notes 16 apply to all parameters and conditions
Current State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X COMMAND INHIBIT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle X X X X Any command otherwise supported for bank m
Row activating, active, or L L H H ACTIVE (select and activate row)
precharging L H L H READ (select column and start READ burst) 7
L H L L WRITE (select column and start WRITE burst) 7
L L H L PRECHARGE
Read L L H H ACTIVE (select and activate row)
(auto precharge disabled) L H L H READ (select column and start new READ burst) 7, 10
L H L L WRITE (select column and start WRITE burst) 7, 11
L L H L PRECHARGE 9
Write L L H H ACTIVE (select and activate row)
(auto precharge disabled) L H L H READ (select column and start READ burst) 7, 12
L H L L WRITE (select column and start new WRITE burst) 7, 13
L L H L PRECHARGE 9
Read L L H H ACTIVE (select and activate row)
(with auto precharge) L H L H READ (select column and start new READ burst) 7, 8, 14
L H L L WRITE (select column and start WRITE burst) 7, 8, 15
L L H L PRECHARGE 9
Write L L H H ACTIVE (select and activate row)
(with auto precharge) L H L H READ (select column and start READ burst) 7, 8, 16
L H L L WRITE (select column and start new WRITE burst) 7, 8, 17
L L H L PRECHARGE 9

Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (Table 17 (page 41)), and
after tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; for example, the cur-
rent state is for bank n and the commands shown can be issued to bank m, assuming
that bank m is in such a state that the given command is supported. Exceptions are cov-
ered below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.

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 256Mb: x4, x8, x16 SDRAM
Truth Tables

Read with auto precharge enabled: Starts with registration of a READ command
with auto precharge enabled and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
Write with auto precharge enabled: Starts with registration of a WRITE command
with auto precharge enabled and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands can only be is-
sued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command/Action column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disa-
bled.
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m burst.
9. The burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CAS latency (CL) later.
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM
should be used one clock prior to the WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered, with
the data-out appearing CL later. The last valid WRITE to bank n will be data-in regis-
tered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The
last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank
m.
14. For a READ with auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CL later. The PRE-
CHARGE to bank n will begin when the READ to bank m is registered.
15. For a READ with auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM
should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered.
16. For a WRITE with auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered, with
the data-out appearing CL later. The PRECHARGE to bank n will begin after tWR is met,
where tWR begins when the READ to bank m is registered. The last valid WRITE bank n
will be data-in registered one clock prior to the READ to bank m.
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The
PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE
to bank m is registered. The last valid WRITE to bank n will be data registered one clock
to the WRITE to bank m.

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 256Mb: x4, x8, x16 SDRAM
Truth Tables

Table 17: Truth Table CKE

Notes 14 apply to all parameters and conditions
Current State CKEn-1 CKEn Commandn Actionn Notes
Power-down L L X Maintain power-down
Self refresh X Maintain self refresh
Clock suspend X Maintain clock suspend
Power-down L H COMMAND INHIBIT or NOP Exit power-down 5
Self refresh COMMAND INHIBIT or NOP Exit self refresh 6
Clock suspend X Exit clock suspend 7
All banks idle H L COMMAND INHIBIT or NOP Power-down entry
All banks idle AUTO REFRESH Self refresh entry
Reading or writing VALID Clock suspend entry
H H See Table 16 (page 39).

Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previ-
ous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of
COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time
for clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges

occurring during the tXSR period. A minimum of two NOP commands must be provided
during the tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recog-
nize the next command at clock edge n + 1.

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 256Mb: x4, x8, x16 SDRAM
Initialization

Initialization
SDRAM must be powered up and initialized in a predefined manner. Operational proce-
dures other than those specified may result in undefined operation. After power is ap-
plied to V DD and V DDQ (simultaneously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified for the clock pin), the SDRAM re-
quires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or
NOP. Starting at some point during this 100s period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP commands must be applied.
After the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH com-
mands can be issued after the LMR command.
The recommended power-up sequence for SDRAM:
1. Simultaneously apply power to V DD and V DDQ.
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-
compatible.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within tim-
ing constraints specified for the clock pin.
4. Wait at least 100s prior to issuing any command other than a COMMAND INHIB-
IT or NOP.
5. Starting at some point during this 100s period, bring CKE HIGH. Continuing at
least through the end of this period, 1 or more COMMAND INHIBIT or NOP com-
mands must be applied.
6. Perform a PRECHARGE ALL command.
7. Wait at least tRP time; during this time NOPs or DESELECT commands must be
given. All banks will complete their precharge, thereby placing the device in the all
banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT com-
mands are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT com-
mands are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode reg-
ister will power up in an unknown state, it should be loaded with desired bit values
prior to applying any operational command. Using the LMR command, program
the mode register. The mode register is programmed via the MODE REGISTER SET
command with BA1 = 0, BA0 = 0 and retains the stored information until it is pro-
grammed again or the device loses power. Not programming the mode register
upon initialization will result in default settings which may not be desired. Out-
puts are guaranteed High-Z after the LMR command is issued. Outputs should be
High-Z already before the LMR command is issued.
13. Wait at least tMRD time, during which only NOP or DESELECT commands are al-
lowed.
At this point the DRAM is ready for any valid command.

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 256Mb: x4, x8, x16 SDRAM
Initialization

Note:
More than two AUTO REFRESH commands can be issued in the sequence. After steps 9
and 10 are complete, repeat them until the desired number of AUTO REFRESH + tRFC
loops is achieved.

Figure 18: Initialize and Load Mode Register

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3
tCK (( (( tCL ((
)) )) ))
CK (( (( tCH (( ((
)) )) )) ))
tCKS tCKH

(( (( (( ((
)) )) )) ))
CKE
(( ((
)) ))
tCMS tCMH
(( (( (( ((
)) )) AUTO )) AUTO )) LOAD MODE
COMMAND NOP2 PRECHARGE NOP2 NOP2 NOP2 ACTIVE
(( (( REFRESH (( REFRESH (( REGISTER
)) )) )) ))

(( (( (( ((
DQM/DQML, )) )) )) ))
DQMU (( (( (( ((
)) )) )) ))

tAS tAH5
(( (( (( ((
A[9:0], )) )) )) ))
(( (( (( CODE ROW
A[12:11] ((
)) )) )) ))

tAS tAH
(( ALL BANKS (( (( ((
)) )) )) ))
A10 (( (( CODE ROW
(( ((
)) )) )) ))
SINGLE BANK

(( (( (( ((
)) )) )) )) Bank
BA[1:0] ALL
(( BANKS (( (( (( Address
)) )) )) ))

(( High-Z ((
DQ )) ))
T = 100s
tRP tRFC tRFC tMRD
MIN

Power-up:
VDD and Precharge AUTO REFRESH AUTO REFRESH Program Mode Register1,3,4
CLK stable all banks
DONT CARE

UNDEFINED

Notes: 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock HIGH time, all commands applied are NOP.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at tP + 1.

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 256Mb: x4, x8, x16 SDRAM
Mode Register

Mode Register
The mode register defines the specific mode of operation, including burst length (BL),
burst type, CAS latency (CL), operating mode, and write burst mode. The mode register
is programmed via the LOAD MODE REGISTER command and retains the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify
the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and
M10Mn should be set to zero to ensure compatibility with future revisions. Mn + 1 and
Mn + 2 should be set to zero to select the mode register.
The mode registers must be loaded when all banks are idle, and the controller must wait
tMRD before initiating the subsequent operation. Violating either of these requirements

will result in unspecified operation.

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 256Mb: x4, x8, x16 SDRAM
Mode Register

Figure 19: Mode Register Definition

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

12 11 10 9 8 7 6 5 4 3 2 1 0
Mode Register (Mx)
Reserved WB Op Mode CAS Latency BT Burst Length

Program Burst Length

BA1, BA0 = 0, 0
to ensure compatibility M2 M1 M0 M3 = 0 M3 = 1
with future devices.
0 0 0 1 1

0 0 1 2 2
M9 Write Burst Mode
0 1 0 4 4
0 Programmed Burst Length
0 1 1 8 8
1 Single Location Access
1 0 0 Reserved Reserved

M8 M7 M6-M0 Operating Mode 1 0 1 Reserved Reserved

0 0 Defined Standard Operation 1 1 0 Reserved Reserved

All other states reserved 1 1 1 Full Page Reserved

M3 Burst Type

0 Sequential

1 Interleaved

M6 M5 M4 CAS Latency

0 0 0 Reserved

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

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 256Mb: x4, x8, x16 SDRAM
Mode Register

Burst Length
Read and write accesses to the device are burst oriented, and the burst length (BL) is
programmable. The burst length determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2,
4, 8, or continuous locations are available for both the sequential and the interleaved
burst types, and a continuous page burst is available for the sequential type. The con-
tinuous page burst is used in conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with fu-
ture versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst wraps within the block when a boundary is reached. The block
is uniquely selected by A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8.
The remaining (least significant) address bit(s) is (are) used to select the starting loca-
tion within the block. Continuous page bursts wrap within the page when the boundary
is reached.

Burst Type
Accesses within a given burst can be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst
type, and the starting column address.

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 256Mb: x4, x8, x16 SDRAM
Mode Register

Table 18: Burst Definition Table

Order of Accesses Within a Burst

Burst Length Starting Column Address Type = Sequential Type = Interleaved
2 A0
0 0-1 0-1
1 1-0 1-0
4 A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8 A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Continuous
n = A0An/9/8 (location 0y) Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1, Not supported
Cn...

Notes: 1. For full-page accesses: y = 2048 (x4); y = 1024 (x8); y = 512 (x16).
2. For BL = 2, A1A9, A11 (x4); A1A9 (x8); or A1A8 (x16) select the block-of-two burst; A0
selects the starting column within the block.
3. For BL = 4, A2A9, A11 (x4); A2A9 (x8); or A2A8 (x16) select the block-of-four burst;
A0A1 select the starting column within the block.
4. For BL = 8, A3A9, A11 (x4); A3A9 (x8); or A3A8 (x16) select the block-of-eight burst;
A0A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0A9, A11 (x4); A0A9 (x8); or A0A8
(x16) select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the fol-
lowing access wraps within the block.
7. For BL = 1, A0A9, A11 (x4); A0A9 (x8); or A0A8 (x16) select the unique column to be
accessed, and mode register bit M3 is ignored.

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 256Mb: x4, x8, x16 SDRAM
Mode Register

CAS Latency
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the
data is valid by clock edge n + m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ command is registered at T0 and
the latency is programmed to two clocks, the DQ start driving after T1 and the data is
valid by T2.
Reserved states should not be used as unknown operation or incompatibility with fu-
ture versions may result.

Figure 20: CAS Latency

T0 T1 T2 T3
CLK

Command READ NOP NOP

tLZ tOH

DQ DOUT
tAC

CL = 2

T0 T1 T2 T3 T4
CLK

Command READ NOP NOP NOP

tLZ tOH

DQ DOUT
tAC
CL = 3

Dont Care Undefined

Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use. Reserved states should not
be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M[2:0] applies to both READ and
WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.

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 256Mb: x4, x8, x16 SDRAM
Bank/Row Activation

Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a
row in that bank must be opened. This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated.
After a row is opened with the ACTIVE command, a READ or WRITE command can be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is reflected in Figure 21 (page 49), which covers
any case where 2 < tRCD (MIN)/tCK 3. (The same procedure is used to convert other
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been precharged. The minimum time interval between
successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVE commands to different banks is defined
by tRRD.

Figure 21: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3

T0 T1 T2 T3

CLK
tCK tCK tCK

Command ACTIVE NOP NOP READ or

WRITE
tRCD(MIN)

Dont Care

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 256Mb: x4, x8, x16 SDRAM
READ Operation

READ Operation
READ bursts are initiated with a READ command, as shown in Figure 15 (page 33). The
starting column and bank addresses are provided with the READ command, and auto
precharge is either enabled or disabled for that burst access. If auto precharge is ena-
bled, the row being accessed is precharged at the completion of the burst. In the follow-
ing figures, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address is
available following the CAS latency after the READ command. Each subsequent data-
out element will be valid by the next positive clock edge. Figure 23 (page 52) shows
general timing for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
signals will go to High-Z. A continuous page burst continues until terminated. At the
end of the page, it wraps to column 0 and continues.
Data from any READ burst can be truncated with a subsequent READ command, and
data from a fixed-length READ burst can be followed immediately by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst either follows the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ com-
mand should be issued x cycles before the clock edge at which the last desired data ele-
ment is valid, where x = CL - 1. This is shown in Figure 23 (page 52) for CL2 and CL3.
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule as-
sociated with a prefetch architecture. A READ command can be initiated on any clock
cycle following a READ command. Full-speed random read accesses can be performed
to the same bank, or each subsequent READ can be performed to a different bank.

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 256Mb: x4, x8, x16 SDRAM
READ Operation

Figure 22: Consecutive READ Bursts

T0 T1 T2 T3 T4 T5 T6

CLK

Command READ NOP NOP NOP READ NOP NOP

X = 1 cycle

Bank, Bank,
Address Col n Col b

DOUT DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3 b

CL = 2

T0 T1 T2 T3 T4 T5 T6 T7

CLK

Command READ NOP NOP NOP READ NOP NOP NOP

X = 2 cycles

Bank, Bank,
Address Col n Col b

DQ DOUT DOUT DOUT DOUT DOUT

CL = 3
Transitioning data Dont Care

Note: 1. Each READ command can be issued to any bank. DQM is LOW.

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 256Mb: x4, x8, x16 SDRAM
READ Operation

Figure 23: Random READ Accesses

T0 T1 T2 T3 T4 T5

CLK

Command READ READ READ READ NOP NOP

Bank, Bank, Bank, Bank,

Address Col n Col a Col x Col m

DQ DOUT DOUT DOUT DOUT

CL = 2

T0 T1 T2 T3 T4 T5 T6

CLK

Command READ READ READ READ NOP NOP NOP

Bank, Bank, Bank, Bank,

Address Col n Col a Col x Col m

DQ DOUT DOUT DOUT DOUT

CL = 3
Transitioning data Dont Care

Note: 1. Each READ command can be issued to any bank. DQM is LOW.

Data from any READ burst can be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst can be followed immediately by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst can be ini-
tiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there is a possibility that the device driving the input data will go Low-Z before
the DQ go High-Z. In this case, at least a single-cycle delay should occur between the
last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 24 (page 53) and
Figure 25 (page 54). The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress da-
ta-out from the READ. After the WRITE command is registered, the DQ will go to High-Z
(or remain High-Z), regardless of the state of the DQM signal, provided the DQM was
active on the clock just prior to the WRITE command that truncated the READ com-
mand. If not, the second WRITE will be an invalid WRITE. For example, if DQM was
LOW during T4, then the WRITEs at T5 and T7 would be valid, and the WRITE at T6
would be invalid.

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 256Mb: x4, x8, x16 SDRAM
READ Operation

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 24
(page 53) shows where, due to the clock cycle frequency, bus contention is avoided
without having to add a NOP cycle, while Figure 25 (page 54) shows the case where an
additional NOP cycle is required.
A fixed-length READ burst may be followed by or truncated with a PRECHARGE com-
mand to the same bank, provided that auto precharge was not activated. The PRE-
CHARGE command should be issued x cycles before the clock edge at which the last de-
sired data element is valid, where x = CL - 1. This is shown in Figure 26 (page 54) for
each possible CL; data element n + 3 is either the last of a burst of four or the last de-
sired data element of a longer burst. Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued until tRP is met. Note that part of
the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-
mand issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvant-
age of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or continuous
page bursts.

Figure 24: READ-to-WRITE

T0 T1 T2 T3 T4

CLK

DQM

Command READ NOP NOP NOP WRITE

Bank, Bank,
Address Col n Col b
tCK
tHZ

DQ DOUT DIN

t
DS

Transitioning data Dont Care

Note: 1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
to any bank. If a burst of one is used, DQM is not required.

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 256Mb: x4, x8, x16 SDRAM
READ Operation

Figure 25: READ-to-WRITE With Extra Clock Cycle

T0 T1 T2 T3 T4 T5

CLK

DQM

Command READ NOP NOP NOP NOP WRITE

Bank, Bank,
Address Col n Col b
tHZ

DQ DOUT DIN

tDS

Transitioning data Dont Care

Note: 1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
to any bank.

Figure 26: READ-to-PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7

CLK

tRP

Command READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE

X = 1 cycle

Bank a, Bank Bank a,

Address Col n (a or all) Row

DQ DOUT DOUT DOUT DOUT

CL = 2
T0 T1 T2 T3 T4 T5 T6 T7

CLK

t RP

Command READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE

X = 2 cycles

Bank a, Bank Bank a,

Address Col (a or all) Row

DQ DOUT DOUT DOUT DOUT

CL = 3
Transitioning data Dont Care

Note: 1. DQM is LOW.

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 256Mb: x4, x8, x16 SDRAM
READ Operation

Continuous-page READ bursts can be truncated with a BURST TERMINATE command

and fixed-length READ bursts can be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 27 (page 55) for each possible CAS la-
tency; data element n + 3 is the last desired data element of a longer burst.

Figure 27: Terminating a READ Burst

T0 T1 T2 T3 T4 T5 T6

CLK

BURST
Command READ NOP NOP NOP
TERMINATE
NOP NOP

X = 1 cycle

Bank,
Address Col n

DQ DOUT DOUT DOUT DOUT

CL = 2
T0 T1 T2 T3 T4 T5 T6 T7

CLK

BURST
Command READ NOP NOP NOP
TERMINATE
NOP NOP NOP

X = 2 cycles

Bank,
Address Col n

DQ DOUT DOUT DOUT DOUT

CL = 3
Transitioning data Dont Care

Note: 1. DQM is LOW.

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 256Mb: x4, x8, x16 SDRAM
READ Operation

Figure 28: Alternating Bank Read Accesses

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

Command ACTIVE NOP READ NOP ACTIVE NOP READ NOP ACTIVE

tCMS tCMH

DQM

tAS tAH
1
Address Row Column m Row Column b Row

tAS tAH Enable auto precharge Enable auto precharge

A10 Row Row Row

tAS tAH

BA0, BA1 Bank 0 Bank 0 Bank 3 Bank 3 Bank 0

tAC tAC tAC tAC tAC

tAC tOH tOH tOH tOH tOH

DQ DOUT DOUT DOUT DOUT DOUT

tLZ

tRCD - bank 0 CL - bank 0 tRP - bank 0 tRCD - bank 0

tRAS - bank 0
tRC - bank 0
tRRD tRCD - bank 3 CL - bank 3

Dont Care Undefined

Note: 1. For this example, BL = 4 and CL = 2.

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 256Mb: x4, x8, x16 SDRAM
READ Operation

Figure 29: READ Continuous Page Burst

T0 T1 T2 T3 T4 T5 T6 ((
Tn + 1 Tn + 2 Tn + 3 Tn + 4
tCL tCK ))
CLK ((
tCH
))

tCKS tCKH
((
CKE ))
((
))
tCMS tCMH
((
))
Command ACTIVE NOP READ NOP NOP NOP NOP (( NOP BURST TERM NOP NOP
))

tCMS tCMH
((
))
DQM ((
))

tAS tAH
((
Address ))
Row Column m
((
))

tAS tAH
((
))
A10 Row ((
))

tAS tAH
((
))
BA0, BA1 Bank Bank
((
))
tAC tAC tAC tAC (( tAC tAC
))
tOH tOH tOH tOH tOH tOH
((
DQ DOUT DOUT DOUT ) ) DOUT DOUT DOUT
((
tLZ ))
tHZ

tRCD CAS latency All locations within same row

Full page completed Dont Care

Full-page burst does not self-terminate. Undefined

Can use BURST TERMINATE command.

Note: 1. For this example, CL = 2.

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 256Mb: x4, x8, x16 SDRAM
READ Operation

Figure 30: READ DQM Operation

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCMS tCMH

Command ACTIVE NOP READ NOP NOP NOP NOP NOP NOP

tCMS tCMH

DQM
tAS tAH

Address Row Column m

tAS tAH
Enable auto precharge

A10 Row

tAS tAH Disable auto precharge

BA0, BA1 Bank Bank

tAC
tAC tOH tAC tOH tOH
DQ
DOUT DOUT DOUT
tLZ tLZ

tRCD tHZ tHZ

CL = 2
Dont Care

Undefined

Note: 1. For this example, BL = 4 and CL = 2.

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 256Mb: x4, x8, x16 SDRAM
WRITE Operation

WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 16 (page 34).
The starting column and bank addresses are provided with the WRITE command and
auto precharge is either enabled or disabled for that access. If auto precharge is ena-
bled, the row being accessed is precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following figures, auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered coincident with the
WRITE command. Subsequent data elements are registered on each successive positive
clock edge. Upon completion of a fixed-length burst, assuming no other commands
have been initiated, the DQ will remain at High-Z and any additional input data will be
ignored (see Figure 31 (page 59)). A continuous page burst continues until terminated;
at the end of the page, it wraps to column 0 and continues.
Data for any WRITE burst can be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst can be followed immediately by data for a WRITE
command. The new WRITE command can be issued on any clock following the previ-
ous WRITE command, and the data provided coincident with the new command ap-
plies to the new command (see Figure 32 (page 60)). Data n + 1 is either the last of a
burst of two or the last desired data element of a longer burst.
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule as-
sociated with a prefetch architecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed random write accesses within a
page can be performed to the same bank, as shown in Figure 33 (page 61), or each
subsequent WRITE can be performed to a different bank.

Figure 31: WRITE Burst

T0 T1 T2 T3

CLK

Command WRITE NOP NOP NOP

Bank,
Address Col n

DQ DIN DIN

Transitioning data Dont Care

Note: 1. BL = 2. DQM is LOW.

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 256Mb: x4, x8, x16 SDRAM
WRITE Operation

Figure 32: WRITE-to-WRITE

T0 T1 T2

CLK

Command WRITE NOP WRITE

Bank, Bank,
Address Col n Col b

DIN DIN DIN

DQ

Transitioning data Dont Care

Note: 1. DQM is LOW. Each WRITE command may be issued to any bank.

Data for any WRITE burst can be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst can be followed immediately by a READ command.
After the READ command is registered, data input is ignored and WRITEs will not be
executed (see Figure 34 (page 61)). Data n + 1 is either the last of a burst of two or the
last desired data element of a longer burst.
Data for a fixed-length WRITE burst can be followed by or truncated with a PRE-
CHARGE command to the same bank, provided that auto precharge was not activated.
A continuous-page WRITE burst can be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be issued tWR after the clock edge at
which the last desired input data element is registered. The auto precharge mode re-
quires a tWR of at least one clock with time to complete, regardless of frequency.
In addition, when truncating a WRITE burst at high clock frequencies ( tCK < 15ns), the
DQM signal must be used to mask input data for the clock edge prior to and the clock
edge coincident with the PRECHARGE command (see Figure 35 (page 62)). Data n + 1
is either the last of a burst of two or the last desired data element of a longer burst. Fol-
lowing the PRECHARGE command, a subsequent command to the same bank cannot
be issued until tRP is met.
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-
mand issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvant-
age of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts or continu-
ous page bursts.

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 256Mb: x4, x8, x16 SDRAM
WRITE Operation

Figure 33: Random WRITE Cycles

T0 T1 T2 T3

CLK

Command WRITE WRITE WRITE WRITE

Bank, Bank, Bank, Bank,

Address Col n Col a Col x Col m

DQ DIN DIN DIN DIN

Transitioning data Dont Care

Note: 1. Each WRITE command can be issued to any bank. DQM is LOW.

Figure 34: WRITE-to-READ

T0 T1 T2 T3 T4 T5

CLK

Command WRITE NOP READ NOP NOP NOP

Bank, Bank,
Address Col n Col b

DQ DIN DIN DOUT DOUT

Transitioning data Dont Care

Note: 1. The WRITE command can be issued to any bank, and the READ command can be to any
bank. DQM is LOW. CL = 2 for illustration.

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 256Mb: x4, x8, x16 SDRAM
WRITE Operation

Figure 35: WRITE-to-PRECHARGE

T0 T1 T2 T3 T4 T5 T6

CLK

tWR @ tCK 15ns

DQM

tRP

Command WRITE NOP PRECHARGE NOP NOP ACTIVE NOP

Bank a, Bank Bank a,

Address Col n (a or all) Row

tWR

DIN DIN
DQ

tWR @ tCK < 15ns

DQM

tRP

Command WRITE NOP NOP PRECHARGE NOP NOP ACTIVE

Bank a, Bank Bank a,

Address Col n (a or all) Row

t WR

DQ DIN DIN

Transitioning data Dont Care

Note: 1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two.

Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command is ignored. The last data written (provided that DQM is LOW at
that time) will be the input data applied one clock previous to the BURST TERMINATE
command. This is shown in Figure 36 (page 63), where data n is the last desired data
element of a longer burst.

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 256Mb: x4, x8, x16 SDRAM
WRITE Operation

Figure 36: Terminating a WRITE Burst

T0 T1 T2

CLK

BURST NEXT
Command WRITE
TERMINATE COMMAND

Bank, Address
Address Col n

DIN Data
DQ

Transitioning data Dont Care

Note: 1. DQM is LOW.

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 256Mb: x4, x8, x16 SDRAM
WRITE Operation

Figure 37: Alternating Bank Write Accesses

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

Command ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE

tCMS tCMH

DQM

tAS tAH

Address Row Column m Row Column b Row

tAS tAH Enable auto precharge Enable auto precharge

A10 Row Row Row

tAS tAH

BA0, BA1 Bank 0 Bank 0 Bank 1 Bank 1 Bank 0

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN DIN DIN DIN DIN DIN DIN DIN

tRCD - bank 0 tWR - bank 0 tRP - bank 0 tRCD - bank 0

tRAS - bank 0
tRC - bank 0 tWR - bank 1
tRRD tRCD - bank 1

Dont Care

Note: 1. For this example, BL = 4.

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 256Mb: x4, x8, x16 SDRAM
WRITE Operation

Figure 38: WRITE Continuous Page Burst

T0 T1 T2 T3 T4 T5 ((
Tn + 1 Tn + 2 Tn + 3
tCL tCK ))
CLK
tCH ((
))

tCKS tCKH
((
))
CKE
((
))
tCMS tCMH
((
))
Command ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP
((
))

tCMS tCMH
((
))
DQM
((
))

tAS tAH
((
))
Address Row Column m ((
))

tAS tAH
((
))
A10 Row ((
))

tAS tAH
((
))
BA0, BA1 Bank Bank ((
))

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
((
))
DQ DIN DIN DIN DIN (( DIN
))
tRCD
Full-page burst
All locations within same row does not self-terminate.
Use BURST TERMINATE
command to stop.1, 2

Full page completed

Dont Care

Notes: 1. tWR must be satisfied prior to issuing a PRECHARGE command.

2. Page left open; no tRP.

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 256Mb: x4, x8, x16 SDRAM
WRITE Operation

Figure 39: WRITE DQM Operation

T0 T1 T2 T3 T4 T5 T6 T7
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

Command ACTIVE NOP WRITE NOP NOP NOP NOP NOP

tCMS tCMH

DQM

tAS tAH

Address Row Column m

tAS tAH
Enable auto precharge
A10 Row

tAS tAH Disable auto precharge

BA0, BA1 Bank Bank

tDS tDH tDS tDH tDS tDH

DQ DIN DIN DIN

tRCD Dont Care

Note: 1. For this example, BL = 4.

Burst Read/Single Write

The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of the programmed burst length.
READ commands access columns according to the programmed burst length and se-
quence, just as in the normal mode of operation (M9 = 0).

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

PRECHARGE Operation
The PRECHARGE command (see Figure 17 (page 35)) is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s) will be available for a sub-
sequent row access some specified time (tRP) after the PRECHARGE command is is-
sued. Input A10 determines whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged (A10 = LOW), inputs BA0 and BA1 select
the bank. When all banks are to be precharged (A10 = HIGH), inputs BA0 and BA1 are
treated as Dont Care. After a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands being issued to that bank.

Auto Precharge
Auto precharge is a feature that performs the same individual-bank PRECHARGE func-
tion described previously, without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst,
except in the continuous page burst mode where auto precharge does not apply. In the
specific case of write burst mode set to single location access with burst length set to
continuous, the burst length setting is the overriding setting and auto precharge does
not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for
each individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. Another command cannot be issued to the same bank until the precharge time
(tRP) is completed. This is determined as if an explicit PRECHARGE command was is-
sued at the earliest possible time, as described for each burst type in the Burst Type
(page 46) section.
Micron SDRAM supports concurrent auto precharge; cases of concurrent auto pre-
charge for READs and WRITEs are defined below.
READ with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a READ on bank n following the programmed CAS la-
tency. The precharge to bank n begins when the READ to bank m is registered (see Fig-
ure 40 (page 68)).
READ with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The pre-
charge to bank n begins when the WRITE to bank m is registered (see Figure 41
(page 69)).
WRITE with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out
appearing CL later. The precharge to bank n will begin after tWR is met, where tWR be-
gins when the READ to bank m is registered. The last valid WRITE to bank n will be da-
ta-in registered one clock prior to the READ to bank m (see Figure 46 (page 74)).
WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to
bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is reg-

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

istered. The last valid data WRITE to bank n will be data registered one clock prior to a
WRITE to bank m (see Figure 47 (page 74)).

Figure 40: READ With Auto Precharge Interrupted by a READ

T0 T1 T2 T3 T4 T5 T6 T7

CLK

READ - AP READ - AP
Command NOP
Bank n
NOP
Bank m
NOP NOP NOP NOP

Bank n Page active READ with burst of 4 Interrupt burst, precharge Idle

Internal tRP - bank n tRP - bank m

states Page active READ with burst of 4 Precharge

Bank m

Bank n, Bank m,
Address Col a Col d

DOUT DOUT DOUT DOUT

DQ
CL = 3 (bank n)

CL = 3 (bank m)
Dont Care

Note: 1. DQM is LOW.

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

Figure 41: READ With Auto Precharge Interrupted by a WRITE

T0 T1 T2 T3 T4 T5 T6 T7

CLK

READ - AP WRITE - AP
Command Bank n
NOP NOP NOP
Bank m
NOP NOP NOP

Page
Bank n active
READ with burst of 4 Interrupt burst, precharge Idle
Internal tRP - bank n tWR - bankm

States
Bank m Page active WRITE with burst of 4 Write-back

Bank n, Bank m,
Address Col a Col d

DQM1

DOUT DIN DIN DIN DIN

DQ

CL = 3 (bank n) Transitioning data Dont Care

Note: 1. DQM is HIGH at T2 to prevent DOUTa + 1 from contending with DINd at T4.

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

Figure 42: READ With Auto Precharge

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCMS tCMH

Command ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE

tCMS tCMH

DQM
tAS tAH

Address Row Column m Row

tAS tAH Enable auto precharge

A10 Row Row

tAS tAH

BA0, BA1 Bank Bank Bank

tAC tAC tAC

tAC tOH tOH tOH tOH

DQ DOUT m DOUT DOUT DOUT

tLZ m+1 m+2 m+3

tRCD tRP tHZ

CL = 2
tRAS
tRC

Dont Care Undefined

Note: 1. For this example, BL = 4 and CL = 2.

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

Figure 43: READ Without Auto Precharge

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCMS tCMH

Command ACTIVE NOP READ NOP NOP NOP PRECHARGE NOP ACTIVE

tCMS tCMH

DQM
tAS tAH

Address Row Column m Row

tAS tAH
All banks
A10 Row Row

Disable auto precharge Single bank

tAS tAH

BA0, BA1 Bank Bank Bank(s) Bank

tAC tAC tAC

tAC tOH tOH tOH tOH

DQ DOUT DOUT DOUT DOUT

tLZ
tRCD tRP tHZ
CL = 2
tRAS
tRC

Dont Care Undefined

Note: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRE-
CHARGE.

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

Figure 44: Single READ With Auto Precharge

T0 T1 T2 T3 T4 T5 T6 T7
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCMS tCMH

Command ACTIVE NOP READ NOP NOP NOP NOP ACTIVE

tCMS tCMH

DQM
tAS tAH

Address Row Column m Row

tAS tAH Enable auto precharge

A10 Row Row

tAS tAH

BA0, BA1 Bank Bank Bank

tAC tOH

DQ DOUT
tLZ
tRCD CL = 2 tRP
tRAS
tRC

Dont Care Undefined

Note: 1. For this example, BL = 1 and CL = 2.

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

Figure 45: Single READ Without Auto Precharge

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCMS tCMH

Command ACTIVE NOP READ NOP NOP PRECHARGE NOP ACTIVE NOP

tCMS tCMH

DQM
tAS tAH

Address Row Column m Row

tAS tAH
All banks
A10 Row Row

Disable auto precharge Single bank

tAS tAH

BA0, BA1 Bank Bank Bank(s) Bank

tAC tOH

DQ DOUT
tLZ

tRCD tHZ tRP

CL = 2
tRAS Dont Care
tRC Undefined

Note: 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRE-
CHARGE.

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

Figure 46: WRITE With Auto Precharge Interrupted by a READ

T0 T1 T2 T3 T4 T5 T6 T7

CLK

WRITE - AP READ - AP
Command NOP
Bank n
NOP
Bank m
NOP NOP NOP NOP

Bank n Page active WRITE with burst of 4 Interrupt burst, write-back Precharge

Internal t WR - bank n
tRP - bank n
tRP - bank m
States
Bank m Page active READ with burst of 4

Bank n, Bank m,
Address Col a Col d

DIN DIN DOUT DOUT

DQ

CL = 3 (bank m)

Dont Care

Note: 1. DQM is LOW.

Figure 47: WRITE With Auto Precharge Interrupted by a WRITE

T0 T1 T2 T3 T4 T5 T6 T7

CLK

WRITE - AP WRITE - AP
Command NOP
Bank n
NOP NOP
Bank m
NOP NOP NOP

Bank n Page active WRITE with burst of 4 Interrupt burst, write-back Precharge
tRP - bank n
Internal tWR - bank n
tWR - bank m
States Page active WRITE with burst of 4 Write-back
Bank m

Bank n, Bank m,
Address Col a Col d

DIN DIN DIN DIN DIN DIN DIN

DQ

Dont Care

Note: 1. DQM is LOW.

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

Figure 48: WRITE With Auto Precharge

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

Command ACTIVE NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE

tCMS tCMH

DQM

tAS tAH

Address Row Column m Row

tAS tAH
Enable auto precharge

A10 Row Row

tAS tAH

BA0, BA1 Bank Bank Bank

tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN DIN DIN DIN

tRCD tWR tRP
tRAS
tRC

Dont Care

Note: 1. For this example, BL = 4.

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

Figure 49: WRITE Without Auto Precharge

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

Command ACTIVE NOP WRITE NOP NOP NOP NOP PRECHARGE NOP ACTIVE

tCMS tCMH

DQM

tAS tAH

Address Row Column m Row

tAS tAH
All banks

A10 Row Row

Disable auto precharge Single bank
tAS tAH

BA0, BA1 Bank Bank Bank Bank

tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN DIN DIN DIN

tRCD tWR tRP
tRAS
tRC

Dont Care

Note: 1. For this example, BL = 4 and the WRITE burst is followed by a manual PRECHARGE.

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

Figure 50: Single WRITE With Auto Precharge

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

Command ACTIVE NOP WRITE NOP NOP NOP NOP ACTIVE NOP

tCMS tCMH

DQM

tAS tAH

Address Row Column m Row

tAS tAH
Enable auto precharge

A10 Row Row

tAS tAH

BA0, BA1 Bank Bank Bank

tDS tDH

DQ DIN
tRCD tWR tRP
tRAS
tRC
Dont Care

Note: 1. For this example, BL = 1.

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 256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation

Figure 51: Single WRITE Without Auto Precharge

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCMS tCMH

Command ACTIVE NOP WRITE NOP NOP PRECHARGE NOP ACTIVE NOP

tCMS tCMH

DQM
tAS tAH

Address Row Column m

tAS tAH
All banks
A10 Row Row

tAS tAH Disable auto precharge Single bank

BA0, BA1 Bank Bank Bank Bank

tDS tDH

DQ DIN

tRCD tWR tRP

tRAS
tRC
Dont Care

Note: 1. For this example, BL = 1 and the WRITE burst is followed by a manual PRECHARGE.

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 256Mb: x4, x8, x16 SDRAM
AUTO REFRESH Operation

AUTO REFRESH Operation

The AUTO REFRESH command is used during normal operation of the device to refresh
the contents of the array. This command is nonpersistent, so it must be issued each
time a refresh is required. All active banks must be precharged prior to issuing an AUTO
REFRESH command. The AUTO REFRESH command should not be issued until the
minimum tRP is met following the PRECHARGE command. Addressing is generated by
the internal refresh controller. This makes the address bits Dont Care during an AU-
TO REFRESH command.
After the AUTO REFRESH command is initiated, it must not be interrupted by any exe-
cutable command until tRFC has been met. During tRFC time, COMMAND INHIBIT or
NOP commands must be issued on each positive edge of the clock. The SDRAM re-
quires that every row be refreshed each tREF period. Providing a distributed AUTO RE-
FRESH commandcalculated by dividing the refresh period (tREF) by the number of
rows to be refreshedmeets the timing requirement and ensures that each row is re-
freshed. Alternatively, to satisfy the refresh requirement a burst refresh can be employed
after every tREF period by issuing consecutive AUTO REFRESH commands for the num-
ber of rows to be refreshed at the minimum cycle rate (tRFC).

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 256Mb: x4, x8, x16 SDRAM
AUTO REFRESH Operation

Figure 52: Auto Refresh Mode

T0 T1 T2 Tn + 1 To + 1
(( tCL ((
CLK )) ))
tCK tCH (( ((
)) ))
(( ((
)) ))
CKE
tCKS tCKH

tCMS tCMH
(( ((
AUTO )) AUTO ))
Command PRECHARGE NOP NOP
REFRESH ( ( NOP REFRESH
NOP
( ( NOP ACTIVE
)) ))

(( ((
)) ))
DQM (( ((
)) ))

(( ((
)) ))
Address (( (( Row
)) ))

All banks (( ((
)) ))
A10 Row
(( ((
)) ))
Single bank

tAS tAH
(( ((
)) ))
BA0, BA1 Bank(s) (( (( Bank
)) ))

DQ High-Z (( ((
)) ))
tRP tRFC tRFC

Precharge all Dont Care

active banks

Note: 1. Back-to-back AUTO REFRESH commands are not required.

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 256Mb: x4, x8, x16 SDRAM
SELF REFRESH Operation

SELF REFRESH Operation

The self refresh mode can be used to retain data in the device, even when the rest of the
system is powered down. When in self refresh mode, the device retains data without ex-
ternal clocking. The SELF REFRESH command is initiated like an AUTO REFRESH com-
mand, except CKE is disabled (LOW). After the SELF REFRESH command is registered,
all the inputs to the device become Dont Care with the exception of CKE, which must
remain LOW.
After self refresh mode is engaged, the device provides its own internal clocking, ena-
bling it to perform its own AUTO REFRESH cycles. The device must remain in self re-
fresh mode for a minimum period equal to tRAS and remains in self refresh mode for an
indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK
must be stable prior to CKE going back HIGH. (Stable clock is defined as a signal cycling
within timing constraints specified for the clock ball.) After CKE is HIGH, the device
must have NOP commands issued for a minimum of two clocks for tXSR because time is
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued accord-
ing to the distributed refresh rate (tREF/refresh row count) as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.

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 256Mb: x4, x8, x16 SDRAM
SELF REFRESH Operation

Figure 53: Self Refresh Mode

T0 T1 T2 ((
Tn + 1 ((
To + 1 To + 2
tCL )) ))
CLK
tCK tCH (( ((
tCKS )) ))

((
))
CKE (( ((
)) ))
tCKS tCKH

tCMS tCMH
(( ((
AUTO )) )) AUTO
Command PRECHARGE NOP NOP ( (
REFRESH (( REFRESH
)) ))

(( ((
)) ))
DQM
(( ((
)) ))

(( ((
)) ))
Address (( ((
)) ))
All banks (( ((
)) ))
A10 (( ((
)) ))
Single bank

tAS tAH
(( ((
)) ))
BA0, BA1 Bank(s) (( ((
)) ))

High-Z (( ((
DQ )) ))
tRP tXSR
Precharge all Enter self refresh mode Exit self refresh mode
active banks (Restart refresh time base)

CLK stable prior to exiting

self refresh mode
Dont Care

Note: 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are
not required.

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 256Mb: x4, x8, x16 SDRAM
Power-Down

Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-
HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CKE, for maximum power
savings while in standby. The device cannot remain in the power-down state longer
than the refresh period (64ms) because no REFRESH operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE
HIGH at the desired clock edge (meeting tCKS).

Figure 54: Power-Down Mode

T0 T1 T2 ((
Tn + 1 Tn + 2
tCK tCL ))
CLK
tCH ((
))
tCKS tCKS

CKE ((
))
tCKS tCKH

tCMS tCMH
((
))
Command PRECHARGE NOP NOP NOP ACTIVE
((
))

((
))
DQM ((
))

((
))
Address Row
((
))

All banks ((
))
A10 Row
((
))
Single bank

tAS tAH
((
))
BA0, BA1 Bank(s) Bank
((
))

High-Z ((
DQ ))

Two clock cycles Input buffers gated off All banks idle
while in power-down mode
Precharge all All banks idle, enter
active banks power-down mode Exit power-down mode
Dont Care

Note: 1. Violating refresh requirements during power-down may result in a loss of data.

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 256Mb: x4, x8, x16 SDRAM
Clock Suspend

Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls when an in-
ternal clock edge is suspended will be ignored; any data present on the DQ balls re-
mains driven; and burst counters are not incremented, as long as the clock is suspen-
ded.
Exit clock suspend mode by registering CKE HIGH; the internal clock and related opera-
tion will resume on the subsequent positive clock edge.

Figure 55: Clock Suspend During WRITE Burst

T0 T1 T2 T3 T4 T5

CLK

CKE

Internal
clock

Command NOP WRITE NOP NOP

Bank,
Address Col n

DIN DIN DIN DIN

Dont Care

Note: 1. For this example, BL = 4 or greater, and DQM is LOW.

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 256Mb: x4, x8, x16 SDRAM
Clock Suspend

Figure 56: Clock Suspend During READ Burst

T0 T1 T2 T3 T4 T5 T6

CLK

CKE

Internal
clock

Command READ NOP NOP NOP NOP NOP

Bank,
Address Col n

DOUT DOUT DOUT DOUT

DQ

Dont Care

Note: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.

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 256Mb: x4, x8, x16 SDRAM
Clock Suspend

Figure 57: Clock Suspend Mode

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCKS tCKH

tCMS tCMH

Command READ NOP NOP NOP NOP NOP WRITE NOP

tCMS tCMH
DQM
tAS tAH

Address Column m Column e

tAS tAH

A10
tAS tAH

BA0, BA1 Bank Bank

tAC
tAC tOH tHZ tDS tDH

DQ DOUT DOUT DIN DIN

tLZ

Dont Care Undefined

Note: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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