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64mb x32 Sdram

PC100-compliant Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access / precharge Programmable burst lengths: 1, 2, 4, 8, or full page auto precharge, includes concurrent auto precharge and auto refresh modes Self refresh mode (not available on AT devices) Single 3.3V +-0.3V power supply Supports CAS latency (CL) of 1, 2, and 3 products and specifications discussed herein are subject to change

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48 views80 pages

64mb x32 Sdram

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64Mb: x32 SDRAM Features

SDR SDRAM
MT48LC2M32B2 512K x 32 x 4 Banks Features
PC100-compliant Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto precharge, includes concurrent auto precharge and auto refresh modes Self refresh mode (not available on AT devices) Auto refresh 64ms, 4096-cycle refresh (commercial and industrial) 16ms, 4096-cycle refresh (automotive) LVTTL-compatible inputs and outputs Single 3.3V 0.3V power supply Supports CAS latency (CL) of 1, 2, and 3

Options
Configuration 2 Meg x 32 (512K x 32 x 4 banks) Plastic package OCPL1 86-pin TSOP II (400 mil) standard 86-pin TSOP II (400 mil) Pb-free 90-ball VFBGA (8mm x 13mm) Pbfree Timing cycle time 5ns (200 MHz) 5.5ns (183 MHz) 6ns (167 MHz) 6ns (167 MHz) 7ns (143 MHz) Operating temperature range Commercial (0C to +70C) Industrial (40C to +85C) Automotive (40C to +105C) Revision
Notes: 1. 2. 3. 4. Off-center parting line. Available only on revision G. Available only on revision J. Contact Micron for availability.

Marking
2M32B2 TG P B5 -5 -552 -6A3 -62 -72 None IT AT4 :G/:J

Table 1: Key Timing Parameters

CL = CAS (READ) latency Speed Grade -5 -55 -6A -6 -7 Clock Frequency (MHz) 200 183 167 167 143 Target tRCD-tRP-CL 3-3-3 3-3-3 3-3-3 3-3-3 3-3-3
tRCD

(ns)

tRP

(ns)

CL (ns) 15 16.5 18 18 21

15 16.5 18 18 20

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

Products and specifications discussed herein are subject to change by Micron without notice.

64Mb: x32 SDRAM Features

Table 2: Address Table
Parameter Configuration Refresh count Row addressing Bank addressing Column addressing 2 Meg x 32 512K x 32 x 4 banks 4K 2K A[10:0] 4 BA[1:0] 256 A[7:0]

Table 3: 64Mb (x32) SDR Part Numbering

Part Numbers MT48LC2M32B2TG MT48LCM32B2P MT48LC2M3B2B51 Note: Architecture 2 Meg x 32 2 Meg x 32 2 Meg x 32 Package 86-pin TSOP II 86-pin TSOP II 90-ball VFBGA

1. FBGA Device Decoder: www.micron.com/decoder.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Features

Contents
General Description ......................................................................................................................................... 7 Automotive Temperature .............................................................................................................................. 7 Functional Block Diagrams ............................................................................................................................... 8 Pin and Ball Assignments and Descriptions ....................................................................................................... 9 Package Dimensions ....................................................................................................................................... 12 Temperature and Thermal Impedance ............................................................................................................ 14 Electrical Specifications .................................................................................................................................. 17 Electrical Specifications IDD Parameters ........................................................................................................ 19 Electrical Specifications AC Operating Conditions ......................................................................................... 21 Functional Description ................................................................................................................................... 24 Commands .................................................................................................................................................... 25 COMMAND INHIBIT .................................................................................................................................. 25 NO OPERATION (NOP) ............................................................................................................................... 26 LOAD MODE REGISTER (LMR) ................................................................................................................... 26 ACTIVE ...................................................................................................................................................... 26 READ ......................................................................................................................................................... 27 WRITE ....................................................................................................................................................... 28 PRECHARGE .............................................................................................................................................. 29 BURST TERMINATE ................................................................................................................................... 29 REFRESH ................................................................................................................................................... 30 AUTO REFRESH ..................................................................................................................................... 30 SELF REFRESH ....................................................................................................................................... 30 Truth Tables ................................................................................................................................................... 31 Initialization .................................................................................................................................................. 36 Mode Register ................................................................................................................................................ 38 Burst Length .............................................................................................................................................. 40 Burst Type .................................................................................................................................................. 40 CAS Latency ............................................................................................................................................... 42 Operating Mode ......................................................................................................................................... 42 Write Burst Mode ....................................................................................................................................... 42 Bank/Row Activation ...................................................................................................................................... 43 READ Operation ............................................................................................................................................. 44 WRITE Operation ........................................................................................................................................... 53 Burst Read/Single Write .............................................................................................................................. 60 PRECHARGE Operation .................................................................................................................................. 61 Auto Precharge ........................................................................................................................................... 61 AUTO REFRESH Operation ............................................................................................................................. 73 SELF REFRESH Operation ............................................................................................................................... 75 Power-Down .................................................................................................................................................. 77 Clock Suspend ............................................................................................................................................... 78

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Features

List of Figures
Figure 1: 2 Meg x 32 Functional Block Diagram ................................................................................................. 8 Figure 2: 86-Pin TSOP (Top View) .................................................................................................................... 9 Figure 3: 90-Ball VFBGA (Top View) ............................................................................................................... 10 Figure 4: 86-Pin Plastic TSOP II (400 mil) Package Codes TG/P ...................................................................... 12 Figure 5: 90-Ball VFBGA (8mm x 13mm) Package Codes B5 ........................................................................... 13 Figure 6: Example: Temperature Test Point Location, 86-Pin TSOP (Top View) ................................................. 15 Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View) ................................................ 16 Figure 8: ACTIVE Command .......................................................................................................................... 26 Figure 9: READ Command ............................................................................................................................. 27 Figure 10: WRITE Command ......................................................................................................................... 28 Figure 11: PRECHARGE Command ................................................................................................................ 29 Figure 12: Initialize and Load Mode Register .................................................................................................. 37 Figure 13: Mode Register Definition ............................................................................................................... 39 Figure 14: CAS Latency .................................................................................................................................. 42 Figure 15: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 43 Figure 16: Consecutive READ Bursts .............................................................................................................. 45 Figure 17: Random READ Accesses ................................................................................................................ 46 Figure 18: READ-to-WRITE ............................................................................................................................ 47 Figure 19: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 48 Figure 20: READ-to-PRECHARGE .................................................................................................................. 48 Figure 21: Terminating a READ Burst ............................................................................................................. 49 Figure 22: Alternating Bank Read Accesses ..................................................................................................... 50 Figure 23: READ Continuous Page Burst ......................................................................................................... 51 Figure 24: READ DQM Operation ................................................................................................................ 52 Figure 25: WRITE Burst ................................................................................................................................. 53 Figure 26: WRITE-to-WRITE .......................................................................................................................... 54 Figure 27: Random WRITE Cycles .................................................................................................................. 55 Figure 28: WRITE-to-READ ............................................................................................................................ 55 Figure 29: WRITE-to-PRECHARGE ................................................................................................................. 56 Figure 30: Terminating a WRITE Burst ............................................................................................................ 57 Figure 31: Alternating Bank Write Accesses ..................................................................................................... 58 Figure 32: WRITE Continuous Page Burst ..................................................................................................... 59 Figure 33: WRITE DQM Operation ............................................................................................................... 60 Figure 34: READ With Auto Precharge Interrupted by a READ ......................................................................... 62 Figure 35: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 63 Figure 36: READ With Auto Precharge ............................................................................................................ 64 Figure 37: READ Without Auto Precharge ....................................................................................................... 65 Figure 38: Single READ With Auto Precharge .................................................................................................. 66 Figure 39: Single READ Without Auto Precharge ............................................................................................. 67 Figure 40: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 68 Figure 41: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 68 Figure 42: WRITE With Auto Precharge ........................................................................................................... 69 Figure 43: WRITE Without Auto Precharge ..................................................................................................... 70 Figure 44: Single WRITE With Auto Precharge ................................................................................................. 71 Figure 45: Single WRITE Without Auto Precharge ............................................................................................ 72 Figure 46: Auto Refresh Mode ........................................................................................................................ 74 Figure 47: Self Refresh Mode .......................................................................................................................... 76 Figure 48: Power-Down Mode ........................................................................................................................ 77 Figure 49: Clock Suspend During WRITE Burst ............................................................................................... 78 Figure 50: Clock Suspend During READ Burst ................................................................................................. 79

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Features

Figure 51: Clock Suspend Mode ..................................................................................................................... 80

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64Mb: x32 SDRAM Features

List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1 Table 2: Address Table ..................................................................................................................................... 2 Table 3: 64Mb (x32) SDR Part Numbering ......................................................................................................... 2 Table 4: Pin and Ball Descriptions .................................................................................................................. 11 Table 5: Temperature Limits .......................................................................................................................... 14 Table 6: Thermal Impedance Simulated Values ............................................................................................... 15 Table 7: Absolute Maximum Ratings .............................................................................................................. 17 Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 17 Table 9: Capacitance ..................................................................................................................................... 18 Table 10: IDD Specifications and Conditions Revision G ................................................................................ 19 Table 11: IDD Specifications and Conditions Revision J ................................................................................. 20 Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 21 Table 13: AC Functional Characteristics ......................................................................................................... 22 Table 14: Truth Table Commands and DQM Operation ................................................................................. 25 Table 15: Truth Table Current State Bank n, Command to Bank n .................................................................. 31 Table 16: Truth Table Current State Bank n, Command to Bank m ................................................................. 33 Table 17: Truth Table CKE ........................................................................................................................... 35 Table 18: Burst Definition Table ..................................................................................................................... 41

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM General Description

General Description
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Each of the 16,777,216-bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[10:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM devices offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

Automotive Temperature
The automotive temperature (AT) option adheres to the following specifications: 16ms refresh rate Self refresh not supported Ambient and case temperature cannot be less than 40C or greater than +105C

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Functional Block Diagrams

Functional Block Diagrams

Figure 1: 2 Meg x 32 Functional Block Diagram

CKE CLK CS# WE# CAS# RAS# CONTROL LOGIC BANK 2 BANK 1 BANK 0 BANK 3

COMMAND DECODE

MODE REGISTER 11

REFRESH 11 COUNTER

ROWADDRESS MUX

BANK 0 ROWADDRESS LATCH & DECODER

2048

BANK0 MEMORY ARRAY (2048 x 256 x 32)

DQM[3:0]

SENSE AMPLIFIERS 32 8192

DATA OUTPUT REGISTER

A[10:0], BA[1:0]

ADDRESS REGISTER

BANK CONTROL LOGIC

I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 256 (x32) COLUMN DECODER 32

DQ[31:0]

DATA INPUT REGISTER

COLUMNADDRESS COUNTER/ LATCH

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Pin and Ball Assignments and Descriptions

Pin and Ball Assignments and Descriptions

Figure 2: 86-Pin TSOP (Top View)

VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE# CAS# RAS# CS# NC BA0 BA1 A10 A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NU NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS

Note:

1. Package may or may not be assembled with a location notch.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Pin and Ball Assignments and Descriptions

Figure 3: 90-Ball VFBGA (Top View)
1 A
DQ26 DQ24 VSS VSSQ DQ25 VDD VDDQ DQ22 DQ23 DQ21

B
DQ28 VDDQ DQ27 VSSQ DQ20 DQ19

C
VSSQ VDDQ VDDQ VSSQ VDD A1

D
VSSQ DQ29 DQ30 DQ17 DQ18

E
VDDQ DQ31 NC NC DQ16

F
VSS DQM3 A3 A2 DQM2

G
A4 A5 A6 A10 A0

H
A7 A8 NC NC BA1 NC

J
CLK CKE A9 BA0 CS# RAS#

K
DQM1 NU NC CAS# WE# DQM0

L
VDDQ DQ8 VSS DQ9 VDD DQ6 DQ7 VSSQ VDDQ VDDQ DQ4

M
VSSQ DQ10 DQ5

N
VSSQ DQ12 DQ14 DQ1 DQ3

P
DQ11 VDDQ DQ15 VSSQ VSS VDDQ VDD VSSQ DQ0

R
DQ13 DQ2

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Pin and Ball Assignments and Descriptions

Table 4: Pin and Ball Descriptions
Symbol CLK CKE Type Input Input Description Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power-down and SELF REFRESH operation (all banks idle), active power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in progress will continue, and DQM operation will retain its DQ mask capability while CS# is HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. DQM0 corresponds to DQ[7:0]; DQM1 corresponds to DQ[15:8]; DQM2 corresponds to DQ[23:16]; and DQM3 corresponds to DQ[31:24]. DQM[3:0] are considered same state when referenced as DQM. Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address inputs: A[10:0] are sampled during the ACTIVE command (row address A[10:0]) and READ or WRITE command (column address A[7:0] with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA[1:0] (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data input/output: Data bus. DQ power supply: DQ power to the die for improved noise immunity. DQ ground: DQ ground to the die for improved noise immunity. Power supply: 3.3V 0.3V. Ground. No connect: These pins/balls should be left unconnected. Not used.

CS#

Input

CAS#, RAS#, WE# DQM[3:0]

Input Input

BA[1:0] A[10:0]

Input Input

DQ[31:0] VDDQ VSSQ VDD VSS NC NU

I/O Supply Supply Supply Supply

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Package Dimensions

Package Dimensions
Figure 4: 86-Pin Plastic TSOP II (400 mil) Package Codes TG/P
22.22 0.08 0.50 TYP 0.61 2X 0.10 +0.07 0.20 -0.03 See Detail A

2X 2.80 11.76 0.20 10.16 0.08

2X R 0.75 Pin #1 ID 2X R 1.00 +0.03 0.15 -0.02 0.25 Gage plane 0.10 1.20 MAX Plated lead finish: TG (90% Sn, 10% Pb) or P (100% Sn) 0.01 0.005 thick per side Plastic package material: Epoxy novolac Package width and length do not include mold protrusion. Allowable protrusion is 0.25 per side. +0.10 0.10 -0.05 0.50 0.10 0.80 TYP

Detail A

Notes:

1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. "2X" means the notch is present in two locations (both ends of the device). 4. Package may or may not be assembled with a location notch.

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64Mb: x32 SDRAM Package Dimensions

Figure 5: 90-Ball VFBGA (8mm x 13mm) Package Codes B5

0.65 0.05

Seating plane A Solder ball material: 62% Sn, 36% Pb, 2% Ag or 96.5% Sn, 3%Ag, 0.5% Cu Substrate material: Plastic laminate Mold compound: Epoxy novolac 0.80 TYP Ball A1 ID

0.12 A 90X 0.45 Dimensions apply to solder balls post reflow. The pre-reflow diameter is 0.42 on a 0.40 SMD ball pad.

6.40

Ball A9

Ball A1 ID Ball A1

0.80 TYP 11.20 0.10 C L 13.00 0.10

5.60 0.05 6.50 0.05

C L 3.20 0.05 4.00 0.05 1.00 MAX

8.00 0.10

Notes:

1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. Recommended pad size for PCB is 0.33mm 0.025mm.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Temperature and Thermal Impedance

Temperature and Thermal Impedance

It is imperative that the SDRAM devices temperature specifications, shown in Temperature Limits below, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the devices thermal impedances correctly. The thermal impedances are listed in Table 6 (page 15) for the applicable die revision and packages being made available. These thermal impedance values vary according to the density, package, and particular design used for each device. Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, Thermal Applications prior to using the thermal impedances listed in Table 6 (page 15). To ensure the compatibility of current and future designs, contact Micron Applications Engineering to confirm thermal impedance values. The SDRAM devices safe junction temperature range can be maintained when the T C specification is not exceeded. In applications where the devices ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications. Table 5: Temperature Limits
Parameter Operating case temperature Commercial Industrial Automotive Junction temperature Commercial Industrial Automotive Ambient temperature Commercial Industrial Automotive Peak reflow temperature Notes: TPEAK TA TJ Symbol TC Min 0 40 40 0 40 40 0 40 40 Max 80 90 105 85 95 110 70 85 105 260 C C 3, 5 C 3 Unit C Notes 1, 2, 3, 4

1. MAX operating case temperature TC is measured in the center of the package on the top side of the device, as shown in Figure 6 (page 15) and Figure 7 (page 16). 2. Device functionality is not guaranteed if the device exceeds maximum TC during operation. 3. All temperature specifications must be satisfied. 4. The case temperature should be measured by gluing a thermocouple to the top-center of the component. This should be done with a 1mm bead of conductive epoxy, as defined by the JEDEC EIA/JESD51 standards. Take care to ensure that the thermocouple bead is touching the case. 5. Operating ambient temperature surrounding the package.

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64Mb: x32 SDRAM Temperature and Thermal Impedance

Table 6: Thermal Impedance Simulated Values
Die Revision G JA (C/W) Airflow = 0m/s 95.2 66.6 70.6 54 122.3 101.9 76.8 56.3 JA (C/W) Airflow = 1m/s 75.3 57.7 57.6 47.3 105.6 93.5 63.1 49.6 JA (C/W) Airflow = 2m/s 69.0 54.6 69.5 52.7 98.1 88.8 63.1 46.9

Package 86-pin TSOP

Substrate Low Conductivity High Conductivity

JB (C/W) 66.5 53.6 35.7 35.2 89.5 87.6 50.1 43.5

JC (C/W) 12.7

90-ball VFBGA

Low Conductivity High Conductivity

7.95

86-pin TSOP

Low Conductivity High Conductivity

20.7

90-ball VFBGA

Low Conductivity High Conductivity

10.4

Notes:

1. For designs expected to last beyond the die revision listed, contact Micron Applications Engineering to confirm thermal impedance values. 2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as typical. 3. These are estimates; actual results may vary.

Figure 6: Example: Temperature Test Point Location, 86-Pin TSOP (Top View)

22.22mm 11.11mm Test point

10.16mm 5.08mm

Note:

1. Package may or may not be assembled with a location notch.

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64Mb: x32 SDRAM Temperature and Thermal Impedance

Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View)
8.00mm 4.00mm

Test point 13.00mm

6.50mm

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Electrical Specifications

Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 7: Absolute Maximum Ratings
Voltage/Temperature Voltage on VDD, VDDQ supply relative to VSS Voltage on inputs, NC, or I/O pins relative to VSS Storage temperature (plastic) Power dissipation Symbol VDD, VDDQ VIN TSTG Min 1 1 55 Max 4.6 4.6 150 1 Unit V V C W

Table 8: DC Electrical Characteristics and Operating Conditions

Notes 13 apply to all parameters and conditions; VDD, VDDQ = 3.3V 0.3V Parameter/Condition Symbol Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output high voltage: IOUT = 4mA Output low voltage: IOUT = 4mA Input leakage current: Any input 0V VIN VDD (All other pins not under test = 0V) Output leakage current: DQs are disabled; 0V VOUT VDDQ Operating temperature: Commercial Industrial Automotive Notes: VDD, VDDQ VIH VIL VOH VOL IL IOZ TA TA TA Min 3 2 0.3 2.4 5 5 0 40 40 Max 3.6 VDD + 0.3 0.8 0.4 5 5 70 85 105 Unit V V V V V A A C C C 4 4 Notes

1. All voltages referenced to VSS. 2. An initial pulse of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential). The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. VDD,min = 3.135V for -6, -55, and -5 speed grades. 4. VIH overshoot: VIH,max = VDDQ + 1.2V for a pulse width 3ns, and the pulse width cannot be greater than one-third of the cycle rate. VIL undershoot: VIL,min = 1.2V for a pulse width 3ns, and the pulse width cannot be greater than one-third of the cycle rate.

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64Mb: x32 SDRAM Electrical Specifications

Table 9: Capacitance
Note 1 applies to all parameters and conditions Package TSOP Package Parameter Input capacitance: CLK Input capacitance: All other input-only balls/pins Input/output capacitance: DQ VFBGA Package Input capacitance: CLK Input capacitance: All other input-only balls/pins Input/output capacitance: DQ Note: Min 2.5 2.5 4.0 1.5 1.5 3 Max 4.0 4.0 6.5 4.0 4.0 6.5 Unit pF pF pF pF pF pF

1. This parameter is sampled. VDD, VDDQ = 3.3V; f = 1 MHz, TA = 25C; pin under test biased at 1.4V. AC can range from 0pF to 6pF.

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64Mb: x32 SDRAM Electrical Specifications IDD Parameters

Electrical Specifications IDD Parameters

Table 10: IDD Specifications and Conditions Revision G
Notes 15 apply to all parameters and conditions; VDD, VDDQ = 3.3V 0.3V Max Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE; tRC tRC (MIN);CL = 3 Standby current: Power-down mode; All banks idle; CKE = LOW Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress Operating current: Burst mode; Continuous burst; READ or WRITE; All banks active; CL = 3 Auto refresh current: CL = 3; CKE, CS# = HIGH Self refresh current: CKE 0.2V
tRFC

Symbol IDD1 IDD2 IDD3 IDD4 IDD5 IDD6

-5 200 2 80 280 225 2

-55 190 2 70 260 225 2

-6 150 2 60 180 225 2

-7 130 2 50 160 225 2

Unit mA mA mA mA mA mA

Notes 6, 7, 8, 9

6, 8, 9, 10 6, 7, 8, 9 6, 7, 8, 9, 10 11

= tRFC (MIN)

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64Mb: x32 SDRAM Electrical Specifications IDD Parameters

Table 11: IDD Specifications and Conditions Revision J
Notes 15 apply to all parameters and conditions; VDD, VDDQ = 3.3V 0.3V Max Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE; tRC tRC (MIN); CL =3 Standby current: Power-down mode; All banks idle; CKE = LOW Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress Operating current: Burst mode; Continuous burst; READ or WRITE; All banks active; CL = 3 Auto refresh current: CL = 3; CKE, CS# = HIGH Self refresh current: CKE 0.2V Notes:
tRFC

Symbol IDD1 IDD2 IDD3 IDD4 IDD5 IDD6

-5 140 2.5 45 140 200 3

-6A 120 2.5 45 120 180 3

Unit mA mA mA mA

Notes 6, 7, 8, 9

6, 8, 9, 10 6, 7, 8, 9

= tRFC (MIN)

mA 6, 7, 8, 9, 10 mA 11

1. All voltages referenced to VSS. 2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC timing and IDD tests have VIL = 0.25V and VIH = 2.75V, with timing referenced to 1.5V crossover point. 4. IDD specifications are tested after the device is properly initialized. 5. VDD = 3.135V for -6, -55, and -5 speed grades. 6. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 7. The IDD current will decrease as the CL is reduced. This is due to the fact that the maximum cycle rate is slower as the CL is reduced. 8. Address transitions average one transition every two clocks. 9. tCK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5. 10. Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels. 11. Enables on-chip refresh and address counters.

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64Mb: x32 SDRAM Electrical Specifications AC Operating Conditions

Electrical Specifications AC Operating Conditions

Table 12: Electrical Characteristics and Recommended AC Operating Conditions
Notes 15 apply to all parameters and conditions; VDD, VDDQ = 3.3V 0.3V -5 -55 -6A6 Parameter Access time from CLK CL = 3 (positive edge) CL = 2 CL = 1 Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CL = 3 CL = 2 CL = 1 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out High-Z time CL = 3 CL = 2 CL = 1 Data-out Low-Z time Data-out hold time ACTIVE-to-PRECHARGE command ACTIVE-to-ACTIVE command period AUTO REFRESH period ACTIVE-to-READ or WRITE delay Refresh period (4096 rows) Refresh period automotive (4096 rows) PRECHARGE command period ACTIVE bank a to ACTIVE bank b command
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-6 Min 1 1.5 2.5 2.5 6 10 20 1 1.5 1 1.5 1 1.5 1 2 42 60 60 18 18 12 Max 5.5 7.5 17 5.5 7.5 17 120k 64 16 Min 1 2 2.75 2.75 7 10 20 1 2 1 2 1 2 1 2.5 42 70 70 20 20 14

-7 Max 5.5 8 17 5.5 8 17 120k 64 16 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns 10 9 8 8 8 7 7 7

Symbol Min
tAC(3) tAC(2) tAC(1) tAH tAS tCH tCL tCK(3) tCK(2) tCK(1) tCKH tCKS tCMH tCMS tDH tDS tHZ(3) tHZ(2) tHZ(1) tLZ tOH tRAS tRC tRFC tRCD tREF tREF AT

Max 4.5 120k 64 16

Min 1 1.5 2 2 5.5 1 1.5 1 1.5 1 1.5 5 1 2 38.7 55 60 16.5 16.5 11

Max 5 120k 64 16

Min 0.8 1.5 2.5 2.5 6 10 20 0.8 1.5 0.8 1.5 0.8 1.5 1 3 42 60 60 18 18 12

Max 5.4 7.5 17 5.4 7.5 17 120k 64 16

1 1.5 2 2 5 1 1.5 1 1.5 1 1.5 4.5 1 1.5 38.7 55 60 15 15 10

tRP tRRD

64Mb: x32 SDRAM Electrical Specifications AC Operating Conditions

Table 12: Electrical Characteristics and Recommended AC Operating Conditions (Continued)
Notes 15 apply to all parameters and conditions; VDD, VDDQ = 3.3V 0.3V -5 -55 -6A6 Parameter Transition time WRITE recovery time Symbol Min
tT tWR

-6 Min 0.3 1 CLK + 6ns 12 70 Max 1.2 Min 0.3 1 CLK + 7ns 14 70

-7 Max 1.2 Unit Notes ns

tCK

Max 1.2

Min 0.3 2

Max 1.2

Min 0.3 1 CLK + 6ns 12 67

Max 1.2

0.3 2

11 12

ns ns

13 14

Exit SELF REFRESH-to-ACTIVE command

tXSR

Table 13: AC Functional Characteristics

Notes 25 apply to all parameters and conditions Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data High-Z during READs WRITE command to input data delay Data-in to ACTIVE command CL = 3 CL = 2 CL = 1 Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to High-Z from PRECHARGE command CL = 3 CL = 2 CL = 1 Notes: Symbol
tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL(3) tDAL(2) tDAL(1) tDPL tBDL tCDL tRDL tMRD tROH(3) tROH(2) tROH(1)

-5 1 1 1 0 0 2 0 5 2 1 1 2 2 3

-55 1 1 1 0 0 2 0 5 2 1 1 2 2 3

-6/6A 1 1 1 0 0 2 0 5 4 3 2 1 1 2 2 3 2 1

-7 1 1 1 0 0 2 0 5 4 3 2 1 1 2 2 3 2 1

Unit
tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK

Notes 15 16 16 15 15 15 15 17, 18 17, 18 17, 18 18, 19 15 15 18, 19 20 15 15 15

1. Minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range is ensured: 0C TA +70C (commercial) 40C TA +85C (industrial) 40C TA +105C (automotive) 2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered

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64Mb: x32 SDRAM Electrical Specifications AC Operating Conditions

up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. Outputs measured at 1.5V with equivalent load:

50pF
5. AC timing and IDD tests have VIL = 0.25V and VIH = 2.75V, with timing referenced to 1.5V crossover point. 6. Not applicable for revision G. 7. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. t 8. HZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 9. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime. 10. JEDEC and PC100 specify three clocks. 11. AC characteristics assume tT = 1ns. 12. Auto precharge mode only. 13. Check factory for availability of specially screened devices having tWR = 10ns. tWR = 1 tCK for 100 MHz and slower (tCK = 10ns and higher) in manual precharge. 14. CLK must be toggled a minimum of two times during this period. 15. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 16. Timing is specified by tCKS. Clock(s) specified as a reference only at minimum cycle rate. 17. Timing is specified by tWR plus tRP. Clock(s) specified as a reference only at minimum cycle rate. 18. Based on tCK = 143 MHz for -7, 166 MHz for -6, 183 MHz for -55, and 200 MHz for -5. 19. Timing is specified by tWR. 20. tCK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5.

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64Mb: x32 SDRAM Functional Description

Functional Description
In general, this 64Mb SDRAM device (512K x 32x 4 banks) is a quad-bank DRAM that operates at 3.3V and include a synchronous interface. All signals are registered on the positive edge of the clock signal, CLK. Each of the 16,777,216-bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A[10:0] select the row). The address bits (A[7:0]) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the device must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation.

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64Mb: x32 SDRAM Commands

Commands
The following table provides a quick reference of available commands, followed by a written description of each command. Additional Truth Tables (Table 15 (page 31), Table 16 (page 33), and Table 17 (page 35)) provide current state/next state information. Table 14: Truth Table Commands and DQM Operation
Note 1 applies to all parameters and conditions Name (Function) COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (select bank and activate row) READ (select bank and column, and start READ burst) WRITE (select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (enter self refresh mode) LOAD MODE REGISTER Write enable/output enable Write inhibit/output High-Z Notes: CS# RAS# CAS# WE# DQM H L L L L L L L L X X X H L H H H L L L X X X H H L L H H L L X X X H H H L L L H L X X X X X L/H L/H X X X X L H ADDR X X Bank/row Bank/col Bank/col X Code X Op-code X X DQ X X X X Valid Active X X X Active High-Z 2 3 3 4 5 6, 7 8 9 9 Notes

1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1 determine which bank is made active. 3. A[0:i] provide column address (where i = the most significant column address for a given device configuration). A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature. BA0 and BA1 determine which bank is being read from or written to. 4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command could coincide with data on the bus. However, the DQ column reads a Dont Care state to illustrate that the BURST TERMINATE command can occur when there is no data present. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks precharged and BA0, BA1 are Dont Care. 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are Dont Care except for CKE. 8. A[11:0] define the op-code written to the mode register. 9. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock delay).

COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the device, regardless of whether the CLK signal is enabled. The device is effectively deselected. Operations already in progress are not affected.

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64Mb: x32 SDRAM Commands NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to the selected device (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER (LMR)

The mode registers are loaded via inputs A[n:0] (where An is the most significant address term), BA0, and BA1(see Mode Register (page 38)). The LOAD MODE REGISTER command can only be issued when all banks are idle and a subsequent executable command cannot be issued until tMRD is met.

ACTIVE
The ACTIVE command is used to activate a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided selects the row. This row remains active for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. Figure 8: ACTIVE Command
CLK CKE CS#
HIGH

RAS#

CAS# WE#

Address

Row address

BA0, BA1

Bank address

Dont Care

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64Mb: x32 SDRAM Commands READ

The READ command is used to initiate a burst read access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed is precharged at the end of the READ burst; if auto precharge is not selected, the row remains open for subsequent accesses. Read data appears on the DQ subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be HighZ two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data. Figure 9: READ Command
CLK CKE CS#
HIGH

RAS#

CAS# WE#

Address A101

Column address EN AP DIS AP

BA0, BA1

Bank address

Dont Care

Note:

1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

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64Mb: x32 SDRAM Commands WRITE

The WRITE command is used to initiate a burst write access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed is precharged at the end of the write burst; if auto precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQ is written to the memory array, subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data is written to memory; if the DQM signal is registered HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that byte/column location. Figure 10: WRITE Command
CLK CKE CS# HIGH

RAS#

CAS# WE#

Address A101

Column address EN AP DIS AP

BA0, BA1

Bank address

Valid address

Dont Care

Note:

1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

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64Mb: x32 SDRAM Commands PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as Dont Care. After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands are issued to that bank. Figure 11: PRECHARGE Command
CLK CKE CS# HIGH

RAS#

CAS# WE#

Address
All banks

A10
Bank selected

BA0, BA1

Bank address

Valid address

Dont Care

BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or continuous page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command is truncated.

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64Mb: x32 SDRAM Commands REFRESH

AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be precharged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command, as shown in Bank/Row Activation (page 43). The addressing is generated by the internal refresh controller. This makes the address bits a Dont Care during an AUTO REFRESH command. Regardless of device width, the 64Mb SDRAM requires 4096 AUTO REFRESH cycles every 64ms (commercial and industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command every 15.625s (commercial and industrial) or 3.906s (automotive) will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms (commercial and industrial) or 16ms (automotive). SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered-down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the SDRAM become a Dont Care with the exception of CKE, which must remain LOW. After self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued at the specified intervals, as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. Self refresh is not supported on automotive temperature devices.

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64Mb: x32 SDRAM Truth Tables

Truth Tables
Table 15: Truth Table Current State Bank n, Command to Bank n
Notes 16 apply to all parameters and conditions Current State CS# RAS# CAS# Any Idle H L L L L L Row active L L L Read (auto precharge disabled) L L L L Write (auto precharge disabled) L L L L Notes: X H L L L L H H L H H L H H H L H X H H L L H L L H L L H H L L H H WE# Command/Action X H H H L L H L L H L L L H L L L COMMAND INHIBIT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) ACTIVE (select and activate row) AUTO REFRESH LOAD MODE REGISTER PRECHARGE READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE (truncate READ burst, start PRECHARGE) BURST TERMINATE READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE (truncate WRITE burst, start PRECHARGE) BURST TERMINATE 7 7 8 9 9 10 9 9 10 11 9 9 10 11 Notes

1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 17 (page 35)) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted (for example, the current state is for a specific bank and the commands shown can be issued to that bank when in that state). Exceptions are covered below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or supported commands to the other bank should be issued on any clock edge occurring during these states. Supported commands to any other bank are determined by the banks current state and the conditions described in this and the following table. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. After tRP is met, the bank will be in the idle state. Row activating: Starts with registration of an ACTIVE command and ends when tRCD is met. After tRCD is met, the bank will be in the row active state.

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64Mb: x32 SDRAM Truth Tables

6. 7. 8. 9. 10. 11.

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64Mb: x32 SDRAM Truth Tables

Table 16: Truth Table Current State Bank n, Command to Bank m
Notes 16 apply to all parameters and conditions Current State CS# RAS# CAS# Any Idle Row activating, active, or precharging H L X L L L L Read (auto precharge disabled) L L L L Write (auto precharge disabled) L L L L Read (with auto precharge) L L L L Write (with auto precharge) L L L L Notes: X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H WE# Command/Action X H X H H L L H H L L H H L L H H L L H H L L COMMAND INHIBIT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any command otherwise supported for bank m ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE 7, 8, 16 7, 8, 17 9 7, 8, 14 7, 8, 15 9 7, 12 7, 13 9 7, 10 7, 11 9 7 7 Notes

1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (Table 17 (page 35)), and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; for example, the current state is for bank n and the commands shown can be issued to bank m, assuming that bank m is in such a state that the given command is supported. Exceptions are covered below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

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64Mb: x32 SDRAM Truth Tables

Read with auto precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. Write with auto precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands can only be issued when all banks are idle. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. All states and sequences not shown are illegal or reserved. READs or WRITEs to bank m listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. Concurrent auto precharge: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m burst. The burst in bank n continues as initiated. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency (CL) later. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used one clock prior to the WRITE command to prevent bus contention. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n will begin when the READ to bank m is registered. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in registered one clock prior to the READ to bank m. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m.

4. 5. 6. 7.

8. 9. 10. 11.

12.

13.

14.

15.

16.

17.

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64Mb: x32 SDRAM Truth Tables

Table 17: Truth Table CKE
Notes 14 apply to all parameters and conditions Current State CKEn-1 CKEn Power-down Self refresh Clock suspend Power-down Self refresh Clock suspend All banks idle All banks idle Reading or writing H Notes: H H L L H L L Commandn X X X COMMAND INHIBIT or NOP COMMAND INHIBIT or NOP X COMMAND INHIBIT or NOP AUTO REFRESH VALID See Table 16 (page 33). Actionn Maintain power-down Maintain self refresh Maintain clock suspend Exit power-down Exit self refresh Exit clock suspend Power-down entry Self refresh entry Clock suspend entry 5 6 7 Notes

1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state after tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during the tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1.

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64Mb: x32 SDRAM Initialization

Initialization
SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. After power is applied to V DD and V DDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands must be applied. After the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it must be loaded prior to applying any operational command. If desired, the two AUTO REFRESH commands can be issued after the LMR command. The recommended power-up sequence for SDRAM: 1. Simultaneously apply power to V DD and V DDQ. 2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTLcompatible. 3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 4. Wait at least 100s prior to issuing any command other than a COMMAND INHIBIT or NOP. 5. Starting at some point during this 100s period, bring CKE HIGH. Continuing at least through the end of this period, 1 or more COMMAND INHIBIT or NOP commands must be applied. 6. Perform a PRECHARGE ALL command. 7. Wait at least tRP time; during this time NOPs or DESELECT commands must be given. All banks will complete their precharge, thereby placing the device in the all banks idle state. 8. Issue an AUTO REFRESH command. 9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 10. Issue an AUTO REFRESH command. 11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 12. The SDRAM is now ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying any operational command. Using the LMR command, program the mode register. The mode register is programmed via the MODE REGISTER SET command with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not programming the mode register upon initialization will result in default settings which may not be desired. Outputs are guaranteed High-Z after the LMR command is issued. Outputs should be High-Z already before the LMR command is issued. 13. Wait at least tMRD time, during which only NOP or DESELECT commands are allowed. At this point the DRAM is ready for any valid command.
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64Mb: x32 SDRAM Initialization

Note: More than two AUTO REFRESH commands can be issued in the sequence. After steps 9 and 10 are complete, repeat them until the desired number of AUTO REFRESH + tRFC loops is achieved. Figure 12: Initialize and Load Mode Register

T0 CK (( ))
(( )) (( ))
tCMS tCMH

tCK

tCKS tCKH

(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))

Tn + 1
tCH

(( )) (( ))

tCL

To + 1

(( )) (( ))

Tp + 1

Tp + 2

Tp + 3

CKE

(( ))

COMMAND

(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))

NOP2

PRECHARGE

AUTO REFRESH

(( )) NOP2 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))

AUTO REFRESH

(( )) NOP2 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))

LOAD MODE REGISTER

NOP2

ACTIVE

DQM/DQML, DQMU

tAS

tAH5

A[9:0], A[12:11]

CODE
tAS tAH

ROW

ALL BANKS SINGLE BANK

A10

(( )) (( )) (( )) (( ))

CODE

ROW

BA[1:0]

ALL BANKS

(( )) T = 100s MIN Power-up: VDD and CLK stable

High-Z

(( ))
tRP tRFC tRFC tMRD

Precharge all banks

AUTO REFRESH

Program Mode Register1,3,4 DONT CARE UNDEFINED

Notes:

1. 2. 3. 4. 5.

The mode register may be loaded prior to the AUTO REFRESH cycles if desired. If CS is HIGH at clock HIGH time, all commands applied are NOP. JEDEC and PC100 specify three clocks. Outputs are guaranteed High-Z after command is issued. A12 should be a LOW at tP + 1.

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64Mb: x32 SDRAM Mode Register

Mode Register
The mode register defines the specific mode of operation, including burst length (BL), burst type, CAS latency (CL), operating mode, and write burst mode. The mode register is programmed via the LOAD MODE REGISTER command and retains the stored information until it is programmed again or the device loses power. Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and M10Mn should be set to zero to ensure compatibility with future revisions. Mn + 1 and Mn + 2 should be set to zero to select the mode register. The mode registers must be loaded when all banks are idle, and the controller must wait tMRD before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.

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64Mb: x32 SDRAM Mode Register

Figure 13: Mode Register Definition

A12 A11 A10

Address Bus

9 WB

3 BT

Mode Register (Mx)

Reserved

Op Mode

CAS Latency

Burst Length

Program BA1, BA0 = 0, 0 to ensure compatibility with future devices.

Burst Length M2 M1 M0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved

M9 0 1

Write Burst Mode Programmed Burst Length Single Location Access

0 0 0 1

M8 0

M7 0

M6-M0 Defined

Operating Mode Standard Operation All other states reserved

1 1 1

M3 0 1

Burst Type Sequential Interleaved

M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved

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64Mb: x32 SDRAM Mode Register Burst Length

Read and write accesses to the device are burst oriented, and the burst length (BL) is programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, 8, or continuous locations are available for both the sequential and the interleaved burst types, and a continuous page burst is available for the sequential type. The continuous page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block when a boundary is reached. The block is uniquely selected by A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Continuous page bursts wrap within the page when the boundary is reached.

Burst Type
Accesses within a given burst can be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address.

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64Mb: x32 SDRAM Mode Register

Table 18: Burst Definition Table
Order of Accesses Within a Burst Burst Length 2 Starting Column Address A0 0 1 4 A1 0 0 1 1 8 A2 0 0 0 0 1 1 1 1 Continuous n = A0An/9/8 (location 0y) Notes: Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1, Cn... Not supported A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1 1-0 0-1 1-0 Type = Sequential Type = Interleaved

1. For full-page accesses: y = 2048 (x4); y = 1024 (x8); y = 512 (x16). 2. For BL = 2, A1A9, A11 (x4); A1A9 (x8); or A1A8 (x16) select the block-of-two burst; A0 selects the starting column within the block. 3. For BL = 4, A2A9, A11 (x4); A2A9 (x8); or A2A8 (x16) select the block-of-four burst; A0A1 select the starting column within the block. 4. For BL = 8, A3A9, A11 (x4); A3A9 (x8); or A3A8 (x16) select the block-of-eight burst; A0A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0A9, A11 (x4); A0A9 (x8); or A0A8 (x16) select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For BL = 1, A0A9, A11 (x4); A0A9 (x8); or A0A8 (x16) select the unique column to be accessed, and mode register bit M3 is ignored.

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64Mb: x32 SDRAM Mode Register CAS Latency

The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ command and the availability of the output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data is valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ start driving after T1 and the data is valid by T2. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 14: CAS Latency
T0 CLK Command READ NOP tLZ DQ tAC CL = 2 T0 CLK Command READ NOP NOP tLZ DQ CL = 3 tAC NOP tOH DOUT T1 T2 T3 T4 NOP tOH DOUT T1 T2 T3

Dont Care

Undefined

Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use. Reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M[2:0] applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.

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64Mb: x32 SDRAM Bank/Row Activation

Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with the ACTIVE command, a READ or WRITE command can be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 15 (page 43), which covers any case where 2 < tRCD (MIN)/tCK 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been precharged. The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. Figure 15: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3
T0 T1 T2 T3

CLK
tCK tCK NOP tRCD(MIN) NOP tCK READ or WRITE

Command

ACTIVE

Dont Care

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64Mb: x32 SDRAM READ Operation

READ Operation
READ bursts are initiated with a READ command, as shown in Figure 9 (page 27). The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. In the following figures, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address is available following the CAS latency after the READ command. Each subsequent dataout element will be valid by the next positive clock edge. Figure 17 (page 46) shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQ signals will go to High-Z. A continuous page burst continues until terminated. At the end of the page, it wraps to column 0 and continues. Data from any READ burst can be truncated with a subsequent READ command, and data from a fixed-length READ burst can be followed immediately by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst either follows the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 17 (page 46) for CL2 and CL3. SDRAM devices use a pipelined architecture and therefore do not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a READ command. Full-speed random read accesses can be performed to the same bank, or each subsequent READ can be performed to a different bank.

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64Mb: x32 SDRAM READ Operation

Figure 16: Consecutive READ Bursts
T0 CLK T1 T2 T3 T4 T5 T6

Command

READ

NOP

READ X = 1 cycle

NOP

Address

Bank, Col n

Bank, Col b

DQ
CL = 2

DOUT n

DOUT n+1

DOUT n+2

DOUT n+3

DOUT b

T0 CLK

Command

READ

NOP

READ

NOP

X = 2 cycles

Address

Bank, Col n

Bank, Col b

DQ
CL = 3

DOUT

Transitioning data

Dont Care

Note:

1. Each READ command can be issued to any bank. DQM is LOW.

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64Mb: x32 SDRAM READ Operation

Figure 17: Random READ Accesses
T0 CLK T1 T2 T3 T4 T5

Command

READ

NOP

Address

Bank, Col n

Bank, Col a

Bank, Col x

Bank, Col m

DQ
CL = 2

DOUT

T0 CLK

Command

READ

NOP

Address

Bank, Col n

Bank, Col a

Bank, Col x

Bank, Col m

DQ
CL = 3

DOUT

Transitioning data

Dont Care

Note:

1. Each READ command can be issued to any bank. DQM is LOW.

Data from any READ burst can be truncated with a subsequent WRITE command, and data from a fixed-length READ burst can be followed immediately by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst can be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there is a possibility that the device driving the input data will go Low-Z before the DQ go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figure 18 (page 47) and Figure 19 (page 48). The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. After the WRITE command is registered, the DQ will go to High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4, then the WRITEs at T5 and T7 would be valid, and the WRITE at T6 would be invalid.

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64Mb: x32 SDRAM READ Operation

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 18 (page 47) shows where, due to the clock cycle frequency, bus contention is avoided without having to add a NOP cycle, while Figure 19 (page 48) shows the case where an additional NOP cycle is required. A fixed-length READ burst may be followed by or truncated with a PRECHARGE command to the same bank, provided that auto precharge was not activated. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 20 (page 48) for each possible CL; data element n + 3 is either the last of a burst of four or the last desired data element of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate fixed-length or continuous page bursts. Figure 18: READ-to-WRITE
T0 T1 T2 T3 T4

CLK

DQM Command Address

READ NOP NOP NOP WRITE

Bank, Col n

Bank, Col b

tCK tHZ DQ
DOUT DIN t

Transitioning data

Dont Care

Note:

1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be to any bank. If a burst of one is used, DQM is not required.

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64Mb: x32 SDRAM READ Operation

Figure 19: READ-to-WRITE With Extra Clock Cycle
T0 CLK DQM Command Address T1 T2 T3 T4 T5

READ Bank, Col n

NOP

WRITE Bank, Col b

tHZ

DOUT

DIN

tDS Transitioning data Dont Care

Note:

1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be to any bank.

Figure 20: READ-to-PRECHARGE

T0 CLK
tRP

Command

READ

NOP

PRECHARGE X = 1 cycle

NOP

ACTIVE

Address

Bank a, Col n

Bank (a or all)

Bank a, Row

DQ
CL = 2

DOUT

T0 CLK

t RP

Command

READ

NOP

PRECHARGE

NOP X = 2 cycles

NOP

ACTIVE

Address

Bank a, Col

Bank (a or all)

Bank a, Row

DQ
CL = 3

DOUT

Transitioning data

Dont Care

Note:

1. DQM is LOW.

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64Mb: x32 SDRAM READ Operation

Continuous-page READ bursts can be truncated with a BURST TERMINATE command and fixed-length READ bursts can be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 21 (page 49) for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. Figure 21: Terminating a READ Burst
T0 CLK T1 T2 T3 T4 T5 T6

Command

READ

NOP

BURST TERMINATE X = 1 cycle

NOP

Address

Bank, Col n

DQ
CL = 2

DOUT

T0 CLK

Command

READ

NOP

BURST TERMINATE

NOP X = 2 cycles

NOP

Address

Bank, Col n

DQ
CL = 3

DOUT

Transitioning data

Dont Care

Note:

1. DQM is LOW.

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64Mb: x32 SDRAM READ Operation

Figure 22: Alternating Bank Read Accesses
T0 CLK tCKS CKE tCMS Command tCMH
NOP READ NOP ACTIVE NOP READ NOP ACTIVE

tCK tCKH

tCL

T2 tCH

ACTIVE

tCMS tCMH DQM tAS Address tAH

Column m Row Column b
1

Row

tAS A10

tAH

Enable auto precharge Row

Row

tAS BA0, BA1

tAH
Bank 0 Bank 3 Bank 3 Bank 0

Bank 0

tAC tAC DQ tRCD - bank 0 tRAS - bank 0 tRC - bank 0 tRRD CL - bank 0 tLZ tOH
DOUT

tAC tOH
DOUT

tRP - bank 0

tRCD - bank 0

tRCD - bank 3

CL - bank 3 Dont Care Undefined

Note:

1. For this example, BL = 4 and CL = 2.

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64Mb: x32 SDRAM READ Operation

Figure 23: READ Continuous Page Burst
T0 T1 tCH T2 T3 T4 T5 T6
(( )) (( ))

CLK
tCKS tCKH

tCL

tCK

Tn + 1

Tn + 2

Tn + 3

Tn + 4

CKE
tCMS tCMH
NOP READ NOP NOP NOP NOP

(( )) (( )) (( )) (( )) (( )) (( ))

Command

ACTIVE

NOP

BURST TERM

NOP

tCMS

tCMH

DQM
tAS tAH
Column m

Address

Row

(( )) (( )) (( )) (( )) (( )) (( ))

tAS

tAH

A10

Row

tAS

tAH
Bank

BA0, BA1

Bank

tAC tOH

tAC tOH
DOUT

tAC

DQ
tLZ tRCD

DOUT

(( DOUT ) ) (( ))

tAC tOH

(( ))

tAC tOH
DOUT

tAC tOH DOUT tOH

DOUT

tHZ

CAS latency

All locations within same row Full page completed Full-page burst does not self-terminate. Can use BURST TERMINATE command. Dont Care Undefined

Note:

1. For this example, CL = 2.

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64Mb: x32 SDRAM READ Operation

Figure 24: READ DQM Operation
T0 T1 T2 tCH T3 T4 T5 T6 T7 T8

CLK
tCKS tCKH

tCK

tCL

CKE
tCMS tCMH
NOP READ NOP NOP NOP NOP NOP NOP

Command

ACTIVE

tCMS

tCMH

DQM
tAS tAH
Row Column m Enable auto precharge

Address
tAS

tAH
Row

A10
tAS

tAH
Bank

Disable auto precharge Bank

BA0, BA1

tAC

DQ
tLZ tRCD CL = 2

tAC

tOH
DOUT

tAC tLZ

tOH
DOUT

tHZ

Dont Care Undefined

Note:

1. For this example, BL = 4 and CL = 2.

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64Mb: x32 SDRAM WRITE Operation

WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 10 (page 28). The starting column and bank addresses are provided with the WRITE command and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following figures, auto precharge is disabled. During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command. Subsequent data elements are registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQ will remain at High-Z and any additional input data will be ignored (see Figure 25 (page 53)). A continuous page burst continues until terminated; at the end of the page, it wraps to column 0 and continues. Data for any WRITE burst can be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst can be followed immediately by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command (see Figure 26 (page 54)). Data n + 1 is either the last of a burst of two or the last desired data element of a longer burst. SDRAM devices use a pipelined architecture and therefore do not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 27 (page 55), or each subsequent WRITE can be performed to a different bank. Figure 25: WRITE Burst
T0 CLK T1 T2 T3

Command

WRITE

NOP

Address

Bank, Col n

DIN

Transitioning data

Dont Care

Note:

1. BL = 2. DQM is LOW.

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64Mb: x32 SDRAM WRITE Operation

Figure 26: WRITE-to-WRITE
T0 CLK T1 T2

Command

WRITE

NOP

WRITE

Address

Bank, Col n

Bank, Col b

DIN

Transitioning data

Dont Care

Note:

1. DQM is LOW. Each WRITE command may be issued to any bank.

Data for any WRITE burst can be truncated with a subsequent READ command, and data for a fixed-length WRITE burst can be followed immediately by a READ command. After the READ command is registered, data input is ignored and WRITEs will not be executed (see Figure 28 (page 55)). Data n + 1 is either the last of a burst of two or the last desired data element of a longer burst. Data for a fixed-length WRITE burst can be followed by or truncated with a PRECHARGE command to the same bank, provided that auto precharge was not activated. A continuous-page WRITE burst can be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock with time to complete, regardless of frequency. In addition, when truncating a WRITE burst at high clock frequencies ( tCK < 15ns), the DQM signal must be used to mask input data for the clock edge prior to and the clock edge coincident with the PRECHARGE command (see Figure 29 (page 56)). Data n + 1 is either the last of a burst of two or the last desired data element of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate fixed-length bursts or continuous page bursts.

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64Mb: x32 SDRAM WRITE Operation

Figure 27: Random WRITE Cycles
T0 CLK T1 T2 T3

Command

WRITE

Address

Bank, Col n

Bank, Col a

Bank, Col x

Bank, Col m

DIN

Transitioning data

Dont Care

Note:

1. Each WRITE command can be issued to any bank. DQM is LOW.

Figure 28: WRITE-to-READ

T0 CLK T1 T2 T3 T4 T5

Command

WRITE

NOP

READ

NOP

Address

Bank, Col n

Bank, Col b

DIN

DOUT

Transitioning data

Dont Care

Note:

1. The WRITE command can be issued to any bank, and the READ command can be to any bank. DQM is LOW. CL = 2 for illustration.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM WRITE Operation

Figure 29: WRITE-to-PRECHARGE
T0 CLK
tWR @ tCK 15ns

DQM
tRP

Command Address

WRITE

NOP

PRECHARGE

NOP

ACTIVE

NOP

Bank a, Col n
tWR

Bank (a or all)

Bank a, Row

DIN

tWR @ tCK < 15ns

DQM
tRP

Command Address

WRITE

NOP

PRECHARGE

NOP

ACTIVE

Bank a, Col n
t WR

Bank (a or all)

Bank a, Row

DIN

Transitioning data

Dont Care

Note:

1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two.

Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command is ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 30 (page 57), where data n is the last desired data element of a longer burst.

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64Mb: x32 SDRAM WRITE Operation

Figure 30: Terminating a WRITE Burst
T0 CLK
BURST TERMINATE NEXT COMMAND

Command

WRITE

Address

Bank, Col n

Address

DIN

Data

Transitioning data

Dont Care

Note:

1. DQM is LOW.

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64Mb: x32 SDRAM WRITE Operation

Figure 31: Alternating Bank Write Accesses
T0 CLK tCKS CKE tCMS Command tCMH
NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE

tCK tCKH

tCL

T2 tCH

ACTIVE

tCMS DQM tAS Address tAH

tCMH

Row

Column m

Row

Column b

Row

tAS A10

tAH

Enable auto precharge Row

Row

tAS BA0, BA1

tAH
Bank 0 Bank 1 Bank 1 Bank 0

Bank 0

tDS DQ tRCD - bank 0 tRAS - bank 0 tRC - bank 0 tRRD

tDH
DIN

tDS

tDH
DIN

tDS

tDH
DIN

tDS

tDH
DIN

tDS

tDH
DIN

tDS

tDH
DIN

tDS

tDH
DIN

tDS

tDH
DIN

tWR - bank 0

tRP - bank 0

tRCD - bank 0 tWR - bank 1

tRCD - bank 1 Dont Care

Note:

1. For this example, BL = 4.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM WRITE Operation

Figure 32: WRITE Continuous Page Burst
T0 CLK tCKS CKE tCMS Command tCMH
NOP WRITE NOP NOP NOP

tCL

T1 tCH

tCK

(( )) (( )) (( )) (( )) (( )) (( ))

Tn + 1

Tn + 2

Tn + 3

tCKH

ACTIVE

NOP

BURST TERM

NOP

tCMS tCMH DQM

(( )) (( ))

tAS Address

tAH
Column m

Row

(( )) (( )) (( )) (( )) (( )) (( ))

tAS A10

tAH

Row

tAS BA0, BA1

tAH
Bank

Bank

tDS DQ tRCD
DIN

tDH

tDS

tDH
DIN

tDS

tDH
DIN

tDS

tDH
DIN

(( )) (( ))

tDS

tDH
DIN Full-page burst does not self-terminate. Use BURST TERMINATE command to stop.1, 2

All locations within same row

Full page completed

Dont Care

Notes:

1. tWR must be satisfied prior to issuing a PRECHARGE command. 2. Page left open; no tRP.

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64Mb: x32 SDRAM WRITE Operation

Figure 33: WRITE DQM Operation
T0 CLK tCKS CKE tCMS Command tCMH
NOP WRITE NOP NOP NOP NOP NOP

tCK tCKH

tCL

T2 tCH

ACTIVE

tCMS tCMH DQM tAS Address tAH

Column m
Enable auto precharge Disable auto precharge

Row

tAS A10

tAH

Row

tAS BA0, BA1

tAH

Bank

tDS DQ tRCD

tDH
DIN

tDS

tDH
DIN

tDS

tDH
DIN

Dont Care

Note:

1. For this example, BL = 4.

Burst Read/Single Write

The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0).

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64Mb: x32 SDRAM PRECHARGE Operation

PRECHARGE Operation
The PRECHARGE command (see Figure 11 (page 29)) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged (A10 = LOW), inputs BA0 and BA1 select the bank. When all banks are to be precharged (A10 = HIGH), inputs BA0 and BA1 are treated as Dont Care. After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.

Auto Precharge
Auto precharge is a feature that performs the same individual-bank PRECHARGE function described previously, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the continuous page burst mode where auto precharge does not apply. In the specific case of write burst mode set to single location access with burst length set to continuous, the burst length setting is the overriding setting and auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. Another command cannot be issued to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Burst Type (page 40) section. Micron SDRAM supports concurrent auto precharge; cases of concurrent auto precharge for READs and WRITEs are defined below. READ with auto precharge interrupted by a READ (with or without auto precharge) A READ to bank m will interrupt a READ on bank n following the programmed CAS latency. The precharge to bank n begins when the READ to bank m is registered (see Figure 34 (page 62)). READ with auto precharge interrupted by a WRITE (with or without auto precharge) A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The precharge to bank n begins when the WRITE to bank m is registered (see Figure 35 (page 63)). WRITE with auto precharge interrupted by a READ (with or without auto precharge) A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (see Figure 40 (page 68)). WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is reg61

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64Mb: x32 SDRAM PRECHARGE Operation

istered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (see Figure 41 (page 68)). Figure 34: READ With Auto Precharge Interrupted by a READ
T0 CLK Command Bank n
NOP READ - AP Bank n NOP READ - AP Bank m NOP NOP NOP NOP

Page active

READ with burst of 4

Interrupt burst, precharge tRP - bank n

Idle tRP - bank m Precharge

Internal states

Bank m

Page active

READ with burst of 4

Address DQ

Bank n, Col a

Bank m, Col d DOUT CL = 3 (bank n) CL = 3 (bank m) DOUT DOUT DOUT

Dont Care

Note:

1. DQM is LOW.

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64Mb: x32 SDRAM PRECHARGE Operation

Figure 35: READ With Auto Precharge Interrupted by a WRITE
T0 CLK Command Bank n
READ - AP Bank n Page active NOP NOP NOP WRITE - AP Bank m NOP NOP NOP

Internal States

READ with burst of 4

Interrupt burst, precharge tRP - bank n

Idle tWR - bankm Write-back

Bank m
Bank n, Col a

Page active

WRITE with burst of 4

Address DQM1 DQ

Bank m, Col d

DOUT

DIN

CL = 3 (bank n)

Transitioning data

Dont Care

Note:

1. DQM is HIGH at T2 to prevent DOUTa + 1 from contending with DINd at T4.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM PRECHARGE Operation

Figure 36: READ With Auto Precharge
T0 CLK tCKS CKE tCMS Command tCMH
NOP READ NOP NOP NOP NOP NOP ACTIVE

tCK tCKH

tCL

T2 tCH

ACTIVE

tCMS DQM tAS Address tAH

tCMH

Row

Column m
Enable auto precharge

Row

tAS A10

tAH

Row

tAS BA0, BA1

tAH
Bank Bank

Bank

tAC DQ tRCD tRAS tRC CL = 2 tLZ

tAC tOH
DOUT m

tAC tOH
DOUT m+1

tAC tOH
DOUT m+2

tOH
DOUT m+3

tRP

tHZ

Dont Care

Undefined

Note:

1. For this example, BL = 4 and CL = 2.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM PRECHARGE Operation

Figure 37: READ Without Auto Precharge
T0 T1 T2 tCH T3 T4 T5 T6 T7 T8

CLK
tCKS tCKH

tCK

tCL

CKE
tCMS tCMH

Command

ACTIVE

NOP

READ

NOP

PRECHARGE

NOP

ACTIVE

tCMS tCMH

DQM
tAS tAH
Row Column m Row

Address
tAS

tAH
Row

All banks Row Disable auto precharge Bank Single bank Bank(s) Bank

A10
tAS

tAH
Bank

BA0, BA1

tAC tAC tOH

DOUT

tAC tOH
DOUT

tOH
DOUT

DQ
tRCD tRAS tRC CL = 2

tLZ

tRP

tHZ

Dont Care

Undefined

Note:

1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM PRECHARGE Operation

Figure 38: Single READ With Auto Precharge
T0 CLK tCKS CKE tCMS Command tCMH
NOP READ NOP NOP NOP NOP ACTIVE

tCK tCKH

tCL

T2 tCH

ACTIVE

tCMS tCMH DQM tAS Address tAS A10 tAS BA0, BA1 tAH
Row Column m Enable auto precharge Row Row

tAH
Row

tAH
Bank Bank Bank

tAC DQ tRCD tRAS tRC CL = 2 tLZ

tOH
DOUT

tRP

Dont Care

Undefined

Note:

1. For this example, BL = 1 and CL = 2.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM PRECHARGE Operation

Figure 39: Single READ Without Auto Precharge
T0 T1 T2 tCH T3 T4 T5 T6 T7 T8

CLK
tCKS tCKH

tCK

tCL

CKE
tCMS tCMH
NOP READ NOP NOP PRECHARGE NOP ACTIVE NOP

Command

ACTIVE

tCMS tCMH

DQM
tAS tAH
Row Column m Row

Address
tAS

tAH
Row

All banks Row Disable auto precharge Bank Single bank Bank(s) Bank

A10
tAS

tAH
Bank

BA0, BA1

tAC

tOH
DOUT

DQ
tRCD tRAS tRC CL = 2

tLZ

tHZ

tRP

Dont Care Undefined

Note:

1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRECHARGE.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM PRECHARGE Operation

Figure 40: WRITE With Auto Precharge Interrupted by a READ
T0 CLK Command Bank n
NOP WRITE - AP Bank n NOP READ - AP Bank m NOP NOP NOP NOP

Internal States

Page active

WRITE with burst of 4

Interrupt burst, write-back t WR - bank n

Precharge tRP - bank n tRP - bank m

Bank m

Page active

READ with burst of 4

Address DQ

Bank n, Col a DIN DIN

Bank m, Col d DOUT DOUT

CL = 3 (bank m)

Dont Care

Note:

1. DQM is LOW.

Figure 41: WRITE With Auto Precharge Interrupted by a WRITE

T0 CLK Command Bank n
NOP WRITE - AP Bank n NOP NOP WRITE - AP Bank m NOP NOP NOP

Page active

WRITE with burst of 4

Interrupt burst, write-back tWR - bank n

Precharge tRP - bank n tWR - bank m Write-back

Internal States

Bank m

Page active

WRITE with burst of 4

Address DQ

Bank n, Col a DIN DIN DIN

Bank m, Col d DIN DIN DIN DIN

Dont Care

Note:

1. DQM is LOW.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM PRECHARGE Operation

Figure 42: WRITE With Auto Precharge
T0 CLK
tCKS tCKH

tCK

tCL

T2
tCH

CKE
tCMS tCMH
NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE

Command

ACTIVE

tCMS tCMH

DQM
tAS tAH

Address

Row
tAS tAH

Column m
Enable auto precharge

Row

A10

Row
tAS tAH

Row

BA0, BA1

Bank

Bank
tDS tDH tDS tDH tDS tDH tDS tDH

Bank

DQ
tRCD tRAS tRC

DIN

DIN
tWR tRP

Dont Care

Note:

1. For this example, BL = 4.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM PRECHARGE Operation

Figure 43: WRITE Without Auto Precharge
T0 T1 T2 tCH T3 T4 T5 T6 T7 T8 T9

CLK
tCKS tCKH

tCK

tCL

CKE
tCMS tCMH
NOP WRITE NOP NOP NOP NOP PRECHARGE NOP ACTIVE

Command

ACTIVE

tCMS tCMH

DQM
tAS tAH

Address

Row
tAS tAH

Column m
All banks

Row

A10

Row
tAS tAH
Disable auto precharge Single bank Bank

Row

BA0, BA1

Bank

Bank
tDS tDH tDS tDH tDS tDH tDS tDH

Bank

DQ
tRCD tRAS tRC

DIN

DIN
tWR tRP

Dont Care

Note:

1. For this example, BL = 4 and the WRITE burst is followed by a manual PRECHARGE.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM PRECHARGE Operation

Figure 44: Single WRITE With Auto Precharge
T0 T1 T2 tCH T3 T4 T5 T6 T7 T8

CLK
tCKS tCKH

tCK

tCL

CKE
tCMS tCMH
NOP WRITE NOP NOP NOP NOP ACTIVE NOP

Command

ACTIVE

tCMS tCMH

DQM
tAS tAH
Column m Row

Address

Row

tAS

tAH

Enable auto precharge

A10

Row

tAS

tAH
Bank Bank

BA0, BA1

Bank

tDS

tDH
DIN

DQ
tRCD tRAS tRC

tWR

tRP

Dont Care

Note:

1. For this example, BL = 1.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM PRECHARGE Operation

Figure 45: Single WRITE Without Auto Precharge
T0 T1 T2 tCH T3 T4 T5 T6 T7 T8

CLK
tCKS tCKH

tCK

tCL

CKE
tCMS tCMH
NOP WRITE NOP NOP PRECHARGE NOP ACTIVE NOP

Command

ACTIVE

tCMS tCMH

DQM
tAS tAH
Row Column m
All banks

Address
tAS

tAH
Row

A10
tAS

Row
Disable auto precharge Single bank

tAH

BA0, BA1

Bank

tDS

tDH

DQ
tRCD tRAS tRC

DIN

tWR

tRP

Dont Care

Note:

1. For this example, BL = 1 and the WRITE burst is followed by a manual PRECHARGE.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM AUTO REFRESH Operation

AUTO REFRESH Operation

The AUTO REFRESH command is used during normal operation of the device to refresh the contents of the array. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be precharged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP is met following the PRECHARGE command. Addressing is generated by the internal refresh controller. This makes the address bits Dont Care during an AUTO REFRESH command. After the AUTO REFRESH command is initiated, it must not be interrupted by any executable command until tRFC has been met. During tRFC time, COMMAND INHIBIT or NOP commands must be issued on each positive edge of the clock. The SDRAM requires that every row be refreshed each tREF period. Providing a distributed AUTO REFRESH commandcalculated by dividing the refresh period (tREF) by the number of rows to be refreshedmeets the timing requirement and ensures that each row is refreshed. Alternatively, to satisfy the refresh requirement a burst refresh can be employed after every tREF period by issuing consecutive AUTO REFRESH commands for the number of rows to be refreshed at the minimum cycle rate (tRFC).

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM AUTO REFRESH Operation

Figure 46: Auto Refresh Mode
T0 CLK
tCK

T2
tCH

(( )) (( ))
(( ))

tCL

Tn + 1

(( )) (( ))
(( ))

To + 1

CKE
tCKS tCMS tCKH tCMH
NOP AUTO REFRESH NOP

Command

PRECHARGE

(( )) ( ( NOP )) (( )) (( ))
(( )) (( ))

AUTO REFRESH

NOP

(( )) ( ( NOP )) (( )) (( ))
(( )) (( )) (( )) (( ))

ACTIVE

DQM

Address
All banks

Row

A10
Single bank tAS tAH

(( )) (( ))

Row

BA0, BA1

Bank(s)

(( )) (( ))
(( )) tRP tRFC tRFC

(( )) (( ))
(( ))

Bank

DQ High-Z

Precharge all active banks

Dont Care

Note:

1. Back-to-back AUTO REFRESH commands are not required.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM SELF REFRESH Operation

SELF REFRESH Operation

The self refresh mode can be used to retain data in the device, even when the rest of the system is powered down. When in self refresh mode, the device retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command, except CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the device become Dont Care with the exception of CKE, which must remain LOW. After self refresh mode is engaged, the device provides its own internal clocking, enabling it to perform its own AUTO REFRESH cycles. The device must remain in self refresh mode for a minimum period equal to tRAS and remains in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH. (Stable clock is defined as a signal cycling within timing constraints specified for the clock ball.) After CKE is HIGH, the device must have NOP commands issued for a minimum of two clocks for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued according to the distributed refresh rate (tREF/refresh row count) as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM SELF REFRESH Operation

Figure 47: Self Refresh Mode
T0 CLK tCK T1 tCH T2 Tn + 1 To + 1 To + 2

tCL

tCKS

(( )) (( ))

(( )) (( )) (( )) (( ))

CKE tCKS tCMS Command tCKH tCMH

NOP AUTO REFRESH

(( ))

PRECHARGE

(( )) (( )) (( )) (( )) (( )) (( ))

NOP ( (

(( ))

))

AUTO REFRESH

DQM

(( )) (( )) (( )) (( )) (( )) (( ))

Address
All banks

A10
Single bank

(( )) (( ))

tAS BA0, BA1

tAH

Bank(s)

(( )) (( ))

High-Z tRP
Precharge all active banks Enter self refresh mode

(( ))

tXSR

Exit self refresh mode (Restart refresh time base)

CLK stable prior to exiting self refresh mode

Dont Care

Note:

1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not required.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Power-Down

Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device cannot remain in the power-down state longer than the refresh period (64ms) because no REFRESH operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE HIGH at the desired clock edge (meeting tCKS). Figure 48: Power-Down Mode
T0 CLK T1 T2 tCH Tn + 1 tCKS Tn + 2

tCK

tCL

tCKS CKE tCKS tCKH

(( )) (( ))

(( ))

tCMS tCMH Command

PRECHARGE NOP NOP

(( )) (( )) (( )) (( )) (( )) (( ))

NOP

ACTIVE

DQM

Address
All banks

Row

A10
Single bank

(( )) (( ))

Row

tAS BA0, BA1

tAH

Bank(s)

(( )) (( ))
(( ))

Bank

High-Z

Two clock cycles Precharge all active banks All banks idle, enter power-down mode

Input buffers gated off while in power-down mode Exit power-down mode

All banks idle

Dont Care

Note:

1. Violating refresh requirements during power-down may result in a loss of data.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Clock Suspend

Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input balls when an internal clock edge is suspended will be ignored; any data present on the DQ balls remains driven; and burst counters are not incremented, as long as the clock is suspended. Exit clock suspend mode by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. Figure 49: Clock Suspend During WRITE Burst
T0 CLK T1 T2 T3 T4 T5

CKE

Internal clock

Command

NOP

WRITE

NOP

Address

Bank, Col n

DIN

Dont Care

Note:

1. For this example, BL = 4 or greater, and DQM is LOW.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Clock Suspend

Figure 50: Clock Suspend During READ Burst
T0 CLK T1 T2 T3 T4 T5 T6

CKE

Internal clock Command

READ

NOP

Address

Bank, Col n

DOUT

Dont Care

Note:

1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.

PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

64Mb: x32 SDRAM Clock Suspend

Figure 51: Clock Suspend Mode
T0 T1 T2 tCH tCKH T3 T4 T5 T6 T7 T8 T9

CLK

tCK

tCL tCKS

CKE
tCKS tCKH tCMS tCMH NOP tCMS tCMH NOP NOP NOP NOP WRITE NOP

Command

READ

DQM
tAS tAH Column e

Address

Column m tAS tAH

A10
tAS tAH Bank tAC tAC tOH DOUT tHZ DOUT tDS tDH DIN DIN Bank

BA0, BA1

tLZ

Dont Care

Undefined

Note:

1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef811ce1fe 64mb_x32_sdram.pdf - Rev. U 03/14 EN

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