512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM

Features

DDR SDRAM UDIMM

MT16VDDT6464A – 512MB
MT16VDDT12864A – 1GB
MT16VDDT25664A – 2GB
For component data sheets, refer to Micron’s Web site: www.micron.com

Features Figure 1: 184-Pin UDIMM (MO-206 R/C B)

• 184-pin, unbuffered dual in-line memory module
(UDIMM) PCB height: 31.75mm (1.25in)
• Fast data transfer rates: PC-2100, PC-2700,
or PC-3200
• 512MB (64 Meg x 64), 1GB (128 Meg x 64),
or 2GB (256 Meg x 64)
• VDD = VDDQ = +2.5V
(-40B: VDD = VDDQ = +2.6V)
• VDDSPD = +2.3V to +3.6V Options Marking
• 2.5V I/O (SSTL_2-compatible) • Operating temperature1
• Internal, pipelined double data rate (DDR) – Commercial (0°C ≤ TA ≤ +70°C) None
2n-prefetch architecture – Industrial (–40°C ≤ TA ≤ +85°C) I
• Bidirectional data strobe (DQS) transmitted/ • Package
received with data—that is, source-synchronous – 200-pin DIMM (standard) G
data capture – 200-pin DIMM (Pb-free) Y
• Differential clock inputs (CK and CK#) • Memory clock, speed, CAS latency
• Multiple internal device banks for concurrent – 5.0ns (200 MHz), 400 MT/s, CL = 3 -40B
operation – 6.0ns (167 MHz), 333 MT/s, CL = 2.5 -335
• Dual rank – 7.5ns (133 MHz), 266 MT/s, CL = 22 -262
• Selectable burst lengths (BL): 2, 4, or 8 – 7.5ns (133 MHz), 266 MT/s, CL = 22 -26A
• Auto precharge option – 7.5ns (133 MHz), 266 MT/s, CL = 2.52 -265
• Auto refresh and self refresh modes: 7.8125µs
1. Contact Micron for industrial temperature
maximum average periodic refresh interval
module offerings.
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum 2. Not recommended for new designs.
compatibility
• Gold edge contacts

Table 1: Key Timing Parameters

Data Rate (MT/s) tRCD tRP tRC
Speed Industry
Grade Nomenclature CL = 3 CL = 2.5 CL = 2 (ns) (ns) (ns) Notes
-40B PC3200 400 333 266 15 15 55
-335 PC2700 – 333 266 18 18 60 1
-262 PC2100 – 266 266 15 15 60
-26A PC2100 – 266 266 20 20 65
-265 PC2100 – 266 200 20 20 65

Notes: 1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications;
actual DDR SDRAM device specifications are 15ns.

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Products and specifications discussed herein are subject to change by Micron without notice.
 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Features

Table 2: Addressing

Parameter 512MB 1GB 2GB

Refresh count 8K 8K 8K
Row address 8K (A0–A12) 8K (A0–A12) 16K (A0–A13)
Device bank address 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Device configuration 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) 1Gb (128 Meg x 8)
Column address 1K (A0–A9) 2K (A0–A9, A11) 2K (A0–A9, A11)
Module rank address 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#)

Table 3: Part Numbers and Timing Parameters – 512MB Modules

Base device: MT46V32M8,1 256Mb DDR SDRAM

Module Module Memory Clock/ Clock Cycles

Part Number2 Density Configuration Bandwidth Data Rate (CL-tRCD-tRP)
MT16VDDT6464AG-40B__ 512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3
MT16VDDT6464AY-40B__ 512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3
MT16VDDT6464AG-335__ 512MB 64 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3
MT16VDDT6464AY-335__ 512MB 64 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3
MT16VDDT6464AG-262__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT16VDDT6464AG-26A__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT16VDDT6464AG-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
MT16VDDT6464AY-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

Table 4: Part Numbers and Timing Parameters – 1GB Modules

Base device: MT46V64M8,1 512Mb DDR SDRAM

Module Module Memory Clock/ Clock Cycles

Part Number2 Density Configuration Bandwidth Data Rate (CL-tRCD-tRP)
MT16VDDT12864AG-40B__ 1GB 128 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3
MT16VDDT12864AY-40B__ 1GB 128 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3
MT16VDDT12864AG-335__ 1GB 128 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3
MT16VDDT12864AY-335__ 1GB 128 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3
MT16VDDT12864AG-262__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT16VDDT12864AG-265__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
MT16VDDT12864AY-265__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

Notes: 1. The data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT16VDDT6464AY-40BG4.

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 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Features

Table 5: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT46V128M8,1 1Gb DDR SDRAM

Module Module Memory Clock/ Clock Cycles

Part Number2 Density Configuration Bandwidth Data Rate (CL-tRCD-tRP)
MT16VDDT25664AG-335__ 2GB 256 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3
MT16VDDT25664AY-335__ 2GB 256 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3
MT16VDDT25664AG-265__ 2GB 256 Meg x 64 2.71 GB/s 7.5ns/333 MT/s 2.5-3-3
MT16VDDT25664AY-265__ 2GB 256 Meg x 64 2.71 GB/s 7.5ns/333 MT/s 2.5-3-3

Notes: 1. The data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT16VDDT6464AY-40BG4.

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 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Pin Assignments and Descriptions

Pin Assignments and Descriptions

Table 6: Pin Assignments
184-Pin DDR UDIMM Front 184-Pin DDR UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VREF 24 DQ17 47 NC 70 VDD 93 VSS 116 VSS 139 VSS 162 DQ47
2 DQ0 25 DQS2 48 A0 71 NC 94 DQ4 117 DQ21 140 NC 163 NC
3 VSS 26 VSS 49 NC 72 DQ48 95 DQ5 118 A11 141 A10 164 VDDQ
4 DQ1 27 A9 50 VSS 73 DQ49 96 VDDQ 119 DM2 142 NC 165 DQ52
5 DQS0 28 DQ18 51 NC 74 VSS 97 DM0 120 VDD 143 VDDQ 166 DQ53
6 DQ2 29 A7 52 BA1 75 CK2# 98 DQ6 121 DQ22 144 NC 1671 NC/A13
7 VDD 30 VDDQ 53 DQ32 76 CK2 99 DQ7 122 A8 145 VSS 168 VDD
8 DQ3 31 DQ19 54 VDDQ 77 VDDQ 100 VSS 123 DQ23 146 DQ36 169 DM6
9 NC 32 A5 55 DQ33 78 DQS6 101 NC 124 VSS 147 DQ37 170 DQ54
10 NC 33 DQ24 56 DQS4 79 DQ50 102 NC 125 A6 148 VDD 171 DQ55
11 VSS 34 VSS 57 DQ34 80 DQ51 103 NC 126 DQ28 149 DM4 172 VDDQ
12 DQ8 35 DQ25 58 VSS 81 VSS 104 VDDQ 127 DQ29 150 DQ38 173 NC
13 DQ9 36 DQS3 59 BA0 82 NC 105 DQ12 128 VDDQ 151 DQ39 174 DQ60
14 DQS1 37 A4 60 DQ35 83 DQ56 106 DQ13 129 DM3 152 VSS 175 DQ61
15 VDDQ 38 VDD 61 DQ40 84 DQ57 107 DM1 130 A3 153 DQ44 176 VSS
16 CK1 39 DQ26 62 VDDQ 85 VDD 108 VDD 131 DQ30 154 RAS# 177 DM7
17 CK1# 40 DQ27 63 WE# 86 DQS7 109 DQ14 132 VSS 155 DQ45 178 DQ62
18 VSS 41 A2 64 DQ41 87 DQ58 110 DQ15 133 DQ31 156 VDDQ 179 DQ63
19 DQ10 42 VSS 65 CAS# 88 DQ59 111 CKE1 134 NC 157 S0# 180 VDDQ
20 DQ11 43 A1 66 VSS 89 VSS 112 VDDQ 135 NC 158 S1# 181 SA0
21 CKE0 44 NC 67 DQS5 90 NC 113 NC 136 VDDQ 159 DM5 182 SA1
22 VDDQ 45 NC 68 DQ42 91 SDA 114 DQ20 137 CK0 160 VSS 183 SA2
23 DQ16 46 VDD 69 DQ43 92 SCL 115 A12 138 CK0# 161 DQ46 184 VDDSPD
Notes: 1. Pin 167 is NC for 512MB and 1GB or A13 for 2GB.

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 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Pin Assignments and Descriptions

Table 7: Pin Descriptions

Symbol Type Description

A0–A13 Input Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0 and BA1) or all device banks (A10 HIGH). The address inputs also provide
the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command. A0–A12 (512MB and1GB) and A0–A13 (2GB).
BA0, BA1 Input Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied.
CK0, CK0#, Input Clock: CK and CK# are differential clock inputs. All control, command, and address input
CK1, CK1#, signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK2, CK2# CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#.
CKE0, CKE1 Input Clock enable: CKE enables (registered HIGH) and CKE disables (registered LOW) the
internal clock, input buffers, and output drivers.
DM0–DM7 Input Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with that input data, during a write access. DM is sampled on
both edges of DQS. Although the DM pins are input-only, the DM loading is designed to
match that of the DQ and DQS pins.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
S0#, S1# Input Chip selects: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
SA0–SA2 Input Presence-detect address inputs: These pins are used to configure the SPD EEPROM
address range on the I2C bus.
SCL Input Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect data
transfer to and from the module.
DQ0–DQ63 I/O Data input/output: Data bus.
DQS0–DQS7 I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data.
Center-aligned with write data. Used to capture data.
SDA I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of
the presence-detect portion of the module.
VDD/VDDQ Supply Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
VDDSPD Supply SPD EEPROM power supply: +2.3V to +3.6V.
VREF Supply SSTL_2 reference voltage (VDD/2).
VSS Supply Ground.
NC – No connect: These pins are not connected on the module.

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 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Functional Block Diagram

Functional Block Diagram

Figure 2: Functional Block Diagram

S1#
S0#
DQS0 DQS4
DM0 DM4
DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS
DQ0 DQ DQ DQ32 DQ DQ
DQ1 DQ DQ DQ33 DQ DQ
DQ2 DQ DQ DQ34 DQ DQ
DQ3 DQ U1 DQ U18 DQ35 DQ U5 DQ U14
DQ4 DQ DQ DQ36 DQ DQ
DQ5 DQ DQ DQ37 DQ DQ
DQ6 DQ DQ DQ38 DQ DQ
DQ7 DQ DQ DQ39 DQ DQ
DQS1 DQS5
DM1 DM5
DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS
DQ8 DQ DQ DQ40 DQ DQ
DQ9 DQ DQ DQ41 DQ DQ
DQ10 DQ DQ DQ42 DQ DQ
DQ11 DQ U2 DQ U17 DQ43 DQ U6 DQ U13
DQ12 DQ DQ DQ44 DQ DQ
DQ13 DQ DQ DQ45 DQ DQ
DQ14 DQ DQ DQ46 DQ DQ
DQ15 DQ DQ DQ47 DQ DQ
DQS2 DQS6
DM2 DM6
DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS
DQ16 DQ DQ DQ48 DQ DQ
DQ17 DQ DQ DQ49 DQ DQ
DQ18 DQ DQ DQ50 DQ DQ
DQ19 DQ U3 DQ U16 DQ51 DQ U7 DQ U12
DQ20 DQ DQ DQ52 DQ DQ
DQ21 DQ DQ DQ53 DQ DQ
DQ22 DQ DQ DQ54 DQ DQ
DQ23 DQ DQ DQ55 DQ DQ
DQS3 DQS7
DM3 DM7
DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS
DQ24 DQ DQ DQ56 DQ DQ
DQ25 DQ DQ DQ57 DQ DQ
DQ26 DQ DQ DQ58 DQ DQ
DQ27 DQ U4 DQ U15 DQ59 DQ U8 DQ U11
DQ28 DQ DQ DQ60 DQ DQ
DQ29 DQ DQ DQ61 DQ DQ
DQ30 DQ DQ DQ62 DQ DQ
DQ31 DQ DQ DQ63 DQ DQ

BA0, BA1 BA0, BA1: DDR SDRAM CK0 U4, U5,

CK0# U14, U15
A0–A13 A0–A13: DDR SDRAM
RAS# RAS#: DDR SDRAM
CAS# CAS#: DDR SDRAM CK1 U1–U3,
WE# WE#: DDR SDRAM CK1# U16–U18
CKE1 CKE0: DDR SDRAM U1, U3, U6, U8, U11, U13, U14, U16
CKE0 CKE1: DDR SDRAM U2, U4, U5, U7, U10, U12, U15, U17 CK2
U6–U8,
CK2#
U11–U13
VDDSPD SPD/EEPROM
VDDQ DDR SDRAM U19
SPD/EEPROM
VDD DDR SDRAM SCL SDA
WP A0 A1 A2
VREF DDR SDRAM
VSS SA0 SA1 SA2
VSS DDR SDRAM

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 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
General Description

General Description
The MT16VDDT6464A, MT16VDDT12864A, and MT16VDDT25664A are high-speed,
CMOS dynamic random access 512MB, 1GB, and 2GB memory modules organized in a
x64 configuration. These modules use DDR SDRAM devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Control, command, and address signals are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.

Serial Presence-Detect Operation

These DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored
in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the
module type and various DDR SDRAM organizations and timing parameters. The
remaining 128 bytes of storage are available for use by the customer. System READ/
WRITE operations between the master (system logic) and the slave EEPROM device
occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA[2:0], which provide eight unique DIMM/EEPROM addresses. Write
protect (WP) is connected to VSS, permanently disabling hardware write protect.

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 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications

Electrical Specifications
Stresses greater than those listed in Table 8 may cause permanent damage to the
module. This is a stress rating only, and functional operation of the module at these or
any other conditions outside those indicated in each device’s data sheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may adversely
affect reliability.

Table 8: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD/VDDQ VDD/VDDQ supply voltage relative to VSS –1.0 +3.6 V
VIN, VOUT Voltage on any pin relative to VSS –0.5 +3.2 V
II Input leakage current; Any input 0V ≤ VIN ≤ VDD; Address inputs, –32 +32 µA
VREF input 0V ≤ VIN ≤ 1.35V (All other pins not under RAS#, CAS#, WE#, BA
test = 0V) S#, CKE 16 16
CK0, CK0# –8 +8
CK1, CK1#, CK2, CK2# –12 +12
DM –4 +4
IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are DQ, DQS –10 +10 µA
disabled
TA DRAM ambient operating temperature1 Commercial 0 +70 °C
Industrial –40 +85 °C

Notes: 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available
on Micron’s Web site.

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 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications

DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades
correlate with component speed grades, as shown in Table 9.

Table 9: Module and Component Speed Grades

DDR components may exceed the listed module speed grades

Module Speed Grade Component Speed Grade

-40B -5B
-335 -6
-262 -75E
-26A -75Z
-265 -75

Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully
designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system’s
memory bus to ensure adequate signal integrity of the entire memory system.

Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to
ensure the required supply voltage is maintained.

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 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications

IDD Specifications
Table 10: IDD Specifications and Conditions – 512MB (Die Revision K)
Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet

Parameter/Condition Symbol -40B -335 Units

t t t t 1
Operating one bank active-precharge current: RC = RC (MIN); CK = CK IDD0 832 752 mA
(MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN); IDD11 992 952 mA
t
CK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock
cycle
Precharge power-down standby current: All device banks idle; Power-down IDD2P2 64 64 mA
mode; tCK = tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); IDD2F2 800 800 mA
CKE = HIGH; Address and other control inputs changing once per clock cycle;
VIN = VREF for DQ, DM, and DQS
Active power-down standby current: One device bank active; Power-down IDD3P2 560 480 mA
mode; tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = IDD3N2 960 880 mA
tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock

cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device bank IDD4R1 1,472 1,132 mA
active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN);
IOUT = 0mA
Operating burst write current: BL = 2; Continuous burst writes; One device IDD4W1 1,472 1,312 mA
bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
tREFC
Auto refresh current = tRFC (MIN) IDD52 2,560 2,560 mA
tREFC
= 7.8125µs IDD5A2 96 96 mA
Self refresh current: CKE ≤ 0.2V IDD62 64 64 mA
Operating bank interleave read current: Four device bank interleaving reads IDD71 2,352 2,192 mA
(BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and
control inputs change only during active READ or WRITE commands
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks in
IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.

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 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications

Table 11: IDD Specifications and Conditions – 512MB (All Other Die Revisions)
Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet

-26A/
Parameter/Condition Symbol -40B -335 -262 -265 Units
t t 1
Operating one bank active-precharge current: RC = RC (MIN); IDD0 1,112 1,032 1,032 992 mA
t
CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2; IDD11 1,392 1,392 1,312 1,192 mA
t
RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control
inputs changing once per clock cycle
Precharge power-down standby current: All device banks idle; IDD2P2 64 64 64 64 mA
Power-down mode; tCK = tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All device banks idle; IDD2F2 960 800 720 720 mA
tCK
= tCK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ, DM, and DQS
Active power-down standby current: One device bank active; IDD3P2 640 480 400 400/ mA
Power-down mode; tCK = tCK (MIN); CKE = LOW 480
Active standby current: CS# = HIGH; CKE = HIGH; One device bank IDD3N2 1,120 960 800 800 mA
active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; IDD4R1 1,632 1,432 1,232 1,232 mA
One device bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); IOUT = 0mA
Operating burst write current: BL = 2; Continuous burst writes; IDD4W1 1,592 1,432 1,232 1,232 mA
One device bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle
tREFC
Auto refresh current = tRFC (MIN) IDD52 4,160 4,080 3,760 3,760/ mA
3,920
tREFC
= 7.8125µs IDD5A2 96 96 96 96 mA
Self refresh current: CKE ≤ 0.2V IDD62 64 64 64 64 mA
Operating bank interleave read current: Four device bank IDD71 3,792 3,312 2,832 2,832/ mA
interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); 2,952
tCK = tCK (MIN); Address and control inputs change only during active

READ or WRITE commands

Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks in
IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.

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 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications

Table 12: IDD Specifications and Conditions – 1GB

Values are for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet

-26A/
Parameter/Condition Symbol -40B -335 -262 -265 Units
t t 1
Operating one bank active-precharge current: RC = RC (MIN); IDD0 1,280 1,080 1,080 960 mA
t
CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2; IDD11 1,520 1,320 1,320 1,200 mA
t
RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control
inputs changing once per clock cycle
Precharge power-down standby current: All device banks idle; IDD2P2 80 80 80 80 mA
Power-down mode; tCK = tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All device banks idle; IDD2F2 880 720 720 640 mA
tCK
= tCK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ, DM, and DQS
Active power-down standby current: One device bank active; IDD3P2 720 560 560 480 mA
Power-down mode; tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One device bank IDD3N2 960 800 800 720 mA
active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; IDD4R1 1,560 1,360 1,360 1,200 mA
One device bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); IOUT = 0mA
Operating burst write current: BL = 2; Continuous burst writes; IDD4W1 1,600 1,440 1,280 1,120 mA
One device bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle
tREFC
Auto refresh current = tRFC (MIN) IDD52 5,520 4,640 4,640 4,480 mA
tREFC
= 7.8125µs IDD5A2 176 160 160 160 mA
Self refresh current: CKE ≤ 0.2V IDD62 80 80 80 80 mA
Operating bank interleave read current: Four device bank IDD71 3,640 3,280 3,240 2,840 mA
interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN);
tCK = tCK (MIN); Address and control inputs change only during active

READ or WRITE commands

Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks in
IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.

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DD16C64_128_256x64A.fm - Rev. E 8/08 EN 12 ©2004 Micron Technology, Inc. All rights reserved
 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications

Table 13: IDD Specifications and Conditions – 2GB

Values are for the MT46V128M8 DDR SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet

Parameter/Condition Symbol -335 -265 Units

t t 1
Operating one bank active-precharge current: RC = RC (MIN); IDD0 1,360 1,240 mA
t
CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2; IDD11 1,640 1,520 mA
t
RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-down IDD2P2 160 160 mA
mode; tCK = tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); IDD2F2 1,040 960 mA
CKE = HIGH; Address and other control inputs changing once per clock cycle;
VIN = VREF for DQ, DM, and DQS
Active power-down standby current: One device bank active; Power-down IDD3P2 560 480 mA
mode; tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; IDD3N2 800 720 mA
tRC
= tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per
clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device IDD4R1 1,840 1,680 mA
bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); IOUT = 0mA

Operating burst write current: BL = 2; Continuous burst writes; One device IDD4W1 1,920 1,760 mA
bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
tREFC
Auto refresh current = tRFC (MIN) IDD52 5,440 5,280 mA
tREFC
= 7.8125µs IDD5A2 160 160 mA
Self refresh current: CKE ≤ 0.2V IDD62 144 144 mA
Operating bank interleave read current: Four device bank interleaving IDD71 4,280 3,960 mA
reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address
and control inputs change only during active READ or WRITE commands
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks in
IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.

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DD16C64_128_256x64A.fm - Rev. E 8/08 EN 13 ©2004 Micron Technology, Inc. All rights reserved
 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Serial Presence-Detect

Serial Presence-Detect
Table 14: Serial Presence-Detect EEPROM DC Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 2.3 3.6 V
Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: Logic 0; All inputs VIL –1.0 VDDSPD × 0.3 V
Output low voltage: IOUT = 3mA VOL – 0.4 V
Input leakage current: VIN = GND to VDD ILI – 10 µA
Output leakage current: VOUT = GND to VDD ILO – 10 µA
Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD ISB – 30 µA
Power supply current: SCL clock frequency = 100 kHz ICC – 2.0 mA

Table 15: Serial Presence-Detect EEPROM AC Operating Conditions

Parameter/Condition Symbol Min Max Units Notes

SCL LOW to SDA data-out valid tAA
0.2 0.9 µs 1
Time the bus must be free before a new transition can start tBUF
1.3 – µs
Data-out hold time tDH
200 – ns
tF
SDA fall time – 300 ns 2
SDA rise time tR
– 300 ns 2
Data-in hold time tHD:DAT
0 – µs
tH:STA
Start condition hold time 0.6 – µs
Clock HIGH period tHIGH
0.6 – µs
Noise suppression time constant at SCL, SDA inputs tI
– 50 ns
tLOW
Clock LOW period 1.3 – µs
SCL clock frequency fSCL
– 400 kHz
Data-in setup time tSU:DAT
100 – ns
tSU:STA
Start condition setup time 0.6 – µs 3
Stop condition setup time tSU:STO 0.6 – µs
WRITE cycle time tWRC
– 10 ms 4

Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.

Serial Presence-Detect Data

For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.

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 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Module Dimensions

Module Dimensions
Figure 3: 184-Pin DDR UDIMM

4.0 (0.157)
Front view MAX
133.50 (5.256)
133.20 (5.244)

2.0 (0.079) R
(4X)
U1 U2 U3 U4 U5 U6 U7 U8
31.9 (1.256)
31.6 (1.244)

2.5 (0.098) D 17.78 (0.7)

(2X) TYP

2.3 (0.091) TYP

0.9 (0.035) R 1.37 (0.054)
Pin 1 1.17 (0.046)
6.35 (0.25) TYP Pin 92
2.2 (0.87) 1.27 (0.05) 1.02 (0.04)
TYP TYP TYP

120.65 (4.75)
TYP

Back view
U10

U11 U12 U13 U14 U15 U16 U17 U18

10.0 (0.394)
TYP

Pin 184 Pin 93 3.8 (0.15)

TYP
49.53 (1.95) 64.77 (2.55)
TYP TYP

73.3 (2.89)
TYP

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for addi-
tional design dimensions.

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prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respec-
tive owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although
considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

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DD16C64_128_256x64A.fm - Rev. E 8/08 EN 15 ©2004 Micron Technology, Inc. All rights reserved.