32GB DDR5 RDIMM ECC Memory Specs
32GB DDR5 RDIMM ECC Memory Specs
Features
• 288-pin, DDR5 registered dual in-line memory                                         U11       U12      U13    U14   U15                    U16   U17   U18    U19      U20
  module (DDR5 RDIMM)
• Fast data transfer rate: PC5-4800
                                                                                                                         Secondary side
• 32GB (4Gig x 80)
• Dual-rank                                                                      Options                                                                         Marking
• 32 internal banks; 8 groups of 4 banks each                                    • Operating temperature
                                                                                   – Commercial (0°C ≤ TOPER ≤ 95°C)                                                           C
                                                                                 • Frequency/CAS latency
                                                                                   – 0.416ns @ CL = 40 (DDR5-4800)                                                            48B
Table 1: Addressing
 Parameter                                                                                                              32GB
 Row     address1                                                                                                 64K (R0-R15)
Notes: 1. These parameters represent the logical address state of the CA bus for different commands. Refer to the command
          truth table in the component data sheet.
Notes: 1. The data sheet for the base device can be found on micron.com.
CCM005-802248454-9
mtc20f2085s1rc_drx8_3112_rdimm.pdf - Rev. E 08/2021
                                                                             1         Micron Technology, Inc. reserves the right to change products or specifications without notice.
                                                                                                                                   © 2020 Micron Technology, Inc. All rights reserved.
                         Products and specifications discussed herein are subject to change by Micron without notice.
CCM005-802248454-9
mtc20f2085s1rc_drx8_3112_rdimm.pdf - Rev. E 08/2021
                                                          2         Micron Technology, Inc. reserves the right to change products or specifications without notice.
                                                                                                                © 2020 Micron Technology, Inc. All rights reserved.
                                                                               32GB (x80, ECC, DR) 288-Pin DDR5 RDIMM
                                                                                                               DQ Map
DQ Map
CCM005-802248454-9
mtc20f2085s1rc_drx8_3112_rdimm.pdf - Rev. E 08/2021
                                                                               3           Micron Technology, Inc. reserves the right to change products or specifications without notice.
                                                                                                                                       © 2020 Micron Technology, Inc. All rights reserved.
                                                                               32GB (x80, ECC, DR) 288-Pin DDR5 RDIMM
                                                                                                               DQ Map
CCM005-802248454-9
mtc20f2085s1rc_drx8_3112_rdimm.pdf - Rev. E 08/2021
                                                                               4         Micron Technology, Inc. reserves the right to change products or specifications without notice.
                                                                                                                                     © 2020 Micron Technology, Inc. All rights reserved.
                                                                               32GB (x80, ECC, DR) 288-Pin DDR5 RDIMM
                                                                                                               DQ Map
CCM005-802248454-9
mtc20f2085s1rc_drx8_3112_rdimm.pdf - Rev. E 08/2021
                                                                               5         Micron Technology, Inc. reserves the right to change products or specifications without notice.
                                                                                                                                     © 2020 Micron Technology, Inc. All rights reserved.
                                                              32GB (x80, ECC, DR) 288-Pin DDR5 RDIMM
                                                                                     IDD Specifications
IDD Specifications
Table 4: DDR5 IDD Specifications and Conditions – 32GB (Die Revision A)
Module IDD is based on PMIC VIN_BULK 12V input current and typical operating range of temperature. Each IDD parameter
includes PMIC efficiency, RCD current and all DRAM current on all supplies (VDD, VDDQ, and VPP).
Notes: 1. One module rank in this IDD/IDDQ/IPP condition, the other rank in IDD2N/IDDQ2N/IPP2N.
       2. Both ranks in this IDD/IDDQ/IPP condition.
CCM005-802248454-9
mtc20f2085s1rc_drx8_3112_rdimm.pdf - Rev. E 08/2021
                                                             6         Micron Technology, Inc. reserves the right to change products or specifications without notice.
                                                                                                                   © 2020 Micron Technology, Inc. All rights reserved.
                                                                                                      32GB (x80, ECC, DR) 288-Pin DDR5 RDIMM
                                                                                                                      Functional Block Diagram
                   CS_n DQS_t DQS_c           CS_n DQS_t DQS_c                    CS_n DQS_t DQS_c         CS_n DQS_t DQS_c
                                                                                                                                                                    &
                                                                                                                                                                                    Q[D:A]CK[A:B]_c
 DQ[23:16]A        DQ[7:0]                    DQ[7:0]               DQ[23:16]B    DQ[7:0]                  DQ[7:0]                                  CK_c             P
         Vss       ZQ        U3       Vss     ZQ        U18                 Vss   ZQ        U9       Vss   ZQ        U12                            CK_t
                                                                                                                                                                     S              Q[D:A]CK[A:B]_t
   DQS3A_t                                                            DQS3B_t                                                                                        C
   DQS3A_c                                                            DQS3B_c
                                                                                                                                           RESET_n                                     QRST[B:A]
                   CS_n DQS_t DQS_c           CS_n DQS_t DQS_c                    CS_n DQS_t DQS_c         CS_n DQS_t DQS_c                                              ZQ
 DQ[31:24]A        DQ[7:0]                    DQ[7:0]               DQ[31:24]B    DQ[7:0]                  DQ[7:0]
                                                                                                                                                                              VSS
         Vss       ZQ        U4       Vss     ZQ        U17                 Vss   ZQ        U10      Vss   ZQ        U11
   DQS4A_t                                                            DQS4B_t
   DQS4A_c                                                            DQS4B_c
                                                                                                                                     VIN_BULK
                   CS_n DQS_t DQS_c           CS_n DQS_t DQS_c                    CS_n DQS_t DQS_c         CS_n DQS_t DQS_c
                                                                                                                                    VIN_MGMT                                                  Output Rail A and B (VDD=1.1V)
    CB[7:0]A       DQ[7:0]                    DQ[7:0]                  CB[7:0]B   DQ[7:0]                  DQ[7:0]                      PCAMP                Power Managment
         Vss       ZQ        U5       Vss     ZQ        U16                 Vss   ZQ        U6       Vss   ZQ        U15                   LSCL               Intigrated Circuit              Output Rail C (VDDQ=1.1V)
                                                                                                                                          LSDA
                                                                                                                                                                    (PMIC)                    Output Rail D (VPP=1.8V)
                                                                                                                                  1.0V LDO output
                                                                                                                                  1.8V LDO output
                                                                                                                                                             AGND                     PGND
Vss Vss
Notes: 1. The ZQ ball on each DDR5 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is
          used for the calibration of the component’s ODT and output driver.
       2. Functional block diagram is for reference only.
CCM005-802248454-9
mtc20f2085s1rc_drx8_3112_rdimm.pdf - Rev. E 08/2021
                                                                                                     7               Micron Technology, Inc. reserves the right to change products or specifications without notice.
                                                                                                                                                                 © 2020 Micron Technology, Inc. All rights reserved.
                                                                    32GB (x80, ECC, DR) 288-Pin DDR5 RDIMM
                                                                                             Revision History
Revision History
Rev. E – 08/2021
                       • Production Release
Rev. D – 02/2021
                       • Preliminary Release
Rev. C – 01/2021
                       • Preliminary Release
Rev. B – 06/2020
                       • Preliminary Release
Rev. A – 06/2020
                       • Preliminary Release