Micron Confidential and Proprietary

4GB, 8GB, 16GB, 32GB: e·MMC

Features

e·MMC Memory
MTFC4GMWDM-3M AIT, MTFC4GMWDM-3M AIT A
MTFC8GLWDM-3M AIT Z, MTFC8GLWDM-AIT Z, MTFC8GLWDM-AIT A
MTFC16GLWDM-4M AIT Z, MTFC32GJWEF-4M AIT Z

Features Figure 1: Micron e·MMC Device

• MultiMediaCard (MMC) controller and NAND Flash

• 153-ball TFBGA and 169-ball TFBGA
(RoHS compliant, "green package")
• VCC: 2.7–3.6V
• VCCQ (dual voltage): 1.65–1.95V; 2.7–3.6V
• Temperature ranges MMC MMC controller MMC
power interface
– Operating temperature: –40˚C to +85˚C
– Storage temperature: –40˚C to +85˚C

MMC-Specific Features
• JEDEC/MMC standard version 4.51-compliant NAND Flash
(JEDEC Standard No. 84-B451) – SPI mode not power NAND Flash
supported1
– Advanced 11-signal interface
– x1, x4, and x8 I/Os, selectable by host
– SDR/DDR modes up to 52 MHz clock speed
– HS200 mode
– Command classes: class 0 (basic); class 2 (block
read); class 4 (block write); class 5 (erase); MMC-Specific Features (Continued)
class 6 (write protection); class 7 (lock card) – Background operation
– Temporary write protection – Reliable write
– Boot operation (high-speed boot) – Discard and sanitize
– Sleep mode – Power-off notification feature
– Replay-protected memory block (RPMB) – Backward compatible with previous MMC
– Secure erase and secure trim • ECC and block management implemented
– Hardware reset signal
– Multiple partitions with enhanced attribute Note: 1. The JEDEC specification is available at
– Permanent and power-on write protection www.jedec.org/sites/default/files/docs/
– High-priority interrupt (HPI) JESD84-B451.pdf.

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4GB, 8GB, 16GB, 32GB: e·MMC

Features

e·MMC Performance

Table 1: HS200 Partition Performance

Typical Values
Condition1 4GB 8GB 16GB 32GB Unit
Sequential write 15 15 25 37 MB/s
Sequential read 120 120 120 150 MB/s
Random write 500 500 900 900 IOPS
Random read 4500 4500 4000 4000 IOPS

Note: 1. Bus in x8 I/O and HS200 modes. Sequential access of chunk saturated; random access of 4KB chunk over 1GB
span. Additional performance data, such as system performance on a specific application board, will be pro-
vided in a separate document upon customer request.

Table 2: 52 MHz DDR2 Performance

Typical Values
Condition1 4GB 8GB 16GB 32GB Unit
Sequential Write 15 15 25 37 MB/s
Sequential Read 80 80 80 80 MB/s
Random Write 500 500 900 900 IOPS
Random Read 4000 4000 3700 3700 IOPS

Note: 1. Bus in x8 I/O and 52 MHz DDR2 modes. Sequential access of chunk saturated; random access of 4KB chunk
over 1GB span. Additional performance data, such as system performance on a specific application board,
will be provided in a separate document upon customer request.

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4GB, 8GB, 16GB, 32GB: e·MMC

Features

e·MMC Current Consumption

Table 3: HS200 Current Consumption

Typical Values (ICC/ICCQ)

Condition1 4GB, 8GB 16GB 32GB Unit
Write 60/10 110/10 110/10 mA
Read 45/50 105/50 105/50 mA
Sleep 125 125 125 µA
Auto-Standby 50/125 50/125 50/125 µA

Note: 1. Bus in x8 I/O and HS200 modes. VCC = 3.6V and VCCQ = 1.95V. 25°C. Measurements done as average RMS cur-
rent consumption. ICCQ in READ operation might be affected by tester load.

Table 4: 52 MHz DDR2 Current Consumption

Typical Values (ICC/ICCQ)

Condition1 4GB, 8GB 16GB 32GB Unit
Write 30/10 110/10 110/10 mA
Read 60/50 75/85 75/85 mA
Sleep 0/125 0/125 0/125 µA
Auto-Standby 50/125 50/125 50/125 µA

Note: 1. Bus in x8 I/O and 52 MHz DDR2 modes. VCC = 3.6V and VCCQ = 1.95V. 25°C. Measurements done as average
RMS current consumption. ICCQ in READ operation might be affected by tester load.

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4GB, 8GB, 16GB, 32GB: e·MMC

Features

Part Numbering Information

Micron® e·MMC memory devices are available in different configurations and densities.

Figure 2: e·MMC Part Numbering

MT FC xx x x xx - xx xxx Z xx

Micron Technology Production Status

Product Family Wafer Process Applied

FC = NAND Flash + controller
Operating Temperature
Range
NAND Flash Density
Special Option
NAND Flash Component
Package Code
Controller Revision

Table 5: Ordering Information

Base Part Number Density Package Shipping

MTFC4GMWDM-3M AIT 4GB 153-ball TFBGA Tray
MTFC4GMWDM-3M AIT A 11.5mm x 13.0mm x 1.2mm Tape and reel
MTFC8GLWDM-AIT Z 8GB 153-ball TFBGA Tray
MTFC8GLWDM-AIT A 11.5mm x 13.0mm x 1.2mm Tape and reel
MTFC8GLWDM-3M AIT Z 8GB 153-ball TFBGA Tray
11.5mm x 13.0mm x 1.2mm Tape and reel
MTFC16GLWDM-4M AIT Z 16GB 153-ball TFBGA Tray
11.5mm x 13.0mm x 1.2mm Tape and reel
MTFC32GJWEF-4M AIT Z 32GB 169-ball TFBGA Tray
14mm x 18mm x 1.2mm Tape and reel

Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead,
an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are
cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder.

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4GB, 8GB, 16GB, 32GB: e·MMC

Features

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4GB, 8GB, 16GB, 32GB: e·MMC

Important Notes and Warnings

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.

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4GB, 8GB, 16GB, 32GB: e·MMC

General Description

General Description
Micron e.MMC is a communication and mass data storage device that includes a Multi-
MediaCard (MMC) interface, a NAND Flash component, and a controller on an ad-
vanced 11-signal bus, which is compliant with the MMC system specification. Its cost
per bit, small package sizes, and high reliability make it an ideal choice for automotive
applications, including information and entertainment, navigation tools, advanced
driving assistance systems, and a variety of other industrial and portable products.
The nonvolatile e.MMC draws no power to maintain stored data, delivers high perform-
ance across a wide range of operating temperatures, and resists shock and vibration dis-
ruption.

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4GB, 8GB, 16GB, 32GB: e·MMC

Signal Descriptions

Signal Descriptions

Table 6: Signal Descriptions

Symbol Type Description

CLK Input Clock: Each cycle of the clock directs a transfer on the command line and on the data line(s). The
frequency can vary between the minimum and the maximum clock frequency.
RST_n Input Reset: The RST_n signal is used by the host for resetting the device, moving the device to the pre-
idle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD
register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.
CMD I/O Command: This signal is a bidirectional command channel used for command and response trans-
fers. The CMD signal has two bus modes: open-drain mode and push-pull mode (see Operating
Modes). Commands are sent from the MMC host to the device, and responses are sent from the
device to the host.
DAT[7:0] I/O Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull mode. By de-
fault, after power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. The
MMC controller can configure a wider data bus for data transfer either using DAT[3:0] (4-bit mode)
or DAT[7:0] (8-bit mode). e.MMC includes internal pull-up resistors for data lines DAT[7:1]. Immedi-
ately after entering the 4-bit mode, the device disconnects the internal pull-up resistors on the
DAT[3:1] lines. Upon entering the 8-bit mode, the device disconnects the internal pull-ups on the
DAT[7:1] lines.
VCC Supply VCC: NAND interface (I/F) I/O and NAND Flash power supply.
VCCQ Supply VCCQ: e.MMC controller core and e.MMC I/F I/O power supply.
VSS1 Supply VSS: NAND I/F I/O and NAND Flash ground connection.
VSSQ1 Supply VSSQ: e.MMC controller core and e.MMC I/F ground connection.
VDDIM Internal voltage node.
NC – No connect: No internal connection is present.
RFU – Reserved for future use: No internal connection is present. Leave it floating externally.

Note: 1. VSS and VSSQ are connected internally.

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4GB, 8GB, 16GB, 32GB: e·MMC

153-Ball Signal Assignments

153-Ball Signal Assignments

Figure 3: 153 Ball (Top View, Ball Down)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

A NC NC DAT0 DAT1 DAT2 RFU RFU NC NC NC NC NC NC NC

B NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC

C NC VDDIM NC VSSQ RFU VCCQ NC NC NC NC NC NC NC NC

D NC NC NC NC NC NC NC

E NC NC NC RFU VCC VSS RFU RFU RFU NC NC NC

F NC NC NC VCC RFU NC NC NC

G NC NC RFU VSS RFU NC NC NC

H NC NC NC RFU VSS NC NC NC

J NC NC NC RFU VCC NC NC NC

K NC NC NC RST_n RFU RFU VSS VCC RFU NC NC NC

L NC NC NC NC NC NC

M NC NC NC VCCQ CMD CLK NC NC NC NC NC NC NC NC

N NC VSSQ NC VCCQ VSSQ NC NC NC NC NC NC NC NC NC

P NC NC VCCQ VSSQ VCCQ VSSQ RFU NC NC RFU NC NC NC NC

Notes: 1. Some previous versions of the JEDEC product or mechanical specification had defined
reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-
vious specifications could have been connected to ground on the system board. To ena-
ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-
chanical specification. Any new PCB footprint implementations should use the new ball
assignments and leave the RFU balls floating on the system board.
2. VCC, VCCQ, VSS, and VSSQ balls must all be connected on the system board.

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4GB, 8GB, 16GB, 32GB: e·MMC

169-Ball Signal Assignments

169-Ball Signal Assignments

Figure 4: 169 Ball (Top View, Ball Down)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

A NC NC NC NC

B NC NC

D NC NC

H NC NC DAT0 DAT1 DAT2 RFU RFU NC NC NC NC NC NC NC

J NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC

K NC VDDIM NC VSSQ RFU VCCQ NC NC NC NC NC NC NC NC

L NC NC NC NC NC NC NC

M NC NC NC RFU VCC VSS RFU RFU RFU NC NC NC

N NC NC NC VCC RFU NC NC NC

P NC NC RFU VSS RFU NC NC NC

R NC NC NC RFU VSS NC NC NC

T NC NC NC RFU VCC NC NC NC

U NC NC NC RST_n RFU RFU VSS VCC RFU NC NC NC

V NC NC NC NC NC NC

W NC NC NC VCCQ CMD CLK NC NC NC NC NC NC NC NC

Y NC VSSQ NC VCCQ VSSQ NC NC NC NC NC NC NC NC NC

AA NC NC VCCQ VSSQ VCCQ VSSQ RFU NC NC RFU NC NC NC NC

AB

AC

AD

AE NC NC

AF

AG NC NC

AH NC NC NC NC

Notes: 1. Empty balls do not denote actual solder balls; they are position indicators only.

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4GB, 8GB, 16GB, 32GB: e·MMC

169-Ball Signal Assignments

2. Some previous versions of the JEDEC product or mechanical specification had defined
reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-
vious specifications could have been connected to ground on the system board. To ena-
ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-
chanical specification. Any new PCB footprint implementations should use the new ball
assignments and leave the RFU balls floating on the system board.
3. VCC, VCCQ, VSS, and VSSQ balls must all be connected on the system board.

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4GB, 8GB, 16GB, 32GB: e·MMC

Package Dimensions

Package Dimensions

Figure 5: 153-Ball TFBGA – 11.50mm x 13.00mm x 1.2mm (Package Code: DM)

Seating plane

A 0.08 A

153X Ø0.319
Dimensions apply
to solder balls post- Ball A1 ID
reflow onØ0.30 SMD (covered by SR) Ball A1 ID
ball pads.
14 12 10 8 6 4 2
13 11 9 7 5 3 1

A
B
C
D
E
6.5 CTR F
G
H
13 ±0.1 J
K
L
M
N
P

0.5 TYP

0.5 TYP 1.1 ±0.1

6.5 CTR 0.164 MIN

11.5 ±0.1
40X Ø0.325 test pads.
Ni/Au plated on pitch.
No solder balls.

Note: 1. Dimensions are in millimeters.

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4GB, 8GB, 16GB, 32GB: e·MMC

Package Dimensions

Figure 6: 169-Ball TFBGA - 14mm x 18mm x 1.2mm (Package Code: EF)

Seating plane

A 0.08 A

169X Ø0.319 Ball A1 ID

Dimensions apply (covered by SR)
to solder balls post-
reflow on Ø0.30 SMD Ball A1 ID
ball pads. 14 12 10 8 6 4 2
13 11 9 7 5 3 1

A
B
C
D
E
F
G
H
J
K
L
18 ±0.1 M
6.5 CTR N
P
R
T
13.5 CTR U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH

0.5 TYP 0.5 TYP 1.1 ±0.1

6.5 CTR 0.164 MIN
14 ±0.1
40X Ø0.325 on pitch.
Ni/Au plated test pads.

Note: 1. Dimensions are in millimeters.

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4GB, 8GB, 16GB, 32GB: e·MMC

Architecture

Architecture
Figure 7: e.MMC Functional Block Diagram

e.MMC

MMC VCCM
controller VCCQM
RST_n
CMD Registers
DAT[7:0]
CLK
OCR CSD RCA
VDDIM
VSS1
CID ECSD DSR
VSSQ1

NAND Flash

Note: 1. VSS and VSSQ are internally connected.

MMC Protocol Independent of NAND Flash Technology

The MMC specification defines the communication protocol between a host and a de-
vice. The protocol is independent of the NAND Flash features included in the device.
The device has an intelligent on-board controller that manages the MMC communica-
tion protocol.
The controller also handles block management functions such as logical block alloca-
tion and wear leveling. These management functions require complex algorithms and
depend entirely on NAND Flash technology (generation or memory cell type).
The device handles these management functions internally, making them invisible to
the host processor.

Defect and Error Management

Micron e.MMC incorporates advanced technology for defect and error management. If
a defective block is identified, the device completely replaces the defective block with
one of the spare blocks. This process is invisible to the host and does not affect data
space allocated for the user.
The device also includes a built-in error correction code (ECC) algorithm to ensure that
data integrity is maintained.
To make the best use of these advanced technologies and ensure proper data loading
and storage over the life of the device, the host must exercise the following precautions:
• Check the status after WRITE, READ, and ERASE operations.
• Avoid power-down during WRITE and ERASE operations.

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4GB, 8GB, 16GB, 32GB: e·MMC

OCR Register

OCR Register
The 32-bit operation conditions register (OCR) stores the voltage profile of the card and
the access mode indication. In addition, this register includes a status information bit.

Table 7: OCR Parameters

OCR Bits OCR Value Description

[31] 1b (ready)/0b (busy)1 Device power-on status bit
[30:29] 10b Sector mode
[28:24] 0 0000b Reserved
[23:15] 1 1111 1111b 2.7–3.6V voltage range
[14:8] 000 0000b 2.0–2.7V voltage range
[7] 1b 1.70–1.95V voltage range
[6:0] 000 0000b Reserved

Note: 1. OCR = C0FF8080h after the device has completed power-up.

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4GB, 8GB, 16GB, 32GB: e·MMC

CID Register

CID Register
The card identification (CID) register is 128 bits wide. It contains the device identifica-
tion information used during the card identification phase as required by e.MMC proto-
col. Each device is created with a unique identification number.

Table 8: CID Register Field Parameters

Name Field Width CID Bits CID Value

Manufacturer ID MID 8 [127:120] FEh
Reserved – 6 [119:114] –
Card/BGA CBX 2 [113:112] 01h
OEM/application ID OID 8 [111:104] –
Product name PNM 48 [103:56] –
Product revision PRV 8 [55:48] –
Product serial number PSN 32 [47:16] –
Manufacturing date MDT 8 [15:8] –
CRC7 checksum CRC 7 [7:1] –
Not used; always 1 – 1 [0] –

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4GB, 8GB, 16GB, 32GB: e·MMC

CSD Register

CSD Register
The card-specific data (CSD) register provides information about accessing the device
contents. The CSD register defines the data format, error correction type, maximum da-
ta access time, and data transfer speed, as well as whether the DS register can be used.
The programmable part of the register (entries marked with W or E in the following ta-
ble) can be changed by the PROGRAM_CSD (CMD27) command.

Table 9: CSD Register Field Parameters

Size Cell CSD CSD

Name Field (Bits) Type1 Bits Value
CSD structure CSD_STRUCTURE 2 R [127:126] 03h
System specification version SPEC_VERS 4 R [125:122] 04h
Reserved2 – 2 – [121:120] –
Data read access time 1 TAAC 8 R [119:112] 6Eh
Data read access time 2 in CLK cycles NSAC 8 R [111:104] 01h
(NSAC × 100)
Maximum bus clock frequency TRAN_SPEED 8 R [103:96] 32h
Card command classes3 CCC 12 R [95:84] 0F5h
Maximum read data block length READ_BL_LEN 4 R [83:80] 09h
Partial blocks for reads supported READ_BL_PARTIAL 1 R [79] 0h
Write block misalignment WRITE_BLK_MISALIGN 1 R [78] 0h
Read block misalignment READ_BLK_MISALIGN 1 R [77] 0h
DSR implemented4 DSR_IMP 1 R [76] 1h
Reserved – 2 – [75:74] –
Device size C_SIZE 12 R [73:62] FFFh
Maximum read current at VDD,min VDD_R_CURR_MIN 3 R [61:59] 07h
Maximum read current at VDD,max VDD_R_CURR_MAX 3 R [58:56] 07h
Maximum write current at VDD,min VDD_W_CURR_MIN 3 R [55:53] 07h
Maximum write current at VDD,max VDD_W_CURR_MAX 3 R [52:50] 07h
Device size multiplier C_SIZE_MULT 3 R [49:47] 07h
Erase group size ERASE_GRP_SIZE 5 R [46:42] 1Fh
Erase group size multiplier ERASE_GRP_MULT 5 R [41:37] 1Fh
Write protect group size WP_GRP_SIZE 4GB-3M 5 R [36:32] 07h
8GB 0Fh
8GB-3M
32GB-4M 1Fh
16GB-4M 1Fh
Write protect group enable WP_GRP_ENABLE 1 R [31] 1h
Manufacturer default ECC DEFAULT_ECC 2 R [30:29] 00h
Write-speed factor R2W_FACTOR 3 R [28:26] 04h
Maximum write data block length WRITE_BL_LEN 4 R [25:22] 09h
Partial blocks for writes supported WRITE_BL_PARTIAL 1 R [21] 0h

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CSD Register

Table 9: CSD Register Field Parameters (Continued)

Size Cell CSD CSD

Name Field (Bits) Type1 Bits Value
Reserved – 4 – [20:17] –
Content protection application CONTENT_PROT_APP 1 R [16] 0h
File-format group FILE_FORMAT_GRP 1 R/W [15] 0h
Copy flag (OTP) COPY 1 R/W [14] 0h
Permanent write protection PERM_WRITE_PROTECT 1 R/W [13] 0h
Temporary write protection TMP_WRITE_PROTECT 1 R/W/E [12] 0h
File format FILE_FORMAT 2 R/W [11:10] 00h
ECC ECC 2 R/W/E [9:8] 00h
CRC CRC 7 R/W/E [7:1] –
Reserved – 1 – [0] –

Notes: 1. R = Read-only;
R/W = One-time programmable and readable;
R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_n
signal, and any CMD0 reset, and readable
2. Reserved bits should be read as 0.
3. CMD0 restriction: CMD0 (SW RESET) is not supported during programming command. If
SW RESET is issued during programming commands, a power cycle is required.
4. The IPEAK, max driving capability can be modified according to the actual capacitive load
on the e·MMC interface signals in the user application board using CMD4. In HS200
mode, the driver strength value is set in EXT_CSD[185] using CMD6.

CMD4 Argument Driving Capability (mA)

0x01000000 4
0x02000000 8
0x04000000 12
0x08000000 16
0x10000000 20
0x20000000 24
0x40000000 28
0x80000000 32

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ECSD Register

ECSD Register
The 512-byte extended card-specific data (ECSD) register defines device properties and
selected modes. The most significant 320 bytes are the properties segment. This seg-
ment defines device capabilities and cannot be modified by the host. The lower 192
bytes are the modes segment. The modes segment defines the configuration in which
the device is working. The host can change the properties of modes segments using the
SWITCH command.

Table 10: ECSD Register Field Parameters

Size Cell ECSD ECSD

Name Field (Bytes) Type1 Bytes Value
Properties Segment
Reserved2 – 7 – [511:505] –
Supported command sets S_CMD_SET 1 R [504] 01h
HPI features HPI_FEATURES 1 R [503] 03h
Background operations support BKOPS_SUPPORT 1 R [502] 01h
Max-packed read commands MAX_PACKED_READS 1 R [501] 3Fh
Max-packed write commands MAX_PACKED_WRITES 1 R [500] 3Fh
Data tag support DATA_TAG_SUPPORT 1 R [499] –
Tag unit size TAG_UNIT_SIZE 1 R [498] –
Tag resources size TAG_RES_SIZE 1 R [497] –
Context management capabilities CONTEXT_CAPABILITIES 1 R [496] –
Large unit size LARGE_UNIT_SIZE_M1 1 R [495] –
Extended partitions attribute support EXT_SUPPORT 1 R [494] –
Reserved – 241 – [493:253] –
Cache size CACHE_SIZE 4 R [252:249] –
Generic CMD6 timeout GENERIC_CMD6_TIME 1 R [248] 19h
Power-off notification (long) timeout POWER_OFF_LONG_TIM 1 R [247] FFh
Background operations status BKOPS_STATUS 1 R [246] 00h
Number of correctly programmed CORRECTLY_PROG_SECTORS_NUM 4 R [245:242] 00000000h
sectors
First initialization time after parti- INI_TIMEOUT_AP 1 R [241] 32h
tioning (first CMD1 to device ready)
Reserved – 1 – [240] –
Power class for 52 MHz, DDR at 3.6V PWR_CL_DDR_52_360 1 R [239] 04h
Power class for 52 MHz, DDR at 1.95V PWR_CL_DDR_52_195 1 R [238] 09h
Power class for 200 MHz at 1.95V PWR_CL_200_195 1 R [237] 09h
Power class for 200 MHz, at 1.3V PWR_CL_200_130 1 R [236] –
Minimum write performance for 8-bit MIN_PERF_DDR_W_8_52 1 R [235] 00h
at 52 MHz in DDR mode
Minimum read performance for 8-bit MIN_PERF_DDR_R_8_52 1 R [234] 00h
at 52 MHz in DDR mode

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ECSD Register

Table 10: ECSD Register Field Parameters (Continued)

Size Cell ECSD ECSD

Name Field (Bytes) Type1 Bytes Value
Reserved – 1 – [233] –
TRIM multiplier TRIM_MULT 4GB-3M 1 R [232] 03h
8GB-3M
8GB
32GB-4M 0Fh
16GB-4M 0Fh
Secure feature support SEC_FEATURE_SUPPORT 1 R [231] 55h
Secure erase multiplier SEC_ERASE_MULT 4GB-3M 1 R [230] 02h
8GB
8GB-3M
32GB-4M 06h
16GB-4M 02h
Secure trim multiplier SEC_TRIM_MULT 4GB-3M 1 R [229] 03h
8GB
8GB-3M
16GB-4M 03h
32GB-4M 09h
Boot information BOOT_INFO 1 R [228] 07h
Reserved – 1 – [227] –
Boot partition size BOOT_SIZE_MULT 4GB-3M 1 R [226] 40h
8GB-3M
8GB 20h
16GB-4M 80h
32GB-4M 80h
Access size ACC_SIZE 4GB-3M 1 R [225] 06h
8GB
8GB-3M
16GB-4M 07h
32GB-4M 08h
High-capacity erase unit size HC_ERASE_GRP_SIZE 4GB-3M 1 R [224] 08h
8GB
8GB-3M
16GB-4M 10h
32GB-4M 20h
High-capacity erase timeout ERASE_TIMEOUT_MULT 1 R [223] 01h
Reliable write-sector count REL_WR_SEC_C 1 R [222] 01h

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ECSD Register

Table 10: ECSD Register Field Parameters (Continued)

Size Cell ECSD ECSD

Name Field (Bytes) Type1 Bytes Value
High-capacity write protect group HC_WP_GRP_SIZE 4GB-3M 1 R [221] 01h
size 8GB-3M 02h
8GB
16GB-4M 02h
32GB-4M 02h
Sleep current (VCC) S_C_VCC 1 R [220] 06h
Sleep current (VCCQ) S_C_VCCQ 1 R [219] 09h
Reserved – 1 – [218] –
Sleep/awake timeout S_A_TIMEOUT 1 R [217] 10h
Reserved – 1 – [216] –
Sector count SEC_COUNT 4GB-3M 4 R [215:212] 724000h
8GB-3M E80000h
8GB E88000h
16GB-4M 1CF0000h
32GB-4M 3A00000h
Reserved – 1 – [211] –
Minimum write performance for 8-bit MIN_PERF_W_8_52 1 R [210] 08h
at 52 MHz
Minimum read performance for 8-bit MIN_PERF_R_8_52 1 R [209] 08h
at 52 MHz
Minimum write performance for 8-bit MIN_PERF_W_8_26_4_52 1 R [208] 08h
at 26 MHz and 4-bit at 52 MHz
Minimum read performance for 8-bit MIN_PERF_R_8_26_4_52 1 R [207] 08h
at 26 MHz and 4-bit at 52 MHz
Minimum write performance for 4-bit MIN_PERF_W_4_26 1 R [206] 08h
at 26 MHz
Minimum read performance for 4-bit MIN_PERF_R_4_26 1 R [205] 08h
at 26 MHz
Reserved – 1 – [204] –
Power class for 26 MHz at 3.6V PWR_CL_26_360 1 R [203] 02h
Power class for 52 MHz at 3.6V PWR_CL_52_360 1 R [202] 02h
Power class for 26 MHz at 1.95V PWR_CL_26_195 1 R [201] 05h
Power class for 52 MHz at 1.95V PWR_CL_52_195 1 R [200] 05h
Partition switching timing PARTITION_SWITCH_TIME 1 R [199] 01h
Out-of-interrupt busy timing OUT_OF_INTERRUPT_TIME 1 R [198] 04h
I/O driver strength DRIVER_STRENGTH 1 R [197] 0Fh
Card type CARD_TYPE 1 R [196] 17h
Reserved – 1 – [195] –
CSD structure version CSD_STRUCTURE 1 R [194] 02h

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ECSD Register

Table 10: ECSD Register Field Parameters (Continued)

Size Cell ECSD ECSD

Name Field (Bytes) Type1 Bytes Value
Reserved – 1 – [193] –
Extended CSD revision EXT_CSD_REV 1 R [192] 06h
Modes Segment
Command set CMD_SET 1 R/W/E_P [191] 00h
Reserved – 1 – [190] –
Command set revision CMD_SET_REV 1 R [189] 00h
Reserved – 1 – [188] –
Power class POWER_CLASS 1 R/W/E_P [187] 00h
Reserved – 1 – [186] –
High-speed interface timing3 HS_TIMING 1 R/W/E_P [185] 00h
Reserved – 1 – [184] –
Bus width mode BUS_WIDTH 1 W/E_P [183] 00h
Reserved – 1 – [182] –
Erased memory content ERASED_MEM_CONT 1 R [181] 00h
Reserved – 1 – [180] –
Partition configuration PARTITION_CONFIG 1 R/W/E, [179] 00h
R/W/E_P
Boot configuration protection BOOT_CONFIG_PROT 1 R/W, [178] 00h
R/W/C_P
Boot bus width BOOT_BUS_WIDTH 1 R/W/E [177] 00h
Reserved – 1 – [176] –
High-density erase group definition ERASE_GROUP_DEF 1 R/W/E_P [175] 00h
Boot write protection status registers BOOT_WP_STATUS 1 R [174] –
Boot area write protection register BOOT_WP 1 R/W, [173] 00h
R/W/C_P
Reserved – 1 – [172] –
User write protection register USER_WP 1 R/W, [171] 00h
R/W/
C_P,
R/W/E_P
Reserved – 1 – [170] –
Firmware configuration FW_CONFIG 1 R/W [169] 00h
RPMB size RPMB_SIZE_MULT 1 R [168] 01h
Write reliability setting register4 WR_REL_SET 1 R/W [167] 1Fh
Write reliability parameter register WR_REL_PARAM 1 R [166] 05h
SANITIZE START operation SANITIZE_START 1 W/E_P [165] –
Manually start background opera- BKOPS_START 1 W/E_P [164] 00h
tions

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ECSD Register

Table 10: ECSD Register Field Parameters (Continued)

Size Cell ECSD ECSD

Name Field (Bytes) Type1 Bytes Value
Enable background operations hand- BKOPS_EN 1 R/W [163] 00h
shake
Hardware reset function RST_n_FUNCTION 1 R/W [162] 00h
HPI management HPI_MGMT 1 R/W/E_P [161] 00h
Partitioning support PARTITIONING_SUPPORT 1 R [160] 03h
Maximum enhanced area size MAX_ENH_SIZE_MULT 4GB-3M 3 R [159:157] 0001C9h
8GB-3M 0001D0h
8GB 0001D1h
16GB-4M 0001CFh
32GB-4M 0001D0h
Partitions attribute PARTITIONS_ATTRIBUTE 1 R/W [156] 00h
Partitioning setting PARTITION_SETTING_COMPLETED 1 R/W [155] 00h
General-purpose partition size GP_SIZE_MULT_GP3 12 R/W [154:152] 000000h
GP_SIZE_MULT_GP2 [151:149] 000000h
GP_SIZE_MULT_GP1 [148:146] 000000h
GP_SIZE_MULT_GP0 [145:143] 000000h
Enhanced user data area size ENH_SIZE_MULT 3 R/W [142:140] 000000h
Enhanced user data start address ENH_START_ADDR 4 R/W [139:136] 00000000h
Reserved – 1 – [135] –
Bad block management mode SEC_BAD_BLK_MGMNT 1 R/W [134] 00h
Reserved – 1 – [133] –
Package case temperature is control- TCASE_SUPPORT 1 W/E_P [132] –
led
Periodic wake-up PERIODIC_WAKEUP 1 R/W/E [131] –
Program CID/CSD in DDR mode sup- PROGRAM_CID_CSD_DDR_SUPPORT 1 R [130] 01h
port
Reserved – 2 TBD [129:128] –
Vendor specific fields VENDOR_SPECIFIC_FIELD 64 <vendor [127:64] –
specif-
ic>
Native sector size NATIVE_SECTOR_SIZE 1 R [63] –
Sector size emulation USE_NATIVE_SECTOR 1 R/W [62] –
Sector size DATA_SECTOR_SIZE 1 R [61] –
1st initialization after disabling sector INI_TIMEOUT_EMU 1 R [60] –
size emulation
Class 6 commands control CLASS_6_CTRL 1 R/W/E_P [59] –
Number of addressed group to be re- DYNCAP_NEEDED 1 R [58] –
leased
Exception events control EXCEPTION_EVENTS_CTRL 2 R/W/E_P [57:56] –

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ECSD Register

Table 10: ECSD Register Field Parameters (Continued)

Size Cell ECSD ECSD

Name Field (Bytes) Type1 Bytes Value
Exception events status EXCEPTION_EVENTS_STATUS 2 R [55:54] –
Extended partitions attribute EXT_PARTITIONS_ATTRIBUTE 2 R/W [53:52] –
Context configuration CONTEXT_CONF 15 R/W/E_P [51:37] –
Packed command status PACKED_COMMAND_STATUS 1 R [36] –
Packed command failure index PACKED_FAILURE_INDEX 1 R [35] –
Power-off notification POWER_OFF_NOTIFICATION 1 R/W/E_P [34] –
Control to turn the Cache ON/OFF CACHE_CTRL 1 R/W/E_P [33] –
Flushing of the cache FLUSH_CACHE 1 W/E_P [32] –
Reserved – 32 TBD [31:0] –

Notes: 1. R = Read-only;
R/W = One-time programmable and readable;
R/W/E = Multiple writable with the value kept after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable;
R/W/C_P = Writable after the value is cleared by a power cycle and assertion of the
RST_n signal (the value not cleared by CMD0 reset) and readable;
R/W/E_P = Multiple writable with the value reset after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable;
W/E_P = Multiple writable with the value reset after power cycle, assertion of the RST_n
signal, and any CMD0 reset, and not readable
2. Reserved bits should be read as 0.
3. tIH parameter in HS200 is 1.2ns. Refer to the JEDEC specification for the device input
timing diagram.
4. Micron has tested power failure under best-application knowledge conditions with posi-
tive results. Customers may request a dedicated test for their specific application condi-
tion. Micron set this register during factory test and used the one-time programming
option.

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DC Electrical Specifications – Device Power

DC Electrical Specifications – Device Power

The device current consumption for various device configurations is defined in the
power class fields of the ECSD register.
VCC is used for the NAND Flash device and its interface voltage; V CCQ is used for the
controller and the e.MMC interface voltage.

Figure 8: Device Power Diagram

VCCM
C3 C4

VCCQM
C1 C2

RST_n
Core regulator
NAND NAND Flash
VDDIM control signals
C5 C6
I/O block

I/O block
NAND
MMC

CLK
Core NAND
CMD
logic block
data bus

VCCQM
DAT[7:0]

MMC controller
VCCQM

Table 11: Absolute Maximum Ratings

Parameters Symbol Min Max Unit

Voltage input VIN –0.6 4.6 V
VCC supply VCC –0.6 4.6 V
VCCQ supply VCCQ –0.6 4.6 V
Storage temperature TSTG –40 85 °C

Note: 1. Voltage on any pin relative to VSS.

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Product Revision

Table 12: Capacitor and Resistance Specifications

Parameter Symbol Typ Units Notes

Pull-up resistance: CMD R_CMD 10 kΩ 1
Pull-up resistance: DAT[7:0] R_DAT 50 kΩ 1
Pull-up resistance: RST_n R_RST_n 50 kΩ 2
CLK/CMD/DAT[7:0] impedance 50 Ω 3
Serial resistance on CLK SR_CLK 22 Ω
VCCQ capacitor C1 2.2 µF 4
C2 0.1
VCC capacitor (≤8GB) C3 2.2 µF 5
C4 0.1
VCC capacitor (>8GB) C3 4.7 µF 5
C4 0.22
VDDIM capacitor (Creg) C5 1 µF 6
C6 0.1

Notes: 1. Used to prevent bus floating.

2. If host does not use H/W RESET (RST_n), pull-up resistance is not needed on RST_n line
(Extended_CSD[162] = 00h).
3. Impedance match.
4. The coupling capacitor should be connected with VCCQ and VSSQ as closely as possible.
5. The coupling capacitor should be connected with VCC and VSS as closely as possible.
6. The coupling capacitor should be connected with VDDIM and VSS as closely as possible.

Product Revision
The table below lists JEDEC v4.51 features not supported in the specified product revi-
sion. See the full JEDEC/MMC Standard No. 84-B451 specification at www.jedec.org/
sites/default/files/docs/JESD84-B451.pdf for more details regarding v4.51 features.

Table 13: Product Revision

Product Revision JEDEC Features Not Supported

1.x Real-time clock, dynamic device capacity, extended partition types, context IDs,
data tag, cache, thermal specification, native sector size, extended security pro-
tocols, packed command

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Revision History

Revision History
Rev. H – 1/19
• Added MPNs

Rev. G – 08/18
• Added Important Notes and Warnings section for further clarification aligning to in-
dustry standards

Rev. F – 07/15
• Changed ACC_SIZE value in ECSD Register for 16GB and 32GB device
• Changed note 3 of the ECSD Register from output to input timing diagram

Rev. E – 03/15
• Updated the values in the e·MMC Performance
• Replaced the V DDIM description in the Signal Descriptions table to: "Internal voltage
node"
• Changed 1.3ns to 1.2ns in note 3 of the ECSD Register Field Parameters table

Rev. D – 06/14
• Updated the values in the e·MMC Performance and e·MMC Consumption tables
• Replaced the V DDIM description in the Signal Descriptions table to: "At least 0.1μF +
1μF capacitors are required to connect V DDIM to ground"
• Updated the e·MMC Part Numbering Information figure
• Updated the ECSD Register table with new ECSD values
• Changed 1.1ns to 1.4ns in note 3 of the ECSD Register Field Parameters table

Rev. C – 11/13
• Added 169-ball and associated information
• Removed Boot Operation table

Rev. B – 07/13
• Updated Current Consumption table
• Updated Boot Operation table
• Updated the following register values: ECSD[226], ECSD[215:212], ECSD159:157]
• Deleted note 5 for the ECSD Register Field Parameters table

Rev. A – 05/13
• Initial release

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Revision History

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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