128Mb: x4, x8, x16

SDRAM

SYNCHRONOUS MT48LC32M4A2 – 8 Meg x 4 x 4 banks

MT48LC16M8A2 – 4 Meg x 8 x 4 banks

DRAM MT48LC8M16A2 – 2 Meg x 16 x 4 banks

For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds

FEATURES
• PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive PIN ASSIGNMENT (Top View)
edge of system clock
• Internal pipelined operation; column address can be 54-Pin TSOP
changed every clock cycle
x4 x8 x16 x16 x8 x4
• Internal banks for hiding row access/precharge
- -VDD 1 54 Vss - -
• Programmable burst lengths: 1, 2, 4, 8, or full page NC DQ0 DQ0 2 53 DQ15 DQ7 NC
• Auto Precharge, includes CONCURRENT AUTO - - VDDQ 3 52 VssQ - -
NC NC DQ1 4 51 DQ14 NC NC
PRECHARGE, and Auto Refresh Modes DQ0 DQ1 DQ2 5 50 DQ13 DQ6 DQ3
• Self Refresh Mode; standard and low power - - VssQ 6 49 VDDQ - -
NC NC DQ3 7 48 DQ12 NC NC
• 64ms, 4,096-cycle refresh NC DQ2 DQ4 8 47 DQ11 DQ5 NC
• LVTTL-compatible inputs and outputs - - VDDQ 9 46 VssQ - -
NC NC DQ5 10 45 DQ10 NC NC
• Single +3.3V ±0.3V power supply DQ1 DQ3 DQ6 11 44 DQ9 DQ4 DQ2
- - VssQ 12 43 VDDQ - -
DQ8 NC NC
OPTIONS MARKING NC
-
NC DQ7
- VDD
13
14
42
41 Vss - -
• Configurations NC NC DQML 15 40 NC - -
- - WE# 16 39 DQMH DQM DQM
32 Meg x 4 (8 Meg x 4 x 4 banks) 32M4 - - CAS# 17 38 CLK - -
16 Meg x 8 (4 Meg x 8 x 4 banks) 16M8 - - RAS# 18 37 CKE - -
- - CS# 19 36 NC - -
8 Meg x 16 (2 Meg x 16 x 4 banks) 8M16 - - BA0 20 35 A11 - -
- - BA1 21 34 A9 - -
• WRITE Recovery (tWR) - - A10 22 33 A8 - -
t
WR = “2 CLK”1 A2 - - A0 23 32 A7 - -
- - A1 24 31 A6 - -
• Package/Pinout - - A2 25 30 A5 - -
Plastic Package – OCPL2 - - A3 26 29 A4 - -
- - VDD 27 28 Vss - -
54-pin TSOP II (400 mil) TG
60-ball FBGA (8mm x 16mm) FB 3,6 Note: The # symbol indicates signal is active LOW. A dash (–)
60-ball FBGA (11mm x 13mm) FC 3,6 indicates x8 and x4 pin function is same as x16 pin function.

• Timing (Cycle Time) 32 Meg x 4 16 Meg x 8 8 Meg x 16

10ns @ CL = 2 (PC100) -8E3,4,5 Configuration 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
7.5ns @ CL = 3 (PC133) -75 Refresh Count 4K 4K 4K
7.5ns @ CL = 2 (PC133) -7E Row Addressing 4K (A0–A11) 4K (A0–A11) 4K (A0–A11)
Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
• Self Refresh Column Addressing 2K (A0–A9, A11) 1K (A0–A9) 512 (A0–A8)
Standard None
Low power L
• Operating Temperature Range KEY TIMING PARAMETERS
Commercial (0oC to +70oC) None
SPEED CLOCK ACCESS TIME SETUP HOLD
Industrial (-40oC to +85oC) IT 3
GRADE FREQUENCY CL = 2* CL = 3* TIME TIME
Part Number Example: -7E 143 MHz – 5.4ns 1.5ns 0.8ns
MT48LC16M8A2TG-7E -7E 133 MHz 5.4ns – 1.5ns 0.8ns
NOTE: 1. Refer to Micron Technical Note: TN-48-05. -75 133 MHz – 5.4ns 1.5ns 0.8ns
2. Off-center parting line. -8E 3,4,5 125 MHz – 6ns 2ns 1ns
3. Consult Micron for availability. -75 100 MHz 6ns – 1.5ns 0.8ns
4. Not recommended for new designs.
-8E 3 ,4,5 100 MHz 6ns – 2ns 1ns
5. Shown for PC100 compatability.
6. See page 59 for FBGA Device Marking Table.
*CL = CAS (READ) latency

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 1 ©2001, Micron Technology, Inc.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
 128Mb: x4, x8, x16
SDRAM

FBGA BALL ASSIGNMENT

(Top View)
32 Meg x 4 16 Meg x 8
8 x 16mm and 11 x 13mm 8 x 16mm and 11 x 13mm
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

A NC Vss VDD NC A DQ7 Vss VDD DQ0

B NC VssQ VDDQ NC B NC VssQ VDDQ NC

C VDDQ DQ3 DQ0 VssQ C VDDQ DQ6 DQ1 VssQ

D NC NC NC NC D DQ5 NC NC DQ2

E NC VssQ VDDQ NC E NC VssQ VDDQ NC

F VDDQ DQ2 DQ1 VssQ F VDDQ DQ4 DQ3 VssQ

G NC NC NC NC G NC NC NC NC

H NC Vss VDD NC H NC Vss VDD NC

J NC DQM WE# CAS# J NC DQM WE# CAS#

K NC CK RAS# NC K NC CK RAS# NC

L NC CKE NC CS# L NC CKE NC CS#

M A11 A9 BA1 BA0 M A11 A9 BA1 BA0

N A8 A7 A0 A10 N A8 A7 A0 A10

P A6 A5 A2 A1 P A6 A5 A2 A1

R A4 Vss VDD A3 R A4 Vss VDD A3

Depopulated Balls Depopulated Balls

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 2 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

128Mb SDRAM PART NUMBERS

PART NUMBER ARCHITECTURE A0-A11 select the row). The address bits registered
MT48LC32M4A2TG 32 Meg x 4 coincident with the READ or WRITE command are used
MT48LC32M4A2FC* 32 Meg x 4 to select the starting column location for the burst
MT48LC32M4A2FB* 32 Meg x 4 access.
MT48LC16M8A2TG 16 Meg x 8 The SDRAM provides for programmable READ
MT48LC16M8A2FC* 16 Meg x 8 or WRITE burst lengths of 1, 2, 4, or 8 locations, or the
MT48LC16M8A2FB* 16 Meg x 8 full page, with a burst terminate option. An auto
MT48LC8M16A2TG 8 Meg x 16 precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
*See page 59 for FBGA Device Marking Table.
burst sequence.
The 128Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This
GENERAL DESCRIPTION architecture is compatible with the 2n rule of prefetch
The Micron® 128Mb SDRAM is a high-speed CMOS, architectures, but it also allows the column address to be
dynamic random-access memory containing 134,217,728 changed on every clock cycle to achieve a high-speed,
bits. It is internally configured as a quad-bank DRAM fully random access. Precharging one bank while access-
with a synchronous interface (all signals are registered on ing one of the other three banks will hide the precharge
the positive edge of the clock signal, CLK). Each of the x4’s cycles and provide seamless high-speed, random-access
33,554,432-bit banks is organized as 4,096 rows by 2,048 operation.
columns by 4 bits. Each of the x8’s 33,554,432-bit banks is The 128Mb SDRAM is designed to operate in 3.3V
organized as 4,096 rows by 1,024 columns by 8 bits. Each memory systems. An auto refresh mode is provided, along
of the x16’s 33,554,432-bit banks is organized as 4,096 with a power-saving, power-down mode. All inputs and
rows by 512 columns by 16 bits. outputs are LVTTL-compatible.
Read and write accesses to the SDRAM are burst ori- SDRAMs offer substantial advances in DRAM operat-
ented; accesses start at a selected location and continue ing performance, including the ability to synchronously
for a programmed number of locations in a programmed burst data at a high data rate with automatic column-
sequence. Accesses begin with the registration of an AC- address generation, the ability to interleave between in-
TIVE command, which is then followed by a READ or ternal banks in order to hide precharge time and the
WRITE command. The address bits registered coinci- capability to randomly change column addresses on each
dent with the ACTIVE command are used to select the clock cycle during a burst access.
bank and row to be accessed (BA0, BA1 select the bank;

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 3 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

TABLE OF CONTENTS
Functional Block Diagram – 32 Meg x 4 ................ 5 Concurrent Auto Precharge .............................. 26
Functional Block Diagram – 16 Meg x 8 ................ 6 Truth Table 2 (CKE) ................................................ 28
Functional Block Diagram – 8 Meg x 16 ................ 7 Truth Table 3 (Current State, Same Bank) ..................... 29
Pin Descriptions ..................................................... 8 Truth Table 4 (Current State, Different Bank) ................. 31
Functional Description ......................................... 9 Absolute Maximum Ratings ................................... 33
Initialization ...................................................... 9 DC Electrical Characteristics
Register Definition ............................................ 9 and Operating Conditions ................................... 33
mode register ................................................ 9 IDD Specifications and Conditions ......................... 33
Burst Length ............................................ 9 Capacitance ............................................................ 34
Burst Type ............................................... 10 AC Electrical Characteristics and Recommended
CAS Latency ............................................ 11 Operating Conditions (Timing Table) ............. 34
Operating Mode ...................................... 11
Timing Waveforms
Write Burst Mode .................................... 11
Initialize and Load mode register ...................... 37
Commands ............................................................. 12
Power-Down Mode ............................................ 38
Truth Table 1 (Commands and DQM Operation) ............ 12
Clock Suspend Mode ......................................... 39
Command Inhibit ............................................. 13
Auto Refresh Mode ............................................ 40
No Operation (NOP) .......................................... 13
Self Refresh Mode .............................................. 41
Load mode register ............................................ 13
Reads
Active ................................................................ 13
Read – Without Auto Precharge ................... 42
Read ................................................................ 13
Read – With Auto Precharge ........................ 43
Write ................................................................ 13
Single Read – Without Auto Precharge ........ 44
Precharge ........................................................... 13
Single Read – With Auto Precharge ............. 45
Auto Precharge .................................................. 13
Alternating Bank Read Accesses ................... 46
Burst Terminate ................................................. 13
Read – Full-Page Burst .................................. 47
Auto Refresh ...................................................... 14
Read – DQM Operation ................................ 48
Self Refresh ........................................................ 14
Writes
Operation ................................................................ 15
Write – Without Auto Precharge ................. 49
Bank/Row Activation ........................................ 15
Write – With Auto Precharge ....................... 50
Reads ................................................................ 16
Single Write – Without Auto Precharge ....... 51
Writes ................................................................ 22
Single Write – With Auto Precharge ............ 52
Precharge ........................................................... 24
Alternating Bank Write Accesses ................. 53
Power-Down ...................................................... 24
Write – Full-Page Burst ................................. 54
Clock Suspend ................................................... 25
Write – DQM Operation .............................. 55
Burst Read/Single Write .................................... 25

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 4 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

FUNCTIONAL BLOCK DIAGRAM

32 Meg x 4 SDRAM

CKE
CLK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
RAS# BANK1

REFRESH 12
MODE REGISTER COUNTER
ROW- 12 BANK0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 1 1
12 4096
LATCH ARRAY DQM
12 & (4,096 x 2,048 x 4)
DECODER

SENSE AMPLIFIERS DATA

4 OUTPUT
4096 REGISTER

2 I/O GATING 4 DQ0-

DQM MASK LOGIC DQ3
BANK READ DATA LATCH
A0-A11, ADDRESS CONTROL WRITE DRIVERS
BA0, BA1 14
REGISTER LOGIC DATA
2 4 INPUT
2048 REGISTER
(x4)

COLUMN
DECODER
COLUMN-
ADDRESS 11
11 COUNTER/
LATCH

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 5 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

FUNCTIONAL BLOCK DIAGRAM

16 Meg x 8 SDRAM

CKE
CLK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
RAS# BANK1

REFRESH 12
MODE REGISTER COUNTER
ROW- 12 BANK0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 1 1
12 4096
LATCH ARRAY DQM
12 & (4,096 x 1,024 x 8)
DECODER

SENSE AMPLIFIERS DATA

8 OUTPUT
4096 REGISTER

2 I/O GATING 8 DQ0-

DQM MASK LOGIC DQ7
BANK READ DATA LATCH
A0-A11, ADDRESS CONTROL WRITE DRIVERS
BA0, BA1 14
REGISTER LOGIC DATA
2 8 INPUT
1024 REGISTER
(x8)

COLUMN
DECODER
COLUMN-
ADDRESS 10
10 COUNTER/
LATCH

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 6 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

FUNCTIONAL BLOCK DIAGRAM

8 Meg x 16 SDRAM

CKE
CLK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
RAS# BANK1

REFRESH 12
MODE REGISTER COUNTER
ROW- 12 BANK0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 2 2
12 4096
LATCH ARRAY DQML,
12 & (4,096 x 512 x 16) DQMH
DECODER

SENSE AMPLIFIERS DATA

16 OUTPUT
4096 REGISTER

2 I/O GATING 16 DQ0-

DQM MASK LOGIC DQ15
BANK READ DATA LATCH
A0-A11, ADDRESS CONTROL WRITE DRIVERS
BA0, BA1 14
REGISTER LOGIC DATA
2 16 INPUT
512 REGISTER
(x16)

COLUMN
DECODER
COLUMN-
ADDRESS 9
9 COUNTER/
LATCH

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 7 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

PIN DESCRIPTIONS
TSOP PIN NUMBERS SYMBOL TYPE DESCRIPTION
38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN and
SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row
active in any bank) or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
19 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is regis-
tered HIGH. CS# provides for external bank selection on systems with
multiple banks. CS# is considered part of the command code.
16, 17, 18 WE#, CAS#, Input Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the
RAS# command being entered.
39 x4, x8: DQM Input Input/Output Mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
15, 39 x16: DQML, DQM is sampled HIGH during a WRITE cycle. The output buffers are
DQMH placed in a High-Z state (two-clock latency) when DQM is sampled HIGH
during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC and
DQMH is DQM. On the x16, DQML corresponds to DQ0-DQ7 and DQMH
corresponds to DQ8-DQ15. DQML and DQMH are considered same state
when referenced as DQM.
20, 21 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
23-26, 29-34, 22, 35 A0-A11 Input Address Inputs: A0-A11 are sampled during the ACTIVE command (row-
address A0-A11) and READ/WRITE command (column-address A0-A9,
A11 [x4]; A0-A9 [x8]; A0-A8 [x16]; with A10 defining auto precharge) to
select one location out of the memory array in the respective bank. A10
is sampled during a PRECHARGE command to determine if all banks are
to be precharged (A10 [HIGH]) or bank selected by BA0, BA1 (A10
[LOW]). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
2, 4, 5, 7, 8, 10, 11, 13, 42, DQ0-DQ15 x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 are
44, 45, 47, 48, 50, 51, 53 NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for x4).
2, 5, 8, 11, 44, 47, 50, 53 DQ0-DQ7 x8: I/O Data Input/Output: Data bus for x8 (2, 8, 47, 53 are NCs for x4).
5, 11, 44, 50 DQ0-DQ3 x4: I/O Data Input/Output: Data bus for x4.
40 NC – No Connect: These pins should be left unconnected.
36 NC – Address input (A12) for the 256Mb and 512Mb devices
3, 9, 43, 49 VDDQ Supply DQ Power: Isolated DQ power on the die for improved noise immunity.
6, 12, 46, 52 VSSQ Supply DQ Ground: Isolated DQ ground on the die for improved noise
immunity.
1, 14, 27 VDD Supply Power Supply: +3.3V ±0.3V.
28, 41, 54 VSS Supply Ground.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 8 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

FUNCTIONAL DESCRIPTION Register Definition

In general, the 128Mb SDRAMs (8 Meg x 4 x 4 banks, MODE REGISTER
4 Meg x 8 x 4 banks and 2 Meg x 16 x 4 banks) are quad- The mode register is used to define the specific mode
bank DRAMs that operate at 3.3V and include a synchro- of operation of the SDRAM. This definition includes the
nous interface (all signals are registered on the positive selection of a burst length, a burst type, a CAS latency, an
edge of the clock signal, CLK). Each of the x4’s 33,554,432- operating mode and a write burst mode, as shown in
bit banks is organized as 4,096 rows by 2,048 columns by Figure 1. The mode register is programmed via the LOAD
4 bits. Each of the x8’s 33,554,432-bit banks is organized MODE REGISTER command and will retain the stored
as 4,096 rows by 1,024 columns by 8 bits. Each of the x16’s information until it is programmed again or the device
33,554,432-bit banks is organized as 4,096 rows by 512 loses power.
columns by 16 bits. Mode register bits M0-M2 specify the burst length,
Read and write accesses to the SDRAM are burst ori- M3 specifies the type of burst (sequential or interleaved),
ented; accesses start at a selected location and continue M4-M6 specify the CAS latency, M7 and M8 specify the
for a programmed number of locations in a programmed operating mode, M9 specifies the write burst mode, and
sequence. Accesses begin with the registration of an AC- M10 and M11 are reserved for future use.
TIVE command, which is then followed by a READ or The mode register must be loaded when all banks are
WRITE command. The address bits registered coincident idle, and the controller must wait the specified time
with the ACTIVE command are used to select the bank before initiating the subsequent operation. Violating ei-
and row to be accessed (BA0 and BA1 select the bank, A0- ther of these requirements will result in unspecified op-
A11 select the row). The address bits (x4: A0-A9, A11; x8: eration.
A0-A9; x16: A0-A8) registered coincident with the READ
or WRITE command are used to select the starting col- Burst Length
umn location for the burst access. Read and write accesses to the SDRAM are burst ori-
Prior to normal operation, the SDRAM must be initial- ented, with the burst length being programmable, as
ized. The following sections provide detailed informa- shown in Figure 1. The burst length determines the maxi-
tion covering device initialization, register definition, mum number of column locations that can be accessed
command descriptions and device operation. for a given READ or WRITE command. Burst lengths of 1,
2, 4, or 8 locations are available for both the sequential
Initialization and the interleaved burst types, and a full-page burst is
SDRAMs must be powered up and initialized in a available for the sequential type. The full-page burst is
predefined manner. Operational procedures other than used in conjunction with the BURST TERMINATE com-
those specified may result in undefined operation. Once mand to generate arbitrary burst lengths.
power is applied to VDD and VDDQ (simultaneously) and Reserved states should not be used, as unknown op-
the clock is stable (stable clock is defined as a signal eration or incompatibility with future versions may re-
cycling within timing constraints specified for the clock sult.
pin), the SDRAM requires a 100µs delay prior to issuing When a READ or WRITE command is issued, a block of
any command other than a COMMAND INHIBIT or NOP. columns equal to the burst length is effectively selected.
Starting at some point during this 100µs period and con- All accesses for that burst take place within this block,
tinuing at least through the end of this period, COM- meaning that the burst will wrap within the block if a
MAND INHIBIT or NOP commands should be applied. boundary is reached. The block is uniquely selected by
Once the 100µs delay has been satisfied with at least A1-A9, A11 (x4), A1-A9 (x8), or A1-A8 (x16) when the burst
one COMMAND INHIBIT or NOP command having been length is set to two; by A2-A9, A11 (x4), A2-A9 (x8), or A2-
applied, a PRECHARGE command should be applied. All A8 (x16) when the burst length is set to four; and by A3-A9,
banks must then be precharged, thereby placing the A11 (x4), A3-A9 (x8), or A3-A8 (x16) when the burst length
device in the all banks idle state. is set to eight. The remaining (least significant) address
Once in the idle state, two AUTO REFRESH cycles bit(s) is (are) used to select the starting location within
must be performed. After the AUTO REFRESH cycles are the block. Full-page bursts wrap within the page if the
complete, the SDRAM is ready for mode register pro- boundary is reached.
gramming. Because the mode register will power up in an
unknown state, it should be loaded prior to applying any
operational command.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 9 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM
Burst Type Table 1
Accesses within a given burst may be programmed to Burst Definition
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
Burst Starting Column Order of Accesses Within a Burst
The ordering of accesses within a burst is determined
Length Address Type = Sequential Type = Interleaved
by the burst length, the burst type and the starting col-
umn address, as shown in Table 1. A0
0 0-1 0-1
2
1 1-0 1-0
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
4
11 10 9 8 7 6 5 4 3 2 1 0
Mode Register (Mx)
1 0 2-3-0-1 2-3-0-1
Reserved* WB Op Mode CAS Latency BT Burst Length 1 1 3-0-1-2 3-2-1-0
A2 A1 A0
*Should program 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
M11, M10 = “0, 0”
to ensure compatibility Burst Length 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
with future devices.
M2 M1 M0 M3 = 0 M3 = 1 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 0 0 1 1
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
0 0 1 2 2
8
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
0 1 0 4 4
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
0 1 1 8 8

1 0 0 Reserved Reserved
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 0 1 Reserved Reserved 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
1 1 0 Reserved Reserved Cn, Cn + 1, Cn + 2
Full n = A0-A11/9/8
1 1 1 Full Page Reserved Cn + 3, Cn + 4...
Page Not Supported
…Cn - 1,
(y) (location 0-y)
Cn…
M3 Burst Type

0 Sequential

1 Interleaved NOTE: 1. For full-page accesses: y = 2,048 (x4), y = 1,024

(x8), y = 512 (x16).
M6 M5 M4 CAS Latency 2. For a burst length of two, A1-A9, A11 (x4), A1-A9
0 0 0 Reserved (x8) or A1-A8 (x16) select the block-of-two burst;
0 0 1 Reserved A0 selects the starting column within the block.
0 1 0 2 3. For a burst length of four, A2-A9, A11 (x4), A2-A9
0 1 1 3 (x8) or A2-A8 (x16) select the block-of-four burst;
1 0 0 Reserved A0-A1 select the starting column within the block.
1 0 1 Reserved 4. For a burst length of eight, A3-A9, A11 (x4), A3-
1 1 0 Reserved
A9 (x8) or A3-A8 (x16) select the block-of-eight
1 1 1 Reserved
burst; A0-A2 select the starting column within the
block.
5. For a full-page burst, the full row is selected and
M8 M7 M6-M0 Operating Mode A0-A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) select
0 0 Defined Standard Operation the starting column.
- - - All other states reserved 6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
M9 Write Burst Mode 7. For a burst length of one, A0-A9, A11 (x4), A0-A9
0 Programmed Burst Length (x8) or A0-A8 (x16) select the unique column to be
1 Single Location Access accessed, and mode register bit M3 is ignored.

Figure 1
Mode Register Definition

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SDRAM
CAS Latency Operating Mode
The CAS latency is the delay, in clock cycles, between The normal operating mode is selected by setting M7
the registration of a READ command and the availability and M8 to zero; the other combinations of values for M7
of the first piece of output data. The latency can be set to and M8 are reserved for future use and/or test modes.
two or three clocks. The programmed burst length applies to both READ and
If a READ command is registered at clock edge n, and WRITE bursts.
the latency is m clocks, the data will be available by clock Test modes and reserved states should not be used
edge n + m. The DQs will start driving as a result of the because unknown operation or incompatibility with fu-
clock edge one cycle earlier (n + m - 1), and provided that ture versions may result.
the relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock Write Burst Mode
cycle time is such that all relevant access times are met, When M9 = 0, the burst length programmed via
if a READ command is registered at T0 and the latency is M0-M2 applies to both READ and WRITE bursts; when
programmed to two clocks, the DQs will start driving M9 = 1, the programmed burst length applies to
after T1 and the data will be valid by T2, as shown in READ bursts, but write accesses are single-location
Figure 2. Table 2 below indicates the operating frequen- (nonburst) accesses.
cies at which each CAS latency setting can be used.
Reserved states should not be used as unknown op-
eration or incompatibility with future versions
Table 2
may result. CAS Latency
ALLOWABLE OPERATING
T0 T1 T2 T3 FREQUENCY (MHz)
CLK
CAS CAS
COMMAND READ NOP NOP
SPEED LATENCY = 2 LATENCY = 3
tLZ tOH -7E ≤ 133 ≤ 143
DQ DOUT -75 ≤ 100 ≤ 133
tAC -8E ≤ 100 ≤ 125
CAS Latency = 2

T0 T1 T2 T3 T4
CLK

COMMAND READ NOP NOP NOP

tLZ tOH

DQ DOUT
tAC

CAS Latency = 3

DON’T CARE

UNDEFINED

Figure 2
CAS Latency

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SDRAM

Commands
Truth Table 1 provides a quick reference of available following the Operation section; these tables provide
commands. This is followed by a written description of current state/next state information.
each command. Three additional Truth Tables appear

TRUTH TABLE 1 – COMMANDS AND DQM OPERATION

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES
COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3
READ (Select bank and column, and start READ burst) L H L H L/H8 Bank/Col X 4
WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 Bank/Col Valid 4
BURST TERMINATE L H H L X X Active
PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5
AUTO REFRESH or SELF REFRESH L L L H X X X 6, 7
(Enter self refresh mode)
LOAD MODE REGISTER L L L L X Op-Code X 2
Write Enable/Output Enable – – – – L – Active 8
Write Inhibit/Output High-Z – – – – H – High-Z 8

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A9; A11 (x4); A0-A9 (x8); or A0-A8 (x16) provide column address; A10 HIGH enables the auto precharge feature
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read
from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

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SDRAM
COMMAND INHIBIT whether or not auto precharge is used. If auto precharge
The COMMAND INHIBIT function prevents new com- is selected, the row being accessed will be precharged at
mands from being executed by the SDRAM, regardless of the end of the WRITE burst; if auto precharge is not
whether the CLK signal is enabled. The SDRAM is effec- selected, the row will remain open for subsequent ac-
tively deselected. Operations already in progress are not cesses. Input data appearing on the DQs is written to the
affected. memory array subject to the DQM input logic level ap-
pearing coincident with the data. If a given DQM signal is
NO OPERATION (NOP) registered LOW, the corresponding data will be written to
The NO OPERATION (NOP) command is used to per- memory; if the DQM signal is registered HIGH, the corre-
form a NOP to an SDRAM which is selected (CS# is LOW). sponding data inputs will be ignored, and a WRITE will
This prevents unwanted commands from being regis- not be executed to that byte/column location.
tered during idle or wait states. Operations already in
progress are not affected. PRECHARGE
The PRECHARGE command is used to deactivate the
LOAD MODE REGISTER open row in a particular bank or the open row in all banks.
The mode register is loaded via inputs A0-A11. See The bank(s) will be available for a subsequent row access
mode register heading in the Register Definition section. a specified time (tRP) after the PRECHARGE command is
The LOAD MODE REGISTER command can only be is- issued. Input A10 determines whether one or all banks
sued when all banks are idle, and a subsequent execut- are to be precharged, and in the case where only one bank
able command cannot be issued until tMRD is met. is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a
ACTIVE bank has been precharged, it is in the idle state and must
The ACTIVE command is used to open (or activate) a be activated prior to any READ or WRITE commands
row in a particular bank for a subsequent access. The being issued to that bank.
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A11 selects the row. This AUTO PRECHARGE
row remains active (or open) for accesses until a Auto precharge is a feature which performs the same
PRECHARGE command is issued to that bank. A individual-bank PRECHARGE function described above,
PRECHARGE command must be issued before opening a without requiring an explicit command. This is accom-
different row in the same bank. plished by using A10 to enable auto precharge in con-
junction with a specific READ or WRITE command. A
READ PRECHARGE of the bank/row that is addressed with the
The READ command is used to initiate a burst read READ or WRITE command is automatically performed
access to an active row. The value on the BA0, BA1 inputs upon completion of the READ or WRITE burst, except in
selects the bank, and the address provided on inputs A0- the full-page burst mode, where auto precharge does not
A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) selects the starting apply. Auto precharge is nonpersistent in that it is either
column location. The value on input A10 determines enabled or disabled for each individual READ or WRITE
whether or not auto precharge is used. If auto precharge command.
is selected, the row being accessed will be precharged at Auto precharge ensures that the precharge is initiated
the end of the READ burst; if auto precharge is not se- at the earliest valid stage within a burst. The user must
lected, the row will remain open for subsequent accesses. not issue another command to the same bank until the
Read data appears on the DQs subject to the logic level on precharge time (tRP) is completed. This is determined as
the DQM inputs two clocks earlier. If a given DQM signal if an explicit PRECHARGE command was issued at the
was registered HIGH, the corresponding DQs will be earliest possible time, as described for each burst type in
High-Z two clocks later; if the DQM signal was registered the Operation section of this data sheet.
LOW, the DQs will provide valid data.
BURST TERMINATE
WRITE The BURST TERMINATE command is used to trun-
The WRITE command is used to initiate a burst write cate either fixed-length or full-page bursts. The most
access to an active row. The value on the BA0, BA1 inputs recently registered READ or WRITE command prior to
selects the bank, and the address provided on inputs A0- the BURST TERMINATE command will be truncated, as
A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) selects the starting shown in the Operation section of this data sheet.
column location. The value on input A10 determines

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SDRAM
AUTO REFRESH retains data without external clocking. The SELF RE-
AUTO REFRESH is used during normal operation of FRESH command is initiated like an AUTO REFRESH
the SDRAM and is analogous to CAS#-BEFORE-RAS# command except CKE is disabled (LOW). Once the SELF
(CBR) REFRESH in conventional DRAMs. This REFRESH command is registered, all the inputs to the
command is nonpersistent, so it must be issued each SDRAM become “Don’t Care” with the exception of CKE,
time a refresh is required. All active banks must be which must remain LOW.
PRECHARGED prior to issuing an AUTO REFRESH Once self refresh mode is engaged, the SDRAM pro-
command. The AUTO REFRESH command should not vides its own internal clocking, causing it to perform its
be issued until the minimum tRP has been met after the own AUTO REFRESH cycles. The SDRAM must remain in
PRECHARGE command as shown in the operation sec- self refresh mode for a minimum period equal to tRAS
tion. and may remain in self refresh mode for an indefinite
The addressing is generated by the internal refresh period beyond that.
controller. This makes the address bits “Don’t Care” The procedure for exiting self refresh requires a se-
during an AUTO REFRESH command. The 128Mb SDRAM quence of commands. First, CLK must be stable (stable
requires 4,096 AUTO REFRESH cycles every 64ms (tREF), clock is defined as a signal cycling within timing con-
regardless of width option. Providing a distributed AUTO straints specified for the clock pin) prior to CKE going
REFRESH command every 15.625µs will meet the refresh back HIGH. Once CKE is HIGH, the SDRAM must have
requirement and ensure that each row is refreshed. Alter- NOP commands issued (a minimum of two clocks) for
natively, 4,096 AUTO REFRESH commands can be issued tXSR because time is required for the completion of any
in a burst at the minimum cycle rate (tRFC), once every internal refresh in progress.
64ms. Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued every 15.625µs or less as both
SELF REFRESH SELF REFRESH and AUTO REFRESH utilize the row re-
The SELF REFRESH command can be used to retain fresh counter.
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the SDRAM

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SDRAM

Operation CLK
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued CKE HIGH
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE com-
mand, which selects both the bank and the row to be CS#
activated (see Figure 3).
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row, RAS#
subject to the tRCD specification. tRCD (MIN) should be
divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after CAS#
the ACTIVE command on which a READ or WRITE com-
mand can be entered. For example, a tRCD specification
of 20ns with a 125 MHz clock (8ns period) results in 2.5 WE#
clocks, rounded to 3. This is reflected in Figure 4, which
covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same
A0–A10, A11 ROW
procedure is used to convert other specification limits ADDRESS
from time units to clock cycles.)
A subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous
BA0, BA1 BANK
active row has been “closed” (precharged). The mini- ADDRESS
mum time interval between successive ACTIVE com-
mands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which Figure 3
results in a reduction of total row-access overhead. The Activating a Specific Row in a
minimum time interval between successive ACTIVE com-
mands to different banks is defined by tRRD.
Specific Bank

T0 T1 T2 T3 T4

CLK

COMMAND READ or
ACTIVE NOP NOP
WRITE

tRCD

DON’T CARE

Figure 4
Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3

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READs
READ bursts are initiated with a READ command, as Upon completion of a burst, assuming no other com-
shown in Figure 5. mands have been initiated, the DQs will go High-Z. A full-
The starting column and bank addresses are provided page burst will continue until terminated. (At the end of
with the READ command, and auto precharge is either the page, it will wrap to column 0 and continue.)
enabled or disabled for that burst access. If auto precharge Data from any READ burst may be truncated with a
is enabled, the row being accessed is precharged at the subsequent READ command, and data from a fixed-length
completion of the burst. For the generic READ com- READ burst may be immediately followed by data from a
mands used in the following illustrations, auto precharge READ command. In either case, a continuous flow of data
is disabled. can be maintained. The first data element from the new
During READ bursts, the valid data-out element from burst follows either the last element of a completed burst
the starting column address will be available following or the last desired data element of a longer burst that is
the CAS latency after the READ command. Each subse- being truncated. The new READ command should be
quent data-out element will be valid by the next positive issued x cycles before the clock edge at which the last
clock edge. Figure 6 shows general timing for each pos- desired data element is valid, where x equals the CAS
sible CAS latency setting. latency minus one.

CLK T0 T1 T2 T3
CLK

CKE HIGH COMMAND READ NOP NOP

tLZ tOH

CS# DQ DOUT
tAC

CAS Latency = 2
RAS#

CAS# T0 T1 T2 T3 T4
CLK

WE#
COMMAND READ NOP NOP NOP
tLZ tOH
A0-A9, A11: x4 COLUMN
A0-A9: x8 ADDRESS DQ DOUT
A0-A8: x16 tAC

A11: x8 CAS Latency = 3

A9, A11: x16
DON’T CARE

ENABLE AUTO PRECHARGE UNDEFINED

A10
DISABLE AUTO PRECHARGE
Figure 6
BA0,1 BANK CAS Latency
ADDRESS

Figure 5
READ Command

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This is shown in Figure 7 for CAS latencies of two and ture. A READ command can be initiated on any clock
three; data element n + 3 is either the last of a burst of four cycle following a previous READ command. Full-speed
or the last desired of a longer burst. The 128Mb SDRAM random read accesses can be performed to the same
uses a pipelined architecture and therefore does not bank, as shown in Figure 8, or each subsequent READ
require the 2n rule associated with a prefetch architec- may be performed to a different bank.

T0 T1 T2 T3 T4 T5 T6

CLK

COMMAND READ NOP NOP NOP READ NOP NOP

X = 1 cycle

BANK, BANK,
ADDRESS COL n COL b

DOUT DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3 b

CAS Latency = 2

T0 T1 T2 T3 T4 T5 T6 T7

CLK

COMMAND READ NOP NOP NOP READ NOP NOP NOP

X = 2 cycles

BANK, BANK,
ADDRESS COL n COL b

DOUT DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3 b

CAS Latency = 3

NOTE: Each READ command may be to any bank. DQM is LOW. DON’T CARE

Figure 7
Consecutive READ Bursts

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SDRAM

T0 T1 T2 T3 T4 T5

CLK

COMMAND READ READ READ READ NOP NOP

BANK, BANK, BANK, BANK,

ADDRESS COL n COL a COL x COL m

DOUT DOUT DOUT DOUT

DQ n a x m

CAS Latency = 2

T0 T1 T2 T3 T4 T5 T6

CLK

COMMAND READ READ READ READ NOP NOP NOP

BANK, BANK, BANK, BANK,

ADDRESS COL n COL a COL x COL m

DOUT DOUT DOUT DOUT

DQ n a x m

CAS Latency = 3

NOTE: Each READ command may be to any bank. DQM is LOW.

DON’T CARE
Figure 8
Random READ Accesses

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Data from any READ burst may be truncated with a to suppress data-out from the READ. Once the WRITE
subsequent WRITE command, and data from a fixed- command is registered, the DQs will go High-Z (or re-
length READ burst may be immediately followed by data main High-Z), regardless of the state of the DQM signal,
from a WRITE command (subject to bus turnaround provided the DQM was active on the clock just prior to
limitations). The WRITE burst may be initiated on the the WRITE command that truncated the READ com-
clock edge immediately following the last (or last de- mand. If not, the second WRITE will be an invalid WRITE.
sired) data element from the READ burst, provided that I/ For example, if DQM was LOW during T4 in Figure 10,
O contention can be avoided. In a given system design, then the WRITEs at T5 and T7 would be valid, while the
there may be a possibility that the device driving the WRITE at T6 would be invalid.
input data will go Low-Z before the SDRAM DQs go High- The DQM signal must be de-asserted prior to the
Z. In this case, at least a single-cycle delay should occur WRITE command (DQM latency is zero clocks for input
between the last read data and the WRITE command. buffers) to ensure that the written data is not masked.
The DQM input is used to avoid I/O contention, as Figure 9 shows the case where the clock frequency allows
shown in Figures 9 and 10. The DQM signal must be for bus contention to be avoided without adding a NOP
asserted (HIGH) at least two clocks prior to the WRITE cycle, and Figure 10 shows the case where the additional
command (DQM latency is two clocks for output buffers) NOP is needed.

T0 T1 T2 T3 T4 T0 T1 T2 T3 T4 T5

CLK CLK

DQM DQM

COMMAND READ NOP NOP NOP NOP WRITE

COMMAND READ NOP NOP NOP WRITE

BANK, BANK,
BANK, BANK, ADDRESS COL n COL b
ADDRESS COL n COL b tHZ
tCK
DQ DOUT n DIN b
tHZ
tDS
DQ DOUT n DIN b

tDS NOTE: A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.

NOTE: A CAS latency of three is used for illustration. The READ

DON’T CARE
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.

Figure 10
Figure 9 READ to WRITE With
READ to WRITE Extra Clock Cycle

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A fixed-length READ burst may be followed by, or desired of a longer burst. Following the PRECHARGE
truncated with, a PRECHARGE command to the same command, a subsequent command to the same bank
bank (provided that auto precharge was not activated), cannot be issued until tRP is met. Note that part of the row
and a full-page burst may be truncated with a precharge time is hidden during the access of the last
PRECHARGE command to the same bank. The data element(s).
PRECHARGE command should be issued x cycles before In the case of a fixed-length burst being executed to
the clock edge at which the last desired data element is completion, a PRECHARGE command issued at the opti-
valid, where x equals the CAS latency minus one. This is mum time (as described above) provides the same op-
shown in Figure 11 for each possible CAS latency; data eration that would result from the same fixed-length
element n + 3 is either the last of a burst of four or the last burst with auto precharge. The disadvantage of the

T0 T1 T2 T3 T4 T5 T6 T7

CLK

t RP

COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE

X = 1 cycle
BANK a, BANK BANK a,
ADDRESS COL n (a or all) ROW

DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3

CAS Latency = 2

T0 T1 T2 T3 T4 T5 T6 T7

CLK

t RP

COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE

X = 2 cycles
BANK a, BANK BANK a,
ADDRESS COL n (a or all) ROW

DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3

CAS Latency = 3

NOTE: DQM is LOW. DON’T CARE

Figure 11
READ to PRECHARGE

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PRECHARGE command is that it requires that the com- mand, provided that auto precharge was not activated.
mand and address buses be available at the appropriate The BURST TERMINATE command should be issued x
time to issue the command; the advantage of the cycles before the clock edge at which the last desired data
PRECHARGE command is that it can be used to truncate element is valid, where x equals the CAS latency minus
fixed-length or full-page bursts. one. This is shown in Figure 12 for each possible CAS
Full-page READ bursts can be truncated with the latency; data element n + 3 is the last desired data ele-
BURST TERMINATE command, and fixed-length READ ment of a longer burst.
bursts may be truncated with a BURST TERMINATE com-

T0 T1 T2 T3 T4 T5 T6

CLK

BURST
COMMAND READ NOP NOP NOP
TERMINATE
NOP NOP

X = 1 cycle
BANK,
ADDRESS COL n

DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3

CAS Latency = 2

T0 T1 T2 T3 T4 T5 T6 T7

CLK

BURST
COMMAND READ NOP NOP NOP
TERMINATE
NOP NOP NOP

X = 2 cycles
BANK,
ADDRESS COL n

DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3

CAS Latency = 3

NOTE: DQM is LOW. DON’T CARE

Figure 12
Terminating a READ Burst

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WRITEs
WRITE bursts are initiated with a WRITE command, command applies to the new command. An example is
as shown in Figure 13. shown in Figure 15. Data n + 1 is either the last of a burst
The starting column and bank addresses are pro- of two or the last desired of a longer burst. The 128Mb
vided with the WRITE command, and auto precharge is SDRAM uses a pipelined architecture and therefore does
either enabled or disabled for that access. If auto not require the 2n rule associated with a prefetch archi-
precharge is enabled, the row being accessed is tecture. A WRITE command can be initiated on any clock
precharged at the completion of the burst. For the ge- cycle following a previous WRITE command. Full-speed
neric WRITE commands used in the following illustra- random write accesses within a page can be performed to
tions, auto precharge is disabled. the same bank, as shown in Figure 16, or each subsequent
During WRITE bursts, the first valid data-in element WRITE may be performed to a different bank.
will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each T0 T1 T2 T3
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have CLK
been initiated, the DQs will remain High-Z and any addi-
tional input data will be ignored (see Figure 14). A full-
page burst will continue until terminated. (At the end of COMMAND WRITE NOP NOP NOP
the page, it will wrap to column 0 and continue.)
Data for any WRITE burst may be truncated with a
BANK,
subsequent WRITE command, and data for a fixed-length ADDRESS COL n
WRITE burst may be immediately followed by data for a
WRITE command. The new WRITE command can be
DIN DIN
issued on any clock following the previous WRITE com- DQ n n+1
mand, and the data provided coincident with the new

NOTE: Burst length = 2. DQM is LOW.

Figure 14
CLK WRITE Burst
CKE HIGH

T0 T1 T2
CS#
CLK
RAS#

COMMAND WRITE NOP WRITE

CAS#

WE# BANK, BANK,

ADDRESS COL n COL b
A0-A9, A11: x4 COLUMN
A0-A9: x8 ADDRESS
A0-A8: x16 DIN DIN DIN
DQ n n+1 b
A11: x8
A9, A11: x16

ENABLE AUTO PRECHARGE

A10 NOTE: DQM is LOW. Each WRITE
DISABLE AUTO PRECHARGE command may be to any bank.

BA0,1 BANK DON’T CARE

ADDRESS

Figure 13 Figure 15
WRITE Command WRITE to WRITE

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Data for any WRITE burst may be truncated with a least one clock plus time, regardless of frequency.
subsequent READ command, and data for a fixed-length In addition, when truncating a WRITE burst, the DQM
WRITE burst may be immediately followed by a READ signal must be used to mask input data for the clock edge
command. Once the READ command is registered, the prior to, and the clock edge coincident with, the
data inputs will be ignored, and WRITEs will not be PRECHARGE command. An example is shown in Figure
executed. An example is shown in Figure 17. Data n + 1 is 18. Data n + 1 is either the last of a burst of two or the last
either the last of a burst of two or the last desired of a desired of a longer burst. Following the PRECHARGE
longer burst. command, a subsequent command to the same bank
Data for a fixed-length WRITE burst may be followed cannot be issued until tRP is met.
by, or truncated with, a PRECHARGE command to the In the case of a fixed-length burst being executed to
same bank (provided that auto precharge was not acti- completion, a PRECHARGE command issued at the opti-
vated), and a full-page WRITE burst may be truncated mum time (as described above) provides the same op-
with a PRECHARGE command to the same bank. The eration that would result from the same fixed-length
PRECHARGE command should be issued tWR after the burst with auto precharge. The disadvantage of the
clock edge at which the last desired input data element is PRECHARGE command is that it requires that the com-
registered. The auto precharge mode requires a tWR of at mand and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
T0 T1 T2 T3 fixed-length or full-page bursts.
CLK

COMMAND WRITE WRITE WRITE WRITE

T0 T1 T2 T3 T4 T5 T6

CLK
BANK, BANK, BANK, BANK,
ADDRESS COL n COL a COL x COL m tWR@ tCK 15ns

DQM

DIN DIN DIN DIN

DQ n a x m
t RP

COMMAND WRITE NOP PRECHARGE NOP NOP ACTIVE NOP

NOTE: Each WRITE command may be to any bank. ADDRESS BANK a, BANK BANK a,
COL n (a or all) ROW
DQM is LOW.
t WR

DIN DIN
Figure 16 DQ n n+1

Random WRITE Cycles tWR@ tCK < 15ns

DQM

T0 T1 T2 T3 T4 T5 t RP

CLK COMMAND WRITE NOP NOP PRECHARGE NOP NOP ACTIVE

BANK a, BANK BANK a,

ADDRESS COL n (a or all) ROW
COMMAND WRITE NOP READ NOP NOP NOP
t WR

DIN DIN
DQ n n+1
BANK, BANK,
ADDRESS COL n COL b
NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length
of two.
DIN DIN DOUT DOUT
DQ n n+1 b b+1 DON’T CARE

NOTE: The WRITE command may be to any bank, and the READ command may
be to any bank. DQM is LOW. CAS latency = 2 for illustration.
Figure 18
WRITE to PRECHARGE
Figure 17
WRITE to READ

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SDRAM
Fixed-length or full-page WRITE bursts can be trun- PRECHARGE
cated with the BURST TERMINATE command. When The PRECHARGE command (see Figure 20) is used to
truncating a WRITE burst, the input data applied coinci- deactivate the open row in a particular bank or the open
dent with the BURST TERMINATE command will be row in all banks. The bank(s) will be available for a subse-
ignored. The last data written (provided that DQM is quent row access some specified time (tRP) after the
LOW at that time) will be the input data applied one clock PRECHARGE command is issued. Input A10 determines
previous to the BURST TERMINATE command. This is whether one or all banks are to be precharged, and in the
shown in Figure 19, where data n is the last desired data case where only one bank is to be precharged, inputs
element of a longer burst. BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state
and must be activated prior to any READ or WRITE com-
T0 T1 T2 mands being issued to that bank.

CLK POWER-DOWN
Power-down occurs if CKE is registered LOW coinci-
dent with a NOP or COMMAND INHIBIT when no ac-
BURST NEXT cesses are in progress. If power-down occurs when all
COMMAND WRITE
TERMINATE COMMAND
banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a row
BANK, (ADDRESS)
active in any bank, this mode is referred to as active
ADDRESS COL n power-down. Entering power-down deactivates the in-
put and output buffers, excluding CKE, for maximum
DIN power savings while in standby. The device may not
DQ (DATA)
n remain in the power-down state longer than the refresh
period (64ms) since no refresh operations are performed
in this mode.
Figure 19 The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
Terminating a WRITE Burst
clock edge (meeting tCKS). See Figure 21.

CLK
((
))
CLK ((
CKE HIGH ))
> tCKS
tCKS

CKE ((
CS# ))

((
))
COMMAND NOP NOP ACTIVE
((
))
RAS#
All banks idle tRCD
Input buffers gated off tRAS

CAS# tRC
Enter power-down mode. Exit power-down mode.

DON’T CARE
WE#

A0-A9
Figure 21
Power-Down
All Banks
A10
Bank Selected

BA0,1 BANK
ADDRESS

Figure 20
PRECHARGE Command

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SDRAM
CLOCK SUSPEND
The clock suspend mode occurs when a column ac- Clock suspend mode is exited by registering CKE
cess/burst is in progress and CKE is registered LOW. In HIGH; the internal clock and related operation will re-
the clock suspend mode, the internal clock is deacti- sume on the subsequent positive clock edge.
vated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled BURST READ/SINGLE WRITE
LOW, the next internal positive clock edge is suspended. The burst read/single write mode is entered by pro-
Any command or data present on the input pins at the gramming the write burst mode bit (M9) in the mode
time of a suspended internal clock edge is ignored; any register to a logic 1. In this mode, all WRITE commands
data present on the DQ pins remains driven; and burst result in the access of a single column location (burst of
counters are not incremented, as long as the clock is one), regardless of the programmed burst length. READ
suspended. (See examples in Figures 22 and 23.) commands access columns according to the programmed
burst length and sequence, just as in the normal mode of
operation (M9 = 0).

T0 T1 T2 T3 T4 T5 T0 T1 T2 T3 T4 T5 T6

CLK CLK

CKE CKE

INTERNAL
INTERNAL CLOCK
CLOCK

COMMAND READ NOP NOP NOP NOP NOP

COMMAND NOP WRITE NOP NOP

BANK,
ADDRESS COL n
BANK,
ADDRESS COL n
DOUT DOUT DOUT DOUT
DQ n n+1 n+2 n+3

DIN DIN DIN

DIN n n+1 n+2
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
NOTE: For this example, burst length = 4 or greater, and DM
is LOW. DON’T CARE

Figure 22 Figure 23
Clock Suspend During WRITE Burst Clock Suspend During READ Burst

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SDRAM
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank n will begin when the READ to bank m is regis-
bank while an access command with auto precharge tered (Figure 24).
enabled is executing is not allowed by SDRAMs, unless 2. Interrupted by a WRITE (with or without auto
the SDRAM supports CONCURRENT AUTO PRECHARGE. precharge): A WRITE to bank m will interrupt a READ
Micron SDRAMs support CONCURRENT AUTO on bank n when registered. DQM should be used two
PRECHARGE. Four cases where CONCURRENT AUTO clocks prior to the WRITE command to prevent bus
PRECHARGE occurs are defined below. contention. The PRECHARGE to bank n will begin
when the WRITE to bank m is registered (Figure 25).
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
on bank n, CAS latency later. The PRECHARGE to

T0 T1 T2 T3 T4 T5 T6 T7

CLK

READ - AP READ - AP
COMMAND NOP
BANK n
NOP
BANK m
NOP NOP NOP NOP

BANK n Page Active READ with Burst of 4 Interrupt Burst, Precharge Idle

Internal t RP - BANK n tRP - BANK m

States Page Active READ with Burst of 4 Precharge

BANK m

BANK n, BANK m,
ADDRESS COL a COL d

DOUT DOUT DOUT DOUT

DQ a a+1 d d+1

CAS Latency = 3 (BANK n)

NOTE: DQM is LOW. CAS Latency = 3 (BANK m)

Figure 24
READ With Auto Precharge Interrupted by a READ

T0 T1 T2 T3 T4 T5 T6 T7

CLK

READ - AP WRITE - AP
COMMAND BANK n
NOP NOP NOP
BANK m
NOP NOP NOP

Page
BANK n Active
READ with Burst of 4 Interrupt Burst, Precharge Idle

Internal tRP - BANK n t WR - BANK m

States Page Active WRITE with Burst of 4 Write-Back

BANK m

BANK n, BANK m,
ADDRESS COL a COL d

1
DQM

DOUT DIN DIN DIN DIN

DQ a d d+1 d+2 d+3

CAS Latency = 3 (BANK n)

NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.

DON’T CARE

Figure 25
READ With Auto Precharge Interrupted by a WRITE
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SDRAM
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto 4. Interrupted by a WRITE (with or without auto
precharge): A READ to bank m will interrupt a WRITE precharge): A WRITE to bank m will interrupt a WRITE
on bank n when registered, with the data-out appear- on bank n when registered. The PRECHARGE to bank
ing CAS latency later. The PRECHARGE to bank n will n will begin after tWR is met, where tWR begins when
begin after tWR is met, where tWR begins when the the WRITE to bank m is registered.
READ to bank m is registered. The last valid WRITE to The last valid data WRITE to bank n will be data
bank n will be data-in registered one clock prior to the registered one clock prior to a WRITE to bank m
READ to bank m (Figure 26). (Figure 27).

T0 T1 T2 T3 T4 T5 T6 T7

CLK

WRITE - AP READ - AP
COMMAND NOP
BANK n
NOP
BANK m
NOP NOP NOP NOP

BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
tRP - BANK n
Internal tWR - BANK n
tRP - BANK m
States Page Active READ with Burst of 4
BANK m

BANK n, BANK m,
ADDRESS COL a COL d

DIN DIN DOUT DOUT

DQ a a+1 d d+1

CAS Latency = 3 (BANK m)

NOTE: 1. DQM is LOW.

Figure 26
WRITE With Auto Precharge Interrupted by a READ

T0 T1 T2 T3 T4 T5 T6 T7

CLK

WRITE - AP WRITE - AP
COMMAND NOP
BANK n
NOP NOP
BANK m
NOP NOP NOP

BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
tRP - BANK n
Internal tWR - BANK n
t WR - BANK m
States Page Active WRITE with Burst of 4 Write-Back
BANK m

BANK n, BANK m,
ADDRESS COL a COL d

DIN DIN DIN DIN DIN DIN DIN

DQ a a+1 a+2 d d+1 d+2 d+3

NOTE: 1. DQM is LOW.

DON’T CARE

Figure 27
WRITE With Auto Precharge Interrupted by a WRITE

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 128Mb: x4, x8, x16
SDRAM

TRUTH TABLE 2 – CKE

(Notes: 1-4)
CKEn-1 CKEn CURRENT STATE COMMANDn ACTIONn NOTES
L L Power-Down X Maintain Power-Down
Self Refresh X Maintain Self Refresh
Clock Suspend X Maintain Clock Suspend
L H Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5
Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6
Clock Suspend X Exit Clock Suspend 7
H L All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry
All Banks Idle AUTO REFRESH Self Refresh Entry
Reading or Writing VALID Clock Suspend Entry
H H See Truth Table 3

NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1
(provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT
or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP
commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at
clock edge n + 1.

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 128Mb: x4, x8, x16
SDRAM

TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)
L H H H NO OPERATION (NOP/Continue previous operation)
L L H H ACTIVE (Select and activate row)
Idle L L L H AUTO REFRESH 7
L L L L LOAD MODE REGISTER 7
L L H L PRECHARGE 11
L H L H READ (Select column and start READ burst) 10
Row Active L H L L WRITE (Select column and start WRITE burst) 10
L L H L PRECHARGE (Deactivate row in bank or banks) 8
Read L H L H READ (Select column and start new READ burst) 10
(Auto L H L L WRITE (Select column and start WRITE burst) 10
Precharge L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) 8
Disabled) L H H L BURST TERMINATE 9
Write L H L H READ (Select column and start READ burst) 10
(Auto L H L L WRITE (Select column and start new WRITE burst) 10
Precharge L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8
Disabled) L H H L BURST TERMINATE 9

NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and
no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to
Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is
met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is
met, the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when
t
RP has been met. Once tRP is met, the bank will be in the idle state.

(Continued on next page)

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 128Mb: x4, x8, x16
SDRAM
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands
must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is
met, the SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been
met. Once tMRD is met, the SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is
met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.

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 128Mb: x4, x8, x16
SDRAM

TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)
L H H H NO OPERATION (NOP/Continue previous operation)
Idle X X X X Any Command Otherwise Allowed to Bank m
Row L L H H ACTIVE (Select and activate row)
Activating, L H L H READ (Select column and start READ burst) 7
Active, or L H L L WRITE (Select column and start WRITE burst) 7
Precharging L L H L PRECHARGE
Read L L H H ACTIVE (Select and activate row)
(Auto L H L H READ (Select column and start new READ burst) 7, 10
Precharge L H L L WRITE (Select column and start WRITE burst) 7, 11
Disabled) L L H L PRECHARGE 9
Write L L H H ACTIVE (Select and activate row)
(Auto L H L H READ (Select column and start READ burst) 7, 12
Precharge L H L L WRITE (Select column and start new WRITE burst) 7, 13
Disabled) L L H L PRECHARGE 9
Read L L H H ACTIVE (Select and activate row)
(With Auto L H L H READ (Select column and start new READ burst) 7, 8, 14
Precharge) L H L L WRITE (Select column and start WRITE burst) 7, 8, 15
L L H L PRECHARGE 9
Write L L H H ACTIVE (Select and activate row)
(With Auto L H L H READ (Select column and start READ burst) 7, 8, 16
Precharge) L H L L WRITE (Select column and start new WRITE burst) 7, 8, 17
L L H L PRECHARGE 9

NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the
previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and
no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when
t
RP has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when
t
RP has been met. Once tRP is met, the bank will be in the idle state.

(Continued on next page)

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 128Mb: x4, x8, x16
SDRAM
NOTE (continued):
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been
interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m
will interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the
WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m
will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The
last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 24).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior
to the WRITE to bank m (Figure 27).

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 128Mb: x4, x8, x16
SDRAM

ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maxi-
Voltage on VDD/VDDQ Supply mum Ratings” may cause permanent damage to the de-
Relative to VSS ........................................ -1V to +4.6V vice. This is a stress rating only, and functional operation
Voltage on Inputs, NC or I/O Pins of the device at these or any other conditions above those
Relative to VSS ........................................ -1V to +4.6V indicated in the operational sections of this specification
Operating Temperature, is not implied. Exposure to absolute maximum rating
TA (commercial) ........................................ 0°C to +70°C conditions for extended periods may affect reliability.
Operating Temperature,
TA (extended; IT parts) ......................... -40°C to +85°C
Storage Temperature (plastic) ................ -55°C to +150°C
Power Dissipation .......................................................... 1W

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 5, 6; notes appear on page 36; VDD/VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD/VDDQ 3 3.6 V
Input High Voltage: Logic 1; All inputs VIH 2 VDD + 0.3 V 22
Input Low Voltage: Logic 0; All inputs VIL -0.3 0.8 V 22
Input Leakage Current:
Any input 0V ≤ VIN ≤ VDD II -5 5 µA
(All other pins not under test = 0V)
Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ IOZ -5 5 µA
Output Levels: VOH 2.4 – V
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA) VOL – 0.4 V

IDD SPECIFICATIONS AND CONDITIONS

(Notes: 1, 5, 6, 11, 13; notes appear on page 36; VDD/VDDQ = +3.3V ±0.3V) MAX
PARAMETER/CONDITION SYMBOL -7E -75 -8E UNITS NOTES
Operating Current: Active Mode; IDD1 160 150 140 mA 3, 18,
Burst = 2; READ or WRITE; tRC = tRC (MIN) 19, 32
Standby Current: Power-Down Mode; IDD2 2 2 2 mA 32
All banks idle; CKE = LOW
Standby Current: Active Mode; IDD3 50 50 40 mA 3, 12,
CKE = HIGH; CS# = HIGH; All banks active after tRCD met; 19, 32
No accesses in progress
Operating Current: Burst Mode; Continuous burst; IDD4 165 150 140 mA 3, 18,
READ or WRITE; All banks active 19, 32
Auto Refresh Current tRFC = tRFC (MIN) IDD5 330 310 270 mA 3, 12,
CKE = HIGH; CS# = HIGH tRFC = 15.625µs IDD6 3 3 3 mA 18, 19,
32, 33
Self Refresh Current: Standard IDD7 2 2 2 mA 4
CKE ≤ 0.2V Low power (L) IDD7 1 1 1 mA

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 33 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

CAPACITANCE
(Note: 2; notes appear on page 36)

PARAMETER - TSOP “TG” Package SYMBOL MIN MAX UNITS NOTES

Input Capacitance: CLK CI 1 2.5 3.5 pF 29
Input Capacitance: All other input-only pins CI2 2.5 3.8 pF 30
Input/Output Capacitance: DQs CIO 4.0 6.0 pF 31

PARAMETER - FBGA “FB” Package SYMBOL MIN MAX UNITS NOTES

Input Capacitance: CLK CI 1 1.5 3.5 pF 34
Input Capacitance: All other input-only pins CI2 1.5 3.8 pF 35
Input/Output Capacitance: DQs CIO 3.0 6.0 pF 36

ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11; notes appear on page 36)

AC CHARACTERISTICS -7E -75 -8E

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES
Access time from CLK (pos. edge) CL = 3 tAC(3) 5.4 5.4 6 ns 27
CL = 2 tAC(2) 5.4 6 6 ns
Address hold time tAH 0.8 0.8 1 ns
Address setup time tAS 1.5 1.5 2 ns
CLK high-level width tCH 2.5 2.5 3 ns
CLK low-level width tCL 2.5 2.5 3 ns
Clock cycle time CL = 3 tCK(3) 7 7.5 8 ns 23
CL = 2 tCK(2) 7.5 10 10 ns 23
CKE hold time tCKH 0.8 0.8 1 ns
CKE setup time tCKS 1.5 1.5 2 ns
CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 1 ns
CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 2 ns
Data-in hold time tDH 0.8 0.8 1 ns
Data-in setup time tDS 1.5 1.5 2 ns
Data-out high-impedance time CL = 3 tHZ(3) 5.4 5.4 6 ns 10
CL = 2 tHZ(2) 5.4 6 6 ns 10
Data-out low-impedance time tLZ 1 1 1 ns
Data-out hold time (load) tOH 3 3 3 ns
Data-out hold time (no load) tOH 1.8 1.8 1.8 ns 28
N
ACTIVE to PRECHARGE command tRAS 37 120,000 44 120,000 50 120,000 ns
ACTIVE to ACTIVE command period tRC 60 66 70 ns
ACTIVE to READ or WRITE delay tRCD 15 20 20 ns
Refresh period (4,096 rows) tREF 64 64 64 ms
AUTO REFRESH period tRFC 66 66 70 ns
PRECHARGE command period tRP 15 20 20 ns
ACTIVE bank a to ACTIVE bank b command tRRD 14 15 20 ns
Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 ns 7
WRITE recovery time tWR 1 CLK + 1 CLK + 1 CLK + – 24
7ns 7.5ns 7ns
14 15 15 ns 25
Exit SELF REFRESH to ACTIVE command tXSR 67 75 80 ns 20

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 34 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 36)

PARAMETER SYMBOL -7E -75 -8E UNITS NOTES

READ/WRITE command to READ/WRITE command tCCD 1 1 1 tCK 17
CKE to clock disable or power-down entry mode tCKED 1 1 1 tCK 14
CKE to clock enable or power-down exit setup mode tPED 1 1 1 tCK 14
DQM to input data delay tDQD 0 0 0 tCK 17
DQM to data mask during WRITEs tDQM 0 0 0 tCK 17
DQM to data high-impedance during READs tDQZ 2 2 2 tCK 17
WRITE command to input data delay tDWD 0 0 0 tCK 17
Data-in to ACTIVE command tDAL 4 5 4 tCK 15, 21
Data-in to PRECHARGE command tDPL 2 2 2 tCK 16, 21
Last data-in to burst STOP command tBDL 1 1 1 tCK 17
Last data-in to new READ/WRITE command tCDL 1 1 1 tCK 17
Last data-in to PRECHARGE command tRDL 2 2 2 tCK 16, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 2 tCK 26
Data-out to high-impedance from PRECHARGE command CL = 3 tROH(3) 3 3 3 tCK 17
CL = 2 tROH(2) 2 2 2 tCK 17

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 35 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

NOTES
1. All voltages referenced to VSS. 15. Timing actually specified by tWR plus tRP; clock(s)
2. This parameter is sampled. VDD, VDDQ = +3.3V; specified as a reference only at minimum cycle rate.
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V. 16. Timing actually specified by tWR.
3. IDD is dependent on output loading and cycle rates. 17. Required clocks are specified by JEDEC functionality
Specified values are obtained with minimum cycle and are not dependent on any timing parameter.
time and the outputs open. 18. The IDD current will increase or decrease propor-
4. Enables on-chip refresh and address counters. tionally according to the amount of frequency alter-
5. The minimum specifications are used only to ation for the test condition.
indicate cycle time at which proper operation over 19. Address transitions average one transition every two
the full temperature range (0°C ≤ TA ≤ +70°C and - clocks.
40°C ≤ TA ≤ +85°C for IT parts) is ensured. 20. CLK must be toggled a minimum of two times during
6. An initial pause of 100µs is required after power-up, this period.
followed by two AUTO REFRESH commands, before 21. Based on tCK = 10ns for -8E and tCK = 7.5ns for -75 and
proper device operation is ensured. (VDD and VDDQ -7E .
must be powered up simultaneously. VSS and VSSQ 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width
must be at same potential.) The two AUTO REFRESH ≤ 3ns, and the pulse width cannot be greater than one
command wake-ups should be repeated any time third of the cycle rate. VIL undershoot: VIL (MIN) = -2V
the tREF refresh requirement is exceeded. for a pulse width ≤ 3ns.
7. AC characteristics assume tT = 1ns. 23. The clock frequency must remain constant (stable
8. In addition to meeting the transition rate specifica- clock is defined as a signal cycling within timing
tion, the clock and CKE must transit between VIH and constraints specified for the clock pin) during access
VIL (or between VIL and VIH) in a monotonic manner. or precharge states (READ, WRITE, including tWR,
9. Outputs measured at 1.5V with equivalent load: and PRECHARGE commands). CKE may be used to
reduce the data rate.
Q 24. Auto precharge mode only. The precharge timing
50pF budget (tRP) begins 7ns for -7E, 7.5ns for -75, and 7ns
for -8E after the first clock delay, after the last WRITE
is executed. May not exceed limit set for precharge
mode.
10. tHZ defines the time at which the output achieves the 25. Precharge mode only.
open circuit condition; it is not a reference to VOH or 26. JEDEC and PC100 specify three clocks.
VOL. The last valid data element will meet tOH before 27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is
going High-Z. guaranteed by design.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with 28. Parameter guaranteed by design.
timing referenced to 1.5V crossover point. If the in- 29. PC100 specifies a maximum of 4pF.
put transition time is longer than 1 ns, then the 30. PC100 specifies a maximum of 5pF.
timing is referenced at VIL (MAX) and VIH (MIN) and 31. PC100 specifies a maximum of 6.5pF.
no longer at the 1.5V crossover point. Refer to Micron 32. For -8E, CL = 2 and tCK = 10ns; for -75, CL = 3 and
Technical Note TN-48-09 for more details. tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns.
12. Other input signals are allowed to transition no more 33. CKE is HIGH during refresh command period
than once every two clocks and are otherwise at valid tRFC (MIN) else CKE is LOW. The IDD6 limit is actu-
VIH or VIL levels. ally a nominal value and does not result in a fail
13. IDD specifications are tested after the device is prop- value.
erly initialized. 34. PC133 specifies a minimum of 2.5pF.
14. Timing actually specified by tCKS; clock(s) specified 35. PC133 specifies a minimum of 2.5pF.
as a reference only at minimum cycle rate. 36. PC133 specifies a minimum of 3.0pF.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 36 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

INITIALIZE AND LOAD MODE REGISTER 1

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3
tCK (( (( tCL ((
CLK )) )) ))
(( (( tCH (( ((
)) )) )) ))
tCKS tCKH
(( (( (( ((
)) )) )) ))
CKE
(( ((
)) ))
tCMS tCMH tCMS tCMH tCMS tCMH
(( (( (( ((
)) )) AUTO )) AUTO )) LOAD MODE
COMMAND NOP PRECHARGE NOP NOP NOP NOP NOP ACTIVE
(( (( REFRESH (( REFRESH (( REGISTER
)) )) )) ))

(( (( (( ((
)) )) )) ))
DQM / ((
(( (( ((
DQML, DQMH )) )) )) ))

tAS tAH
(( (( (( ((
)) )) )) ))
A0-A9, A11 (( (( CODE ROW
(( ((
)) )) )) ))

tAS tAH
(( ALL BANKS (( (( ((
)) )) )) ))
A10 (( (( CODE ROW
(( ((
)) )) )) ))
SINGLE BANK

(( (( (( ((
)) ALL )) )) ))
BA0, BA1 (( BANK
(( BANKS (( ((
)) )) )) ))

(( High-Z ((
DQ
)) ))
T = 100µs
tRP tRFC tRFC tMRD
MIN

Power-up:
VDD and Precharge AUTO REFRESH AUTO REFRESH Program Mode Register 2, 3, 4
CLK stable all banks
DON’T CARE

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAH 0.8 0.8 1 ns tCKS 1.5 1.5 2 ns
tAS 1.5 1.5 2 ns tCMH 0.8 0.8 1 ns
tCH 2.5 2.5 3 ns tCMS 1.5 1.5 2 ns
tCL 2.5 2.5 3 ns tMRD3 2 2 2 tCK
tCK (3) 7 7.5 8 ns tRFC 66 66 70 ns
tCK (2) 7.5 10 10 ns tRP 15 20 20 ns
tCKH 0.8 0.8 1 ns

*CAS latency indicated in parentheses.

NOTE: 1. If CS# is HIGH at clock HIGH time, all commands applied are NOP, with CKE a “Don’t Care.”
2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 37 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

POWER-DOWN MODE 1

T0 T1 T2 ((
Tn + 1 Tn + 2
tCK tCL ))
CLK
tCH ((
))
tCKS tCKS

CKE ((
))
tCKS tCKH

tCMS tCMH
((
))
COMMAND PRECHARGE NOP NOP NOP ACTIVE
((
))

((
DQM / ))
DQML, DQMH ((
))

((
))
A0-A9, A11 ROW
((
))

ALL BANKS ((
))
A10 ROW
((
SINGLE BANK ))

tAS tAH
((
))
BA0, BA1 BANK(S) BANK
((
))

High-Z
((
DQ ))
Two clock cycles Input buffers gated off while in
power-down mode
Precharge all All banks idle, enter All banks idle
active banks power-down mode Exit power-down mode

DON’T CARE

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAH 0.8 0.8 1 ns tCK(2) 7.5 10 10 ns
tAS 1.5 1.5 2 ns tCKH 0.8 0.8 1 ns
tCH 2.5 2.5 3 ns tCKS 1.5 1.5 2 ns
tCL 2.5 2.5 3 ns tCMH 0.8 0.8 1 ns
tCK (3) 7 7.5 8 ns tCMS 1.5 1.5 2 ns

*CAS latency indicated in parentheses.

NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 38 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

CLOCK SUSPEND MODE 1

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCKS tCKH

tCMS tCMH

COMMAND READ NOP NOP NOP NOP NOP WRITE NOP

tCMS tCMH
DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 COLUMN m 2 COLUMN e 2

tAS tAH

A10
tAS tAH

BA0, BA1 BANK BANK

tAC
tAC tOH tHZ tDS tDH

DQ tLZ
DOUT m DOUT m + 1 DOUT e DOUT e + 1

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 6 ns tCKS 1.5 1.5 2 ns
tAC (2) 5.4 6 6 ns tCMH 0.8 0.8 1 ns
tAH 0.8 0.8 1 ns tCMS 1.5 1.5 2 ns
tAS 1.5 1.5 2 ns tDH 0.8 0.8 1 ns
tCH 2.5 2.5 3 ns tDS 1.5 1.5 2 ns
tCL 2.5 2.5 3 ns tHZ(3) 5.4 5.4 6 ns
tCK(3) 7 7.5 8 ns tHZ(2) 5.4 6 6 ns
tCK(2) 7.5 10 10 ns tLZ 1 1 1 ns
tCKH 0.8 0.8 1 ns tOH 3 3 3 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 39 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

AUTO REFRESH MODE

T0 T1 T2 Tn + 1 To + 1
(( t CL ((
CLK )) ))
t CK t CH (( ((
)) ))
(( ((
)) ))
CKE

t CKS t CKH

t CMS t CMH
(( ((
AUTO )) AUTO ))
COMMAND PRECHARGE NOP NOP
REFRESH ( ( NOP REFRESH
NOP
( ( NOP ACTIVE
)) ))

(( ((
DQM / )) ))
DQML, DQMH (( ((
)) ))

(( ((
)) ))
A0-A9, A11 ROW
(( ((
)) ))

ALL BANKS (( ((
)) ))
A10 ROW
(( ((
SINGLE BANK )) ))

t AS t AH
(( ((
)) ))
BA0, BA1 BANK(S) BANK
(( ((
)) ))

DQ High-Z (( ((
)) ))
t RP t RFC1 t RFC1

Precharge all DON’T CARE

active banks

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAH 0.8 0.8 1 ns tCKH 0.8 0.8 1 ns
tAS 1.5 1.5 2 ns tCKS 1.5 1.5 2 ns
tCH 2.5 2.5 3 ns tCMH 0.8 0.8 1 ns
tCL 2.5 2.5 3 ns tCMS 1.5 1.5 2 ns
tCK (3) 7 7.5 8 ns tRFC 66 66 70 ns
tCK (2) 7.5 10 10 ns tRP 15 20 20 ns

*CAS latency indicated in parentheses.

NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 40 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

SELF REFRESH MODE

T0 T1 T2 ((
Tn + 1 ((
To + 1 To + 2
tCL )) ))
CLK
tCK tCH (( ((
)) ))
tCKS
≥ tRAS min1
((
))
CKE (( ((
)) ))
tCKS tCKH

tCMS tCMH
(( ((
AUTO )) )) AUTO
COMMAND PRECHARGE NOP REFRESH ((
NOP ( ( or COMMAND
INHIBIT REFRESH
)) ))

(( ((
DQM/ )) ))
DQML, DQMH (( ((
)) ))

(( ((
)) ))
A0-A9, A11
(( ((
)) ))
ALL BANKS (( ((
)) ))
A10
(( ((
SINGLE BANK )) ))

tAS tAH
(( ((
)) ))
BA0, BA1 BANK(S) (( ((
)) ))

High-Z (( ((
DQ )) ))
tRP tXSR

Precharge all Enter self refresh mode Exit self refresh mode
active banks
(Restart refresh time base)
CLK stable prior to exiting DON’T CARE
self refresh mode

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAH 0.8 0.8 1 ns tCKS 1.5 1.5 2 ns
tAS 1.5 1.5 2 ns tCMH 0.8 0.8 1 ns
tCH 2.5 2.5 3 ns tCMS 1.5 1.5 2 ns
tCL 2.5 2.5 3 ns tRAS 37 120,000 44 120,000 50 120,000 ns
tCK (3) 7 7.5 8 ns tRP 15 20 20 ns
tCK (2) 7.5 10 10 ns tXSR 75 75 80 ns
tCKH 0.8 0.8 1 ns

*CAS latency indicated in parentheses.

NOTES: 1. No maximum time limit for Self Refresh. tRAS max applies to non-Self Refresh mode.
2. tXSR requires minimum of two clocks regardless of frequency or timing.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 41 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

READ – WITHOUT AUTO PRECHARGE 1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCMS tCMH

COMMAND ACTIVE NOP READ NOP NOP NOP PRECHARGE NOP ACTIVE

tCMS tCMH
DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m2 ROW

tAS tAH
ALL BANKS
A10 ROW ROW

tAS tAH DISABLE AUTO PRECHARGE SINGLE BANKS

BA0, BA1 BANK BANK BANK(S) BANK

tAC tAC tAC

tAC tOH tOH tOH tOH

DQ DOUT m DOUT m+1 DOUT m+2 DOUT m+3

tLZ
tHZ
tRCD CAS Latency tRP
tRAS
tRC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAC(3) 5.4 5.4 6 ns tCMH 0.8 0.8 1 ns
tAC(2) 5.4 6 6 ns tCMS 1.5 1.5 2 ns
tAH 0.8 0.8 1 ns tHZ(3) 5.4 5.4 6 ns
tAS 1.5 1.5 2 ns tHZ(2) 5.4 6 6 ns
tCH 2.5 2.5 3 ns tLZ 1 1 1 ns
tCL 2.5 2.5 3 ns tOH 3 3 3 ns
tCK(3) 7 7.5 8 ns tRAS 37 120,000 44 120,000 50 120,000 ns
tCK(2) 7.5 10 10 ns tRC 60 66 70 ns
tCKH 0.8 0.8 1 ns tRCD 15 20 20 ns
tCKS 1.5 1.5 2 ns tRP 15 20 20 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 42 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

READ – WITH AUTO PRECHARGE 1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE

tCMS tCMH
DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m 2 ROW

tAS tAH ENABLE AUTO PRECHARGE

A10 ROW ROW

tAS tAH

BA0, BA1 BANK BANK BANK

tAC tAC tAC

tAC tOH tOH tOH tOH

DQ DOUT m DOUT m + 1 DOUT m + 2 DOUT m + 3

tLZ
tHZ
tRCD CAS Latency tRP
tRAS
tRC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 6 ns tCMH 0.8 0.8 1 ns
tAC (2) 5.4 6 6 ns tCMS 1.5 1.5 2 ns
tAH 0.8 0.8 1 ns tHZ(3) 5.4 5.4 6 ns
tAS 1.5 1.5 2 ns tHZ(2) 5.4 6 6 ns
tCH 2.5 2.5 3 ns tLZ 1 1 1 ns
tCL 2.5 2.5 3 ns tOH 3 3 3 ns
tCK (3) 7 7.5 8 ns tRAS 37 120,000 44 120,000 50 120,000 ns
tCK (2) 7.5 10 10 ns tRC 60 66 70 ns
tCKH 0.8 0.8 1 ns tRCD 15 20 20 ns
tCKS 1.5 1.5 2 ns tRP 15 20 20 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 43 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

SINGLE READ – WITHOUT AUTO PRECHARGE 1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH

tCKS tCKH

CKE
tCMS tCMH

COMMAND ACTIVE NOP READ NOP 3 NOP 3 PRECHARGE NOP ACTIVE NOP

tCMS tCMH
DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m2 ROW

tAS tAH
ALL BANKS
A10 ROW ROW

tAS tAH DISABLE AUTO PRECHARGE SINGLE BANKS

BA0, BA1 BANK BANK BANK(S) BANK

tAC tOH

DQ DOUT m
tLZ
tHZ
tRCD CAS Latency tRP
tRAS
tRC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 6 ns tCMH 0.8 0.8 1 ns
tAC (2) 5.4 6 6 ns tCMS 1.5 1.5 2 ns
tAH 0.8 0.8 1 ns tHZ(3) 5.4 5.4 6 ns
tAS 1.5 1.5 2 ns tHZ(2) 5.4 6 6 ns
tCH 2.5 2.5 3 ns tLZ 1 1 1 ns
tCL 2.5 2.5 3 ns tOH 3 3 3 ns
tCK (3) 7 7.5 8 ns tRAS 37 120,000 44 120,000 50 120,000 ns
tCK (2) 7.5 10 10 ns tRC 60 66 70 ns
tCKH 0.8 0.8 1 ns tRCD 15 20 20 ns
tCKS 1.5 1.5 2 ns tRP 15 20 20 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
3. PRECHARGE command not allowed or tRAS would be violated.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 44 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

SINGLE READ – WITH AUTO PRECHARGE 1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP NOP3 NOP3 READ NOP NOP ACTIVE NOP

tCMS tCMH
DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m2 ROW

tAS tAH ENABLE AUTO PRECHARGE

A10 ROW ROW

tAS tAH

BA0, BA1 BANK BANK BANK

tAC
t OH

DQ DOUT m
tRCD CAS Latency tHZ

tRAS tRP
tRC

DON’T CARE
UNDEFINED

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 6 ns tCMH 0.8 0.8 1 ns
tAC (2) 5.4 6 6 ns tCMS 1.5 1.5 2 ns
tAH 0.8 0.8 1 ns tHZ(3) 5.4 5.4 6 ns
tAS 1.5 1.5 2 ns tHZ(2) 5.4 6 6 ns
tCH 2.5 2.5 3 ns tLZ 1 1 1 ns
tCL 2.5 2.5 3 ns tOH 3 3 3 ns
tCK (3) 7 7.5 8 ns tRAS 37 120,000 44 120,000 50 120,000 ns
tCK (2) 7.5 10 10 ns tRC 60 66 70 ns
tCKH 0.8 0.8 1 ns tRCD 15 20 20 ns
tCKS 1.5 1.5 2 ns tRP 15 20 20 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
3. READ command not allowed else tRAS would be violated.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 45 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

ALTERNATING BANK READ ACCESSES 1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP READ NOP ACTIVE NOP READ NOP ACTIVE

tCMS tCMH
DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m 2 ROW COLUMN b 2 ROW

tAS tAH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE

A10 ROW ROW ROW

tAS tAH

BA0, BA1 BANK 0 BANK 0 BANK 3 BANK 3 BANK 0

tAC tAC tAC tAC tAC

tAC tOH tOH tOH tOH tOH

DQ DOUT m DOUT m + 1 DOUT m + 2 DOUT m + 3 DOUT b

tLZ

tRCD - BANK 0 CAS Latency - BANK 0 tRP - BANK 0 tRCD - BANK 0

tRAS - BANK 0
tRC - BANK 0
tRRD tRCD - BANK 3 CAS Latency - BANK 3

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 6 ns tCMH 0.8 0.8 1 ns
tAC (2) 5.4 6 6 ns tCMS 1.5 1.5 2 ns
tAH 0.8 0.8 1 ns tLZ 1 1 1 ns
tAS 1.5 1.5 2 ns tOH 3 3 3 ns
tCH 2.5 2.5 3 ns tRAS 44 120,000 44 120,000 50 120,000 ns
tCL 2.5 2.5 3 ns tRC 60 66 70 ns
tCK (3) 7 7.5 8 ns tRCD 15 20 20 ns
tCK(2) 7.5 10 10 ns tRP 15 20 20 ns
tCKH 0.8 0.8 1 ns tRRD 14 15 20 ns
tCKS 1.5 1.5 2 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 46 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

READ – FULL-PAGE BURST 1

T0 T1 T2 T3 T4 T5 T6 ((
Tn + 1 Tn + 2 Tn + 3 Tn + 4
tCL tCK ))
CLK
tCH ((
))

tCKS tCKH
((
CKE ))
((
))
tCMS tCMH
((
))
COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP BURST TERM NOP NOP
((
))

tCMS tCMH ((
DQM / ))
DQML, DQMH ((
))

tAS tAH
((
))
A0-A9, A11 ROW COLUMN m 2 ((
))

tAS tAH
((
))
A10 ROW ((
))

tAS tAH
((
))
BA0, BA1 BANK BANK
((
))

tAC tAC tAC ( ( tAC tAC

tAC tOH tOH tOH ) ) tOH tOH tOH
((
))
DQ DOUT m DOUT m+1 DOUT m+2 DOUT m-1 DOUT m DOUT m+1
((
tLZ ))
tHZ
512 (x16) locations within same row
1,024 (x8) locations within same row
tRCD CAS Latency 2,048 (x4) locations within same row

Full page completed DON’T CARE

Full-page burst does not self-terminate.
3 UNDEFINED
Can use BURST TERMINATE command.

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MNI MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 6 ns tCKS 1.5 1.5 2 ns
tAC (2) 5.4 6 6 ns tCMH 0.8 0.8 1 ns
tAH 0.8 0.8 1 ns tCMS 1.5 1.5 2 ns
tAS 1.5 1.5 2 ns tHZ(3) 5.4 5.4 6 ns
tCH 2.5 2.5 3 ns tHZ(2) 5.4 6 6 ns
tCL 2.5 2.5 3 ns tLZ 1 1 1 ns
tCK (3) 7 7.5 8 ns tOH 3 3 3 ns
tCK (2) 7.5 10 10 ns tRCD 15 20 20 ns
tCKH 0.8 0.8 1 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the CAS latency = 2.

2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
3. Page left open; no tRP.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 47 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

READ – DQM OPERATION 1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE
tCMS tCMH

COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP NOP

tCMS tCMH

DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m 2

tAS tAH
ENABLE AUTO PRECHARGE
A10 ROW
DISABLE AUTO PRECHARGE
tAS tAH

BA0, BA1 BANK BANK

tAC
tAC tOH tAC tOH tOH

DQ DOUT m DOUT m + 2 DOUT m + 3

tLZ
tHZ tLZ tHZ

tRCD CAS Latency

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAC (3) 5.4 5.4 6 ns tCKS 1.5 1.5 2 ns
tAC (2) 5.4 6 6 ns tCMH 0.8 0.8 1 ns
tAH 0.8 0.8 1 ns tCMS 1.5 1.5 2 ns
tAS 1.5 1.5 2 ns tHZ(3) 5.4 5.4 6 ns
tCH 2.5 2.5 3 ns tHZ(2) 5.4 6 6 ns
tCL 2.5 2.5 3 ns tLZ 1 1 1 ns
tCK (3) 7 7.5 8 ns tOH 3 3 3 ns
tCK (2) 7.5 10 10 ns tRCD 15 20 20 ns
tCKH 0.8 0.8 1 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 48 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

WRITE – WITHOUT AUTO PRECHARGE 1

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP PRECHARGE NOP ACTIVE

tCMS tCMH

DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m 3 ROW

tAS tAH
ALL BANKS

A10 ROW ROW

DISABLE AUTO PRECHARGE SINGLE BANK
tAS tAH

BA0, BA1 BANK BANK BANK BANK

tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3

tRCD t WR 2 tRP
tRAS
tRC

DON’T CARE

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAH 0.8 0.8 1 ns tCMS 1.5 1.5 2 ns
tAS 1.5 1.5 2 ns tDH 0.8 0.8 1 ns
tCH 2.5 2.5 3 ns tDS 1.5 1.5 2 ns
tCL 2.5 2.5 3 ns tRAS 37 120,000 44 120,000 50 120,000 ns
tCK (3) 7 7.5 8 ns tRC 60 66 70 ns
tCK (2) 7.5 10 10 ns tRCD 15 20 20 ns
tCKH 0.8 0.8 1 ns tRP 15 20 20 ns
tCKS 1.5 1.5 2 ns tWR 14 15 15 ns
tCMH 0.8 0.8 1 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of frequency.
3. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 49 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

WRITE – WITH AUTO PRECHARGE 1

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE

tCMS tCMH
DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m 2 ROW

tAS tAH
ENABLE AUTO PRECHARGE

A10 ROW ROW

tAS tAH

BA0, BA1 BANK BANK BANK

tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3

tRCD tWR tRP
tRAS
tRC

DON’T CARE

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAH 0.8 0.8 1 ns tCMS 1.5 1.5 2 ns
tAS 1.5 1.5 2 ns tDH 0.8 0.8 1 ns
tCH 2.5 2.5 3 ns tDS 1.5 1.5 2 ns
tCL 2.5 2.5 3 ns tRAS 37 120,000 44 120,000 50 120,000 ns
tCK (3) 7 7.5 8 ns tRC 60 66 70 ns
tCK (2) 7.5 10 10 ns tRCD 15 20 20 ns
tCKH 0.8 0.8 1 ns tRP 15 20 20 ns
tCKS 1.5 1.5 2 ns tWR 1 CLK + 1 CLK + 1 CLK + –
tCMH 0.8 0.8 1 ns 7ns 7.5ns 7ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 50 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

SINGLE WRITE – WITHOUT AUTO PRECHARGE 1

T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP 4 NOP 4 PRECHARGE NOP ACTIVE NOP

tCMS tCMH

DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m 3

tAS tAH
ALL BANKS

A10 ROW ROW

DISABLE AUTO PRECHARGE SINGLE BANK
tAS tAH

BA0, BA1 BANK BANK BANK BANK

tDS tDH

DQ DIN m
tRCD t WR 2 tRP
tRAS
tRC

DON’T CARE

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAH 0.8 0.8 1 ns tCMS 1.5 1.5 2 ns
tAS 1.5 1.5 2 ns tDH 0.8 0.8 1 ns
tCH 2.5 2.5 3 ns tDS 1.5 1.5 2 ns
tCL 2.5 2.5 3 ns tRAS 37 120,000 44 120,000 50 120,000 ns
tCK (3) 7 7.5 8 ns tRC 60 66 70 ns
tCK (2) 7.5 10 10 ns tRCD 15 20 20 ns
tCKH 0.8 0.8 1 ns tRP 15 20 20 ns
tCKS 1.5 1.5 2 ns tWR 14 15 15 ns
tCMH 0.8 0.8 1 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
4. PRECHARGE command not allowed else tRAS would be violated.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 51 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

SINGLE WRITE – WITH AUTO PRECHARGE 1

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP3 NOP3 NOP3 WRITE NOP NOP NOP ACTIVE NOP

tCMS tCMH
DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m 2 ROW

tAS tAH
ENABLE AUTO PRECHARGE

A10 ROW ROW

tAS tAH

BA0, BA1 BANK BANK BANK

tDS tDH

DQ DIN m
tRCD tWR tRP
tRAS
tRC

DON’T CARE

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAH 0.8 0.8 1 ns tCMS 1.5 1.5 2 ns
tAS 1.5 1.5 2 ns tDH 0.8 0.8 1 ns
tCH 2.5 2.5 3 ns tDS 1.5 1.5 2 ns
tCL 2.5 2.5 3 ns tRAS 37 120,000 44 120,000 50 120,000 ns
tCK (3) 7 7.5 8 ns tRC 60 66 70 ns
tCK (2) 7.5 10 10 ns tRCD 15 20 20 ns
tCKH 0.8 0.8 1 ns tRP 15 20 20 ns
tCKS 1.5 1.5 2 ns tWR 1 CLK + 1 CLK + 1 CLK + –
tCMH 0.8 0.8 1 ns 7ns 7.5ns 7ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1.

2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
3. WRITE command not allowed else tRAS would be violated.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 52 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

ALTERNATING BANK WRITE ACCESSES 1

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE

tCMS tCMH
DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m 2 ROW COLUMN b 2 ROW

tAS tAH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE

A10 ROW ROW ROW

tAS tAH

BA0, BA1 BANK 0 BANK 0 BANK 1 BANK 1 BANK 0

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3 DIN b DIN b + 1 DIN b + 2 DIN b + 3

tRCD - BANK 0 tWR - BANK 0 tRP - BANK 0 tRCD - BANK 0

tRAS - BANK 0
tRC - BANK 0
tRRD tRCD - BANK 1 tWR - BANK 1

DON’T CARE

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAH 0.8 0.8 1 ns tDH 0.8 0.8 1 ns
tAS 1.5 1.5 2 ns tDS 1.5 1.5 2 ns
tCH 2.5 2.5 3 ns tRAS 37 120,000 44 120,000 50 120,000 ns
tCL 2.5 2.5 3 ns tRC 60 66 70 ns
tCK (3) 7 7.5 8 ns tRCD 15 20 20 ns
tCK (2) 7.5 10 10 ns tRP 15 20 20 ns
tCKH 0.8 0.8 1 ns tRRD 14 15 20 ns
tCKS 1.5 1.5 2 ns tWR 1 CLK + 1 CLK + 1 CLK + –
tCMH 0.8 0.8 1 ns 7ns 7.5ns 7ns
tCMS 1.5 1.5 2 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 53 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

WRITE – FULL-PAGE BURST

T0 T1 T2 T3 T4 T5 ((
Tn + 1 Tn + 2 Tn + 3
tCL tCK ))
CLK
tCH ((
))

tCKS tCKH
((
))
CKE
((
))
tCMS tCMH
((
))
COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP
((
))

tCMS tCMH
((
DQM / ))
DQML, DQMH ((
))

tAS tAH
((
))
A0-A9, A11 ROW COLUMN m 1
((
))

tAS tAH
((
))
A10 ROW ((
))

tAS tAH
((
))
BA0, BA1 BANK BANK
((
))

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
((
))
DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3 (( DIN m - 1
))
tRCD
Full-page burst does not
512 (x16) locations within same row self-terminate. Can use
1,024 (x8) locations within same row BURST TERMINATE
2,048 (x4) locations within same row
command to stop.2, 3

Full page completed DON’T CARE

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAH 0.8 0.8 1 ns tCKS 1.5 1.5 2 ns
tAS 1.5 1.5 2 ns tCMH 0.8 0.8 1 ns
tCH 2.5 2.5 3 ns tCMS 1.5 1.5 2 ns
tCL 2.5 2.5 3 ns tDH 0.8 0.8 1 ns
tCK (3) 7 7.5 8 ns tDS 1.5 1.5 2 ns
tCK(2) 7.5 10 10 ns tRCD 15 20 20 ns
tCKH 0.8 0.8 1 ns

*CAS latency indicated in parentheses.

NOTE: 1. x16: A9 and A11 = “Don’t Care”

x8: A11 = “Don’t Care”
2. tWR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 54 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

WRITE – DQM OPERATION 1

T0 T1 T2 T3 T4 T5 T6 T7
tCK tCL
CLK
tCH
tCKS tCKH

CKE

tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP

tCMS tCMH
DQM /
DQML, DQMH
tAS tAH

A0-A9, A11 ROW COLUMN m 2

tAS tAH
ENABLE AUTO PRECHARGE
A10 ROW
tAS tAH DISABLE AUTO PRECHARGE

BA0, BA1 BANK BANK

tDS tDH tDS tDH tDS tDH

DQ DIN m DIN m + 2 DIN m + 3

tRCD
DON’T CARE

TIMING PARAMETERS

-7E -75 -8E -7E -75 -8E

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tAH 0.8 0.8 1 ns tCKS 1.5 1.5 2 ns
tAS 1.5 1.5 2 ns tCMH 0.8 0.8 1 ns
tCH 2.5 2.5 3 ns tCMS 1.5 1.5 2 ns
tCL 2.5 2.5 3 ns tDH 0.8 0.8 1 ns
tCK (3) 7 7.5 8 ns tDS 1.5 1.5 2 ns
tCK (2) 7.5 10 10 ns tRCD 15 20 20 ns
tCKH 0.8 0.8 1 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 55 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

54-PIN PLASTIC TSOP (400 mil)

22.30 SEE DETAIL A

22.14
.71
.80 TYP
.10 (2X)
.45
.30

2.80
11.86
11.66
PIN #1 ID
10.24
10.08

.75 (2X)
.18
.13
1.00 (2X) .25

.20
.05
.10 .60
.40
1.2 MAX
.80
TYP

DETAIL A

NOTE: 1. All dimensions in millimeters MAX or typical where noted.

MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 56 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

FBGA “FB” PACKAGE

60-BALL, 8mm x 16mm

0.850 ±0.075
0.325 ±0.025 0.205 MAX.

SEATING PLANE

0.10

5.60
2.40 ± 0.05
CTR
∅0.45 ± 0.05 (TYP)
0.80 (TYP)

PIN #1 ID

8.00 ±0.05

16.00 ±0.10 11.20

5.60 ±0.05 0.80

(TYP)

1.20 MAX.
2.80 ±0.05
4.00 ±0.05

8.00 ±0.10

(Bottom View)

NOTE: 1. All dimensions in millimeters.

2. Recommended Pad size for PCB is 0.33mm±0.025mm.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 57 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

FBGA “FC” PACKAGE

60-BALL, 11mm x 13mm

0.850 ±0.075
0.325 ± 0.025 0.205 MAX.

SEATING PLANE

0.10

5.60
2.40 ±0.05
CTR
∅ 0.45 ±0.05 (TYP)
0.80 (TYP)

PIN #1 ID

6.50 ±0.05

13.00 ±0.10 11.20

5.60 ±0.05 0.80

(TYP)

2.80 ±0.05 1.20 MAX

5.50 ±0.05

11.00 ±0.10

(Bottom View)

NOTE: 1. All dimensions in millimeters.

2. Recommended Pad size for PCB is 0.33mm±0.025mm.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 58 ©2001, Micron Technology, Inc.
 128Mb: x4, x8, x16
SDRAM

FBGA DEVICE MARKING DBFCF

Due to the size of the package, Micron’s standard part
number is not printed on the top of each device. Instead, Speed Grade
an abbreviated device mark comprised of a five-digit D = -8E
alphanumeric code is used. The abbreviated device marks F = -75
N = -7E
are cross referenced to Micron part numbers in Table 1.

Width ( I/Os)
B = x4
C = x8
D = x16

Device Density
F = 128Mb

Product Type
B = 3.3V SDR SDRAM (60-ball, "FB", 8mm x 16mm)
C = 3.3V SDR SDRAM (60-ball, "FC", 11mm x 13mm)

Product Group
D = DRAM
Z = DRAM ENGINEERING SAMPLE

CROSS REFERENCE FOR FBGA DEVICE MARKING

ENGINEERING PRODUCTION
PART NUMBER ARCHITECTURE FBGA SAMPLE MARKING
MT48LC32M4A2FC-75 32 Meg x 4 60-ball, 11x13 ZCFBF DCFBF
MT48LC32M4A2FC-7E 32 Meg x 4 60-ball, 11x13 ZCFBN DCFBN
MT48LC32M4A2FB-75 32 Meg x 4 60-ball, 8x16 ZBFBF DBFBF
MT48LC32M4A2FB-7E 32 Meg x 4 60-ball, 8x16 ZBFBN DBFBN
MT48LC16M8A2FC-75 16 Meg x 8 60-ball, 11x13 ZCFCF DCFCF
MT48LC16M8A2FC-7E 16 Meg x 8 60-ball, 11x13 ZCFCN DCFCN
MT48LC16M8A2FB-75 16 Meg x 8 60-ball, 8x16 ZBFCF DBFCF
MT48LC16M8A2FB-7E 16 Meg x 8 60-ball, 8x16 ZBFCN DBFCN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.

128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02 59 ©2001, Micron Technology, Inc.