6.

Logical Effort

Jacob Abraham

Department of Electrical and Computer Engineering

The University of Texas at Austin
VLSI Design
Fall 2020

September 15, 2020

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 1 / 31
 Review: See Additional Notes Posted

Calculate the Elmore delay from C to F in the circuit. The widths

of the pass transistors are shown, and the inverters have
minimum-sized

Use the Elmore delay approximation to find the worst-case rise and
fall delays at output F for the following circuit. The gate sizes of
the transistors are shown in the figure. Assume NO sharing of
diffusion regions, and the worst-case conditions for the initial
charge on a node.

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 1 / 31
 Example: Delay with Different Input Sequences
Find the delays for the given input
transitions (gate sizes shown in figure)

Assumptions: diffusion capacitance is

equal to the gate capacitance, the
resistance of an nMOS transistor with
unit width is R and the resistance of a
pMOS transistor with width 2 is also R,
and NO sharing of diffusion regions

Off-path capacitances can contribute to

delay, and if a node does not need to be
charged (or discharged), its capacitance
can be ignored

ABCD = 0101 → ABCD = 1101

ABCD = 1111 → ABCD = 0111
ABCD = 1010 → ABCD = 1101
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 2 / 31
 Delay with Different Input Sequence, Cont’d
Look at the charges on the nodes
at the end of the first input of the
sequence; only the capacitances
of the nodes which would change
with the second vector need to be
considered

ABCD = 0101 →
ABCD = 1101;
Delay = 36RC

ABCD = 1111 →
ABCD = 0111;
Delay = 16RC

ABCD = 1010 →
ABCD = 1101;
Delay = 43RC

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 3 / 31
 Delay Components

Delay has two parts

Parasitic Delay
6 or 7 RC
Independent of Load

Effort Delay
4h RC
Proportional to load capacitance

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 4 / 31
 Contamination Delay

Minimum (Contamination) Delay

Best-case (contamination) delay can be substantially less than
propagation delay
Example, If both inputs fall simultaneously
Important for “hold time” (will see later in the course)

tcdr =
(3 + 2h)RC
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 5 / 31
 Introduction to Logical Effort

Chip designers have to face a bewildering array of choices

What is the best circuit topology for a function?
How many stages of logic give least delay?
How wide should the transistors be?

Logical effort is one method to make these decisions

Uses a simple model of delay
Allows back-of-the-envelope calculations
Helps make rapid comparisons between alternatives
Emphasizes remarkable symmetries

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 6 / 31
 Example
Design the decoder for a register file
Decoder specifications
16 word register file
Each word is 32 bits wide
Each bit presents load of 3 unit-sized transistors
True and complementary address inputs A[3:0]
Each input may drive 10 unit-sized transistors

Need to decide
How many stages to use?
How large should each
gate be?
How fast can decoder
operate?
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 7 / 31
 Delay in a Logic Gate
Express delay in a process-independent unit
τ = 3RC
d= dabs ≈ 12 ps in 180 nm process
τ
40 ps in 0.6 µm process
Delay has two components: d = f + p
Effort delay, f = gh (stage effort)
g: Logical Effort h: Electrical Effort=Cout /Cin
Measures relative ability of Ratio of output to input
gate to deliver current capacitances, sometimes called
g ≡ 1 for inverter fanout effort

Parasitic delay, p
Represents delay of gate driving no load
Set by internal parasitic capacitance

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 8 / 31
 Delay Plots

d=f +p
= gh + p

What about
NOR2?

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 9 / 31
 Computing Logical Effort

Logical effort is the ratio of the input capacitance of a

gate to the input capacitance of an inverter delivering
the same output current
Measure from delay vs. fanout plots
Or, estimate by counting transistor widths

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 10 / 31
 Catalog of Gates

Logical Effort of common gates

Number of inputs
Gate type
1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate/Mux 2 2 2 2 2
XOR, XNOR 4,4 6,12,6 8,16,16,8

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 11 / 31
 Catalog of Gates

Parasitic delay of common gates

In multiples of pinv (≈ 1)

Number of inputs
Gate type
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate/Mux 2 4 6 8 2n
XOR, XNOR 4 6 8

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 12 / 31
 Example: Ring Oscillator

Estimate the frequency of an N-stage ring oscillator

Logical Effort: g = 1 31 stage ring

Electrical Effort: h = 1 oscillator in 0.6
Parasitic Delay: p = 1 µm process has
frequency of
Stage Delay: d = 2
∼ 200 MHz
Frequency: fosc = 1/(2 · N · d) = 1/4N

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 13 / 31
 Example: FO4 Inverter
Estimate the delay of a fanout-of-4 (FO4) inverter

The FO4 delay is about:

Logical Effort: g = 1
200 ps in a 0.6µm process
Electrical Effort: h = 4
60 ps in a 180 nm process
Parasitic Delay: p = 1
f/3 ns in a f µm process
Stage Delay: d = 5
(f/3 ps in a f nm process)
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 14 / 31
 Example Problem
A particular technology node has a FO4 delay of 9 ps. How many
minimum size (2:1) inverters need to be included in a ring
oscillator so that the frequency is close to 7.3 GHz?

FO4 delay = 15RC = 9ps

Stage delay = 6RC = 3.6ps

1
f= =⇒
2×N ×d
1
N=
2×f ×d
1
=
2 × 7.3 × 3.6 × 10−3
= 19.05

Number of inverters = 19
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 15 / 31
 Multistage Logic Networks

Logical effort generalizes to multistage networks

Q
Path Logical Effort, G = gi
C
Path Electrical Effort, H = Cout−path
Q Q in−path
Path Effort, F = fi = gi hi

Can we write F = GH in general?

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 16 / 31
 Consider Paths that Branch

G = 1
H = 90 / 5 = 18
GH = 18
h1 = (15 +15)/5 = 6
h2 = 90/15 = 6
F = g1 g2 h1 h2 = 36 = 2GH

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 17 / 31
 Branching Effort and Multistage Delays

Branching Effort accounts for branching between stages in path

Con path + Cof f path
b=
Con path
Y Y
B= bi (Note : hi = BH)
Now, path effort, F = GBH

Multistage Delays
X
Path Effort Delay, DF = fi
X
Path Parasitic Delay, P = pi
X
Path Delay, D = d i = DF + P

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 18 / 31
 Designing Fast Circuits

X
D= di = DF + P
Delay is smallest when each stage bears same effort
1
fˆ = gi hi = F N
Thus, the minimum delay of an N-stage path is

1
D = NF N + P

This is a key result of logical effort

Find fastest possible delay
Doesn’t require calculating gate sizes

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 19 / 31
 Gate Sizes

How wide should the gates be for the least delay?

Cout
fˆ = gh = g
Cin
gi Couti
=⇒ Cini =
fˆ

Working backward, apply capacitance transformation to find

input capacitance of each gate given load it drives
Check work by verifying input capacitance specification is met

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 20 / 31
 Example: 3-stage Path

Select gate sizes x and y for least delay from A to B

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 21 / 31
 Example: 3-stage Path, Cont’d

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F=√ GBH = 125
Best Stage Effort ˆ
f = 3F =5
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22 = 4.4 FO4

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 22 / 31
 Example: 3-stage Path, Cont’d

Work backward for sizes

y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 23 / 31
 Best Number of Stages
How many stages should a path use?
Minimizing number of stages is not always fastest
Example: drive 64-bit datapath with unit inverter

1
D = NF N + P
1
D = N(64) N + N

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 24 / 31
 Sensitivity Analysis
How sensitive is delay to using exactly the best number of stages?

2.4 < ρ < 6 gives delay within 15% of optimal

We can be sloppy
For example, use ρ = 4
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 25 / 31
 Decoder Example: Number of Stages
16 word, (32 bit) register file
Each bit presents load of 3 unit-sized
transistors
True and complementary address inputs
A[3:0]
Each input may drive 10 unit-sized
transistors
Find: number of stages, sizes of gates, speed
Decoder effort is mainly electrical and branching
Electrical Effort: H = (32*3)/10 = 9.6
Branching Effort: B = 8
If we neglect logical effort (assume G = 1)
Path Effort: F = GBH = 76.8
Number of Stages: N = log4 F = 3.1
Try a 3-stage design
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 26 / 31
 Decoder: Gate Sizes and Delay

Logical Effort: G = 1 * 6/3 * 1 = 2

Path Effort: F = GBH = 154
1
Stage Effort: fˆ = F 3 = 5.36
Path Delay: D = 3fˆ + 1 + 4 + 1 = 22.1
Gate sizes: z = 96*1/5.36 = 18
Gate sizes: y = 18*2/5.36 = 6.7

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 27 / 31
 Decoder: Comparison

Compare many alternatives with a spreadsheet

Design N G P D
NAND4-INV 2 2 5 29.8
NAND2-NOR2 2 20/9 4 30.1
INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
NAND2-INV-NAND2-INV 4 16/9 6 19.7
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 28 / 31
 Review of Definitions

Term Stage Path

Number of stages 1 N
Q
Logical effort g G= gi
Cout Cout−path
Electrical effort h= Cin H= Cin−path
Con−path +Cof f −path Q
Branching effort b= Con−path B= bi
Effort f = gh F = GBH
P
Effort delay f DF = fi
P
Parasitic delay p P = pi
P
Delay d=f+p D= di = DF + P

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 29 / 31
 Method of Logical Effort
1. Compute path effort F = GBH
2. Estimate best number of stages N = log4 F
3. Sketch path with N stages
1
4. Estimate least delay D = NF N + P
1
5. Determine best stage effort fˆ = F N
6. Find gate sizes Cin = gi Cfout

Limits of logical effort

Chicken and egg problem
Need path to compute G
But, don’t know number of stages without G
Simplistic delay model, neglects input rise time effects
Interconnect
Iteration required in designs with significant wires
Maximum speed only
Not minimum area/power for constrained delay

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 30 / 31
 Summary of Logical Effort

Logical effort is useful for thinking of delay in circuits

Numeric logical effort characterizes gates
NANDs are faster than NORs in CMOS
Paths are fastest when effort delays are ∼4
Path delay is weakly sensitive to stages, sizes
But using fewer stages doesn’t mean faster paths
Delay of path is about log4 F FO4 inverter delays
Inverters and NAND2 best for driving large caps
Provides language for discussing fast circuits, but requires
practice to master

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob Abraham, September 15, 2020 31 / 31