a Four-Channel, Four-Quadrant

Analog Multiplier
MLT04
FEATURES FUNCTIONAL BLOCK DIAGRAM
Four Independent Channels 18-Lead Epoxy DIP (P Suffix)
Voltage IN, Voltage OUT 18-Lead Wide Body SOIC (S Suffix)
No External Parts Required
8 MHz Bandwidth W1 1 18 W4
Four-Quadrant Multiplication
Voltage Output; W = (X × Y)/2.5 V GND1 2 17 GND4

0.2% Typical Linearity Error on X or Y Inputs X1 3 16 X4

Excellent Temperature Stability: 0.005% Y1 4 15 Y4
±2.5 V Analog Input Range MLT-04
MLT04
917
8
7
6
5
4
3
2
110
11
12
13
14
15
16
8
Operates from ±5 V Supplies V
CC
5 14 V
EE

Low Power Dissipation: 150 mW typ Y2 6 13 Y3

Spice Model Available X2 7 12 X3

APPLICATIONS GND2 8 11 GND3

Geometry Correction in High-Resolution CRT Displays W2 9 10 W3
Waveform Modulation & Generation
Voltage Controlled Amplifiers W = (X • Y)/2.5V
Automatic Gain Control
Modulation and Demodulation

GENERAL DESCRIPTION Fabricated in a complementary bipolar process, the MLT04

The MLT04 is a complete, four-channel, voltage output analog includes four 4-quadrant multiplying cells which have been laser-
multiplier packaged in an 18-pin DIP or SOIC-18. These complete trimmed for accuracy. A precision internal bandgap reference
multipliers are ideal for general purpose applications such as voltage normalizes signal computation to a 0.4 scale factor. Drift over
controlled amplifiers, variable active filters, “zipper” noise free temperature is under 0.005%/°C. Spot noise voltage of 0.3 µV/√Hz
audio level adjustment, and automatic gain control. Other applica- results in a THD + Noise performance of 0.02% (LPF = 22 kHz)
tions include cost-effective multiple-channel power calculations for the lower distortion Y channel. The four 8 MHz channels
(I × V), polynomial correction generation, and low frequency consume a total of 150 mW of quiescent power.
modulation. The MLT04 multiplier is ideally suited for generating The MLT04 is available in 18-pin plastic DIP, and SOIC-18
complex, high-order waveforms especially suitable for geometry surface mount packages. All parts are offered in the extended
correction in high-resolution CRT display systems. industrial temperature range (–40°C to +85°C).

100

40
V CC = +5V VCC = +5V
V EE = –5V V = –5V
10 EE
T A = +25°C TA = +25°C
20 90
Ø – Phase Degrees

THD + NOISE – %
Av GAIN – dB

8.9MHz
Av (X OR Y) –3dB
0 0 1
LPF = 500kHz

THDX: X = 2.5VP, Y = +2.5V DC

Ø (X OR Y)
–20 –90
X & Y MEASUREMENTS 0.1
SUPERIMPOSED:
THDY: Y = 2.5VP, X = +2.5V DC
X = 100mV RMS, Y = 2.5V DC
–40 Y = 100mV RMS, X = 2.5V DC
0.01
1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M
FREQUENCY – Hz FREQUENCY – Hz

Figure 1. Gain & Phase vs. Frequency Response Figure 2. THD + Noise vs. Frequency

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
MLT04–SPECIFICATIONS (V CC = +5 V, VEE = –5 V, VIN = ±2.5 VP, RL = 2 kΩ, TA = +25°C unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Units

MULTIPLIER PERFORMANCE 1
Total Error2 X EX –2.5 V < X < +2.5 V, Y = +2.5 V –5 ±2 5 % FS
Total Error2 Y EY –2.5 V < Y < +2.5 V, X = +2.5 V –5 ±2 5 % FS
Linearity Error2 X LEX –2.5 V < X < +2.5 V, Y = +2.5 V –1 ± 0.2 +1 % FS
Linearity Error2 Y LEY –2.5 V < Y < +2.5 V, X = +2.5 V –1 ± 0.2 +1 % FS
Total Error Drift TCEX X = –2.5 V, Y = 2.5 V, TA = –40°C to +85°C 0.005 %/°C
Total Error Drift TCEY Y = –2.5 V, X = 2.5 V, TA = –40°C to +85°C 0.005 %/°C
Scale Factor3 K X = ± 2.5 V, Y = ± 2.5 V, TA = –40°C to +85°C 0.38 0.40 0.42 1/V
Output Offset Voltage ZOS X = 0 V, Y = 0 V, TA= –40°C to +85°C –50 ± 10 50 mV
Output Offset Drift TCZOS X = 0 V, Y = 0 V, TA= –40°C to +85°C 50 µV/°C
Offset Voltage, X XOS X = 0 V, Y = ± 2.5 V, TA = –40°C to +85°C –50 ± 10.5 50 mV
Offset Voltage, Y YOS Y = 0 V, X = ± 2.5 V, TA = –40°C to +85°C –50 ± 10.5 50 mV
DYNAMIC PERFORMANCE
Small Signal Bandwidth BW VOUT = 0.1 V rms 8 MHz
Slew Rate SR VOUT = ± 2.5 V 30 53 V/µs
Settling Time tS VOUT = ∆2.5 V to 1% Error Band 1 µs
AC Feedthrough FTAC X = 0 V, Y = 1 V rms @ f = 100 kHz –65 dB
Crosstalk @ 100 kHz CTAC X = Y = 1 V rms Applied to Adjacent Channel –90 dB
OUTPUTS
Audio Band Noise EN f = 10 Hz to 50 kHz 76 µV rms
Wide Band Noise EN Noise BW = 1.9 MHz 380 µV rms
Spot Noise Voltage eN f = 1 kHz 0.3 µV/√Hz
Total Harmonic Distortion THDX f = 1 kHz, LPF = 22 kHz, Y = 2.5 V 0.1 %
THDY f = 1 kHz, LPF = 22 kHz, X = 2.5 V 0.02 %
Open Loop Output Resistance ROUT 40 Ω
Voltage Swing VPK VCC = +5 V, VEE = –5 V ± 3.0 ± 3.3 VP
Short Circuit Current ISC 30 mA
INPUTS
Analog Input Range IVR GND = 0 V –2.5 +2.5 V
Bias Current IB X=Y=0V 2.3 10 µA
Resistance RIN 1 MΩ
Capacitance CIN 3 pF
SQUARE PERFORMANCE
Total Square Error ESQ X=Y=1 5 % FS
POWER SUPPLIES
Positive Current ICC VCC = 5.25 V, VEE = –5.25 V 15 20 mA
Negative Current IEE VCC = 5.25 V, VEE = –5.25 V 15 20 mA
Power Dissipation PDISS Calculated = 5 V × ICC + 5 V × IEE 150 200 mW
Supply Sensitivity PSSR X = Y = 0 V, VCC = ∆5% or VEE = ∆5% 10 mV/V
Supply Voltage Range VRANGE For VCC & VEE ± 4.75 ± 5.25 V
NOTES
1
Specifications apply to all four multipliers.
2
Error is measured as a percent of the ± 2.5 V full scale, i.e., 1% FS = 25 mV.
3
Scale Factor K is an internally set constant in the multiplier transfer equation W = K × X × Y.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS* ORDERING INFORMATION*

Supply Voltages VCC, VEE to GND ±7 V
Inputs XI, YI VCC, VEE Temperature Package Package
Outputs WI VCC, VEE Model Range Description Option
Operating Temperature Range –40°C to +85°C
MLT04GP –40°C to +85°C 18-Pin P-DIP N-18
Maximum Junction Temperature (T J max) +150°C
MLT04GS –40°C to +85°C 18-Lead SOIC SOL-18
Storage Temperature –65°C to +150°C
MLT04GS-REEL –40°C to +85°C 18-Lead SOIC SOL-18
Lead Temperature (Soldering, 10 sec) +300°C
MLT04GBC +25°C Die
Package Power Dissipation (TJ max–TA)/θJA
Thermal Resistance θJA *For die specifications contact your local Analog sales office. The MLT04
PDIP-18 (N-18) 74°C/W contains 211 transistors.
SOIC-18 (SOL-18) 89°C/W
*Stresses above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification are not implied.

–2– REV. B
 MLT04
FUNCTIONAL DESCRIPTION ANALOG MULTIPLIER ERROR SOURCES
The MLT04 is a low cost quad, 4-quadrant analog multiplier with Multiplier errors consist primarily of input and output offsets, scale
single-ended voltage inputs and voltage outputs. The functional factor errors, and nonlinearity in the multiplying core. An expres-
block diagram for each of the multipliers is illustrated in Figure 3. sion for the output of a real analog multiplier is given by:
Due to packaging constraints, access to internal nodes for externally
adjusting scale factor, output offset voltage, or additional summing V O = ( K + ∆K ){(VX + X OS )(V Y + Y OS ) + ZOS + f ( X , Y )}
signals is not provided. where: K = Multiplier Scale Factor
+VS ∆K = Scale Factor Error
VX = X-Input Signal
X1, X2, X3, X4 MLT04 XOS = X-Input Offset Voltage
VY = Y-Input Signal
G1, G2, G3, G4 0.4 W1, W2, W3, W4
YOS = Y-Input Offset Voltage
ZOS = Multiplier Output Offset Voltage
ƒ(X, Y) = Nonlinearity
Y1, Y2, Y3, Y4
Executing the algebra to simplify the above expression yields
–VS expressions for all the errors in an analog multiplier:
Figure 3. Functional Block Diagram of Each MLT04
Multiplier
Term Description Dependence on Input
Each of the MLT04’s analog multipliers is based on a Gilbert cell KVXVY True Product Goes to Zero As Either or
multiplier configuration, a 1.23 V bandgap reference, and a unity- Both Inputs Go to Zero
connected output amplifier. Multiplier scale factor is determined ∆KVYVY Scale-Factor Error Goes to Zero at VX, VY = 0
through a differential pair/trimmable resistor network external to
the core. An equivalent circuit for each of the multipliers is shown VXYOS Linear “X” Feedthrough Proportional to VX
in Figure 4. Due to Y-Input Offset
VYXOS Linear “Y” Feedthrough Proportional to VY
VCC Due to X-Input Offset
XOSYOS Output Offset Due to X-, Independent of VX, VY
W Y-Input Offsets
INTERNAL OUT
BIAS
ZOS Output Offset Independent of VX, VY
ƒ(X, Y) Nonlinearity Depends on Both V X, VY.
Contains Terms Dependent
XIN 22k
22k 22k SCALE on VX, VY, Their Powers
FACTOR and Cross Products
GND
YIN
200µA 200µA 200µA 200µA 200µA 200µA
VEE
As shown in the table, the primary static errors in an analog
multiplier are input offset voltages, output offset voltage, scale
Figure 4. Equivalent Circuit for the MLT04 factor, and nonlinearity. Of the four sources of error, only two are
externally trimmable in the MLT04: the X- and Y-input offset
Details of each multiplier’s output-stage amplifier are shown in voltages. Output offset voltage in the MLT04 is factory-trimmed to
Figure 5. The output stages idles at 200 µA, and the resistors in ± 50 mV, and the scale factor is internally adjusted to ± 2.5% of full
series with the emitters of the output stage are 25 Ω. The output scale. Input offset voltage errors can be eliminated by using the
stage can drive load capacitances up to 500 pF without oscillation. optional trim circuit of Figure 6. This scheme then reduces the net
For loads greater than 500 pF, the outputs of the MLT04 should error to output offset, scale-factor (gain) error, and an irreducible
be isolated from the load capacitance with a 100 Ω resistor. nonlinearity component in the multiplying core.
VCC +VS

50kΩ I
±100mV
50kΩ FOR XOS, YOS TRIM
25Ω
CONNECT TO SUM
W NODE OF AN EXT OP AMP
OUT
25Ω –VS

Figure 6. Optional Offset Voltage Trim Configuration

VEE

Figure 5. Equivalent Circuit for MLT04 Output Stages

REV. B –3–
MLT04
Feedthrough
In the ideal case, the output of the multiplier should be zero if
100
either input is zero. In reality, some portion of the nonzero input

VERTICAL – 5mV/DIV
90
will “feedthrough” the multiplier and appear at the output. This is
caused by the product of the nonzero input and the offset voltage of
the “zero” input. Introducing an offset equal to and opposite of the
“zero” input offset voltage will null the linear component of the X-INPUT: ±2.5V @ 10Hz
feedthrough. Residual feedthrough at the output of the multiplier 10
Y-INPUT: +2.5V
YOS NULLED
0%
is then irreducible core nonlinearity. T = +25°C
A

Typical X- and Y-input feedthrough curves for the MLT04 are

shown in Figures 7 and 8, respectively. These curves illustrate HORIZONTAL – 0.5V/DIV
MLT04 feedthrough after “zero” input offset voltage trim.
Residual X-input feedthrough measures 0.08% of full scale, Figure 9. X-Input Nonlinearity @ Y = +2.5 V
whereas residual Y-input feedthrough is almost immeasurable.

X-INPUT: ±2.5V @ 10Hz

100 YOS NULLED 100
VERTICAL – 5mV/DIV

VERTICAL – 5mV/DIV
90 TA = +25°C 90

X-INPUT: ±2.5V @ 10Hz

10 10
Y-INPUT: –2.5V
0%
YOS NULLED
0%
T = +25°C
A

HORIZONTAL – 0.5V/DIV HORIZONTAL – 0.5V/DIV

Figure 7. X-Input Feedthrough with YOS Nulled Figure 10. X-Input Nonlinearity @ Y = –2.5 V

Y-INPUT: ±2.5V @ 10Hz

Y-INPUT: ±2.5V @ 10Hz
X-INPUT: +2.5V
100 XOS NULLED 100
XOS NULLED
VERTICAL – 5mV/DIV

90
VERTICAL – 5mV/DIV

90 TA = +25°C
TA = +25°C

10 10

0% 0%

HORIZONTAL – 0.5V/DIV HORIZONTAL – 0.5V/DIV

Figure 8. Y-Input Feedthrough with XOS Nulled Figure 11. Y-Input Nonlinearity @ X = +2.5 V

Nonlinearity
Y-INPUT: ±2.5V @ 10Hz
Multiplier core nonlinearity is the irreducible component of error. 100
X-INPUT: –2.5V
XOS NULLED
It is the difference between actual performance and “best-straight-
VERTICAL – 5mV/DIV

90
T = +25°C
A
line” theoretical output, for all pairs of input values. It is expressed
as a percentage of full scale with all other dc errors nulled. Typical
X- and Y-input nonlinearities for the MLT04 are shown in Figures
9 through 12. Worst-case X-input nonlinearity measured less than
10
0.2%, and Y-input nonlinearity measured better than 0.06%. For 0%
modulator/demodulator or mixer applications it is, therefore,
recommended that the carrier be connected to the X-input while
the signal is applied to the Y-input. HORIZONTAL – 0.5V/DIV

Figure 12. Y-Input Nonlinearity @ X = –2.5 V

–4– REV. B
 Typical Performance Characteristics – MLT04

12 180
TA = +25°C
9 V = ±5V 135
S
VX = 100mV
6 VY = +2.5V 90
OUTPUT NOISE VOLTAGE – 100µV/DIV

PHASE – Degrees
NBW = 10Hz –50kHz 3 45

GAIN –dB
100
TA = +25°C GAIN
90 0 0

–3 –45
PHASE
–6 –90

10 –9 PHASE = 68.3° –135

0% @ 7.142 MHz
–12 –180
10k 100k 1M 10M
TIME = 10ms/DIV FREQUENCY – Hz

Figure 13. Broadband Noise Figure 16. X-Input Gain and Phase vs. Frequency

12 180
T A = +25°C
9 V S = ±5V 135
V X = +2.5V
6 V Y = 100mV 90
OUTPUT NOISE VOLTAGE – 625µV/DIV

PHASE – Degrees
NBW = 1.9MHz 3 45
TA = +25°C
GAIN –dB

100
GAIN
90
0 0

–3 –45
PHASE
–6 –90

10
0%
–9 PHASE = 68.1° –135
@ 8.064 MHz
–12 –180
10k 100k 1M 10M
TIME = 10ms/DIV FREQUENCY – Hz

Figure 14. Broadband Noise Figure 17. Y-Input Gain and Phase vs. Frequency

10000 8

6
VS = ±5V CL= 320pF
CL= 560pF
TA = +25°C 4
CL= 220pF
Hz

2
1000
NOISE DENSITY – nV/

AV GAIN – dB

–2 NO CL
–4 CL= 100pF
100
–6
VS = ±5V
–8 RL = 2kΩ
TA = +25°C
–10

0 –12
10 100 1k 10k 100k 1M 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz FREQUENCY – Hz

Figure 15. Noise Density vs. Frequency Figure 18. Amplitude Response vs. Capacitive Load

REV. B –5–
MLT04 – Typical Performance Characteristics
0

ΩX-INPUT = +2.5V
VS = ±5V
100
RL = 10kΩ
TA = +25°C

VERTICAL – 50mV/DIV
–20 90 TA = +25°C
FEEDTHROUGH – dB

–40 VX = 0V
VY = 1Vpk

10
–60 0%

VY = 0V
–80 VX = 1Vpk
TIME – 100ns/DIV

–100 Figure 22. Y-Input Small-Signal Transient Response,

1k 10k 100k 1M 3M
FREQUENCY – Hz
CL = 30 pF

Figure 19. Feedthrough vs. Frequency ΩX-INPUT = +2.5V

100 RL = 10kΩ

VERTICAL – 50mV/DIV
90 TA = +25°C

0
TA = 25°C
VS = ±5V
–20 VX = ±2.5Vpk
VY = +2.5VDC 10
0%
CROSSTALK – dB

–40

–60 TIME – 100ns/DIV

–80 Figure 23. Y-Input Small-Signal Transient Response,

CL = 100 pF
–100

–120
100
1k 10k 100k 1M 10M
90
VERTICAL – 1V/DIV

FREQUENCY – Hz

Figure 20. Crosstalk vs. Frequency

10
ΩX-INPUT: +2.5V
0% RL = 10kΩ
2.0
TA = +25°C
1.5 ΩVS = ±5V
RL = 2kΩ
1.0 TA = +25°C TIME = 100ns/DIV
Y = 100mV RMS
X = 2.5VDC
0.5
Figure 24. Y-Input Large-Signal Transient Re-
AV GAIN – dB

0 sponse, CL = 30 pF
–0.5 X = 100mV RMS
Y = 2.5VDC
–1.0

–1.5 100
90
VERTICAL – 1V/DIV

–2.0

–2.5

–3.0
1k 10k 100k 1M 10M 100M
FREQUENCY – Hz ΩX-INPUT: +2.5V
10
0%
RL = 10kΩ
TA = +25°C
Figure 21. Gain Flatness vs. Frequency
TIME = 100ns/DIV

Figure 25. Y-Input Large-Signal Transient Response,

CL = 100 pF

–6– REV. B
 MLT04
1 9 80
VS = ±5V
VX = +2.5V
X-INPUT
Y = +2.5VDC V = 100mV
Y

PHASE @ –3dB BW – Degrees

8 75

–3dB-BANDWIDTH – MHz
0.1 –3dB BW
THD + NOISE – %

7 70
ΩVS = ±5V
RL = 2kΩ
0.01 T A = +25° C
PHASE @ –3dB BW
fO = 1kHz
6 65
FLPF = 22kHz
Y-INPUT
X = +2.5VDC

0.001 5 60
0.1 1 10 –75 –50 –25 0 25 50 75 100 125
INPUT SIGNAL LEVEL – Volts P-P TEMPERATURE – °C

Figure 26. THD + Noise vs. Input Signal Level Figure 29. Y-Input Gain Bandwidth vs. Temperature

0.3 8
≤V = +2.5V, –2.5V ≤ V ≤ +2.5V
X Y Vs = ±5V
V = +2.5V, –2.5V ≤ V ≤ +2.5V

MAXIMUM OUTPUT SWING – Volts p-p

Y X 7
0.2

6
LINEARTY ERROR – %

0.1 1%
DISTORTION
5

0 4

3
–0.1

2 ΩTA = +25°C
–0.2 RL = 2kΩ
1 VS = ±5V

–0.3 0
–75 –50 –25 0 25 50 75 100 125 1k 10k 100k 1M 10M
TEMPERATURE – °C FREQUENCY – Hz

Figure 27. Linearity Error vs. Temperature Figure 30. Maximum Output Swing vs. Frequency

9 80 4.5
V = ±5V
S
V = 100mV 4.0
X
V = +2.5V
Y POSITIVE SWING
3.5
PHASE @ –3dB BW – Degrees

8 75
–3dB-BANDWIDTH – MHz

OUTPUT SWING – Volts

3.0

–3dB BW
2.5
7 70
2.0
NEGATIVE SWING
PHASE @ –3dB BW 1.5

6 65
1.0
VS = ±5V
0.5 TA = +25°C

5 60 0
–75 –50 –25 0 25 50 75 100 125 10 100 1k 10k
TEMPERATURE – °C ΩLOAD RESISTANCE – Ω

Figure 28. X-Input Gain Bandwidth vs. Temperature Figure 31. Maximum Output Swing vs. Resistive Load

REV. B –7–
MLT04

300 0.407
SS = 1000 MULTIPLIERS TA = +25°C VS = ±5V
V = ±5V NO LOAD
S
250 X = ±2.5V 0.406

SCALE FACTOR – 1/V

200 YOS @ X = ±2.5V
0.405
XOS @ Y = ±2.5V
UNITS

150

0.404
100

0.403
50

0 0.402
–12.5 –10 –7.5 –5 –2.5 0 2.5 5 7.5 10 12.5 –75 –50 –25 0 25 50 75 100 125
OFFSET VOLTAGE – mV TEMPERATURE – °C

Figure 32. Offset Voltage Distribution Figure 35. Scale Factor vs. Temperature

400
6
T = +25°C
VS = ±5V A
350 SS = 1000
MULTIPLIERS VS = ±5V
4 VX = VY = 0V
XOS, Y = ±2.5V 300

2
250
VOS – mV

UNITS

0 200

150
–2
YOS, X = ±2.5V 100

–4
50

0
–6
–75 –50 –25 0 25 50 75 100 125 –15 –12 –9 –6 –3 0 3 6 9 12 15
TEMPERATURE – °C OUTPUT OFFSET VOLTAGE – mV

Figure 33. Offset Voltage vs. Temperature Figure 36. Output Offset Voltage (ZOS) Distribution

400 10
SS = 1000 MULTIPLIERS
TA = +25°C V = ±5V
350 s
VS = ±5V
OUTPUT OFFSET VOLTAGE – mV

300 5

250
UNITS

200 0

150

100
–5

50

0
–10
0.395 0.3975 0.400 0.4025 0.405 0.4075 0.410 0.4125 0.415 –75 –50 –25 0 25 50 75 100 125
SCALE FACTOR – 1/V TEMPERATURE – °C

Figure 34. Scale Factor Distribution Figure 37. Output Offset Voltage (ZOS) vs. Temperature

–8– REV.B
 MLT04
17 15
VS = ±5V
NO LOAD 12
σX +3σ
VX = VY = 0

OUTPUT VOLTAGE OFFSET – mV

9
16
SUPPLY CURRENT – mA

15 0 X

–3

–6
14
–9

–12 σX –3σ

13 –15
–75 –50 –25 0 25 50 75 100 125 0 200 400 600 800 1000
TEMPERATURE – °C HOURS OF OPERATION AT +125°C

Figure 38. Supply Current vs. Temperature Figure 41. Output Voltage Offset (ZOS) Distribution
Accelerated by Burn-in

100 0.424

TA = +25°C 0.420
VS = ±5V
POWER SUPPLY REJECTION – dB

80 0.416
SCALE FACTOR – 1/V σX +3σ
0.412
+PSRR
60 0.408

0.404 X
–PSRR
0.400
40
0.396
σX –3σ
20 0.392

0.388

0 0.384
100 1k 10k 100k 1M 0 200 400 600 800 1000
FREQUENCY – Hz HOURS OF OPERATION AT +125°C

Figure 39. Power Supply Rejection vs. Frequency Figure 42. Scale Factor (K) Distribution Acceler-
ated by Burn-in

1.25

1.0
σX +3σ
0.75
LINEARITY ERROR – %

0.50

0.25
X
0

–0.25

–0.50

–0.75
σX –3σ
–1.0

–1.25
0 200 400 600 800 1000
HOURS OF OPERATION AT +125°C

Figure 40. Linearity Error (LE) Distribution Accelerated

by Burn-in

REV. B –9–
MLT04
APPLICATIONS The equation shows a dc term at the output which will vary
The MLT04 is well suited for such applications as modulation/ strongly with the amplitude of the input, V IN. The output dc offset
demodulation, automatic gain control, power measurement, analog can be eliminated by capacitively coupling the MLT04’s output
computation, voltage-controlled amplifiers, frequency doublers, with a high-pass filter. For optimal spectral performance, the
and geometry correction in CRT displays. filter’s cutoff frequency should be chosen to eliminate the input
fundamental frequency.
Multiplier Connections
Figure 43 llustrates the basic connections for multiplication. Each A source of error in this configuration is the offset voltages of the X
of the four independent multipliers has single-ended voltage inputs and Y inputs. The input offset voltages produce cross products
(X, Y) and a low impedance voltage output (W). Also, each with the input signal to distort the output waveform. To circum-
multiplier has its own dedicated ground connection (GND) which vent this problem, Figure 45 illustrates the use of inverting
is connected to the circuit’s analog common. For best perfor- amplifiers configured with an OP285 to provide a means by which
mance, circuit layout should be compact with short component the X- and Y-input offsets can be trimmed.
leads and well-bypassed supply voltage feeds. In applications where
fewer than four multipliers are used, all unused analog inputs must ΩP1
50kΩ
be returned to the analog common. –5V +5V
XOS TRIM
ΩR5
500kΩ R2
10k

W1 1 W1 W4 18 W4 R1
10k 3 + 1/4 MLT04
2
2 GND1 GND4 17 A1 1
C1
3 + 100pF
X1 3 X1 X4 16 X4 W1
VIN 2 0.4 1 VO
A1, A2 = 1/2 OP285 ΩRL
Y1 4 Y1 Y4 15 Y4
MLT04 10kΩ
5 +
+5V 5 VCC 17
1
10
11
12
13
14
15
16
98
8
7
6
5
4
3
2 VEE 14 –5V A2 7 4 +
R3 6
0.1µF Y2 6 Y2 Y3 13 Y3 0.1µF 10k

X2 7 X2 X3 12 R4
X3 ΩR6 10k
500kΩ
GND2 YOS TRIM
8 GND3 11
–5V +5V
W2 9 W3 10 W3 ΩP2
W2 50kΩ

W1–4 = 0.4 (X1–4 • Y1–4) Figure 45. Frequency Doubler with Input Offset Voltage
Trims
Figure 43. Basic Multiplier Connections
Feedback Divider Connections
Squaring and Frequency Doubling The most commonly used analog divider circuit is the “inverted
As shown in Figure 44, squaring of an input signal, V IN, is achieved multiplier” configuration. As illustrated in Figure 46, an “inverted
by connecting the X-and Y-inputs in parallel to produce an output multiplier” analog divider can be configured with a multiplier
of VIN2/2.5 V. The input may have either polarity, but the output operating in the feedback loop of an operational amplifier. The
will be positive. general form of the transfer function for this circuit configuration is
+5V
given by:
0.1µF
 R2  VIN
VO = −2.5 V ×  ×
 R1  VX
VIN
X + 1/4 MLT04
Here, the multiplier operates as a voltage-controlled potentiometer
GND W that adjusts the loop gain of the op amp relative to a control signal,
0.4 W = 0.4 VIN2
VX. As the control signal to the multiplier decreases, the output of
the multiplier decreases as well. This has the effect of reducing
Y
+ negative feedback which, in turn, decreases the amplifier’s loop
gain. The result is higher closed-loop gain and reduced circuit
0.1µF
bandwidth. As VX is increased, the output of the multiplier
increases which generates more negative feedback — closed-loop
–5V
gain drops and circuit bandwidth increases. An example of an
“inverted multiplier” analog divider frequency response is shown in
Figure 44. Connections for Squaring
Figure 47.

When the input is a sine wave given by V IN sin ωt, the squaring
circuit behaves as a frequency doubler because of the trigonometric
identity:

(VIN sin ωt )2 V 2  1
= IN   (1 − cos 2 ωt )
2.5V 2.5V  2 

–10– REV. B
 MLT04
1/4 MLT04 X1 1/4 MLT04 X1
+ 3 3
+
VX
D1
1N4148
W1 GND1 W1
1 0.4 2 1 0.4 2

R2
10k R2
Y1 10k Y1
+ 4 4
R1 R1
10k 10k
VIN 2 V 2
IN
OP113 6 VO OP113 6 V
O
3 + 3 +
VIN
VO = –2.5V • VO = –2.5V • VIN
VX

Figure 46. “Inverted-Multiplier” Configuration for

Voltage-Controlled Low-Pass Filter
Analog Division
The circuit in Figure 49 illustrates how to construct a voltage-
controlled low-pass filter with an analog multiplier. The advantage
90 with this approach over conventional active-filter configurations is
80 AVOL that the overall characteristic cut-off frequency, ωO, will be directly
OP113 proportional to a multiplying input voltage. This permits the
70
construction of filters in which the capacitors are adjustable
60 (directly or inversely) by a control voltage. Hence, the frequency
50 scale of a filter can be manipulated by means of a single voltage
GAIN – dB

VX = 0.025V
40
without affecting any other parameters. The general form of the
circuit’s transfer function is given by:
30

20
VX = 0.25V
 
 
VO  R2   1 
= −
10
 
 R1    R2 + R1   2.5RC 
VX = 2.5V
VIN 
0
+
  R1   VX 
s 1

100 1k 10k 100k 1M 10M
 
FREQUENCY – Hz
In this circuit, the ratio of R2 to R1 sets the passband gain, and the
break frequency of the filter, ωLP, is given by:
Figure 47. Signal-Dependent Feedback Makes Variables
Out of Amplifier Bandwidth and Stability  R1   VX 
ωLP =   
 R1 + R2   2.5RC 
Although this technique works well with almost any operational
amplifier, there is one caveat: for best circuit stability, the unity-
gain crossover frequency of the operational amplifier should be
equal to or less than the MLT04’s 8 MHz bandwidth. X1
3 1/4 MLT04
+
+
Connection for Square Rooting VX
C
R
Another application of the “inverted multiplier” configuration is the GND1 W1 10k
80pF
square-root function. As shown in Figure 48, both inputs of the 2 0.4 1

MLT04 are wired together and are used as the output of the
2
circuit. Because the circuit configuration exhibits the following 1 VO
A1
generalized transfer function: + 3 +
R1 4 R2
 R2  10k Y1 10k A1 = 1/2 OP285
VO = −2.5 ×   ×VIN
 R1 
VIN
VO 1
=–
the input signal voltage is limited to the range –2.5 V ≤ VIN < 0. To VIN
1+S
5RC
VX
prevent circuit latchup due to positive feedback or input signal
VX
polarity reversal, a 1N4148-type junction diode is used in series fLP = ; fLP = MAX @ VX = 2.5V
with the output of the multiplier. π10πRC

Figure 48. Connections for Square Rooting Figure 49. A Voltage-Controlled Low-Pass Filter
For example, if R1 = R2 = 10 kΩ , R = 10 kΩ , and C = 80 pF,

REV. B –11–
MLT04
then the output of the circuit has a pole at frequencies from 1 kHz OUTLINE DIMENSIONS
to 100 kHz for VX ranging from 25 mV to 2.5 V. The performance Dimensions shown in inches and (mm).
of this low-pass filter is illustrated in Figure 20.
18-Lead Epoxy DIP (P Suffix)

30 18 10

C1845–18–10/93
0.280 (7.11)
PIN 1 0.240 (6.10)
20 1 9

0.925 (23.49) 0.325 (8.25)

10 0.845 (21.47) 0.015
0.300 (7.62)
(0.38)
GAIN – dB

0.210 MIN
(5.33)
0 MAX
0.130
0.160 (4.06) (3.30)
0.115 (2.93) MIN
15°
– 10 V = 0.025V 0.25V 2.5V 0.015 (0.38)
X 0°
0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.20)
0.014 (0.356) (2.54) 0.045 (1.15) PLANE
BSC
– 20

– 30
10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz 18-Lead Wide-Body SOL (S Suffix)
Figure 50. Low-Pass Cutoff Frequency vs. Control
Voltage, VX
18 10
With this approach, it is possible to construct parametric biquad
0.2992 (7.60)
filters whose parameters (center frequency, passband gain, and Q) 0.2914 (7.40)
can be adjusted with dc control voltages. 0.4193 (10.65)
0.3937 (10.00)
PIN 1
1 9

0.4625 (11.75) 0.1043 (2.65)

0.4469 (11.35) 0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)

8° 0.0500 (1.27)
0.0118 (0.30) 0.0192 (0.49) 0° 0.0157 (0.40)
0.0500 (1.27) 0.0125 (0.32)
0.0040 (0.10) BSC 0.0138 (0.35)
0.0091 (0.23)

PRINTED IN U.S.A.

–12– REV. B