a Internally Trimmed

Precision IC Multiplier
AD534
FEATURES PIN CONFIGURATIONS
Pretrimmed to ⴞ0.25% max 4-Quadrant Error (AD534L)
TO-100 (H-10A) TO-116 (D-14)
All Inputs (X, Y and Z) Differential, High Impedance for
Package Package
[(X1 – X 2) (Y 1 – Y 2 )/10 V] + Z2 Transfer Function
Scale-Factor Adjustable to Provide up to X100 Gain X1
Low Noise Design: 90 ␮V rms, 10 Hz–10 kHz X2 +VS
X1 1 14 +VS

Low Cost, Monolithic Construction X2 2 13 NC

Excellent Long Term Stability SF AD534 OUT NC 3 12 OUT

AD534
TOP VIEW SF 4 TOP VIEW 11 Z1
APPLICATIONS (Not To Scale) (Not to Scale) 10 Z2
Y1 Z1 NC 5
High Quality Analog Signal Processing
Y1 6 9 NC
Differential Ratio and Percentage Computations
Y2 Z2 Y2 7 –VS
Algebraic and Trigonometric Function Synthesis –VS
8

Wideband, High-Crest rms-to-dc Conversion NC = NO CONNECT

Accurate Voltage Controlled Oscillators and Filters
Available in Chip Form LCC (E-20A)
Package

+VS
PRODUCT DESCRIPTION

NC

NC
X1
X2
The AD534 is a monolithic laser trimmed four-quadrant multi- 3 2 1 20 19
plier divider having accuracy specifications previously found
only in expensive hybrid or modular products. A maximum NC 4 18 OUT
multiplication error of ± 0.25% is guaranteed for the AD534L NC 5 17 NC
without any external trimming. Excellent supply rejection, low AD534
SF 6 TOP VIEW 16 Z1
temperature coefficients and long term stability of the on-chip (Not To Scale)
NC 7 15 NC
thin film resistors and buried Zener reference preserve accuracy
even under adverse conditions of use. It is the first multiplier to NC 8 14 Z2

offer fully differential, high impedance operation on all inputs,

including the Z-input, a feature which greatly increases its flex- 9 10 11 12 13
Y1

Y2

–VS
NC

NC
ibility and ease of use. The scale factor is pretrimmed to the
standard value of 10.00 V; by means of an external resistor, this NC = NO CONNECT

can be reduced to values as low as 3 V.

such as those used to generate sine and tangent. The utility of
The wide spectrum of applications and the availability of several this feature is enhanced by the inherent low noise of the AD534:
grades commend this multiplier as the first choice for all new 90 µV, rms (depending on the gain), a factor of 10 lower than
designs. The AD534J (± 1% max error), AD534K (± 0.5% max) previous monolithic multipliers. Drift and feedthrough are also
and AD534L (± 0.25% max) are specified for operation over the substantially reduced over earlier designs.
0°C to +70°C temperature range. The AD534S (±1% max) and
AD534T (± 0.5% max) are specified over the extended tempera- UNPRECEDENTED FLEXIBILITY
ture range, –55°C to +125°C. All grades are available in her- The precise calibration and differential Z-input provide a degree
metically sealed TO-100 metal cans and TO-116 ceramic DIP of flexibility found in no other currently available multiplier.
packages. AD534J, K, S and T chips are also available. Standard MDSSR functions (multiplication, division, squaring,
square-rooting) are easily implemented while the restriction to
PROVIDES GAIN WITH LOW NOISE particular input/output polarities imposed by earlier designs has
The AD534 is the first general purpose multiplier capable of been eliminated. Signals may be summed into the output, with
providing gains up to X100, frequently eliminating the need for or without gain and with either a positive or negative sense.
separate instrumentation amplifiers to precondition the inputs. Many new modes based on implicit-function synthesis have
The AD534 can be very effectively employed as a variable gain been made possible, usually requiring only external passive
differential input amplifier with high common-mode rejection. components. The output can be in the form of a current, if
The gain option is available in all modes, and will be found to desired, facilitating such operations as integration.
simplify the implementation of many function-fitting algorithms

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD534–SPECIFICATIONS (@ T = + 25ⴗC, ⴞV = 15 V, R ≥ 2 k⍀) A S

Model AD534J AD534K AD534L

Min Typ Max Min Typ Max Min Typ Max Units
MULTIPLIER PERFORMANCE ( X1 – X 2 )(Y1 – Y 2 ) ( X1 – X 2 )(Y1 – Y 2 ) ( X1 – X 2 )(Y1 – Y 2 )
Transfer Function + Z2 + Z2 + Z2
10 V 10 V 10 V
Total Error 1 (–10 V ≤ X, Y ≤ +10 V) ⴞ1.0 ⴞ0.5 ⴞ0.25 %
TA = min to max ±1.5 ± 1.0 ± 0.5 %
Total Error vs. Temperature ±0.022 ± 0.015 ± 0.008 %/°C
Scale Factor Error
(SF = 10.000 V Nominal) 2 ±0.25 ± 0.1 ± 0.1 %
Temperature-Coefficient of
Scaling Voltage ±0.02 ± 0.01 ± 0.005 %/°C
Supply Rejection (± 15 V ± 1 V) ±0.01 ± 0.01 ± 0.01 %
Nonlinearity, X (X = 20 V p-p, Y = 10 V) ±0.4 ± 0.2 ⴞ0.3 ± 0.10 ⴞ0.12 %
Nonlinearity, Y (Y = 20 V p-p, X = 10 V) ±0.2 ± 0.1 ⴞ0.1 ± 0.005 ⴞ0.1 %
Feedthrough 3, X (Y Nulled,
X = 20 V p-p 50 Hz) ±0.3 ± 0.15 ⴞ0.3 ± 0.05 ⴞ0.12 %
Feedthrough 3, Y (X Nulled,
Y = 20 V p-p 50 Hz) ±0.01 ± 0.01 ⴞ0.1 ± 0.003 ⴞ0.1 %
Output Offset Voltage ±5 ⴞ30 ±2 ⴞ15 ±2 ⴞ10 mV
Output Offset Voltage Drift 200 100 100 µV/°C
DYNAMICS
Small Signal BW (V OUT = 0.1 rms) 1 1 1 MHz
1% Amplitude Error (CLOAD = 1000 pF) 50 50 50 kHz
Slew Rate (V OUT 20 p-p) 20 20 20 V/µs
Settling Time (to 1%, ∆VOUT = 20 V) 2 2 2 µs
NOISE
Noise Spectral-Density SF = 10 V 0.8 0.8 0.8 µV/√Hz
SF = 3 V4 0.4 0.4 0.4 µV/√Hz
Wideband Noise f = 10 Hz to 5 MHz 1 1 1 mV/rms
Wideband Noise f = 10 Hz to 10 kHz 90 90 90 µV/rms
OUTPUT
Output Voltage Swing ⴞ11 ⴞ11 ⴞ11 V
Output Impedance (f ≤ 1 kHz) 0.1 0.1 0.1 Ω
Output Short Circuit Current
(R L = 0, T A = min to max) 30 30 30 mA
Amplifier Open Loop Gain (f = 50 Hz) 70 70 70 dB
INPUT AMPLIFIERS (X, Y and Z) 5
Signal Voltage Range (Diff. or CM ±10 ± 10 ± 10 V
Operating Diff.) ±12 ± 12 ± 12 V
Offset Voltage X, Y ±5 ⴞ20 ±2 ⴞ10 ±2 ⴞ10 mV
Offset Voltage Drift X, Y 100 50 50 µV/°C
Offset Voltage Z ±5 ⴞ30 ±2 ⴞ15 ±2 ± 10 mV
Offset Voltage Drift Z 200 100 100 µV/°C
CMRR 60 80 70 90 70 90 dB
Bias Current 0.8 2.0 0.8 2.0 0.8 2.0 µA
Offset Current 0.1 0.1 0.05 0.2 µA
Differential Resistance 10 10 10 MΩ
DIVIDER PERFORMANCE ( Z 2 − Z1 ) ( Z 2 − Z1 ) ( Z 2 − Z1 )
Transfer Function (X1 > X2) 10 V + Y1 10 V + Y1 10 V + Y1
( X1 − X 2 ) ( X1 − X 2 ) ( X1 − X 2 )
Total Error 1 (X = 10 V, –10 V ≤ Z ≤ +10 V) ±0.75 ± 0.35 ± 0.2 %
(X = 1 V, –1 V ≤ Z ≤ +1 V) ±2.0 ± 1.0 ± 0.8 %
(0.1 V ≤ X ≤ 10 V, –10 V ≤ Z ≤ 10 V) ±2.5 ± 1.0 ± 0.8 %
SQUARE PERFORMANCE ( X1 − X 2 )2 ( X1 − X 2 )2 ( X1 − X 2 )2
Transfer Function + Z2 + Z2 + Z2
10 V 10 V 10 V
Total Error (–10 V ≤ X ≤ 10 V) ±0.6 ± 0.3 ± 0.2 %
SQUARE-ROOTER PERFORMANCE
Transfer Function (Z 1 ≤ Z2) 10 V ( Z 2 − Z1 ) + X 2 10 V ( Z 2 − Z1 ) + X 2 10 V ( Z 2 − Z1 ) + X 2

Total Error 1 (1 V ≤ Z ≤ 10 V) ±1.0 ± 0.5 ± 0.25 %

POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance ±15 ± 15 ± 15 V
Operating ±8 ⴞ18 ±8 ⴞ18 ±8 ⴞ18 V
Supply Current
Quiescent 4 6 4 6 4 6 mA
PACKAGE OPTIONS
TO-100 (H-10A) AD534JH AD534KH AD534LH
TO-116 (D-14) AD534JD AD534KD AD534LD
Chips AD534K Chips
NOTES Specifications shown in boldface are tested on all production units at final electrical
1
Figures given are percent of full scale, ± 10 V (i.e., 0.01% = 1 mV). test. Results from those tests are used to calculate outgoing quality levels. All min and
2
May be reduced down to 3 V using external resistor between –V S and SF. max specifications are guaranteed, although only those shown in boldface are tested
3
Irreducible component due to nonlinearity: excludes effect of offsets. on all production units.
4
Using external resistor adjusted to give SF = 3 V.
5
See Functional Block Diagram for definition of sections.
Specifications subject to change without notic e.

–2– REV. B
 AD534
Model AD534S AD534T
Min Typ Max Min Typ Max Units
MULTIPLIER PERFORMANCE ( X1 – X 2 )(Y1 – Y 2 ) ( X1 – X 2 )(Y1 – Y 2 )
Transfer Function + Z2 + Z2
10 V 10 V
Total Error1 (–10 V ≤ X, Y ≤ +10 V) ⴞ1.0 ⴞ0.5 %
TA = min to max ⴞ2.0 ±1.0 %
Total Error vs. Temperature ⴞ0.02 ⴞ0.01 %/°C
Scale Factor Error
(SF = 10.000 V Nominal)2 ±0.25 ±0.1 %
Temperature-Coefficient of
Scaling Voltage ±0.02 ⴞ0.005 %/°C
Supply Rejection (±15 V ± 1 V) ±0.01 ±0.01 %
Nonlinearity, X (X = 20 V p-p, Y = 10 V) ±0.4 ±0.2 ⴞ0.3 %
Nonlinearity, Y (Y = 20 V p-p, X = 10 V) ±0.2 ±0.1 ⴞ0.1 %
Feedthrough 3, X (Y Nulled,
X = 20 V p-p 50 Hz) ±0.3 ±0.15 ⴞ0.3 %
Feedthrough 3, Y (X Nulled,
Y = 20 V p-p 50 Hz) ±0.01 ±0.01 ⴞ0.1 %
Output Offset Voltage ±5 ±30 ±2 ⴞ15 mV
Output Offset Voltage Drift 500 300 µV/°C
DYNAMICS
Small Signal BW (VOUT = 0.1 rms) 1 1 MHz
1% Amplitude Error (CLOAD = 1000 pF) 50 50 kHz
Slew Rate (VOUT 20 p-p) 20 20 V/µs
Settling Time (to 1%, ∆VOUT = 20 V) 2 2 µs
NOISE
Noise Spectral-Density SF = 10 V 0.8 0.8 µV/√Hz
SF = 3 V 4 0.4 0.4 µV/√Hz
Wideband Noise f = 10 Hz to 5 MHz 1.0 1.0 mV/rms
Wideband Noise f = 10 Hz to 10 kHz 90 90 µV/rms
OUTPUT
Output Voltage Swing ±11 ±11 V
Output Impedance (f ≤ 1 kHz) 0.1 0.1 Ω
Output Short Circuit Current
(RL = 0, TA = min to max) 30 30 mA
Amplifier Open Loop Gain (f = 50 Hz) 70 70 dB
INPUT AMPLIFIERS (X, Y and Z) 5
Signal Voltage Range (Diff. or CM ±10 ±10 V
Operating Diff.) ±12 ±12 V
Offset Voltage X, Y ±5 ⴞ20 ±2 ⴞ10 mV
Offset Voltage Drift X, Y 100 150 µV/°C
Offset Voltage Z ±5 ⴞ30 ±2 ⴞ15 mV
Offset Voltage Drift Z 500 300 µV/°C
CMRR 60 80 70 90 dB
Bias Current 0.8 2.0 0.8 2.0 µA
Offset Current 0.1 0.1 µA
Differential Resistance 10 10 MΩ
DIVIDER PERFORMANCE ( Z 2 − Z1 ) ( Z 2 − Z1 )
Transfer Function (X1 > X2) 10 V + Y1 10 V + Y1
( X1 − X 2 ) ( X1 − X 2 )
Total Error1 (X = 10 V, –10 V ≤ Z ≤ +10 V) ±0.75 ±0.35 %
(X = 1 V, –1 V ≤ Z ≤ +1 V) ±2.0 ±1.0 %
(0.1 V ≤ X ≤ 10 V, –10 V ≤ Z ≤ 10 V) ±2.5 ±1.0 %
SQUARE PERFORMANCE ( X1 − X 2 )2 ( X1 − X 2 )2
Transfer Function + Z2 + Z2
10 V 10 V
Total Error (–10 V ≤ X ≤ 10 V) ±0.6 ±0.3 %
SQUARE-ROOTER PERFORMANCE
Transfer Function (Z1 ≤ Z2 ) 10 V ( Z 2 − Z1 ) + X 2 10 V ( Z 2 − Z1 ) + X 2

Total Error1 (1 V ≤ Z ≤ 10 V) ±1.0 ±0.5 %

POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance ±15 ±15 V
Operating ±8 ⴞ22 ±8 ⴞ22 V
Supply Current
Quiescent 4 6 4 6 mA
PACKAGE OPTIONS
TO-100 (H-10A) AD534SH AD534TH
TO-116 (D-14) AD534SD AD534TD
E-20A AD534SE
Chips AD534S Chips AD534T Chips
NOTES Specifications shown in boldface are tested on all production units at final electrical
1
Figures given are percent of full scale, ± 10 V (i.e., 0.01% = 1 mV). test. Results from those tests are used to calculate outgoing quality levels. All min and
2
May be reduced down to 3 V using external resistor between –V S and SF. max specifications are guaranteed, although only those shown in boldface are tested
3
Irreducible component due to nonlinearity: excludes effect of offsets. on all production units.
4
Using external resistor adjusted to give SF = 3 V.
5
See Functional Block Diagram for definition of sections.
Specifications subject to change without notice.

REV. B –3–
AD534
CHIP DIMENSIONS AND BONDING DIAGRAM ABSOLUTE MAXIMUM RATINGS
Dimensions shown in inches and (mm).
AD534J, K, L AD534S, T
Contact factory for latest dimensions.
X1 +VS OUT Supply Voltage ± 18 V ± 22 V
Internal Power Dissipation 500 mW *
X2
Output Short-Circuit to Ground Indefinite *
Input Voltages, X1 X2 Y 1 Y 2 Z 1 Z 2 ± VS *
Rated Operating Temperature Range 0°C to +70°C –55°C to
0.076 +125°C
SF (1.93)
Storage Temperature Range –65°C to +150°C *
Z1 Lead Temperature Range, 60 s Soldering +300°C *
*Same as AD534J Specs.

+VS

Y1
470kV
50kV TO APPROPRIATE
Y2 –VS Z2 INPUT TERMINAL
0.100 (2.54) 1kV
THE AD534 IS AVAILABLE IN LASER - TRIMMED CHIP FORM
–VS
Thermal Characteristics
Thermal Resistance θJC = 25°C/W for H-10A Figure 1. Optional Trimming Configuration
θJA = 150°C/W for H-10A
θJC = 25°C/W for D-14 or E-20A
θJA = 95°C/W for D-14 or E-20A
ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD534JD 0°C to +70°C Side Brazed DIP D-14
AD534KD 0°C to +70°C Side Brazed DIP D-14
AD534LD 0°C to +70°C Side Brazed DIP D-14
AD534JH 0°C to +70°C Header H-10A
AD534JH/+ 0°C to +70°C Header H-10A
AD534KH 0°C to +70°C Header H-10A
AD534KH/+ 0°C to +70°C Header H-10A
AD534LH 0°C to +70°C Header H-10A
AD534K Chip 0°C to +70°C Chip
AD534SD –55°C to +125°C Side Brazed DIP D-14
AD534SD/883B –55°C to +125°C Side Brazed DIP D-14
AD534TD –55°C to +125°C Side Brazed DIP D-14
AD534TD/883B –55°C to +125°C Side Brazed DIP D-14
JM38510/13902BCA –55°C to +125°C Side Brazed DIP D-14
JM38510/13901BCA –55°C to +125°C Side Brazed DIP D-14
AD534SE –55°C to +125°C LCC E-20A
AD534SE/883B –55°C to +125°C LCC E-20A
AD534TE/883B –55°C to +125°C LCC E-20A
AD534SH –55°C to +125°C Header H-10A
AD534SH/883B –55°C to +125°C Header H-10A
AD534TH –55°C to +125°C Header H-10A
AD534TH/883B –55°C to +125°C Header H-10A
JM38510/13902BIA –55°C to +125°C Header H-10A
JM38510/13901BIA –55°C to +125°C Header H-10A
AD534S Chip –55°C to +125°C Chip
AD534T Chip –55°C to +125°C Chip
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD534 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. B
 AD534
FUNCTIONAL DESCRIPTION The user may adjust SF for values between 10.00 V and 3 V by
Figure 2 is a functional block diagram of the AD534. Inputs are connecting an external resistor in series with a potentiometer
converted to differential currents by three identical voltage-to- between SF and –VS. The approximate value of the total resis-
current converters, each trimmed for zero offset. The product tance for a given value of SF is given by the relationship:
of the X and Y currents is generated by a multiplier cell using
Gilbert’s translinear technique. An on-chip “Buried Zener” SF
RSF = 5.4K
provides a highly stable reference, which is laser trimmed to 10 − SF
provide an overall scale factor of 10 V. The difference between
XY/SF and Z is then applied to the high gain output amplifier. Due to device tolerances, allowance should be made to vary RSF;
This permits various closed loop configurations and dramati- by ± 25% using the potentiometer. Considerable reduction in
cally reduces nonlinearities due to the input amplifiers, a domi- bias currents, noise and drift can be achieved by decreasing SF.
nant source of distortion in earlier designs. The effectiveness of This has the overall effect of increasing signal gain without the
the new scheme can be judged from the fact that under typical customary increase in noise. Note that the peak input signal is
conditions as a multiplier the nonlinearity on the Y input, with always limited to 1.25 SF (i.e., ± 5 V for SF = 4 V) so the overall
X at full scale (± 10 V), is ± 0.005% of FS; even at its worst transfer function will show a maximum gain of 1.25. The per-
point, which occurs when X = ±6.4 V, it is typically only formance with small input signals, however, is improved by
± 0.05% of FS Nonlinearity for signals applied to the X input, using a lower SF since the dynamic range of the inputs is now
on the other hand, is determined almost entirely by the multi- fully utilized. Bandwidth is unaffected by the use of this option.
plier element and is parabolic in form. This error is a major Supply voltages of ± 15 V are generally assumed. However,
factor in determining the overall accuracy of the unit and hence satisfactory operation is possible down to ± 8 V (see Figure 16).
is closely related to the device grade. Since all inputs maintain a constant peak input capability of
± 1.25 SF some feedback attenuation will be necessary to
AD534 STABLE +VS achieve output voltage swings in excess of ± 12 V when using
SF REFERENCE higher supply voltages.
AND BIAS –VS

TRANSFER FUNCTION
X1 +
OPERATION AS A MULTIPLIER
V-1
– (X1 – X2) (Y1 – Y2) Figure 3 shows the basic connection for multiplication. Note
X2 VO = A – (Z1 – Z2)
TRANSLINEAR that the circuit will meet all specifications without trimming.
MULTIPLIER SF
ELEMENT
Y1 +
V-1 +VS
Y2 – X INPUT X1 +15V
A OUT 610V FS
612V PK
HIGH GAIN X2 OUTPUT , 612V PK
Z1 +
OUTPUT OUT
V-1 0.75 ATTEN (X1 – X2) (Y1 – Y2)
Z2 – AMPLIFIER = + Z2
SF Z1 10V
AD534
Figure 2. Functional Block Diagram Z2
OPTIONAL SUMMING
INPUT, Z, 610V PK
The generalized transfer function for the AD534 is given by: Y1
Y INPUT
610V FS
 ( X − X 2 ) (Y1 − Y 2 )  612V PK
V OUT = A  1 − ( Z1 − Z2 ) Y2 –VS –15V
 SF 
Figure 3. Basic Multiplier Connection
where A = open loop gain of output amplifier, typically
In some cases the user may wish to reduce ac feedthrough to a
70 dB at dc minimum (as in a suppressed carrier modulator) by applying an
X, Y, Z = input voltages (full scale = ± SF, peak = external trim voltage (± 30 mV range required) to the X or Y
± 1.25 SF) input (see Figure 1). Figure 19 shows the typical ac feedthrough
with this adjustment mode. Note that the Y input is a factor of
SF = scale factor, pretrimmed to 10.00 V but adjustable 10 lower than the X input and should be used in applications
by the user down to 3 V. where null suppression is critical.
In most cases the open loop gain can be regarded as infinite, The high impedance Z2 terminal of the AD534 may be used to
and SF will be 10 V. The operation performed by the AD534, sum an additional signal into the output. In this mode the out-
can then be described in terms of equation: put amplifier behaves as a voltage follower with a 1 MHz small
signal bandwidth and a 20 V/µs slew rate. This terminal should
( X1 − X 2 ) (Y1 − Y 2 ) = 10 V ( Z1 − Z2 ) always be referenced to the ground point of the driven system,
particularly if this is remote. Likewise, the differential inputs
should be referenced to their respective ground potentials to
realize the full accuracy of the AD534.

REV. B –5–
AD534
A much lower scaling voltage can be achieved without any re- X1 +VS
X INPUT
duction of input signal range using a feedback attenuator as 610V FS
CURRENT-SENSING
shown in Figure 4. In this example, the scale is such that VOUT 612V PK
X2 RESISTOR, RS, 2kV MIN
OUT
= XY, so that the circuit can exhibit a maximum gain of 10.
This connection results in a reduction of bandwidth to about SF Z1
80 kHz without the peaking capacitor CF = 200 pF. In addition, AD534
Z2 (X1 – X2) (Y1 – Y2) 1
the output offset voltage is increased by a factor of 10 making IOUT =
10V RS
external adjustments necessary in some applications. Adjust- Y INPUT Y1 INTEGRATOR
ment is made by connecting a 4.7 MΩ resistor between Z1 and 610V FS CAPACITOR
612V PK (SEE TEXT)
the slider of a pot connected across the supplies to provide Y2 –VS

± 300 mV of trim range at the output.

Figure 5. Conversion of Output to Current
X1 +VS +15V
X INPUT OPERATION AS A SQUARER
610V FS
612V PK
X2 OUTPUT , 612V PK Operation as a squarer is achieved in the same fashion as the
OUT = (X1 – X2) (Y1 – Y2) multiplier except that the X and Y inputs are used in parallel.
(SCALE = 1V)
AD534 90kV
The differential inputs can be used to determine the output
SF Z1 OPTIONAL
10kV PEAKING polarity (positive for X1 = Yl and X 2 = Y2, negative if either one
CAPACITOR
Z2 CF = 200pF
of the inputs is reversed). Accuracy in the squaring mode is
Y1
typically a factor of 2 better than in the multiplying mode, the
Y INPUT
610V FS largest errors occurring with small values of output for input
612V PK –VS –15V below 1 V.
Y2

If the application depends on accurate operation for inputs that

Figure 4. Connections for Scale-Factor of Unity are always less than ± 3 V, the use of a reduced value of SF is
Feedback attenuation also retains the capability for adding a recommended as described in the Functional Description sec-
signal to the output. Signals may be applied to the high imped- tion (previous page). Alternatively, a feedback attenuator may
ance Z2 terminal where they are amplified by +10 or to the be used to raise the output level. This is put to use in the differ-
common ground connection where they are amplified by +1. ence-of-squares application to compensate for the factor of 2
Input signals may also be applied to the lower end of the 10 kΩ loss involved in generating the sum term (see Figure 8).
resistor, giving a gain of –9. Other values of feedback ratio, up The difference-of-squares function is also used as the basis for a
to X100, can be used to combine multiplication with gain. novel rms-to-dc converter shown in Figure 15. The averaging
Occasionally it may be desirable to convert the output to a cur- filter is a true integrator, and the loop seeks to zero its input.
rent, into a load of unspecified impedance or dc level. For ex- For this to occur, (VIN)2 – (VOUT)2 = 0 (for signals whose period
ample, the function of multiplication is sometimes followed by is well below the averaging time-constant). Hence VOUT is
integration; if the output is in the form of a current, a simple forced to equal the rms value of VIN. The absolute accuracy of
capacitor will provide the integration function. Figure 5 shows this technique is very high; at medium frequencies, and for
how this can be achieved. This method can also be applied in signals near full scale, it is determined almost entirely by the
squaring, dividing and square rooting modes by appropriate ratio of the resistors in the inverting amplifier. The multiplier
choice of terminals. This technique is used in the voltage- scaling voltage affects only open loop gain. The data shown is
controlled low-pass filter and the differential-input voltage-to- typical of performance that can be achieved with an AD534K,
frequency converter shown in the Applications section. but even using an AD534J, this technique can readily provide
better than 1% accuracy over a wide frequency range, even for
crest-factors in excess of 10.

–6– REV. B
 AD534
OPERATION AS A DIVIDER OPERATION AS A SQUARE ROOTER
The AD535, a pin-for-pin functional equivalent to the AD534, The operation of the AD534 in the square root mode is shown
has guaranteed performance in the divider and square-rooter in Figure 7. The diode prevents a latching condition which
configurations and is recommended for such applications. could occur if the input momentarily changes polarity. As
Figure 6 shows the connection required for division. Unlike shown, the output is always positive; it may be changed to a
earlier products, the AD534 provides differential operation on negative output by reversing the diode direction and interchang-
both numerator and denominator, allowing the ratio of two ing the X inputs. Since the signal input is differential, all combi-
floating variables to be generated. Further flexibility results from nations of input and output polarities can be realized, but
access to a high impedance summing input to Y1. As with all operation is restricted to the one quadrant associated with each
dividers based on the use of a multiplier in a feedback loop, the combination of inputs.
bandwidth is proportional to the denominator magnitude, as
OUTPUT, 612V PK
shown in Figure 23.
= 10V (Z2 – Z1) +X2

+
X INPUT X1 +VS +15V OUTPUT, 612V PK X1 +VS +15V REVERSE RL
(DENOMINATOR) 10V (Z2 – Z1)
+10V FS = + Y1 THIS AND X (MUST BE
+12V PK – X2 (X1 – X2) INPUTS FOR PROVIDED)
X2 NEGATIVE
OUT
OUT OUTPUTS
SF Z1 Z INPUT OPTIONAL – Z INPUT
SF Z1
AD534 (NUMERATOR) SUMMING
610V FS, 612V PK AD534 10V FS
Z2 INPUT,
Z2 + 12V PK
OPTIONAL X, 610V PK
SUMMING
Y1
INPUT Y1
610V PK
Y2 –VS –15V
Y2 –VS –15V

Figure 6. Basic Divider Connection Figure 7. Square-Rooter Connection

Without additional trimming, the accuracy of the AD534K In contrast to earlier devices, which were intolerant of capacitive
and L is sufficient to maintain a 1% error over a 10 V to 1 V loads in the square root modes, the AD534 is stable with all
denominator range. This range may be extended to 100:1 by loads up to at least 1000 pF. For critical applications, a small
simply reducing the X offset with an externally generated trim adjustment to the Z input offset (see Figure 1) will improve
voltage (range required is ± 3.5 mV max) applied to the unused accuracy for inputs below 1 V.
X input (see Figure 1). To trim, apply a ramp of +100 mV to
+V at 100 Hz to both X1 and Z1 (if X2 is used for offset adjust-
ment, otherwise reverse the signal polarity) and adjust the trim
voltage to minimize the variation in the output.*
Since the output will be near +10 V, it should be ac-coupled for
this adjustment. The increase in noise level and reduction in
bandwidth preclude operation much beyond a ratio of 100 to 1.
As with the multiplier connection, overall gain can be intro-
duced by inserting a simple attenuator between the output and
Y2 terminal. This option, and the differential-ratio capability of
the AD534 are utilized in the percentage-computer application
shown in Figure 12. This configuration generates an output
proportional to the percentage deviation of one variable (A) with
respect to a reference variable (B), with a scale of one volt per
percent.

*See the AD535 data sheet for more details.

REV. B –7–
AD534–Applications Section
The versatility of the AD534 allows the creative designer to
implement a variety of circuits such as wattmeters, frequency +VS
X1 +15V
doublers and automatic gain controls to name but a few. MODULATION
INPUT, 6EM
X2 EM
OUT OUTPUT = 16 E sin vt
A X1 +VS +15V 10V C
A–B
2 SF Z1
X2 2 2
OUT OUTPUT = A – B AD534
10V
30kV Z2
CARRIER
SF Z1 Y1
INPUT
AD534 10kV EC sin vt
Z2 Y2 –VS –15V

B Y1
A+B
2 THE SF PIN OR A Z-ATTENUATOR CAN BE USED TO PROVIDE OVERALL
Y2 –VS –15V SIGNAL AMPLIFICATION, OPERATION FROM A SINGLE SUPPLY POSSIBLE;
BIAS Y2 TO VS/2.

Figure 8. Difference-of-Squares Figure 11. Linear AM Modulator

X1 +VS +15V
CONTROL INPUT, +VS +15V
X1
EC, ZERO TO 65V 9kV
X2
OUT OUTPUT, 612V PK A–B
SET X2 OUTPUT = (100V)
39kV E E OUT B
GAIN AD534 = C S (1% PER VOLT)
1kV 2kV 0.1V 1kV
–VS Z1
SF
1kV 0.005mF SF Z1
Z2 AD534
A INPUT
Y1 Z2 (6)
SIGNAL INPUT, B INPUT Y1
ES, 65V PK (+VE ONLY)
Y2 –VS –15V
Y2 –VS –15V
NOTES:
1) GAIN IS X 10 PER-VOLT OF EC, ZERO TO X 50
2) WIDEBAND (10Hz – 30kHz) OUTPUT NOISE IS 3mV RMS, TYP
CORRESPONDING TO A.F.S. S/N RATIO OF 70dB OTHER SCALES, FROM 10% PER VOLT TO 0.1% PER VOLT
3) NOISE REFERRED TO SIGNAL INPUT, WITH EC = 65V, IS 60mV RMS, TYP CAN BE OBTAINED BY ALTERING THE FEEDBACK RATIO.
4) BANDWITH IS DC TO 20kHz, –3dB, INDEPENDENT OF GAIN

Figure 9. Voltage-Controlled Amplifier Figure 12. Percentage Computer

X1 +VS +15V X1 +VS +15V

X2
OUT OUTPUT = (10V) sin u X2
18kV OUT
AD534 p Eu
4.7kV WHERE u = OUTPUT, 65V/PK
2 10V AD534 y
SF Z1 = (10V)
10kV SF Z1 1+y
4.3kV
Y
WHERE y =
Z2 (10V)
Z2
INPUT, Eu 3kV
Y1
0 TO +10V INPUT, Y 610V FS Y1

Y2 –VS –15V
Y2 –VS –15V

USING CLOSE TOLERANCE RESISTORS AND AD534L, ACCURACY

OF FIT IS WITHIN 60.5% AT ALL POINTS. u IS IN RADIANS.

Figure 10. Sine-Function Generator Figure 13. Bridge-Linearization Function

–8–
 AD534
+15V

ADJ 8kHz 2kV

39kV
X1 +VS +15V
3-30p

X2 82kV
OUT 2
ADJ
1kHz 7 OUTPUT
AD534 615V APPROX.
3
SF Z1 AD211
500V 2.2kV
PINS 5, 6, 8 TO +15V
(= R)
Z2 PINS 1, 4 TO –15V
+ Y1 EC 1
CONTROL f=
INPUT, EC 0.01 40 CR
100mV TO 10V – (= C)
Y2 –VS –15V = 1kHz PER VOLT
WITH VALUES SHOWN
CALIBRATION PROCEDURE:
WITH EC = 1.0V, ADJUST POT TO SET f = 1.000kHz. WITH EC = 8.0V ADJUST
TRIMMER CAPACITOR TO SET f = 8.000kHz. LINEARITY WILL TYPICALLY BE
WITHIN 6 0.1% OF FS FOR ANY OTHER INPUT.
DUE TO DELAYS IN THE COMPARATOR, THIS TECHNIQUE IS NOT SUITABLE
FOR MAXIMUM FREQUENCIES ABOVE 10kHz. FOR FREQUENCIES ABOVE
10kHz THE AD537 VOLTAGE-TO-FREQUENCY CONVERTER IS RECOMMENDED.
A TRIANGLE-WAVE OF 65V PK APPEARS ACROSS THE 0.01mF CAPACITOR; IF
USED AS AN OUTPUT, A VOLTAGE-FOLLOWER SHOULD BE INTERPOSED.

Figure 14. Differential-Input Voltage-to-Frequency Converter

MATCHED TO 0.025%

20kV 10kV 10kV

–

AD741K +

+VS 5kV
X1 +15V
10mF
INPUT NONPOLAR
10kV +
5V RMS FS X2
610V PEAK OUT
AD534 10mF SOLID Ta
RMS + DC SF Z1
10kV OUTPUT
MODE – 0 TO +5V
AC RMS 10kV
Z2 +
Y1 AD741J
10MV
Y2 –VS +15V
ZERO
–15V ADJ
20kV

CALIBRATION PROCEDURE:
WITH 'MODE' SWITCH IN 'RMS + DC' POSITION, APPLY AN INPUT OF +1.00VDC.
ADJUST ZERO UNTIL OUTPUT READS SAME AS INPUT. CHECK FOR INPUTS
OF 610V; OUTPUT SHOULD BE WITHIN 60.05% (5mV).
ACCURACY IS MAINTAINED FROM 60Hz TO 100kHz, AND IS TYPICALLY HIGH
BY 0.5% AT 1MHz FOR VIN = 4V RMS (SINE, SQUARE OR TRIANGULAR-WAVE).
PROVIDED THAT THE PEAK INPUT IS NOT EXCEEDED, CREST-FACTORS UP
TO AT LEAST TEN HAVE NO APPRECIABLE EFFECT ON ACCURACY .
INPUT IMPEDANCE IS ABOUT 10kV; FOR HIGH (10MV) IMPEDANCE, REMOVE
MODE SWITCH AND INPUT COUPLING COMPONENTS.
FOR GUARANTEED SPECIFICATIONS THE AD536A AND AD636 ARE OFFERED
AS A SINGLE PACKAGE RMS-TO-DC CONVERTER.

Figure 15. Wideband, High-Crest Factor, RMS-to-DC Converter

REV. B –9–
AD534–Typical Performance Curves (typical at +25ⴗC, with V = ⴞ15 V dc, unless otherwise noted) S

14 1000
PEAK POSITIVE OR NEGATIVE SIGNAL – Volts

OUTPUT, RL 2kV

12

PK-PK FEEDTHROUGH – mV
ALL INPUTS, SF = 10V 100

10

10
X-FEEDTHROUGH
8

1
6 Y-FEEDTHROUGH

4 0.1
8 10 12 14 16 18 20 10 100 1k 10k 100k 1M 10M
POSITIVE OR NEGATIVE SUPPLY – Volts FREQUENCY – Hz

Figure 16. Input/Output Signal Range vs. Supply Voltages Figure 19. AC Feedthrough vs. Frequency

800 1.5

NOISE SPECTRAL DENSITY – mV/ Hz

700

600
SCALING VOLTAGE = 10V
BIAS CURRENT – nA

1
500 SCALING VOLTAGE = 10V

400

300
0.5
SCALING VOLTAGE = 3V
200

SCALING VOLTAGE = 3V
100

0 0
–60 –40 –20 0 20 40 60 80 100 120 140 10 100 1k 10k 100k
TEMPERATURE – 8C FREQUENCY – Hz

Figure 17. Bias Currents vs. Temperature Figure 20. Noise Spectral Density vs. Frequency
(X, Y or Z Inputs)

90 100

80
OUTPUT NOISE VOLTAGE – mV rms

90
70
CONDITIONS:
60 10Hz – 10kHz BANDWIDTH
CMRR – dB

TYPICAL FOR 80
50 ALL INPUTS

40
70
30

20 60

10

0 50
100 1k 10k 100k 1M 2.5 5 7.5 10
FREQUENCY – Hz SCALING VOLTAGE, SF – Volts

Figure 18. Common-Mode Rejection Ratio vs. Frequency Figure 21. Wideband Noise vs. Scaling Voltage

–10–
 AD534
10 +60

0dB = 0.1V RMS, RL= 2kV

0 +40
OUTPUT RESPONSE – dB

VX = 100mV dc

( VVOZ )
VZ = 10mV rms
CL = 0pF

OUTPUT – dB
+20
–10
CL 1000pF VX = 1V dc
CL 1000pF
CF = 0 VZ = 100mV rms
CF 200pF

0
–20
NORMAL VX = 10V dc
WITH X10
FEEDBACK CONNECTION VZ = 1V rms
ATTENUATOR

–30 –20
10k 100k 1M 10M 1k 10k 100k 1M 10M
FREQUENCY – Hz FREQUENCY – Hz

Figure 22. Frequency Response as a Multiplier Figure 23. Frequency Response vs. Divider Denominator
Input Voltage

REV. B –11–
AD534
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

H-10A Package
TO-100
REFERENCE PLANE

C495e–0–6/99
0.562 (14.30)
0.115 (2.92)
0.185 (4.70) 0.500 (12.70)
0.165 (4.19)
0.23 (5.84)

0.355 (9.02) 5 6 7
0.305 (7.75) 4 8
0.370 (9.40) 3 9
0.335 (8.51) 2 1 10
0.045 (1.14)
0.029 (0.74)
0.021 (0.53)
(DIM. B)
0.044 (1.12) 0.016 (0.41)
0.032 (0.81) 0.019 (0.48) 0.034 (0.86)
0.040 (1.01) (DIM. A) 0.028 (0.71)
0.016 (0.41)
0.010 (0.25)
SEATING PLANE 368

D-14 Package
TO-116
0.430
(10.92)

0.040 R 14 8
(1.02)
0.265 0.029 60.010
(6.73) (7.37 60.25)

PIN 1 1 7

0.700 60.010 0.31 60.01

17.78 60.25 (7.87 60.25)
0.035 60.010
0.89 60.25
0.085 (2.16) 0.095 (2.41)

0.180 60.030
0.125 (3.18) MIN 4.57 60.76 0.10 60.002
(0.25 60.05)
0.30
(7.62)
0.017 +0.003
0.100 0.047 60.007 REF
–0.002 (2.54)
0.430 +0.080
–0.050

E-20A Package
LCC
0.075
0.200 (5.08) (1.91)
BSC REF
0.100 0.015 (0.38)
(2.54) MIN
0.055 (1.40) BSC
0.045 (1.14)
0.028 (0.71)
0.022 (0.56)
0.050
(1.27)

PRINTED IN U.S.A.
BOTTOM PIN 1
BSC VIEW

0.040 REF 3 458

(1.02 3 458) 0.020 REF 3 458
3 PLACES (0.51 3 458)

0.358 (9.09)
0.342 (8.69)

0.100 (2.54)
0.060 (1.52)

–12– REV. B