Hardware Descriptive Language
TECHNOLOGICAL UNIVERSITY OF THE PHILIPPINES
Ayala Blvd. cor San Marcelino St. Ermina, Manila
Activity no.2
CPET7L – 2A
Thursday 7:00AM to 10:00PM
Submitted By:
Almarines, Jerico
Cochangco, Joshua
Dabon, Eugene
Ferrolino, Japhet
Mendoza, Aldrin Daniel G.
Submitted To:
Engr. AIMEE G. ACOBA
CPE Faculty
Hardware Descriptive Language
Type the question then screenshot the result of your program.
Part 1: Programming Exercises: Create a Dataflow Modeling Verilog HDL program for the
following statement:
1. Listed down the Basic codes in Verilog program
a. 2 input - OR gate
b. 2 input - NAND gate
c. 3 input - NOR date
d. 3 input - XOR gate
e. 3 input - XNOR gate
Part 2: Full Adder
1. Full Adder is the adder which adds three inputs and produces two outputs. The first
two inputs are A and B and the third input is an input carry as Carry in. The output
carry is designated as Carry out and the normal output is designated as S which is
SUM.
2. S= A B Cin C=AB + Cin (A B)
Hardware Descriptive Language
OR Gate
module or2(input a, input b, output y);
assign y = a | b;
endmodule
module tb_or2;
reg a, b;
wire y;
or2 dut(a, b, y);
initial begin
$display(" time a b y ");
$monitor($time, " %b %b %b ", a, b, y);
#1 a = 0; b = 0;
#1 a = 0; b = 1;
#1 a = 1; b = 0;
#1 a = 1; b = 1;
end
endmodule
Hardware Descriptive Language
NAND Gate
module nand2 (x,a,b);
input a,b;
output x;
assign x=~(a&b);
endmodule
module tb_nand2;
reg a,b;
wire x;
nand2 dut(x,a,b);
initial begin
$monitor($time, "a=%b b=%b x=%b", a,b,x);
#1 a = 0; b = 0;
#1 a = 0; b = 1;
#1 a = 1; b = 0;
#1 a = 1; b = 1;
#1 $finish;
end
endmodule
Hardware Descriptive Language
NOR Gate
module nor3(input a, input b, input c, output y);
assign y = ~(a | b | c);
endmodule
module tb_nor3;
reg a, b, c;
wire y;
nor3 dut(a, b, c, y);
initial begin
$monitor($time, " a=%b b=%b c=%b y=%b", a, b, c, y);
#1 a = 0; b = 0; c = 0;
#1 a = 0; b = 0; c = 1;
#1 a = 0; b = 1; c = 0;
#1 a = 0; b = 1; c = 1;
#1 a = 1; b = 0; c = 0;
#1 a = 1; b = 0; c = 1;
#1 a = 1; b = 1; c = 0;
#1 a = 1; b = 1; c = 1;
#1 $finish;
end
endmodule
Hardware Descriptive Language
XOR Gate
module xor3 (a,b,c,x);
input a,b,c;
output x;
assign x=a^b^c;
endmodule
module tb_xor3;
reg a, b, c;
wire x;
xor3 dut(a, b, c, x);
initial begin
$monitor($time, " a=%b b=%b c=%b y=%b", a, b, c, x);
#1 a = 0; b = 0; c = 0;
#1 a = 0; b = 0; c = 1;
#1 a = 0; b = 1; c = 0;
#1 a = 0; b = 1; c = 1;
#1 a = 1; b = 0; c = 0;
#1 a = 1; b = 0; c = 1;
#1 a = 1; b = 1; c = 0;
#1 a = 1; b = 1; c = 1;
#1 $finish;
end
endmodule
Hardware Descriptive Language
XNOR Gate
module nor3(input a, input b, input c, output y);
assign y = ~(a | b | c);
endmodule
module tb_nor3;
reg a, b, c;
wire y;
nor3 dut(a, b, c, y);
initial begin
$monitor($time, " a=%b b=%b c=%b y=%b", a, b, c, y);
#1 a = 0; b = 0; c = 0;
#1 a = 0; b = 0; c = 1;
#1 a = 0; b = 1; c = 0;
#1 a = 0; b = 1; c = 1;
#1 a = 1; b = 0; c = 0;
#1 a = 1; b = 0; c = 1;
#1 a = 1; b = 1; c = 0;
#1 a = 1; b = 1; c = 1;
#1 $finish;
end
endmodule
Hardware Descriptive Language
FULL ADDER
module full_adder(input a, input b, input cin, output cout, output sum);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule
module tb_full_adder;
reg a, b, cin;
wire cout, sum;
full_adder dut(a, b, cin, cout, sum);
initial begin
$monitor($time, " a=%b b=%b cin=%b sum=%b cout=%b", a, b, cin, sum, cout);
#1 a = 0; b = 0; cin = 0;
#1 a = 0; b = 0; cin = 1;
#1 a = 0; b = 1; cin = 0;
#1 a = 0; b = 1; cin = 1;
#1 a = 1; b = 0; cin = 0;
#1 a = 1; b = 0; cin = 1;
#1 a = 1; b = 1; cin = 0;
#1 a = 1; b = 1; cin = 1;
#1 $finish;
end
endmodule
