Calibre® Chip-Level Verification Quick Reference

Software Version 2020.2

Overview Calibre Reconnaissance

Running a complete sign-off verification on a chip-level design that Calibre Reconnaissance can significantly improve performance for
is under development can produce large numbers of results that non-sign-off DRC runs. If you are verifying a large design that is in
are difficult to navigate, manage, and resolve. This document the development stage, it is recommended that you invoke
describes techniques and features available in Calibre that can Calibre Recon as follows:
help you analyze and manage DRC runs on incomplete data. calibre -drc -hier -turbo -recon svrf.rules
o Configuring a run to improve performance
To run Calibre Recon from Calibre Interactive, enable the “Recon”
o Reducing runtime with Calibre Reconnaissance
checkbox on the Inputs tab. To run Recon from Calibre RealTime
o Improving results debugging with DRC Analyze Digital, select a check recipe for Recon.
o Configuring RVE for enhanced layer highlighting The Recon feature automatically chooses a subset of rules to run
o Excluding and waiving blocks from a verification run from your rule file. No modifications to your rule file or environment
Applying these features before sign-off verification provides you is necessary.
with a better starting point for debugging design verification issues. You should run Calibre Recon during the development of your
design and for the initial DRC runs on large, finalized designs.
Requirements Once you have corrected issues found with the Calibre Recon runs,
In addition to the licenses required by your rule file, you must have you can proceed to a full Calibre sign-off DRC run.
a Calibre RealTime Digital license to run Calibre Reconnaissance
and DRC Analyze.
No changes are necessary to your foundry rules or environment.
General Performance Tips
Setup Recommendations
• Run DRC using an OASIS layout with CBLOCK and Strict mode
to achieve the best performance.
• For initial, standard Calibre nmDRC runs (without -analyze), set
the DRC Maximum Results and DFM Defaults RDB Maximum
statements to a reasonably small value, such as 500. Do not use
ALL unless the design is small.
• Use the Layout Ignore Layer statement to completely exclude a
layer from the run. This can be used to ignore fill shapes, but you
can also use it to remove any incomplete or unnecessary layer
from the verification run. The results from a Calibre Recon run are the same as a standard
Calibre nmDRC run, so you can follow the same debugging and
Single Machines fixing flow that you use in your established verification process. If
If there are enough CPUs and memory on a machine to handle the you want to run only the rule checks that were unselected, use the
design and rule file complexity, consider using a single machine. inverse option:
calibre –drc –hier –turbo –hyper “drc_rule_file” calibre -drc -hier -turbo -recon -inverse svrf.rules

To add or remove rules from a Calibre Recon run, include the

Multiple Machines DRC Recon Add Check and DRC Recon Remove Check SVRF
calibre –drc -hier –turbo –hyper remote –remotedata statements in your rule file.
–recoveroff –remotefile “remote_file” “drc_rules”
Calibre DRC Analyze
Always use the -remotedata and -recoveroff options for jobs with The DRC Analyze feature uses Calibre RVE to present various
remotes. After the initial hyper-flex run, review the transcript for statistical representations of DRC results. You can use these
“SHARED = ” for the final operation. If the value is not equal to enhanced results to focus on chip-level errors that have a higher
“0/0”, and there is free memory on remotes, then specify fixing priority and impact on the design flow. The analysis results
“-remotedata 2” in the next Calibre invocation. include histograms, colormaps, and sortable tables of rule checks.
The histograms can be based on hierarchical cells or windows. You
For an N CPU remote, Calibre uses an additional N GB of memory can customize the histograms by selecting different results and
for the data server, which avoids transferring data amongst the windows under different bin ranges.
master and remotes. The colormaps can be viewed in separate windows or overlayed on
the layout. The colormaps indicate the distribution of errors across
Runs on Small Blocks a design. You can use the colormap as a navigational starting point
• Run multi-threaded on a single machine. For improved to investigate the cause of different rule checks and then probe
performance, use as many CPUs as available. down into the per-cell and per-window errors in the design.
• Always enable hyperscaling. A key advantage of this flow is that it does not require any
modifications to the foundry rules and the overhead on runtime is
Runs on Large or Top-Level Blocks
small (approximately 10% increase in runtime and 20% increase in
• Use the MTflex option (distributed run). memory) compared to the enhanced facilities provided by the
• Use HyperRemote to execute more operations in parallel (the graphical analysis features.
minimum recommended number of CPUs is 24). It is recommended that you run DRC Analyze with Recon as a
• Increase the number of CPUs for large designs. starting point for all Calibre DRC verification runs.

Unpublished work. © Siemens 2020

 Running Calibre Recon and DRC Analyze Excluding Incomplete Blocks (Gray Box)
1. Invoke Calibre Recon with DRC Analyze mode: When performing initial verification on the top-level, a design may
calibre -drc -hier -turbo -analyze -recon rules.svrf contain unfinished blocks, even though the connections from the
blocks to surrounding cells are established. The top-left block in
2. Open the layout in your preferred layout viewer and open the this example is unfinished, but the external connections are routed.
analyze.dfmd database in Calibre RVE for DFM. For example:
calibredrv -m chip.oas -rve -dfm analyze.dfmdb

3. Choose View > Bar Chart from the Chip Summary tab.
This provides a graphical distribution of the rule check results. A standard DRC run may include numerous results from the
This can help you determine which checks need investigating. incomplete blocks. This increases difficulty in debugging real
problems in the design. You can exclude blocks from a run, yet still
check the interacting regions on the perimeters of the blocks using
the Calibre Auto-Waivers tool or an SVRF statement.
Gray Box Using DRC (SVRF)
4. Choose View > Table to return to the previous view. LAYOUT WINDEL CELL cell_name ... [HIER] {[BY LAYER layer
[PRIMARY]] | [ORIGINAL [OCCUPIED]]} [HALO distance]
5. Right-click on a rule check and choose Histogram Hierarchy
Windows > Count. The following command removes the contents of the
This window reports the number of errors found within windows omsp_frontend cell from the verification run, but keeps 100 user
of your design. The windows with high numbers of errors (the units of geometry around the extents of the cell:
bars on the right of the chart) may be of the most interest. Layout Windel Cell “omsp_frontend” HIER HALO 100

Gray Box Using Calibre Auto-Waivers

Include the following command in your criteria file to remove blocks
from the verification run with waivers:
EXCLUDE_CELL cell_name [cell_name …] [HALO halo_value]
[BY_LAYER layer_name] [PRESERVE layer_to_keep …]
Remove the entire block from
6. Right click on the bar with the most results and choose Highlight
processing:
this bar. This highlights the windows in your layout.
EXCLUDE_CELL omsp_frontend

Remove the block from processing,

but keep the distance h from the
edges and keep layers M1 and V1..
EXCLUDE_CELL omsp_frontend
HALO h PRESERVE M1 V1
Remove the block from processing,
7. In the Chip Summary tab, right-click on a rule check and choose but keep the distance h from the
Colormap Hierarchy Windows > Count. This colormap edge of the block. Waive all errors
displays the location of the violations from the selected check. for ruleA within the waiver layer,
which is x distance from the cell
extents .
EXCLUDE_CELL omsp_frontend
HALO h
ruleA WAIVE_EXTENT x
Optimizing Result Highlighting
Calibre RVE supports optional highlighting in the DRC results tab
that enables you to easily view design polygons involved in the rule
8. Right-click on the colormap and choose Colormap Windows. check results, without manually setting visibility on the layers.
This overlays the colormap on your layout window. To use this feature, you must create a CTO file that controls
Calibre RVE layer visibility in the design tool. Do the following:
9. Right-click on one of the windows in the colormap in Calibre RVE
and choose Highlight Errors. 1. In Calibre Interactive, click Outputs and enable the “Create CTO
file” and “Groups” options.
2. Click Run DRC.
3. In Calibre RVE, choose Tools > Import CTO File.
Layers not involved
in the check are
automatically hidden
This operation overlays the actual errors on your layout. upon highlighting
the result
Tip: You can also create an on-the-fly RDB for a specific rule by
right-clicking on the rule and choosing Browse Hierarchy Errors >
Count in the Chip Summary tab. Note, you can also create a CTO file from Calibre RVE by choosing
Tools > Create CTO File from a DRC results tab.

Unpublished work. © Siemens 2020. This document contains information that is confidential and proprietary to Mentor Graphics Corporation, Siemens
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