EE-612
Lecture 4/5
MOS Capacitors
Joerg Appenzeller
Electrical and Computer Engineering
Purdue University
West Lafayette, IN USA
Fall 2024
Slides were developed by Prof. Mark Lundstrom
Appenzeller EE-612 F’24 1
outline
1) Short review
2) Gate voltage / surface potential relation
3) The flatband voltage
4) MOS capacitance vs. voltage
5) Gate voltage and inversion layer charge
Appenzeller EE-612 F’24 2
1) short review (bulk semiconductor)
log10 QS S
C/cm 2
QS Qi ~ eq S / 2 kBT
QS Qacc ~ e q S / 2 kBT
accumulation depletion inversion
QS QD ~ S kBT q
dQ
C S
dV
Appenzeller EE-612 F’24 3
1) short review
qS EC
x 0
EF
qVG 0
EFM EV
S VG ?
Appenzeller EE-612 F’24 4
outline
1) Short review
2) Gate voltage / surface potential relation
3) The flatband voltage
4) MOS capacitance vs. voltage
5) Gate voltage and inversion layer charge
Appenzeller EE-612 F’24 5
2) flat-band conditions
“flat band” Evac
• when the gate electrode Fermi level
lines up with the semiconductor
Fermi level, the bands are flat in the
semiconductor M S
EC
• this occurs at V’G = 0 when the gate VG EF
electrode workfunction equals the
EV
semiconductor workfunction
M S eV
M S V
S 0
Appenzeller EE-612 F’24 6
gate voltage and S
VOX 0 S 0 0
VG S VOX
EC
DOX VG S EOX tOX
EF
EV QS
qVG 0 VG S tOX
OX
QS
VG S
DOX OX EOX QS COX
OX
COX F/cm 2
tOX
Appenzeller EE-612 F’24 7
gate voltage and S
S VG
QS S
S VG S VOX S
COX
2 B
QS 2nB Si k BT eq S /2 kB T
QS 2q Si N A S
VT VG
Appenzeller EE-612 F’24 8
threshold voltage, VT
S 2 B onset of inversion
QS (2 B )
VG VT 2 B
COX
QS (2 B ) QD (2 B ) 2q Si N A (2 B )
VT 2 B 2q Si N A (2 B ) COX
Appenzeller EE-612 F’24 9
outline
1) Short review
2) Gate voltage / surface potential relation
3) The flatband voltage
4) MOS capacitance vs. voltage
5) Gate voltage and inversion layer charge
Appenzeller EE-612 F’24 10
flatband voltage
In an ideal MOS-C, S = 0 when VG’ = VFB = 0.
In a real MOS-C, charges at the oxide-silicon
interface, in the oxide, and gate-
semiconductor workfunction differences all
shift the flatband voltage.
Appenzeller EE-612 F’24 11
interface charge
VOX 0 S 0 0
EC
DOX
EF
qVG 0 EV
VG S EOX tOX
DOX QS QF QIT S
VG S QS COX QF COX QIT ( S ) COX
Appenzeller EE-612 F’24 12
charge in the oxide
DL DR QM
QM EC DR QS
DL DR ER QS OX
EF
EL ER QM OX
EV
VOX xM EL (tOX xM )ER
QS x M QM
0 x M t ox x VOX
COX tOX COX
QS xM QM
VG S
COX tOX COX
Appenzeller EE-612 F’24 13
distributed charge in the oxide
tOX
EC
QM Q(x)dx
0
EF
tOX
EV
xQ(x)dx
xM 0
tOX
0 t ox x Q(x)dx
0
QS xM QM
VG S
COX tOX COX
Appenzeller EE-612 F’24 14
additional information
For more information on the oxide-silicon interface and the origin of
the various charges, see:
1) R.F. Pierret, Semiconductor Device Fundamentals, pp. 650-671
Addison-Wesley, 1996
2) J.A. Del Alamo, EE 6720J/ 3.43J Integrated Microelectronic
Devices,Fall 2002
Lecture 22: “The Si Surface and MOS Structure”
Available from MIT OpenCourseWare:
http://ocw.mit.edu
‘Electrical Engineering and Computer Science’
‘Graduate’
Appenzeller EE-612 F’24 15
gate oxides 2008
• Typically SiON with k ~ 4.6 for 15% N2 (not SiO2 with k = 3.9).
• Use of thicker oxides with higher k gives less gate leakage.
• SiON is more resistant to boron penetration.
• But, SiON degrades mobility and reliability (NBTI). Engineering the N2
profile may help.
• Typically grown in dry 02, followed by plasma nitridation and rapid
thermal anneal. Results in 10-15% N2.
• NIT ~ 5 x 1010 cm-2 (corresponds to 500 traps/mm2)
• Oxide scaling has stopped at ~1.1 nm due to gate leakage.
Introduction of high-k beginning at 45-32 nm node.
(Source: M.A. Alam, Purdue Univ, 8/06)
Appenzeller EE-612 F’24 16
re-cap
QS
VG S VOX S
COX
fast charge
QS xM QM
VG S QF COX QIT ( S ) COX
COX tOX COX
fixed charge charge in oxide
Under flatband conditions: S QS 0
x M QM
QF COX QIT ( S 0) COX
VFB
t C
OX OX
Appenzeller EE-612 F’24 17
gate-semicond. workfunction differences
EVAC
flat band
S
M qm S M
EC EC
EF VG 0 EF
EV EV
S 0
Appenzeller EE-612 F’24 18
M < S
EVAC q S 0
M qm S
EC
S
EC
EF
EF
EV
EV
Vbi ms 0
Appenzeller EE-612 F’24 19
flatband voltage
VG 0 VFB ms Vbi 0
EC
VG 0 EC
EF VG VFB 0
EF
EV
EV
Vbi ms 0 S 0
Appenzeller EE-612 F’24 20
flatband voltage
QS
recall: VG S
COX
VG VG VFB
QS
VG VFB S
COX
QF QIT S xM QM
VFB ms
COX COX tOX COX
Appenzeller EE-612 F’24 21
outline
1) Short review
2) Gate voltage / surface potential relation
3) The flatband voltage
4) MOS capacitance vs. voltage
5) Gate voltage and inversion layer charge
Appenzeller EE-612 F’24 22
capacitance
dQG d QS
VG vS sin t CG
dVG dVG
QS
+ VG VFB S
COX
- p-Si dVG d S 1
d QS d QS COX
1 1 1
CG CS COX
Appenzeller EE-612 F’24 23
capacitance
VG 1 1 1
CG CS COX
COX
S d QS
CS
CS d S
QS S
already
understood!
Appenzeller EE-612 F’24 24
a closer look
QS
VG VFB S
COX
QF QIT S xM QM QIT S
VFB ms VFB
COX COX tOX COX COX
1 1 1
CG CS C IT COX
Appenzeller EE-612 F’24 25
surface state capacitance
VG
1 1 1
CG CS C IT COX
COX
S
d QS
CS
CSi C IT d S
d QIT
C IT
d S
Appenzeller EE-612 F’24 26
capacitance vs. voltage
CG
Cacc COX Cinv
CFB low frequency
VG
Appenzeller EE-612 F’24 27
(i) accumulation capacitance
d Qacc Qacc
CS VG S
d S COX
Qacc ~ eq S /2kBT Qacc COX VG S
CS
Qacc COX VG S
CS
(2k BT / q) (2kBT / q)
CS VG S
1
COX (2kBT / q)
Appenzeller EE-612 F’24 28
another way to look at it
OX
COX
tOX
CS Si tOX
1
Si COX OX t acc
CS
t acc
Appenzeller EE-612 F’24 29
accumulation capacitance
CG
Cacc COX Cinv
CFB
low frequency
VG
1 1 1
Cacc COX
Cacc CS COX
Appenzeller EE-612 F’24 30
flat band capacitance
flat band
QS 0
dQS Si
CS (FB) EC
d S LD
VG 0 EF
Si kBT EV
LD
q2 N A
S 0
Appenzeller EE-612 F’24 31
flat band capacitance
CG
Cacc COX Cinv
CFB
low frequency
VG
VFB
1 LD 1
CFB COX
CFB Si COX
Appenzeller EE-612 F’24 32
depletion capacitance
q S 0
QS QD 2q Si N A S
EC
dQS Si
CS C D
d S WD EF
EV
2 Si S
WD
qN A
Appenzeller EE-612 F’24 33
depletion capacitance
CG
Cacc COX Cinv
CFB
low frequency
VG
1 WD 1
Cdepl COX
Cdepl Si COX
Appenzeller EE-612 F’24 34
inversion capacitance
d Qinv S 2 B
CS
d S
EC
Qinv ~ eq S /2kBT
Qinv EF
CS
(2k BT / q) EV
COX VG VT
CS
(2kBT / q)
CS
VG VT
1
COX (2kBT / q)
Appenzeller EE-612 F’24 35
inversion capacitance
CG
Cacc COX Cinv
CFB
low frequency
VG
1 1 1
Cinv COX
Cinv CS COX
Appenzeller EE-612 F’24 36
EOT(electrical) in inversion
CG
Cacc COX Cinv
CFB
low frequency
VG
OX
Cinv EOTelectrical tOX
EOTelectrical
Appenzeller EE-612 F’24 37
role of frequency
CG
Cacc COX Cinv
CFB
low frequency
VG
Appenzeller EE-612 F’24 38
inversion capacitance (high frequency)
QS QD ( S ) Qi S S 2 B
dQS dQD ( S ) dQI S
CS
d S
d S
d S
X EC
EF
dQD Si
CS EV
d S S 2 B
Wdm
2 Si 2 B
Wdm 2 B
qN A
Appenzeller EE-612 F’24 39
inversion capacitance (high frequency)
CG
Cacc COX Cinv
CFB
high frequency
VG
1 Wdm 1
Cinv COX
Cinv Si COX
Appenzeller EE-612 F’24 40
low vs. high frequency
VG
QS QD Qinv
COX
CS CS dep CS inv
?
X
CS dep CS (inv)
may (or may not) be able
to follow the ac signal
Appenzeller EE-612 F’24 41
low or high frequency?
n+-Si n+-Si
ni
G
2
p-Si
p-Si
typically observe hi- typically observe low-
frequency CV frequency CV
Appenzeller EE-612 F’24 42
MOS CV recap
CG
Cacc COX Cinv
Si
Si CS inv
CS acc CFB tinv
t acc
low frequency
Si
CS depl
WD high frequency
VG
Appenzeller EE-612 F’24 43
outline
1) Short review
2) Gate voltage / surface potential relation
3) The flatband voltage
4) MOS capacitance vs. voltage
5) Gate voltage and inversion layer charge
Appenzeller EE-612 F’24 44
inversion charge - gate voltage relation
QS S
VG VFB S
COX
At threshold:
QD (2 B )
VT VFB 2 B
COX
Beyond threshold:
VG VT S 2 B
QI ( S ) QD ( S ) QD (2 B )
COX COX
Appenzeller EE-612 F’24 45
surface potential beyond threshold
V VG VT
COX
COX
S S V
CS (inv) CS (inv) COX
Appenzeller EE-612 F’24 46
inversion charge - gate voltage relation (ii)
Beyond threshold:
QI ( S ) QD ( S ) QD (2 B )
VG VT S 2 B
COX COX
COX
S V 0
Cinv COX
Qi
VG VT QI COX VG VT
COX
Appenzeller EE-612 F’24 47
inversion charge - gate voltage relation (iii)
Beyond threshold:
QI ( S ) QD ( S ) QD (2 B )
VG VT S 2 B
COX COX
QI
VG VT S (neglect depletion charge variation)
COX
COX
S V
CS (inv) COX QI CG VG VT
COX CS (inv)
CG
CS (inv) COX
Appenzeller EE-612 F’24 48
summary
1) Short review
2) Gate voltage / surface potential relation
3) The flatband voltage
4) MOS capacitance vs. voltage
5) Gate voltage and inversion layer charge
Appenzeller EE-612 F’24 49