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ED - Final Lecture-7

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0% found this document useful (0 votes)
55 views16 pages

ED - Final Lecture-7

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c.sunjid707
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Electronic Devices

Final Term
Lecture - 07

Reference book:
Electronic Devices and Circuit Theory
(Chapter-7)
Robert L. Boylestad and L. Nashelsky , (11th Edition)
Faculty of Engineering
American International University-Bangladesh
SELF-BIAS EXAMPLE Contd.
• Plot the transfer curve using IDSS and VP using shorthand method:

VGS ID

0 IDSS

0.3VP IDSS/2

0.5VP IDSS/4

VP 0mA

Faculty of Engineering
American International University-Bangladesh
SELF-BIAS EXAMPLE Contd.
• Superimpose the load line on top of the transfer curve:

Faculty of Engineering
American International University-Bangladesh
JFET: VOLTAGE-DIVIDER BIAS
• The source VDD was separated into two equivalent sources to permit a further
separation of the input and output regions of the network.
• Since IG = 0A, Kirchoff’s current law requires that IR1= IR2 and the series equivalent
circuit appearing to the left of the figure can be used to find the level of VG.

Faculty of Engineering
American International University-Bangladesh
VOLTAGE-DIVIDER BIAS
• VG can be found using the voltage divider rule:
RV
VG  2 DD
R1  R2
• Using Kirchoff’s Law on the input loop:
VD  VDD  I D RD VDS  VDD  I D ( RD  RS )

VS  I D RS VGS  VG  I D RS

• Rearranging and using ID =IS:


VDD
I R1  I R 2 
R1  R2

• Again the Q point needs to be established by plotting


a line that intersects the transfer curve.

Faculty of Engineering
American International University-Bangladesh
VOLTAGE-DIVIDER BIAS
• Graphical Approach ( to find VGSQ and IDQ):
• Plot a line for:
» VGS = VG when ID = 0A
» VGS = 0V when ID = VG/RS.
• Plot the transfer curve using IDSS and VP using shorthand method.
• The Q-point is located at the intersection.

VGS ID
0 IDSS
0.3VP IDSS/2 VGS  VG  I D RS
0.5VP IDSS/4
VP 0mA

Faculty of Engineering
American International University-Bangladesh
EFFECT OF INCREASING VALUES OF RS

Faculty of Engineering
American International University-Bangladesh
JFET: VOLTAGE-DIVIDER BIAS EXAMPLE
• Determine IDQ, VGSQ, VD, VS, VDS and VDG.

R2VDD
VG  VGS  VG  I D RS
R1  R2

VDS  VDD  I D ( RD  RS )

VGSQ  1.8V I DQ  2.4mA

VD  10.24V VS  3.6V

VDS  6.64V VDG  8.24V

Faculty of Engineering
American International University-Bangladesh
VOLTAGE-DIVIDER BIAS EXAMPLE Contd.
• Graphical Approach ( to find VGSQ and IDQ):
• Plot a line for:
» VGS = VG when ID = 0A
» VGS = 0V when ID = VG/RS.
• Plot the transfer curve using IDSS and VP
using shorthand method.
• Identify the Q-point.

VS  I D RS
R2VDD
VG 
R1  R2
VDS  VDD  I D ( RD  RS )
VGS  VG  I D RS VDS  VD  VS
VD  VDD  I D RD VDG  VD  VG

Faculty of Engineering
American International University-Bangladesh
D-MOSFET SELF-BIAS
• D-MOSFET bias circuits are similar to
JFETs.

• The only difference is that D-MOSFETs can


operate with positive values of VGS and with
ID values that exceed IDSS.

IG  0A ID  IS

VGS 2
ID  IDSS(1 )
VP

Faculty of Engineering
American International University-Bangladesh
D-MOSFET SELF-BIAS

• Graphical Approach (to find VGSQ and IDQ):

• Plot the transfer curve using IDSS and VP using


shorthand method.

• Plot ID vs VGS using VGS = -IDRS.

• Take a positive value of VGS and find the ID value


using
VGS 2
ID  IDSS(1 )
VP

• The Q-point is located at the intersection.

Faculty of Engineering
American International University-Bangladesh
D-MOSFET SELF-BIAS EXAMPLE

• Determine the IDQ, VGSQ and VD.


• Graphical Approach (to find VGSQ and IDQ):

• Plot the transfer curve using IDSS and VP


using shorthand method.

• Take a positive value of VGS and find the ID


value using
VGS 2
ID  IDSS(1 )
VP

• Plot ID vs VGS using VGS = -IDRS.


• Identify the intersection Q-point.

Faculty of Engineering
American International University-Bangladesh
D-MOSFET SELF-BIAS EXAMPLE

VD  VDD  I D RD VGS 2
ID  IDSS(1 )
VP
VGSQ = -4.3 V

IDQ = 1.7 mA
VGS
ID  
VD = 9.46 V RS

Faculty of Engineering
American International University-Bangladesh
D-MOSFET VOLTAGE-DIVIDER BIAS

• D-MOSFET bias circuits are similar to JFETs.

IG  0A ID  IS

VGS 2
ID  IDSS(1 )
VP

Faculty of Engineering
American International University-Bangladesh
D-MOSFET VOLTAGE-DIVIDER BIAS

• Graphical Approach (to find VGSQ and IDQ):

• Plot the transfer curve using IDSS and VP using


shorthand method.

• Take a positive value of VGS and find the ID


value using
VGS 2
ID  IDSS(1 )
VP

• Plot ID vs VGS using VGS = VG - IDRS.

• The Q-point is located at the intersection.

Faculty of Engineering
American International University-Bangladesh
End of Lecture-7

Faculty of Engineering
American International University-Bangladesh

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