STM32WL33xx

Datasheet

Multiprotocol LPWAN 32-bit MCU Arm® Cortex®-M0+ 2(G)FSK, 4(G)FSK, ASK,

D-BPSK, up to 256KB flash, 32KB SRAM

Features
• Includes ST state-of-the-art patented technology
• Ultra-low power sub-1GHz wireless system-on-chip
• Programmable MCU
VFQFPN48 (6 x 6 mm) – Core: Arm® Cortex®-M0+ 32-bit, running up to 64 MHz
– Program memory: 64-Kbyte / 128-Kbyte / 256-Kbyte flash memory
– Data memory: 16-Kbyte / 32-Kbyte SRAM (full retention)
– Additional storage: 1-Kbyte OTP (user data)
• Radio
VFQFPN32 (5 x 5 mm) – Frequency bands: 159-185 MHz, 413-479 MHz, 826-958 MHz
– Air data rate from 0.1 to 600 kbit/s
– Programmable TX power up to +20dBm
– RX sensitivity @ 1% BER:
◦ -132 dBm @300 bit/s 433 MHz OOK
◦ -128 dBm @300 bit/s 868 MHz 2(G)FSK
Product summary
◦ -112 dBm @38.4 bit/s 868 MHz 2(G)FSK
Reference Part number – Modulation schemes:
STM32WL33C8 ◦ 2(G)FSK, 2(G)MSK, 4(G)FSK
STM32WL33CB ◦ OOK, ASK
STM32WL33CC ◦ D-BPSK
STM32WL33xx ◦ DSSS (direct sequence spread spectrum)
STM32WL33K8
◦ I/Q channels data access
STM32WL33KB
◦ Compatible with proprietary and standardized wireless protocols
STM32WL33KC (W-MBUS, Sigfox, Mioty, KNX-RF, IEEE 802.15.4g, others)
– Suitable for worldwide certifications:
◦ Europe: ETSI EN 300 220, category 1 compliant, ETSI EN 303
131
◦ US: FCC part 15 and part 90
◦ Japan: ARIB STD T67, T108
– Fully-configurable hardware sequencer for autonomous radio operations
(Sniff mode, Frequency hopping, Low Duty Cycle mode, Listen before
talk)
• Wakeup radio receiver
– Low power autonomous wakeup receiver (LPAWUR), featuring:
◦ OOK data receiver channel
◦ Sensitivity: -50 dBm
◦ Current consumption: 4 µA in always-on autonomous mode

DS14221 - Rev 5 - November 2024 www.st.com

For further information contact your local STMicroelectronics sales office.
 STM32WL33xx

• Ultra-low power architecture

– Dynamic current consumption: 21 µA/MHz
– 14 nA in Shutdown mode
– 960 nA in Deepstop mode
– Radio only consumption:
◦ 4 mA in RX
◦ 8 mA in TX @ +10 dBm
◦ 78 mA in TX @ +20 dBm
– Consumption: 1.3 mA current in WFI conditions (direct HSE mode)
– Wakeup capability from both Deepstop and Shutdown modes
• Peripherals and analog front-end
– LCD driver with up to 96 (12x8) or 64 (16x4) matrix elements
– 12-bit ADC: up to 1 Msample/s with 8 single ended channels (or 4 differentials)
– 1x comparator
– 1x 6-bit sample-and-hold DAC output
– 1x LC sensor controller (for autonomous rotary-wheel based flow metering)
– Battery voltage monitoring with low-level detection
– Temperature monitoring
• Communication interfaces
– Up to 32 GPIOs (VFQFPN48), all with retention capability
– Up to 17 GPIOs (VFQFPN32), all with retention capability
– 1x USART. Supports of LIN, Smartcard Protocol, IrDA, SIR ENDEC specifications, and modem
operations (CTS/RTS)
– 1x LPUART (available also in low-power mode), with wakeup capability
– 1x SPI
– 1x SPI with I2S interface multiplexed
– 2x I2C (SMBus/PMBus)
– 1x DMA 8 channels controller, supporting ADC, DAC, SPIs, I2Cs, USART, LPUART, timers, AES
• Clock sources and timers
– Flexible clocking scheme, featuring:
◦ 64 MHz (HSI or PLL)
◦ Fail-safe 48 MHz crystal oscillator (HSE), with integrated trimming capacitors
◦ 32 kHz crystal oscillator (LSE)
◦ Integrated low-power 32 kHz RC (LSI)
– 1x 16-bits, four channels general purpose timer
– 1x 16-bits, two channels general purpose timer
– 1x RTC
– 1x independent watchdog
– Radio timer with wakeup capability
• Security
– Secure bootloader with SWD disabling
– AES-128 co-processor and 16-bit TRNG
– Embedded UART bootloader with selectable write and read-out protection
• Operating range and reset
– Ultra-low-power power-on-reset (POR) and power-down-reset (PDR)
– Programmable voltage detector (PVD)
– Supply voltage: from 1.7 to 3.6 V
– Temperature range: -40 ºC to 105 ºC
• All packages are ECOPACK2 compliant

DS14221 - Rev 5 page 2/91

 STM32WL33xx

Applications
• Asset tracking
• Wireless sensors
• Industrial monitoring and control
• Home energy management systems
• Smart home and alarm systems
• Building automation
• Heat cost allocator
• Remote metering

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 STM32WL33xx
Introduction

1 Introduction

This document provides the ordering information and mechanical device characteristics of the STM32WL33xx
microcontrollers, based on Arm® core.
This document must be read in conjunction with the STM32WL33xx reference manual (RM0511).
For information on the device errata with respect to the datasheet and reference manual, refer to the
STM32WL33xx errata sheet (ES0612).
For information on the Arm® Cortex®-M0+ core, refer to the Cortex®-M0+ technical reference manual, available
from the www.arm.com website.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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 STM32WL33xx
Introduction

1.1 Glossary

Table 1. Definition of terms

Acronym Description

AES Advanced encryption standard hardware accelerator

AHB Advanced high-performance bus
APB Advanced peripheral bus
BOR Brown out reset
CHF Channel filter
CRC Cyclic redundancy check
DMAMUX Direct memory access multiplexer
ETSI European telecommunications standards institute
GFSK Gaussian frequency shift keying
HSE High speed external clock oscillator
HSI High speed Internal clock oscillator
IRQ Interrupt request
LDO Low drop output
LPWAN Low-power wide-area network
LSE Low-speed external clock oscillator
LSI Low-speed internal clock oscillator
OTP One time programmable
PDR Power down reset
POR Power on reset
PVD Programmable voltage detector
PWR Power controller
SMPS Switch mode power supply
SPI Serial peripheral interface (communication standard)
SWD Single wire debug
LPAWUR Low power autonomous wakeup radio
SYSCFG System configuration
TIM Timer
VREF Voltage reference
WFI Wait for instruction (Arm instruction entering low power mode)
WDG Watchdog

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 STM32WL33xx
Description

2 Description

The STM32WL33xx is a high performance ultra-low power wireless application processor, intended for RF
wireless applications in the sub-1 GHz band. It is designed to operate in both the license-free ISM and SRD
frequency bands such as 433, 868, and 915 MHz.
It adopts a single-core architecture embedding an Arm® 32-bit Cortex®-M0+ CPU that can operate up to 64 MHz.
It integrates high-speed and flexible memory types: up to 256 Kbyte flash memory, and up to 32 Kbyte RAM, one-
time programmable (OTP) memory area of 1 Kbyte.
The STM32WL33xx embeds a wide set of peripherals, including a 20-pin (16 segments + 4 commons) LCD
driver, 12-bit, 8 channel ADC, analog comparator, DAC, LC sensor controller, RTC, IWDG, general purpose
timers, AES-128, RNG, CRC, communication interfaces such as USART, SPI, and I2C. Moreover, the security
features enable secure boot with USART/SWD block (write protection) and sensitive information storage in flash
(read-out protection).
Direct data transfer between memory and peripherals and from memory-to-memory is supported by seven DMA
channels with fully-flexible channel mapping by the DMAMUX peripheral.
It can be configured to support standalone or network processor applications. In the first configuration, the
STM32WL33xx operates as single device in the application for managing both the application code and
proprietary sub-1 GHz protocol stacks.
It operates in the -40 to +105 °C temperature range from a 1.7 V to 3.6 V power supply. A comprehensive set of
power-saving modes enables the design of low-power applications.
The integrated highly efficient SMPS step-down converter together with the state transition speed between low-
power and active states minimize in every condition the average current consumption enabling the
STM32WL33xx to be the wireless application processor most suited for battery-operated applications.
The STM32WL33xx comes in different package versions supporting up to 32 I/Os for the VFQFPN48 package
and 17 I/Os for the VFQFPN32 package.

Figure 1. Block diagram

32 kHz XO
48 MHz XO
32 kHz RC
64 MHz RC RF_SUBG
(ana)
MR_SUBG
RCC (dig) wakeup
SW / JTAG MPU
NVIC DMA MUX
GPIOA
CM0+ DMA BM 4S/1M LPAWUR
8ch wakeup LPAWUR
GPIOB AHB Up
Radio (ana)
AHB0

CRC (dig)
BUSMATRIX 3S/7M
RNG
AHB
AES Flash SRAM0 SRAM1 down
interface CTRL CTRL
PWRCTRL SRAM0 SRAM1 APB
Flash bridge
(16 Kbytes) (16 Kbytes)
(256 Kbytes
/8 Kbytes)
POR/
BOR APB APB
APB0 APB1
PVD bridge bridge
COMPCTRL

VDD CLKDETR
DBGMCU
LCD 16x4

DACCTRL
TIMER16

ADCITF
LCSCTRL

LPUART
SYSCFG

USART
TIMER2

SP13
I2C2
I2C1

SP11
IWDG

RTC

LDO
/SMPS
1 x DAC
COMP

ADC
Scaler

VDD12o VDD12I
analog

Temp.
1x
LCD

sensor
VDD12o_ram1

VDD power domain

DT58201

VDD12o power domain

VDD12I power domain
VDD12o_ram1 supply

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 STM32WL33xx
Functional overview

3 Functional overview

3.1 Architecture
The devices embed a sub-GHz RF subsystem that interfaces with a generic microcontroller subsystem using an
Arm Cortex-M0+ core. The main system consists of a 32-bit multilayer AHB bus-matrix interconnect:
• Three masters:
– CPU (Cortex® -M0+) core S-bus
– DMA1
– Sub-1 GHz radio subsystem
• Seven slaves:
– Internal flash memory on CPU (Cortex®-M0+) S bus
– Internal SRAM0 (16 Kbytes)
– Internal SRAM1 (16 Kbytes)
– APB0 peripherals (through an AHB to APB bridge)
– APB1 peripherals (through an AHB to APB bridge)
– AHB0 peripherals
– AHBRF including AHB to APB bridge and Radio peripherals (connected to APB2)
The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even
when several high-speed peripherals work simultaneously. This architecture is shown in Figure 2.

Figure 2. STM32WL33xx system architecture

ARM DMA
Radio system
Cortex-M0+ 7ch
seq

AHB UP Conv

S0 S1 S2 S3 S4 S5

Flash
M0

Flash
Controller
M1

SRAM0
M2

SRAM1

APB0
M3

AHB2APB
peripherals
APB1
M4

AHB2APB
peripherals
AHB0
M5

peripherals
AHB APB2
M6

AHB2APB
DOWN conv LPAWUR
DT58200.V1

BusMatrix 6x7
BusMatrix 6x7

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 STM32WL33xx
Functional overview

The system consists of a Cortex®-M0+ “Radio protocol and application” processor with its radio sub-system.
There is a single flash memory to be used by the CPU for both sub-1 GHz protocols and application
management. The peripherals are located on the different system buses (AHB, APB0, APB1, APB2 for the radio
system). There are 2 SRAM banks, a SRAM0 always power supplied and SRAM1 that can be programmed to be
always on or switchable.

3.2 Arm Cortex-M0+ core with MPU

The STM32WL33xx contains an Arm Cortex-M0+ microcontroller core. The Cortex-M0+ provides a low-cost
platform that meets the needs of CPU implementation, with a reduced pin count and low-power consumption,
while delivering outstanding computational performance and an advanced response to interrupts. The Cortex-M0+
can run from 1 MHz up to 64 MHz. The Cortex-M0+ processor is built on a highly area and power optimized 32-bit
processor core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy
efficiency through a small but powerful instruction set and extensively optimized design, providing high-end
processing hardware including a single-cycle multiplier. The interrupts are handled by the Cortex-M0+ nested
vector interrupt controller (NVIC). The NVIC controls specific Cortex-M0+ interrupts as well as the STM32WL33xx
peripheral interrupts. With its embedded Arm core, the STM32WL33xx family is compatible with all Arm tools and
software.

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 STM32WL33xx
Functional overview

3.3 Memories

3.3.1 Embedded flash memory

The flash controller implements the erase and program flash memory operation. The flash controller also
implements the read and write protection.
The flash memory features are:
• Memory organization:
– 1 bank of 256 Kbytes
– Page size: 2 Kbytes
• 32-bit wide data read/write
• Page erase (2 Kbytes) and mass erase
Flash controller features:
• flash memory read operations
• flash memory write operations: single data write, or 4x32-bits burst write
• flash memory erase operations
• page write protection mechanism (by 4 segments of variable sizes from 1 to 127 pages)
Option-byte loader hardware mechanism reserved for ST analog trimming bits.

3.3.2 Embedded SRAM

The STM32WL33xx integrates a total of 32 Kbytes of embedded SRAM split into two 16 Kbyte banks.

3.3.3 Embedded OTP

The one-time-programmable (OTP) is a memory of 1 Kbyte dedicated for user data. The user can protect the
OTP data area by writing the last word at address 0x1000 1BFC and by performing a system reset. This operation
freezes the OTP memory from further unwanted write operations.

3.3.4 Memory protection unit (MPU)

The MPU is used to manage accesses to memory to prevent one task from accidentally corrupting the memory or
resources used by any other active task. This memory area is organized into up to 8 protected areas. The MPU is
especially helpful for applications where critical or certified code must be protected against the behavior of other
tasks.

3.4 RF subsystem
The STM32WL33xx embeds an ultra-low-power radio supporting Sub-1GHz operation.
It integrates a high performance ultra-low power Sub-1GHz transceiver supporting different modulation schemes:
2(G)FSK, 4(G)FSK, OOK and ASK and air data rate programmable from 0.1 to 300 kbit/s for 2-GFSK and up to
600 kbit/s for 4-GFSK.
Moreover, the device integrates a Wake-Up radio system based on OOK receiver (LPAWUR).
The STM32WL33xx RF output power can be programmed to deliver up to +20 dBm, in TX+TXHP mode, enabling
long communication ranges. Up to +16 dBm in TXHP mode or up to +10 dBm in TX modes, exploiting the
extremely optimized architecture for ultra-low-current consumption and battery-operated system.
The STM32WL33xx receiver offers best in class sensitivity performance together with extremely low current
consumption. Moreover, it is compliant with ETSI CAT1 adjacent channel selectivity specification and very high
blocker rejection, resulting in receiver robustness and in the capability to demodulate packets even in the
presence of high interferer signals in very crowed frequency channel.
The IQ data access in receiver mode, coupled with polar mode control of the transmitter, enables the
implementation of custom modulation schemes using the embedded microcontroller or using an external DSP.

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 STM32WL33xx
Functional overview

3.4.1 RF front-end
The RF front-end is based on a direct modulation of the carrier in TX and used a low IF architecture in RX mode.
In transmit mode, three different topologies, with dedicated BOM configuration on the board, address operations
in different output power range according to the selection of TX and TX_HP.
Moreover, the output power is user selectable through the dedicated programmable register. A linearized,
smoothed analog control offers a clean power ramp-up.
In receive mode, the automatic gain control (AGC) can reduce the chain gain at both RF and IF locations, for
optimized interferer rejections. Thanks to the use of complex filtering and highly accurate I/Q architecture, high
sensitivity and excellent linearity can be achieved.

Figure 3. Sub-1GHz IP block diagram

SUBG_RX_CLK SUBG_RX_DATA

SoC
MR_SUBG
Global
(digital RF IP) registers
SoC APB
interface
RFSUBG Radio FSM
(analog RF IP) Radio
RRM
registers
Receive

RX RX analog chain In RX
Data link layer

Data buffer SoC AHB SoC

In TX manager interface RAM
2x
TX HP PA

SD
TX PA Freq. synth
PA interface

Radio control
Transmit

Power interrupts
control
Time
management

wakeup request
Wakeup/Sleep
management sleep allowance

DT58203
SUBG_TX_CLK SUBG_TX_DATA

3.4.2 TX and RX event alert

The STM32WL33xx is provided with the TX_SEQUENCE and RX_SEQUENCE signals which alert, respectively,
transmission and reception activities.
A signal can be enabled for TX and RX on two pins, through alternate functions:
• TX_SEQUENCE is available on PA10 (AF2) or PB14 (AF2)
• RX_SEQUENCE is available on PA8 (AF2) or PA11 (AF2)
The signal is high when radio is in TX (or RX), low otherwise.
The signals can be used to control external antenna switching and support coexistence with other wireless
technologies.
Note: The RF_ACTIVITY signal is used to notify if there is an ongoing RF operation (either TX or RX). It is a logical
OR between the RX_SEQUENCE and TX_SEQUENCE.

3.4.3 Low power autonomous wake up receiver (LPAWUR)

The STM32WL33xx includes an always-on ultra-low-power wake-up receiver. It is intended to use the reception of
a specific frame to trig the wake up the entire SOC while in Deepstop mode. To work correctly the receiver needs
a 32 kHz clock which can either be supplied by the internal LSI block or an external 32 kHz crystal.

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 STM32WL33xx
Functional overview

Figure 4. Wake up radio block diagram

WakeUp radio IP

Always-on Power domain Interruptible Power

domain

SoC Bus Matrix

AFE Configuration

Retained APB
Registers AHB2APB
Management
Analog Front-End

AFE Interface Digital

Controller

Switchable
Registers

interrupt IRQ

Wake-up event
Sleep allowance

DT58203.V1
The Receiver uses the Manchester OOK modulation only (G.E.Thomas encoding).
The default data rate is 1 kbit/s for the raw data which gives 2 kbit/s after Manchester encoding.
The frame format is a specific frame as described below, with few configurable bit fields in order to expand the
use of the WakeUp Radio IP.
The specific frame is composed of:
• a bit sync of 40 bits defined at ‘0’
• a frame sync of 8 bits corresponding to the pattern 0x99
• a payload of 56 bits
• a CRC defined on 16 bits, and calculated on the payload only

Figure 5. LPAWUR frame format

Manchester encoding

CRC calculation
Frame
bit sync Payload CRC
Sync
16 bits
40 bits 8 bits 56 bits
Init : 0x0000
0x0000000000 0x99
DT58204.V1

Polynom: 0x8005
(x16 + x15 + x2 + 1)

The analog section of the receiver is equipped with an automatic gain control system (AGC) which senses the
input signal level and acts to avoid saturation.

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 STM32WL33xx
Functional overview

3.5 Power supply management

3.5.1 SMPS step-down converter

The device integrates a step-down converter to improve low power performance when the VDD (aka VDDIO)
voltage is high enough.
The SMPS output voltage can be programmed from 1.2 V to 2.4 V with a granularity of 100 mV. The SMPS output
voltage can be controlled by the PWRC_CR5.SMPSLVL[3:0] register.
The relation between the SMPSLVL and the VOUT of the SMPS is given by Table 2:

Table 2. SMPS output voltage

SMPSLV VOUT Min. VBATT

0 1.2 V 1.95 V
1 1.2 V 1.95 V
2 1.2 V 1.95 V
3 1.3 V 1.95 V
4 1.4 V 2.0 V
5 1.5 V 2.0 V
6 1.6 V 2.15 V
7 1.7 V 2.2 V
8 1.8 V 2.3 V
9 1.9 V 2.45 V
10 2.0 V 2.6 V
11 2.1 V 2.7 V
12 2.2 V 2.8 V
13 2.3 V 2.8 V
14 2.4 V 2.9 V
15 2.4 V 2.9 V

It is internally clocked at 4 MHz or 8 MHz. It can be clocked at a frequency in-between 4 MHz and 8 MHz by
means of the KRM feature. In this case the SMPS can be clocked at System Clock divided by 8 to 16 by unitary
steps. This feature is useful to avoid that the channel to be received is at a frequency that is an integer multiple of
the SMPS clock.
The device can operate without the internal SMPS either by using a dedicated hardware setting, or by using the
bypass-on-the-fly (BOF) feature. The bypass-on-the-fly permits internal connection of the SMPS output to the
battery via a current-limited switch (Static mode), or bypass of the SMPS by the use of an internal regulator
(dynamic). In both modes the SMPS is off while the bypass-on-the-fly is operating, and a programmable current
limitation is provided. The static mode connects the SMPS output to the battery after the first start-up of the
STM32WL33xx, and the connection is maintained until a reset occurs. In this case, the transmission is limited to
+14dBm. The dynamic mode bypasses the SMPS with a regulator. For instance, this can be done dynamically to
use the SMPS during transmission and to bypass the SMPS via a regulator during reception.
The SMPS has the following possible configurations:
• SMPS_ON
– the VFBSD pin of the SMPS outputs a regulated voltage (from 1.2V to 2.4V)
– the SMPS needs a clock.
• No SMPS
– VFBSD pin must be connected or to an external supply or to VDD
– VLXSD pin must be floating
– the SMPS does not need a clock

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 STM32WL33xx
Functional overview

• STATIC BYPASS ON THE FLY

– the VFBSD pin is internally connected to VDDSD via a switch, with a maximum current of 40 mA
– the SMPS doesn’t need a clock and is disabled
• DYNAMIC BYPASS ON THE FLY
– the VFBSD pin internally connected to the output of a programmable voltage regulator, with a
maximum current of 40mA.
– the SMPS doesn’t need a clock and is disabled
Except for the configuration SMPS OFF, an L/C BOM must be present on the board and connected to the VFBSD
pad.

Figure 6. Power supply configuration

3.5.2 SMPS bypass on-the-fly (BOF)

Bypass on-the-fly (BOF) is a feature that allows the SMPS to be bypassed. This can be done directly with a power
switch (static bypass mode), or via an LDO (dynamic bypass mode).
In case extra radio sensitivity is needed, the user can switch to dynamic bypass mode before entering radio
receiver mode. In this way the SPSM is OFF. When BOF is done in static bypass mode, the SMPS is disabled
and the SMPS output is connected to the battery via an internal switch. In this case both Deepstop and Run mode
operations can be chosen.
When BOF is done in dynamic bypass mode, the SMPS is disabled and the LDO is enabled. The LDO is
connected between the battery and the VFBSD pin and its output voltage is programmable like the SMPS.
A current limitation is implemented in both static and dynamic bypass modes.

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 STM32WL33xx
Functional overview

3.5.3 Linear voltage regulators

The digital power supplies are provided by different regulators:
• main LDO (MLDO):
– provides 1.2 V from a 1.4 to 3.6 V input voltage
– supplies both VDD12i and VDD12o when the device is active
– is disabled during the low power mode (Deepstop)
• Low power LDO (LPREG):
– stays enabled during both active and low power phases
– provides 1.0 V or 1.2 V voltage selectable by software
– not connected to the digital domain when the device is active
– connected to the VDD12o domain during low power mode (Deepstop)
• Dedicated LDO (RFLDO) to provide a 1.2 V to the analog RF block
The embedded SMPS step-down converter is inserted between the external power and the LDOs.

Figure 7. Power supply domains overview

VDD VLX VFB

SMPS

LP Reg Main Reg RF LDOs

Always ON Interruptible Analog RF

VDDIO VDD12 domain
LSI, LSE, MR_SUBGHz_wakeup VDD12I
BOR, PVD, LPAWUR, LPUART, HSI, HSE,
PWR33, RCC33 COMP, RTC, IWDG, MR_SUBGHz,
LCD, DAC, LCSC, LPAWUR,

DT58206
PWRCo, RCCo Peripheral RCCi

3.5.4 Power voltage supervisor

The STM32WL33xx device embeds several power voltage monitoring:
• Power On reset (POR) / Power Down reset (PDR) / Brown-Out reset (BOR)
• BORH monitoring
• Power voltage detector (PVD)

3.6 Operating modes

The STM32WL33xx supports three main operating modes:
• Run mode
• Deepstop mode
• Shutdown mode
The transition from one mode to another one is managed through a PMU state machine.

3.6.1 Run mode

In Run mode, the STM32WL33xx is fully operational.
In Run mode:
• both regulators (MLDO and LPREG) are enabled
• the MLDO provides the power supply for both VDD12i and VDD12o

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 STM32WL33xx
Functional overview

• the system clock and the bus clock are running

• the CPU core and the radio can be used
• the power consumption may be reduced by gating the clock of the unused peripherals

3.6.2 Deepstop mode

Deepstop is the only low power mode of the STM32WL33xx allowing the restart from a saved context
environment and the application at wake-up to go on running.
The conditions to enter Deepstop mode are:
• The radio (MR_SUBG) is sleeping (no radio activity)
• The CPU is sleeping (WFI with SLEEPDEEP bit activated)
• No unmasked wake-up sources are active (including those from a previous wakeup sequence for which the
software did not clear the associated flag after wakeup) the PWRC_CR1.LPMS bit is equal to 0.
• The system is clocked on RC64MPLL (HSI or PLL locked mode)
• Reset PWRC_CR5.GPIORET bit when PWRC_DBGR.DEEPSTOP2 bit is set, otherwise set
PWRC_CR5.GPIORET bit
• If SMPS clock variable rate multiplier is enabled RCC_KRMR.KRMEN=1, in order to guarantee a good
SMPS startup at next wakeup, its mandatory to put RCC_CFGR.SMPSDIV=0.
In Deepstop mode:
• The system and the bus clocks are stopped as the RC64MPLL block is OFF
• the VDD12i power domain is switched off
• the VDDI2o power domain is ON and supplied by the LPREG which regulated voltage is:
– 1.2 V if the LCD is enabled (LCD_CR.LCDEN=1)
– 1.2 V if the Comparator scaler is enabled (COMP.SCALEN=1)
– 1.2 V if the bit PWRC_CR2.LPREG_FORCE_VH=1
– 1.0 V in all the other cases
The current regulation status of the LPREG is reported by the PWRC_CR2.LPREG_VH_STATUS bit:
• the RAM0 bank is kept in retention
• the other RAM banks are in retention or not, depending on software choice in PWRC_CR2 register
• the slow clock can be running or stopped, depending on the software configuration present before
Deepstop entry:
– ON or OFF
– LSE or LSI source
• The Comparator, LCD, RTC, IWDOG, LC Sensor Controller, DAC and LPUART stay active (if enabled and
one slow clock source is ON).
• The MR_SUBG wakeup block including its timer stay active (if enabled and one slow clock source is ON).
• The LPAWUR RFIP wakeup block including its timer stay active (if enabled and one slow clock source is
ON).
• The configurations of all the I/Os are latched before entering Deepstop mode:
– AF configuration is latched only for the I/Os on which is mapped at least one pin of a peripheral that
can be active in Deepstop mode (Comparator, LCD, RTC, IWDOG, LC Sensor Controller, DAC and
LPUART)
– I/Os analog switches configuration is retained for the I/Os on which is mapped at least one analog pin
of a peripheral that can be active in Deepstop mode (comparator)
– all the I/Os able to be in output driving either a static low or high level, some of them also the slow
clock information LCO or the RTC_OUT.
A version of the Deepstop mode called DEEPSTOP2 has been implemented to emulate the Deepstop mode
without losing the debugger connection and breakpoints nor watchpoints.
• This variant can be selected by setting the PWRC_DBGR.DEEPSTOP2 bit.
• In this case, the Deepstop mode sequence (entry and exit) is done without shutting down the VDD12i
power domain.
Possible wake-up sources are:

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 STM32WL33xx
Functional overview

• The radio block is able to generate two events to wake up the system through its embedded wake-up timer
running on low speed clock:
– SUBG RFIP wakeup time is reached
• the LPAWUR RFIP is able to generate a wakeup event
• the LCD is able to generate a wakeup event
• the COMP is able to generate a wakeup event (with polarity selection, like I/Os)
• the RTC is able to generate a wakeup event
• the LC sensor controller is able to generate a wakeup event
• the LPUART is able to generate a wakeup event
• the IWDG is able to generate a reset event
• All I/Os are able to wake up the system.
At wakeup, the hardware resources located in the VDD12i power domain are reset, the CPU reboots. The reason
for wakeup is visible in a PWRC register.

3.6.3 Shutdown mode

The Shutdown mode is the least power consuming mode. The conditions to enter Shutdown mode are the same
conditions needed to enter Deepstop mode except that the PWRC_CR1.LPMS bit must be equal to 1.
(PWRC_DBGR.DEEPSTOP2 bit must be maintained equal to 0).
In Shutdown mode, the STM32WL33xx is in ultra-low power consumption: all voltage regulators, clocks and the
RF interface are not powered. The STM32WL33xx can enter shutdown mode by internal software sequence.
There are two ways to exit shutdown mode: by asserting and de-asserting the RSTN pin or by configurable pulse
polarity on GPIO PB0.
In Shutdown mode:
• The system is powered down as both the regulators are OFF
• The VDDIO power domain is ON
• All the clocks are OFF, LSI and LSE are OFF
• The I/O pull-ups and pull-downs can be controlled during Shutdown mode, depending on the software
configuration
• Two wake-up sources are available: a low pulse on the RSTN pin or a configurable pulse polarity on GPIO
PB0.
The exit from Shutdown is like a POR start up. The BOR feature can be enabled or disabled during Shutdown.

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 STM32WL33xx
Functional overview

3.7 Reset management

The STM32WL33xx offers two resets:
• PORESETn: this reset is provided by the APMU analog power management unit block and corresponds to
a POR or BOR root cause. It is linked to power voltage ramp-up or ramp-down. This reset impacts all
resources of the STM32WL33xx device.
Exit from Shutdown mode is equivalent to a POR/BOR and thus generates a PORESETn.
• The PADRESETn (system reset): this reset is built through several sources:
– PORESETn
– Reset due to the watchdog The STM32WL33xx embeds a watchdog timer, which may be used to
recover from software crashes.
– Reset due to CPU Lockup. The Cortex-M0+ generates a lockup to indicate the core is in the lock-up
state resulting from an unrecoverable exception. The lock-up reset is masked if a debugger is
connected to the Cortex-M0+.
– Software system reset. The system reset request is generated by the debug circuitry of the Cortex-
M0+. The debugger sets the SYSRESETREQ bit of the application interrupt and reset control register
(AIRCR). This system reset request through the AIRCR can also be done by the embedded software
(into the hardfault handler for instance).
– Reset from the NRSTn external pin The NRSTn pin toggles to inform that a reset has occurred.
The PADRESETn resets all resources of the STM32WL33xx, except:
• debug features
• flash controller key management
• RTC timer
• power controller unit
• part of the RCC registers
The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case
of reset from the RSTN external pad, the reset pulse is generated when the pad is asserted low.

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 STM32WL33xx
Functional overview

3.8 Clock management

Three different clock sources may be used to drive the system clock (CLK_SYS) of the STM32WL33xx (see
Figure 8. Fast clock tree generation):
• HSI: high speed internal 64 MHz RC oscillator
• PLL64M: 64 MHz PLL clock based on HSE 48 MHz
• HSE (High Speed External):
– high speed 48 MHz external crystal
or
– provided by a single ended 48 MHz input instead of a crystal
The STM32WL33xx has also a slow frequency clock tree used by some peripherals (RTC, watchdog, LPUART,
LCDC, LPAWUR and MR_SUBG radio timer). Three different clock sources can be used for this slow clock tree:
• LSI: low speed low drift internal RC with a fixed frequency between 24 kHz and 49 kHz depending on the
sample. It is called the 32 kHz clock within this document for simplicity.
• LSE:
– 32.768 kHz low speed external crystal.
or
– provided by a single-ended 32.768 kHz input instead of a crystal
• The CLOCK_ROOT_DIV/512 (see Figure 8): In this case, the slow clock is not available in Deepstop mode
and it must not be used for peripherals working in Deepstop mode.
Figure 8 provides an overview of the fast clock tree in the STM32WL33xx.

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 STM32WL33xx
Functional overview

Figure 8. Fast clock tree generation

LSI RC0
32 kHz
CLKSLOWSEL
LCOSEL

CLK_RTC
1 10
CK_WDG
LCO CK_MR_SUBGHz_WKUP
0 01 CLK_LPAWUR_WKUP
CLK_LCD
CLK_ROOT_DIV / 512 11 CLK_SCI_WKUP

OSC32k_OUT CLK_TIM2
LSE OSC CLKTIM16
32 kHz
OSC32k_IN SYSCLKDIV

SYSCLK PRE CLKSYS

OSC_OUT /1, /2, /3, /6, to:
HSE OSC
/12, /24, /48 CPU
48 MHz or 1 CLK_ROOT 1
AHB0
OSC_IN 50 MHz APB0
0 SYSCLK PRE 0 APB2
/1, /2, /4, /8, SRAM
/16, /32, /64 AES

RC64MPLL HSESEL
HSESEL
HSI 64 MHz
+ PLL x 4/3 SYSCLKDIV
/2 00
01 CLK_SPI3 / I2S
CLKANA_ADC CLK_ROOT_DIV CLK_SYS 1x

CLK_SMPS

CLK_SYS SPI3I2CCLKSEL

MCO /1, /2, .., /32

HSE LSE 1
/3 1 CLK_LPUART
HSI 0
/4 0
HSE / 2048
LPUCLKSEL
HSESEL
CLK_SMPS_KRM
MCOSEL
1
/4 1 CLK_SMPS
0
/2 0
KRMEN
CLK_USART
SMPSDIV CLK_I2C
CLK_FLASH
CLK_PWR
CLK_RNG
CLK_MR_SUBGHz
CLK_LPAWUR_WKUP
CLKANA_ADC
CLKDIG_ADC

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Functional overview

3.8.1 System clock details

The HSI and the PLL64M clocks are provided by the same analog block which can synthesize:
• a non-accurate clock (target is 1% typical) when no external XO provides an input clock to this block
• an accurate clock when the external XO provides the 48 MHz and once its internal PLL is locked.
The use of PLL64M or HSE as clock source is mandatory for sub-1 GHz radio operations (because a high
accuracy clock is needed).
This fast clock source is used to generate all the fast clock of the device through dividers as shown in Figure 8.
After reset, the CLK_SYS is divided by four to provide a 16 MHz to the whole system (CPU, DMA, memories, and
peripherals). Then the software can program another system clock frequency (CLK_SYS) in the following way
using the RCC_CFGR.CLKSYSDIV bits:
• 000: CLK_SYS is CLK_ROOT
• 001: CLK_SYS is CLK_ROOT/2
• 010: CLK_SYS is CLK_ROOT/4 (HSESEL = 0) or CLK_ROOT/3 (HSESEL = 1)
• 011: CLK_SYS is CLK_ROOT/8 (HSESEL = 0) or CLK_ROOT/6 (HSESEL = 1) (forbidden when radio is in
use)
• 100: CLK_SYS is CLK_ROOT/16 (HSESEL = 0) or CLK_ROOT/12 (HSESEL = 1) (forbidden when radio or
ADC is in use)
• 101: CLK_SYS is CLK_ROOT/32 (HSESEL = 0) or CLK_ROOT/24 (HSESEL = 1) (forbidden when radio or
ADC is in use)
• 110: CLK_SYS is CLK_ROOT/64 (HSESEL = 0) or CLK_ROOT/48 (HSESEL = 1) (forbidden when radio or
ADC is in use)
Forbidden configuration means that the “in use” feature cannot work if the system clock runs at this frequency.
Special care must be taken when programming the CLK_SYS as some constraints need to be respected:
CLK_SYS frequency must be greater or equal to CLK_MR_SUBGHz.

3.9 Boot mode

Following CPU boot, the application software can modify the memory map at address 0x0000 0000. This
modification is performed by programming the REMAP bit in the flash controller. The following memory can be
remapped:
• main flash memory SRAM0 memory
The STM32WL33xx SOC has a pre-programmed bootloader supporting USART protocol with automatic baud rate
detection. The main features of the embedded bootloader are:
• auto baud rate detection up to 1 Mbps
• flash mass erase, section erase
• flash programming
• flash readout protection enable/disable
The pre-programmed bootloader is an application, which is stored in the STM32WL33xx internal ROM at
manufacturing time by STMicroelectronics. This application allows upgrading the device flash memory with a user
application using a serial communication channel (USART).
The bootloader is activated by hardware by forcing PA10 high during hardware reset, otherwise, application
residing in flash memory is launched.
STMicroelectronics provides a boot loader executed after each CPU reboot. This boot loader has its own
documentation.

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 STM32WL33xx
Functional overview

3.10 General purpose inputs/outputs (GPIO)

Each general-purpose I/O port has four 32-bit configuration registers, two 32-bit data registers, and a 32-bit set/
reset register. In addition, all GPIOs have a 32-bit locking register and two 32-bit alternate function selection
registers.
Each of the GPIO pins can be configured by software:
• Output states: push-pull or open drain + pull-up/down
• Output data from output data register or peripheral (alternate function output)
• Speed selection for each I/O
• Input states: floating, pull-up/down, analog
• Input data to input data register or peripheral (alternate function input)
• Bit set and reset register for bitwise write access
• Locking mechanism provided to freeze the I/O port configurations
• Analog function
• Alternate function selection registers
• Fast toggle capable of changing every clock cycle
• Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral
functions.

3.11 Direct memory access (DMA)

Direct memory access (DMA) provides high-speed data transfer between peripherals and memory as well as
memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources
free for other operations. The implemented DMA has an arbiter for handling the priority between DMA requests.
The DMA main features are as follows:
• Eight independently configurable channels (requests)
• Each of the eight channels is connected to dedicated hardware DMA requests, software trigger is also
supported on each channel. This configuration is done by software
• Priorities between requests from channels of the DMA are software programmable (4 levels consisting of
very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, and so
on.)
• Independent source and destination transfer size (byte, half word, word), emulating packing and
unpacking. Source/destination addresses must be aligned on the data size
• Support for circular buffer management
• event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together
in a single interrupt request for each channel
• Memory-to-memory transfer (SRAM0/SRAM1)
• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers
• Access to SRAMs, APB0 and APB1 peripherals as source and destination
• Programmable number of data to be transferred: up to 65536

3.12 Nested vectored interrupt controller (NVIC)

The interrupts are handled by the Cortex-M0+ Nested Vector Interrupt Controller (NVIC). The NVIC controls
specific Cortex-M0+ interrupts (address 0x00 to 0x3C) as well as 32 user interrupts (address 0x40 to 0xBC). In
the STM32WL33xx device, the user interrupts have been connected to the interrupt signals of the different
peripherals (GPIO, flash controller, timer, USART, and so on). These interrupts can be controlled using the ISER,
ICER, ISPR and ICOR registers (see “Cortex-M0+ Devices Generic User Guide”).

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Functional overview

3.13 Advanced encryption standard hardware accelerator (AES)

The AES hardware accelerator can be used to both encrypt and decrypt data using the AES algorithm. It is a fully
compliant implementation of the advanced encryption standard (AES) as defined by Federal Information
Processing Standards Publication (FIPS PUB 197, 2001 November 26). Multiple key sizes and chaining modes
are supported: ECB, CBC, CTR for key sizes of 128 bits The AES is a 32-bit AHB peripheral. It supports DMA
single transfers for incoming and outgoing data (two DMA channels required). The AES IP provides hardware
acceleration to AES crypto algorithm packaged in STM32WL33xx crypto library (excluding key length of 192-bit).
The main features of the AESare:
• NIST FIPS publication 197, Advanced Encryption Standard (AES) compliant implementation
• 128-bit data block processing
• Support for cipher keys length of 128-bit
• Encryption and decryption with multiple chaining modes: – Electronic Code Book (ECB) – Cipher Block
Chaining (CBC) – Counter Mode (CTR)
• 51 clock cycles for processing one 128-bit block of data with a 128-bit key in ECB mode
• Integrated key scheduler with its key derivation stage (ECB or CBC decryption only)
• 32-bit AHB interface for register accesses, supporting complete word access only (32- bit). NB: AHB
sequential accesses are not supported.
• 128-bit registers for storing initialization vectors (4× 32-bit)
• 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer
• Automatic data flow control with support of direct memory access (DMA) using two channels (one for
incoming data, one for processed data). Single transfers only.
• Data swapping logic to support 1-bit, 8-bit, 16-bit or 32-bit data
• Possibility for software to suspend a message if the IP needs to process another message with a higher
priority (context swapping)

3.14 True random number generator (RNG)

The RNG is a random number generator based on a continuous analog noise that provides a 16-bit value to the
host when read.

3.15 Cyclic redundancy check (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator
with polynomial value and size. Among other applications, the CRC-based techniques are used to verify data
transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify the
flash memory integrity. The CRC calculation unit helps to compute a signature of the software during runtime,
which can later be compared with a reference signature generated at link-time, and which can be stored at a
given memory location.

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Functional overview

3.16 General purpose timers

The STM32WL33xx embeds one general purpose timer (TIM2) supporting up to 4 independent channels, one
general purpose timer (TIM16) supporting one single channel and one complementary.

3.16.1 General Purpose timer (TIM2)

The general purpose 16-bit timer (TIM2) consists of a 16-bit auto-reload counter driven by a programmable
prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or
generating output waveforms (output compare, PWM). Pulse lengths and waveform periods can be modulated
from a few microseconds to several milliseconds using the timer prescaler on the timer input clock which is at
32MHz.
The TIM2 main features are:
• 16-bit up, down, up/down auto-reload counter
• 16-bit programmable prescaler allowing division (also “on the fly”) the counter clock frequency either by any
factor between 1 and 65536
• Up to 4 independent channels for:
– input capture
– output compare
– PWM generation (edge and center-aligned mode)
– one-pulse mode output
• Synchronization circuit to control the timer with external signals and to interconnect several timers together
• Repetition counter to update the timer registers only after a given number of cycles of the counter
• Interrupt/DMA generation on the following events:
– update: counter overflow/underflow, counter initialization (by software or internal/external trigger)
– input capture
– output comparison
– trigger event (counter start, stop, initialization or count by internal/external trigger)
• Supports incremental (quadrature) encoder for positioning purposes
• Trigger input for external clock or cycle-by-cycle current management
• The counter can be frozen in debug mode

3.16.2 General purpose timer (TIM16)

The TIM16 timer consists of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for
a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output
waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using
the timer prescaler and the RCC clock controller prescaler.
The main TIM16 features are:
• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor
between 1 and 65535
• One channel for:
– input capture
– output comparison
– PWM generation (edge-aligned mode)
– one-pulse mode output
– trigger event (counter start, stop, initialization or count by internal/external trigger)
• Complementary output with programmable dead-time
• Synchronization circuit to control the timer with external signals and to interconnect several timers together
• Repetition counter to update the timer registers only after a given number of cycles of the counter
• Break input to put the timer’s output signals in the reset state or a known state

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 STM32WL33xx
Functional overview

• Interrupt/DMA generation on the following events:

– update: counter overflow
– input capture
– output comparison
– break input (interrupt request)
• Synchronization circuit to trigger the DAC
• The counter can be frozen in debug mode.

3.17 Independent watchdog (IWDG)

TheSTM32WL33 integrates an embedded watchdog peripheral which offers a combination of high safety level,
timing accuracy and flexibility of use. The independent watchdog peripheral serves to detect and resolve
malfunctions due to software failure, and to trigger system reset when the counter reaches a given timeout value.
The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active
even if the main clock fails.
The IWDG is best suited to applications which require the watchdog to run as a totally independent process
outside the main application but have lower timing accuracy constraints. The counter can be frozen in debug
mode.

3.18 Real-time clock (RTC)

The STM32WL33xx integrates a real-time clock (RTC). It is an independent BCD timer/counter. The RTC
provides a time of day/clock/calendar with programmable alarm interrupt. RTC includes also a periodic
programmable wake-up flag with interrupt capability. The RTC provides an automatic wake-up to manage all low
power modes.
Two 32-bit registers contain seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of
month), month, and year, expressed in binary coded decimal format (BCD). The sub-second value is also
available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed
automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the
programmable alarm sub seconds, seconds, minutes, hours, day, and date.
One anti-tamper detection pin with programmable filter is available. A timestamp feature can be used to save the
calendar content. This function can be triggered by an event on the timestamp pin, by a tamper event, or by a
switch to Deepstop mode.
A digital calibration circuit is available to compensate for quartz crystal inaccuracy. After power-on reset, all RTC
registers are protected against possible parasitic write accesses. As long as the supply voltage remains in the
operating range, the RTC never stops, regardless of the device status (Run mode, low power mode or under
system reset).
The RTC contains 5 backup registers which are supplied through a switch that takes power either from the
VDD12I supply (when present) or from the VDD12O pin.
The backup registers are 32-bit registers used to store 20 bytes of user application data when VDD12I power is
not present. They are not reset by a system or power reset, or when the device wakes up from Deepstop mode.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device
from the low-power modes. The counter can be frozen in debug mode.

3.19 Inter-integrated circuit interface (I2C)

The I2C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial
I2C bus. It provides multi master capability, and controls all I2C bus-specific sequencing, protocol, arbitration, and
timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
It is also SMBus (system management bus) and PMBus (power management bus) compatible.
DMA can be used to reduce CPU overload. The counter can be frozen in debug mode.

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 STM32WL33xx
Functional overview

3.20 Universal synchronous/asynchronous receiver transmitter (USART)

The STM32WL33xx embeds a universal synchronous asynchronous receiver transmitter (USART) that offers a
flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ
asynchronous serial data format. The USART offers a very wide range of baud rates using a fractional baud rate
generator.
It supports synchronous one-way communication and half-duplex single wire communication. It also supports the
LIN (local interconnection network), SmartCard Protocol and IrDA (infrared data association) SIR ENDEC
specifications, and modem operations (CTS/RTS). It also supports multiprocessor communications.
High speed data communication is possible by using the DMA (direct memory access) for multibuffer
configuration.
The USART main features are:
• Full-duplex asynchronous communication
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or 8 to give flexibility between speed and clock tolerance
• Baud rate generator systems
• Two internal FIFOs for transmit and receive data, that can be enabled/disabled by software. FIFOs come
with status flags for FIFOs states.
• A common programmable transmit and receive baud rate of up to 2Mbit/s with the clock frequency at 16
MHz and oversampling is by 8
• Dual clock domain with a dedicated kernel clock allowing baud rate programming independent from the
PCLK reprogramming.
• Auto baud rate detection
• Programmable data word length (7 or 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous master/slave mode and clock output/input for synchronous communications
• SPI slave transmission underrun error flag Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Communication control/error detection flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Interrupt sources with flags
• Multiprocessor communications
• Wake up from mute mode (by idle line detection or address mark detection)

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 STM32WL33xx
Functional overview

3.21 Low power universal asynchronous receiver transmitter (LPUART)

The low power universal asynchronous receiver transmitted (LPUART) is an UART which allows bidirectional
UART communications with a limited power consumption. Only 32.768 kHz LSE clock is required to allow UART
communications up to 9600 baud/s. Higher baud rates can be reached when the LPUART is clocked by clock
sources different from the LSE clock.
Even when the microcontroller is in stop mode, the LPUART can wait for an incoming UART frame while having
an extremely low energy consumption. The LPUART includes all necessary hardware support to make
asynchronous serial communications possible with minimum power consumption.
It supports half-duplex single wire communications and modem operations (CTS/RTS). It also supports
multiprocessor communications.
DMA (direct memory access) can be used for data transmission/reception.
The main features are:
• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Programmable baud rate
• From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source
• Higher baud rates can be achieved by suing a higher frequency clock source
• Two internal FIFOs for transmit and receive data, that can be enabled/disabled by software. FIFOs come
with status flags for FIFOs states.
• Dual clock domain allowing:
– UART functionality and wakeup from stop mode
– convenient baud rate programming independent from the PCLK reprogramming
• Programmable data word length (7 or 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Transfer detection flags:
– receive buffer full
– transmit buffer empty
– busy and end-of-transmission flags
• Parity control:
– transmits parity bit
– checks parity of received data byte
• Four error detection flags:
– overrun error
– noise detection
– frame error
– parity error
• Interrupt sources with flags
• Multiprocessor communications: the LPUART enters mute mode if the address does not match
• Wakeup from mute mode (by idle line detection or address mark detection)

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 STM32WL33xx
Functional overview

3.22 Serial peripheral interface (SPI/I2S)

The STM32WL33xx embeds two serial peripheral interfaces (SPIs), the SPI1 and SPI3. The SPI3 supports I2S
protocol in addition to SPI features. SPI1 does not support I2S.
SPI or I2S mode is selectable by software. SPI Motorola mode is selected by default after a device reset.
The SPI interfaces allow communication at up to 32 Mbit/s in both master and slave modes.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial
communication with external devices. The interface can be configured as master, and in this case it provides the
communication clock (SCK) to the external slave device. The interface is also capable of operating in multimaster
configuration.
The Inter-IC sound (I2S) protocol is also a synchronous serial communication interface. It can operate in slave or
master mode with full duplex and half-duplex communication. It can address four different audio standards
including the Philips I2S standard, the MSB- and LSB-justified standards and the PCM standard.
The main SPI features are:
• Master or slave operation
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4-bit to 16-bit data size selection
• Multimaster mode capability
• 8 master mode baud rate prescalers up to fPCLK/2
• Slave mode frequency up to fPCLK/2
• NSS management by hardware or software for both master and slave: dynamic change of master/slave
operations
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Dedicated transmission and reception flags with interrupt capability
• SPI bus busy status flag
• SPI Motorola support
• Hardware CRC feature for reliable communication:
– CRC value can be transmitted as last byte in Tx mode
– automatic CRC error checking for last received byte
• Master mode fault, overrun flags with interrupt capability
• CRC error flag
• Two 32-bit embedded Rx and Tx FIFOs with DMA capability
• SPI TI mode support
• DMA capability for transmission and reception (16-bit wide)
The main I2S features are:
• Half-duplex communication (only transmitter or receiver)
• Master or slave operations
• 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz)
• Data format may be 16-bit, 24-bit or 32-bit
• Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data frame) by audio
channel
• Programmable clock polarity (steady state)
• Underrun flag in slave transmission mode, overrun flag in reception mode (master and slave) and Frame
Error Flag in reception and transmitter mode (slave only)
• 16-bit register for transmission and reception with one data register for both channel sides

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 STM32WL33xx
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• Supported I2S protocols:

– I2S Philips standard
– MSB-Justified standard (left-justified)
– LSB-Justified standard (right-justified)
– PCM standard (with short and long frame synchronization on 16-bit channel frame or 16-bit data
frame extended to 32-bit channel frame)
• Data direction is always MSB first
• DMA capability for transmission and reception (16-bit wide)
• Master clock can be output to drive an external audio component. Ratio is fixed at 256 × FS (where FS is
the audio sampling frequency)

3.23 Liquid crystal display controller (LCD)

The LCD controller is a digital controller/driver for monochrome passive liquid crystal display (LCD) with up to 8
common terminals and up to 16 segment terminals to drive 64 (16x4) or 96 (12x8) LCD picture elements (pixels).
The exact number of terminals depends on the device pinout.
The LCD is made up of several segments (pixels or complete symbols) which can be turned visible or invisible.
Each segment consists of a layer of liquid crystal molecules aligned between two electrodes. When a voltage
greater than a threshold voltage is applied across the liquid crystal, the segment becomes visible. The segment
voltage must be alternated to avoid an electrophoresis effect in the liquid crystal (which degrades the display).
The waveform across a segment must then be generated so as to avoid having a direct current (DC).
The main LCD features are:
• Highly flexible frame rate control.
• Supports Static, 1/2, 1/3, 1/4 and 1/8 duty
• Supports Static, 1/2, 1/3 and 1/4 bias
• Double buffered memory allows data in LCD_RAM registers to be updated at any time by the application
firmware without affecting the integrity of the data displayed.
– LCD data RAM of up to 16 x 32-bit registers which contain pixel information (active/inactive)
• Software selectable LCD output voltage (contrast) from VLCDmin to VLCDmax
• No need for external analog components:
– Astep-up converter is embedded to generate an internal VLCD voltage higher than VDD
– Software selection between external and internal VLCD voltage source. In the case of an external
source, the internal boost circuit is disabled to reduce power consumption
– A resistive network is embedded to generate intermediate VLCD voltages
– The structure of the resistive network is configurable by software to adapt the power consumption to
match the capacitive charge required by the LCD panel.
– Integrated voltage output buffers for higher LCD driving capability
• The contrast can be adjusted using two different methods:
– When using the internal step-up converter, the software can adjust VLCD between VLCDmin and
VLCDmax
– Programmable dead time (up to 8 phase periods) between frames
• Full support of Low power modes: the LCD controller can be displayed in DEESTOP mode or can be fully
disabled to reduce power consumption
• Built in phase inversion for reduced power consumption and EMI (electromagnetic interference)
• Start of frame interrupt to synchronize the software when updating the LCD data RAM
• Blink capability:
– Up to 1, 2, 3, 4, 8 or all pixels which can be programmed to blink at a configurable frequency
– Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz
• Used LCD segment and common pins should be configured as GPIO alternate functions and unused
segment, and common pins can be used for general purpose I/O or for another peripheral alternate
function.

DS14221 - Rev 5 page 28/91

 STM32WL33xx
Functional overview

3.24 Analog digital converter (ADC)

The STM32WL33xx SOC embeds a 12-bit ADC. The ADC consists in a 12-bit successive approximation analog-
to-digital converter (SAR) with 2 x 8 multiplexed channels allowing measurements of up to eight external sources
and up to three internal sources.
The main ADC features are:
• Conversion frequency is up to 1 Msample/s
• Three input voltage ranges are supported (0 to 1.2 V, 0 to 2.4 V, 0 to 3.6 V)
• Up to eight analog single ended channels or four analog differential inputs or a mix of both.
• Temperature sensor conversion.
• Battery level conversion up to 3.6 V
• ADC mode conversion only available, programmable in continuous or single mode
• ADC Down Sampler for multi-purpose applications to improve analog performance while off-loading the
CPU (ratio adjustable from 1 to 128)
• A watchdog feature to inform when data is outside thresholds
• DMA capability
• Interrupt sources with flags

3.24.1 Temperature sensor

The temperature sensor can be used to measure the junction temperature (Tj) of the device. The temperature
sensor is internally connected to the ADC input channels which are used to convert the sensor output voltage to a
digital value. To improve the accuracy of the temperature sensor measurement, each device is individually
factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory
area, accessible in read-only mode.

3.25 Analog comparator (COMP)

The STM32WL33xx output embeds one ultra-low power analog comparator COMP.
The comparator can be used for a variety of functions including:
• Wake-up from low-power mode triggered by an analog signal
• Analog signal conditioning
• Cycle-by-cycle current control loop when combined with a PWM output from a timer
• The comparator has configurable plus and minus inputs used for flexible voltage selection:
– multiplexed I/O pins
– internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by scaler (buffered
voltage divider)
– DAC output
• Programmable hysteresis
• Programmable speed / consumption
• The outputs can be redirected to an I/O or to timer inputs for triggering:
– break events for fast PWM shutdown
– cycle-by-cycle current control, using OCREF_CLR_INT through ETR inputs
– capture events
• Comparator output with blanking source
• The comparator has interrupt generation capability with wake-up from Sleep and Deepstop modes (through
the PWR controller).

DS14221 - Rev 5 page 29/91

 STM32WL33xx
Functional overview

3.26 Digital to analog converter (DAC)

The STM32WL33xx embeds one ultra-low power 6-bit DAC module. The DAC may be used in conjunction with
the DMA controller.
The DAC has three output channels:
• DACOUT_GPIO connected to GPIO PA13
• DACOUT_VCMBUF connected to VCMBUFF
• DACOUT_COMPMINUS connected to COMP MINUS input
Main DAC features:
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• DMA capability
• DMA underrun error detection and interrupt generation
• External triggers (GPIO, TIM16) for conversion
• Input voltage reference

3.27 LC sensor controller (LCSC)

The LC sensor controller controls DAC, COMP power-on/power-off and dedicated GPIOs (PB1, PA14, PB2) for
the measurement of LC networks damping times. The LC damping time measurements are used in fluid (typically
water) metering applications.
In this kind of application, the flow of a fluid in a pipe forces the rotation of a wheel, whose number of revolutions
permits to quantify the amount of consumed fluid. Three external LC networks, positioned on top of the wheel,
permit the counting of the revolutions. These networks are to be connected to identified GPIOs. Two of them allow
to find the position of the rotating wheel, whereas the other one is necessary to avoid tamper.
LC sensor controller main features:
• Manage the sequence of measurement of the 3 LC available networks (LCA, LCB, LCT)
• Manages the power-on/power-off of COMP, DAC
• Count the number of comparator (COMP) output edges for each LC to determine the wheel position or if
there is any tamper
• Count the number of wheel revolutions (a full revolution means that the wheel has started rotating from a
defined initial position up to returning to this position)
• Wakeup from low-power modes (WFI or Deepstop) and notify the system through an interrupt when the
total number of wheel revolutions reaches a given threshold fixed by the application user.

3.28 Debug support (DBG)

The STM32WL33xx embeds an Arm serial wire debug (SWD) interface that enables interactive debugging and
programming of the device. The interface is composed of only two pins: SWDIO and SWCLK. The enhanced
debugging features for developers allow up to 4 breakpoints and up to 2 watchpoints.

DS14221 - Rev 5 page 30/91

 STM32WL33xx
Pinouts and pin description

4 Pinouts and pin description

The STM32WL33xx comes in two package versions: VQFPN32 offering 17 GPIOs, and VFQFPN48 offering 32
GPIOs.

Figure 9. Pinout top view (QFN32 package - 5 mm x 5 mm)

VDDSD
VSSSD
VFBSD

VLXSD
VCAP
PB2
PB1
PB0
32
31
30
29
28
27
26
25
PA2 1 24 NRST
PA3 2 23 PB7
VDD_1 3 22 PA1
PA0 4 21 OSCIN
PA11 5
VFQFPN32 20 OSCOUT
PA10 6 19 VDDRF
PA9 7 18 TX
PA8 8 17 TX_HP
10

12
13
14
15
16
11
9
PB6
PB12
PB13
PB14
PB15

RX
EXTGND
LPAWUR

DT58209V1
Exposed ground pad

Figure 10. Pinout top view (VFQFPN48 package - 6 mm x 6 mm)

VDDSD
VSSSD
VFBSD

VLXSD
VCAP
PA15
PA14
PA13
PA12
PB2
PB1
PB0
48
47
46
45
44
43
42
41
40
39
38
37

PA2 1 36 NRST
PA3 2 35 PB8
VDD_1 3 34 PB9
PB3 4 33 PB10
PB4 5 32 PB11
PB5 6 31 PB7
PA0 7
VFQFPN48 30 PA1
PA4 8 29 OSCIN
PA11 9 28 OSCOUT
PA10 10 27 VDDRF
PA9 11 26 TX
PA8 12 25 TX_HP
13
14
15
16
17
18
19
20
21
22
23
24
PB6

PB12
PB13
PB14
PB15
VDD2

RX
EXTGND
PA5
PA6
PA7

LPAWUR

Exposed ground pad

DT58210V1

Note: All PAx and PBx type pins can wake up the circuit.

DS14221 - Rev 5 page 31/91

 STM32WL33xx
Pinouts and pin description

Table 3. Pin description

Pin number
Pin Name (function
VFQFPN VFQFPN Pin type Alternate functions Additional functions
after reset)
32 48

SWDIO, USART1_CK,
1 1 PA2 I/O TIM16_CH1, I2S3_MCK, ADC_VINM2
TIM2_CH1, LCD_SEG1
SWCLK, USART1_RTS_DE,
TIM16_CH1N, SPI3_SCK/
2 2 PA3 I/O ADC_VINP2
I2S3_CK, TIM2_CH2,
LCD_SEG2
3 3 VDD_1 S - 1.7 to 3.6 V battery voltage input
USART1_CTS, LPUART1_TX,
- 4 PB3 I/O SPI1_MOSI, TIM2_CH4, ADC_VINP0, COMP1_INN2
LCD_SEG8
LPUART1_TX, SPI3_MISO,
- 5 PB4 I/O ADC_VINM3, VCMBUFF
LCD_SEG13/LCD_COM5
LPUART1_RX, SPI3_NSS/
- 6 PB5 I/O I2S3_WS, LCD_SEG14/ ADC_VINP3
LCD_COM6
I2C1_SCL, USART_CTS,
4 7 PA0 I/O TIM2_CH3, LCD_SEG12/ -
LCD_COM4
LCO, LPUART1_TX,
- 8 PA4 I/O -
COMP1_OUT, TIM2_CH1
MCO, RX_SEQUENCE,
5 9 PA11 I/O SPI3_MOSI/I2S3_SD, -
SUBG_TX_CLOCK, LCD_SEG5
LPUART1_CTS,
6 10 PA10 I/O TX_SEQUENCE, I2S3_MCK, LCO
SUBG_TX_DATA, LCD_SEG4
USART1_TX, RTC_OUT,
7 11 PA9 I/O SPI3_NSS/I2S3_WS, -
TIM2_CH4, LCD_SEG3
RTC_OUT/RTC_TAMP1/
RTC_TS, USART1_RX,
8 12 PA8 I/O -
RX_SEQUENCE, SPI3_MISO,
TIM2_CH3, LCD_COM0
I2C1_SCL, LPUART1_TX,
COMP1_OUT, SPI3_SCK/
9 13 PB6 I/O -
I2S3_CK, TIM2_CH3,
LCD_SEG15/LCD_COM7
MCO, LPUART1_RX,
- 14 PA5 I/O -
TIM2_CH2, LCD_SEG9
I2C2_SCL, USART1_CTS,
- 15 PA6 I/O -
TIM2_CH1
I2C2_SDA, LPUART1_RTS_DE,
- 16 PA7 I/O -
TIM2_CH2
USART1_RTS_DE,
10 17 PB12 I/O LPUART1_CTS, LCO, SXTALO
TIM2_CH3
11 18 PB13 I/O I2C2_SMBA, TIM2_CH4 SXTALI
I2C1_SMBA, USART1_RX,
12 19 PB14 I/O TX_SEQUENCE, MCO, PVD_VIN
TIM2_ETR, LCD_COM3

DS14221 - Rev 5 page 32/91

 STM32WL33xx
Pinouts and pin description

Pin number
Pin Name (function
VFQFPN VFQFPN Pin type Alternate functions Additional functions
after reset)
32 48

USART1_TX, COMP1_OUT,
13 20 PB15 I/O -
LCD_VLCD
- 21 VDD2 S - 1.7 to 3.6 V battery voltage input
14 22 RX LPAWUR I/RF - RF RX port
15 23 RX I/RF - RF RX port
16 24 EXTGND S - -
17 25 TX_HP O/RF - RF TX port
18 26 TX O/RF - RF TX port
1.7 to 3.6 V battery voltage
19 27 VDDRF S -
input
20 28 OSCOUT I/O - 48 MHz crystal
21 29 OSCIN I/O - 48 MHz crystal
I2C1_SDA, USART1_TX,
22 30 PA1 I/O TIM16_BRK, TIM2_CH4, -
LCD_SEG0
I2C1_SDA, LPUART1_RX,
RF_ACTIVITY, SPI3_MOSI/
23 31 PB7 I/O -
I2S3_SD, TIM2_ETR,
LCD_COM2
I2C1_SCL, USART1_RTS_DE,
- 32 PB11 I/O LC_ACTIVITY, SPI1_SCK, -
TIM2_CH1
I2C1_SDA, SPI1_NSS,
- 33 PB10 I/O -
TIM2_CH2
USART1_TX, LPUART1_CTS,
- 34 PB9 I/O -
SPI1_MOSI
USART1_CK, LPUART_RX,
- 35 PB8 I/O -
SPI1_MISO, TIM2_CH4
24 36 NRST RSTS - Reset pin
1.7 to 3.6 V battery voltage input
25 37 VDDSD S -
SMPS input
26 38 VLXSD S - SMPS LX pin
27 39 VSSSD S - SMPS Ground
28 40 VFBSD S - SMPS output
29 41 VCAP S - 1.2 V digital core
I2C1_SMBA, SWDIO,
- 42 PA12 I/O -
SPI1_NSS, TIM2_CH1
I2C2_SCL, SWCLK, SPI1_SCK,
- 43 PA13 I/O COMP1_INN0, DACOUT_GPIO
TIM2_ETR, LCD_SEG10
I2C2_SDA, SPI1_MISO,
- 44 PA14 I/O COMP1_INP, LCB
LCD_SEG11
I2C2_SMBA, USART1_RX,
- 45 PA15 I/O -
SPI1_MOSI

DS14221 - Rev 5 page 33/91

 STM32WL33xx
Pinouts and pin description

Pin number
Pin Name (function
VFQFPN VFQFPN Pin type Alternate functions Additional functions
after reset)
32 48

USART1_RX,
LPUART1_RTS_DE,
30 46 PB0 I/O TIM16_CH1, SPI1_NSS, COMP1_INN1, ADC_VINM1
ANTENNA_SWITCH,
LCD_COM1
USART1_CK, SWDIO,
31 47 PB1 I/O TIM16_CH1N, SPI1_SCK, COMP1_INP, ADC_VINP1, LCA
SUBG_RX_DATA, LCD_SEG6
USART1_RTS_DE, SWCLK,
32 48 PB2 I/O TIM16_BRK, SPI1_MISO, COMP1_INP, ADC_VINM0, LCT
SUBG_RX_CLK, LCD_SEG7
Exposed Exposed
GND S - Ground
pad pad

Table 4. Alternate function port A

AF0 AF1 AF2 AF3 AF4 AF5 AF6

I2C1/I2C2/ SYS_AF/
Port SYS_AF/ SYS_AF/ SYS_AF/ SYS_AF/ SYS_AF/
SYS_AF/RTC/ USART/ Single-wire
TIM2/COMP SPI1/SPI3 TIM2 LCD
USART debug
LPUART

LCD_SEG12
PA0 I2C1_SCL USART1_CTS - - TIM2_CH3 -
/LCD_COM4
PA1 I2C1_SDA USART1_TX TIM16_BRK - TIM2_CH4 - LCD_SEG0
PA2 SWDIO USART1_CK TIM16_CH1 I2S3_MCK TIM2_CH1 SWDIO LCD_SEG1

USART1_RTS_ SPI3_SCK/
PA3 SWCLK TIM16_CH1N TIM2_CH2 SWCLK LCD_SEG2
DE I2S3_CK
PA4 LCO LPUART1_TX COMP1_OUT - TIM2_CH1 - -
PA5 MCO LPUART1_RX - - TIM2_CH2 - LCD_SEG9
PA6 I2C2_SCL USART1_CTS - - TIM2_CH1 - -
LPUART1_RTS
PA7 I2C2_SDA - - TIM2_CH2 - -
_DE
RTC_OUT/
Port A RX_SEQUEN
PA8 RTC_TAMP1/ USART1_RX SPI3_MISO TIM2_CH3 - LCD_COM0
CE
RTC_TS
SPI3_NSS/
PA9 - USART1_TX RTC_OUT TIM2_CH4 - LCD_SEG3
I2S3_WS
TX_SEQUEN SUBG_TX_
PA10 - LPUART1_CTS I2S3_MCK - LCD_SEG4
CE DATA

RX_SEQUEN SPI3_MOSI/ SUBG_TX_

PA11 MCO - LCD_SEG5
CE I2S3_SD CLOCK

PA12 I2C1_SMBA SWDIO - SPI1_NSS TIM2_CH1 - -

PA13 I2C2_SCL SWCLK - SPI1_SCK TIM2_ETR - LCD_SEG10
PA14 I2C2_SDA - - SPI1_MISO - - LCD_SEG11
PA15 I2C2_SMBA USART1_RX - SPI1_MOSI - - -

DS14221 - Rev 5 page 34/91

 STM32WL33xx
Pinouts and pin description

Table 5. Alternate function port B

AF0 AF1 AF2 AF3 AF4 AF5 AF6

I2C1/I2C2/ SYS_AF/
Port SYS_AF/ SYS_AF/ SYS_AF/
SYS_AF/RTC/ USART/ SYS_AF/ LCD
TIM16/COMP SPI1/SPI3 TIM2
USART LPUART

LPUART1_RTS ANTENNA_
PB0 USART1_RX TIM16_CH1 SPI1_NSS - LCD_COM1
_DE SWITCH
SUBG_RX_
PB1 USART1_CK SWDIO TIM16_CH1N SPI1_SCK - LCD_SEG6
DATA
USART1_RTS_ SUBG_RX_
PB2 SWCLK TIM16_BRK SPI1_MISO - LCD_SEG7
DE CLOCK
PB3 USART1_CTS LPUART1_TX - SPI1_MOSI TIM2_CH4 - LCD_SEG8
LCD_SEG1
PB4 - LPUART1_TX - SPI3_MISO - - 3/
LCD_COM5

SPI3_NSS/ LCD_SEG1
PB5 - LPUART1_RX - - - 4/
I2S3_WS LCD_COM6

SPI3_SCK/ LCD_SEG1
PB6 I2C1_SCL LPUART1_TX COMP1_OUT TIM2_CH3 - 5/
I2S3_CK LCD_COM7
Port B

RF_ACTIVIT SPI3_MOSI/
PB7 I2C1_SDA LPUART1_RX TIM2_ETR - LCD_COM2
Y I2S3_SD
PB8 USART1_CK LPUART1_RX - SPI1_MISO TIM2_CH4 - -
PB9 USART1_TX LPUART1_CTS - SPI1_MOSI - - -
PB10 I2C1_SDA - - SPI1_NSS TIM2_CH2 - -
USART1_RTS_ LC_ACTIVIT
PB11 I2C1_SCL SPI1_SCK TIM2_CH1 - -
DE Y
USART1_RTS_
PB12 LPUART1_CTS LCO - TIM2_CH3 - -
DE
PB13 I2C2_SMBA - - - TIM2_CH4 - -
TX_SEQUEN
PB14 I2C1_SMBA USART1_RX MCO TIM2_ETR - LCD_COM3
CE
PB15 - USART1_TX COMP1_OUT - - - LCD_VLCD

DS14221 - Rev 5 page 35/91

 STM32WL33xx
Application circuits

5 Application circuits

The schematics below are purely indicative.

Figure 11. STM32WL33xx application circuit without SMPS, VFQFPN48 package

VDD

C56

GND

VDD
GND
C61 C2
48
47
46
45
44
43
42
41
40
39
38
37

GND
PB1

VCAP
PB2

PB0
PA15

PA13

VFBSD
VSSSD
VLXSD
VDDSD
PA14

PA12

36
NRST
35
VDD PB8
1 34
PA2 PB9
2 33
PA3 PB10 X1
3 32
VDD_1 PB11 48MHz
4 31
PB3 PB7
C12 5
6
7
PB4
PB5 STM32WL33 PA1
OSCIN
30
29
28
VDD
PA0 OSCOUT GND
8 27
PB14/ ATB1/PVD_VIN
PB12 / ATB3 / SXTAL0

PA4 VDDRF VDD

PB13 / ATB2 / SXTALI

GND 9 26
PA11 TX
10 25 C13
PA10 TX_HP L3 C50
11 C49
PA9
12
PA8
PB15/ ATB0

EXP_PAD
LPAWUR

EXTGND

GND GND
VDD_2

GND
TX
C6
PB6
PA5
PA6
PA7

RX

Open
L4 L5
21
13

23
14
15
16
17
18
19
20

22

24

49

L6
TX_HP
C9 C10 C11 C66

Short
R48

GND

GND GND GND

C37
GND L7 C54 J1
GND L14
0R
VDD C62 C63
R49 C15
NM NM
C14
VDD C52

GND GND GND

GND GND
GND L8 C60
Matching network for exernal antenna
L10 NM

GND

Matching network for LPAWUR path

DT58212

DS14221 - Rev 5 page 36/91

 STM32WL33xx
Application circuits

Figure 12. STM32WL33xx application circuit with SMPS, VFQFPN48 package

L2

C4 C56

GND L1

VDD
GND
C61 C2 C1
48
47
46
45
44
43
42
41
40
39
38
37
GND GND
PB1

VCAP
PB2

PB0
PA15

PA13

VFBSD
VSSSD
VLXSD
VDDSD
PA14

PA12
36
NRST
35
VDD PB8
1 34
PA2 PB9
2 33
PA3 PB10 X1
3 32
VDD_1 PB11 48MHz
4 31
PB3 PB7
C12 5 30
6
7
PB4
PB5
PA0
STM32WL33 PA1
OSCIN
OSCOUT
29
28
GND
8 27
PB14/ ATB1/PVD_VIN
PB12 / ATB3 / SXTAL0

PA4 VDDRF VDD

PB13 / ATB2 / SXTALI

GND 9 26
PA11 TX
10 25 C13
PA10 TX_HP L3 C50
11 C49
PA9
12
PA8
PB15/ ATB0

EXP_PAD
LPAWUR

EXTGND

GND GND
VDD_2

GND
TX
C6
PB6
PA5
PA6
PA7

RX

Open
L4 L5
21
13

23
14
15
16
17
18
19
20

22

24

49

L6
C67 R75 TX_HP
C9 C10 C11 C66

Short
R48

R76 GND
GND X3
GND GND GND
C37 C68 R74
GND L7 C54 J1
GND L14
0R
VDD C62 C63
R49 C15
NM NM
C14
VDD C52

GND GND GND

GND GND
GND L8 C60
Matching network for external antenna
L10 NM

GND

DT58213
Matching network for LPAWUR path

Table 6. Application circuit external components

Components Description

C12 Decoupling capacitor for VDD_1

C52 Decoupling capacitor for VDD_2
C13 Decoupling capacitor for VDDRF
C61 Decoupling capacitor for VCAP
C1, C2 Decoupling capacitor for VDDSD. Input capacitors for internal DCDC converter
C4, C56 Output capacitors for internal DCDC converter
L2 Power inductor for DCDC converter.
L1 SMPS noise filter
C49, C50 Decoupling capacitor for PA VDD pin
C67, C68 32.768 kHz crystal loading capacitors
L3 RF choke inductor
L7, C14, C15 Filter/matching for RX path
L4, C9, L5, C10 Filter/matching for TX path
C6, L6, C11 Notch filter and low pass filter
C54, C60, C66 DC blocking capacitors
X1 48 MHz crystal
L10, L8 Filter/matching network for RX LPAWUR path

DS14221 - Rev 5 page 37/91

 STM32WL33xx
Electrical characteristics

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to ground (GND).

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the following standard
conditions:
• Ambient temperature is TA = 25 °C
• Supply voltage is VDD: 3.3 V
• System clock frequency is 64 MHz (clock source HSI)
• SMPS clock frequency is 4 MHz, if not specified otherwise
Data based on characterization results, design simulation and/or technology characteristics are indicated in the
table footnotes and are not tested in production. Based on characterization, the minimum and maximum values
refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V. They are given only as design
guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of
samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error
less than or equal to the value indicated (mean ± 2σ).

DS14221 - Rev 5 page 38/91

 STM32WL33xx
Electrical characteristics

6.2 Absolute maximum ratings

Absolute maximum ratings are those values above which damage to the device may occur. Functional operation
under these conditions is not implied. All voltages refer to GND.

Table 7. Absolute maximum ratings

Pin name Comment Min. Max. Unit

VDD_1, VDD_2, VDDRF,

DC-DC converter supply voltage input and output -0.3 +3.9
VDDSD
VCAP DC voltage on linear voltage regulator 0.3 +1.4
OSCOUT, OSCIN DC Voltage on HSE 0.3 +1.32
PAx and PBx DC voltage on digital input/output pins 0.3 +3.9
VLXSD, VFBSD DC voltage on analog pins 0.3 +3.9 V
XTAL0/PB12, XTAL1/PB13 DC voltage on XTAL pins 0.3 +3.9
RX DC voltage on RF pin 0.3 +1.4
TX DC voltage on RF pin 0.3 +3.9
TX_HP DC voltage on RF pin 0.3 +3.9
RX LPAWUR DC voltage on RF pin 0.3 +3.9
Variations between different supplies: VDD_x and
|ΔVDD| - 50 mV
VDDRF, VDD_x and VDDSD(1)

1. VDD_1 and VDD_2 to be shorted on PCB.

Table 8. Current characteristics

Symbol Ratings Max. Unit

ΣIVDD Total current into sum of all VDD power lines (source) 130

ΣIVGND Total current out of sum of all ground lines (sink) 130

IVDD(PIN) Maximum current into each VDD power pin (source) 100

IVGND(PIN) Maximum current out of each ground pin (sink) 100

Output current sunk by any I/O and control pin 20 mA

IIO(PIN)
Output current sourced by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins 100
ΣIIO(PIN)
Total output current sourced by sum of all I/Os and control pins 100
Σ|IINJ(PIN)| Total injected current (sum of all I/Os and control pins) -50

Table 9. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -40 to +125

°C
TJ Maximum junction temperature 125

DS14221 - Rev 5 page 39/91

 STM32WL33xx
Electrical characteristics

6.3 Operating conditions

6.3.1 Operating range

Table 10. Operating range

Parameter Min. Typ. Max. Unit

Operating battery supply voltage (VBAT) 1.7 3.3 3.6 V

Operating ambient temperature range -40 25 +105 °C

6.3.2 Thermal properties

The maximum chip junction temperature (TJmax.) must never exceed the values in general operating conditions.
The maximum chip-junction temperature, TJ max., in degrees Celsius, can be calculated using the equation:

T Jmax . = TAmax. + PDmax × θJA (1)

where:
• TA max. is the maximum ambient temperature in °C
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W
• PD max. is the sum of PINT max. and PI/O max. (PD max. = PINT max. + PI/O max.)
• PINT max. is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power
PI/O max represents the maximum power dissipation on output pins:
• PI/O max. = Σ (VOL × IOL) + Σ ((VDD – VOH) × IOH)
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the applications.

Table 11. Thermal data

Symbol Parameter Value Unit

Thermal resistance junction-ambient VFQFPN48 - 6 mm x 6 mm 25.1

QJA °C/W
Thermal resistance junction-ambient VFQFPN32 - 5 mm x 5 mm 26.9

DS14221 - Rev 5 page 40/91

 STM32WL33xx
Electrical characteristics

6.3.3 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient
temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program
location in memory and executed binary code.
The MCU is put under the following conditions:
• all I/O pins are in pull-up or pull-down configuration
• all peripherals are disabled except when explicitly mentioned
• the flash memory access time is adjusted with the minimum number of wait states.

Table 12. Shutdown and Reset current

Typ.
Symbol Parameter Test condition Unit
VDD = 3.3 V

Shutdown - 14 nA
ICORE
Current under Reset condition - 955 µA

Table 13. Current consumption in Deepstop mode

Typ.
Symbol Parameter Test condition Unit
VDD = 3.3 V

No timer, only wake-up GPIO enabled, RAM0 retained 910 nA

No timer, only wake-up GPIO enabled, all RAM retained 980 nA
(32 kHz LSI), RAM0 retained 1460 nA
(32 kHz LSI), all RAM retained 1540 nA
(32 kHz LSE), RAM0 retained 1163 nA
(32 kHz LSE), all RAM retained 1240 nA
Timer source LSI RTC ON 1710 nA

ICORE Deepstop current(1) Timer source LSI IWDG ON 1558 nA

Timer source LSI, RTC and IWDG ON 1748 nA
Timer source LSE RTC ON 1430 nA
Timer source LSE IWDG ON 1273 nA
Timer source LSE LPUART ON 1370 nA
Timer source LSE RTC, LPUART and IWDG ON 1670 nA

Timer source LSE VLCD external, static duty(2) 1880 nA

Timer source LSE VLCD external, 1/4 duty(3) 2090 nA

1. The current consumption in Deepstop mode is measured considering that the entire SRAM is retained.
2. LCD division ratio 256, all pixels active, no LCD connected.
3. LCD 1/3 bias, division ratio 64, all pixels active, no LCD connected.

DS14221 - Rev 5 page 41/91

 STM32WL33xx
Electrical characteristics

Table 14. Current consumption in Run and WFI mode with SMPS ON (SMPS frequency 4 MHz, SMPS Vout
=1.4 V)

Typ.
Symbol Parameter Test condition Unit
VDD = 3.3 V

CPU in Run (16 MHz). Dhrystone, clock source PLL64 2172 µA

CPU in Run (32 MHz). Dhrystone, clock source PLL64 2532 µA
CPU in Run (64 MHz). Dhrystone, clock source PLL64 3210 µA
ICORE Supply current
CPU in WFI (16 MHz), all peripherals off, clock source PLL64 1899 µA
CPU in WFI (32 MHz), all peripherals off, clock source PLL64 1984 µA
CPU in WFI (64 MHz), all peripherals off, clock source PLL64 2143 µA
Computed value: (CPU 64 MHz Dhrystone - CPU 32 MHz Dhrystone) /
IDYNAMIC Dynamic current 21.18 μA/MHz
32

Table 15. Current consumption in Run and WFI mode with SMPS bypassed

Typ.
Symbol Parameter Test condition Unit
VDD = 3.3 V

CPU in Run (16 MHz). Dhrystone, clock source PLL64 2422 µA

CPU in Run (32 MHz). Dhrystone, clock source PLL64 3245 µA
CPU in Run (64 MHz). Dhrystone, clock source PLL64 4771 µA
ICORE Supply current in Run mode
CPU in WFI (16 MHz), all peripherals off, clock source PLL64 1788 µA
CPU in WFI (32 MHz), all peripherals off, clock source PLL64 1989 µA
CPU in WFI (64 MHz), all peripherals off, clock source PLL64 2368 µA
Computed value: (CPU 64 MHz Dhrystone - CPU 32 MHz
IDYNAMIC Dynamic current 47.68 µA/MHz
Dhrystone) / 32

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 STM32WL33xx
Electrical characteristics

Table 16. Peripheral current consumption at VDD=3.3V, T=25°C System clock 32 MHz, SMPS ON

Peripheral Typical value Unit

GPIOA 1
GPIOB 1
DMA 38
AES 32
RNG 103
CRC 6
SYSCFG 34
RTC 18
WDG 11
USART 77
LPUART 56
SPI1 29
SPI3 38
I2S3 45 µA
I2C1 37
I2C2 37
TIM2 152
TIM16 94
LCD 11
COMP 1
PVD 0
MRSUBG 68
LPAWUR 4
DBGMCU 1
SYSTICK 10
DAC 375
ADC 28

DS14221 - Rev 5 page 43/91

 STM32WL33xx
Electrical characteristics

6.3.4 RF general characteristics

All performance data are referred to a 50 Ω antenna connector, via reference design.
Two reference test conditions are used in the RX measurements: high performance mode (HPM), where the
priority is given to the performances, and low power mode (LPM) where the priority is given to the low
consumption.
High performance mode (HPM) conditions: VDD = 3.3 V, TA = 25 o C, SMPS ON, SMPS frequency 4 MHz (unless
otherwise stated), SMPS Vout = 1.4 V,16 MHz system clock, HSIPLL mode, HSE GMC setting 0x0A and
PA_LEVEL7 = 81.
Low power mode (LPM) conditions: SMPS ON (unless otherwise stated), SMPS frequency 4 MHz (unless
otherwise stated), SMPS Vout =1.2 V, LDO RF bypassed, 16 MHz system clock, HSE direct mode, HSE GMC
setting 0x0A.
For RX current consumption, the global SOC consumption is reported as well as the computed contribution due to
the sub-1 GHz radio alone (difference between the global consumption and the SOC consumption in WFI mode).
Transmission measurements are performed for VDD = 3.3 V, TA = 25 o C, SMPS ON, high performance mode
(HPM).

Table 17. Current consumption in reception, fc = 915 MHz

Parameter Test condition HPM LPM Unit

STM32WL33xx supply current As detailed above 7.0 5.7

CPU current CPU in WFI state 1.8 1.3 mA
Radio supply current contribution Computed value 5.2 4.4

Table 18. Current consumption in reception, fc = 868 MHz (SMPS clock frequency = 4.27 MHz)

Parameter Test condition HPM LPM Unit

STM32WL33xx supply current As detailed above 6.8 5.6

CPU current CPU in WFI state 1.8 1.3 mA
Radio supply current contribution Computed value 5.0 4.3

Table 19. Current consumption in reception, fc = 433 MHz

Parameter Test condition HPM LPM Unit

STM32WL33xx supply current As detailed above 6.7 5.5

CPU current CPU in WFI state 1.8 1.3 mA
Radio supply current contribution Computed value 4.9 4.2

Table 20. Current consumption in transmission, fc = 433 MHz

Parameter Test condition HPM Unit

Measurements TX @ CW 10 dBm
12.5 mA
TX pin connected, TX Mode

Measurements TX @ CW 14 dBm
25 mA
Supply current TXHP pin connected, TXHP mode
Measurements TX @ CW 16 dBm
TXHP pin connected, TXHP mode PA_DEGEN_ON 31 mA
VSMPS = 1.6 V

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 STM32WL33xx
Electrical characteristics

Table 21. Current consumption in transmission mode, fc = 868 MHz

Parameter Test condition HPM Unit

Measurements TX @ CW 10 dBm
TX pin connected, TX Mode 10 mA
PA_LEVEL7 = 78
Measurements TX @ CW 14 dBm
22 mA
TXHP pin connected, TXHP mode
Supply current
Measurements TX @ CW 16 dBm
30.5 mA
TXHP pin connected, TXHP mode, VSMPS = 1.5 V, PA_DEGEN_ON
Measurements TX @ CW 20 dBm
TX + TXHP pins connected 80 mA
VSMPS = 2 V, PA_DEGEN_ON

Table 22. Current consumption in transmission mode, fc = 915 MHz

Parameter Test condition HPM Unit

Measurements TX @ CW 10 dBm
10.5 mA
TX pin connected, TX Mode
Measurements TX @ CW 14 dBm
22 mA
TXHP pin connected, TXHP mode

Supply current Measurements TX @ CW 16 dBm

TXHP pin connected, TXHP mode, VSMPS 30.5 mA
= 1.5 V PA_DEGEN_ON
Measurements TX @ CW 20 dBm
TX+TXHP pin connected, TX+TXHP mode, 80 mA
VSMPS = 2.2 V PA_DEGEN_ON

Table 23. RF state transition times

Parameter Test condition Typ. Unit

RADIO ENABLE to TX time Including PLL calibration 111 µs

RADIO ENABLE to RX time Including PLL calibration 101 µs
RX to TX Including PLL calibration 87 µs
TX to RX Including PLL calibration 102 µs

Table 24. General characteristics

Parameter Typ. Unit

413-479 MHz
Frequency range
826-958 MHz
2-(G)FSK 0.1-300 ks/s
Symbol rate 4-(G)FSK 0.1-300 ks/s
OOK/ASK 0.1-125 ks/s
Symbol rate accuracy ±100 ppm
Frequency deviation FDEV 0.15 - 500 kHz

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 STM32WL33xx
Electrical characteristics

If "Manchester" or "3-out-of-6" or FEC coding options are enabled the actual bit rate is affected as follows:

Table 25. Data rate with different coding options

Coding option 2GFSK[kbit/s] 4GFSK[kbit/s]

NRZ 300 600

FEC 150 300
Manchester 150 Not supported
3-out-of-6 200 Not supported

6.3.5 RF receiver
Characteristics measured over recommended operating conditions unless otherwise specified. All typical values
are referred to 25°C temperature, VBAT = 3.3 V, no frequency offset in the RX signal.
All performance figures are referred to the reference designs optimized for each different configuration. The
reference designs associated with each configuration are listed below:
• 169 MHz: STDES-WL3C4EEW
• 433 MHz: STDES-WL3C4SML
• 868 MHz: STDES-WL3C4SMH
• 915 MHz: STDES-WL3C4SHH
Two reference test conditions are used in the RX measurements: High performance mode (HPM), where the
priority is given to the performances, Low power mode (LPM) where the priority is given to the low consumption.
• High performance mode (HPM) conditions: VDD = 3.3V, TA = 25o C, SMPS ON, SMPS frequency 4 MHz
(unless otherwise stated), SMPS Vout =1.4V, 16 MHz system clock, HSIPLL mode, HSE GMC setting
0x0A.
• Low power mode (LPM) conditions: SMPS ON, SMPS frequency 4MHz (unless otherwise stated), SMPS
Vout =1.2V, LDO RF bypassed, 16 MHz system clock, HSE direct mode, HSE GMC setting 0x0A.
RX blocking and selectivity tests are performed in ETSI conditions: the wanted signal is 3dB higher than the ETSI
sensitivity, given by the following formula:

ETSI_sensitivity = 10 log CHFkHz - 117 dBm

Table 26. RF receiver characteristics

Parameter Description Typical value Unit

Receiver channel bandwidth range - 1.8-1100 kHz

Rx maximum power RF input power in RX operation mode 10 dBm

Interferers are continuous wave @ 6 MHz and 12 MHz 433 MHz -19
Input third order intercept point dBm
offset from carrier 868 MHz -19
433 MHz 151-j103
Input impedance at LNA Max. RX gain R // C 868 MHz 51-j107 Ω
169 MHz 176 - j265

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 STM32WL33xx
Electrical characteristics

Table 27. Sensitivity at 169 MHz (SMPS clock frequency= 4 MHz)

SMPS OFF HPM/LPM SMPS ON

Parameter Test condition Unit
0.1% BER 1% BER 0.1% BER 1% BER

DR = 1.2 kbit/s, FDEV = 4 kHz,

-123 -125 -123 -125
CHF = 10 kHz
DR = 2.4 kbit/s, FDEV = 2.4 kHz,
-121 -123 -121 -123
CHF = 8 kHz
Sensitivity
DR = 4.8 kbit/s, FDEV = 2.4 kHz,
BER @ 2-GFSK, -121 -123 -121 -123 dBm
CHF = 10 kHz
BT = 0.5
DR = 6.4 kbit/s, FDEV = 6.4 kHz,
-117 -119 -117 -119
CHF = 20 kHz
DR = 38.4 kbit/s, FDEV = 20 kHz,
-112 -114 -112 -114
CHF = 100 kHz
DR = 2.4 ks/s, FDEV = 1.2 kHz,
-115 -118 -115 -118
CHF = 5 kHz
Sensitivity
DR = 4.8 ks/s, FDEV = 2.4 kHz,
BER @ 4-GFSK, -112 -115 -112 -115 dBm
CHF = 10 kHz
BT = 0.5
DR = 9.6 ks/s, FDEV = 4.8 kHz,
-109 -112 -109 -112
CHF = 20 kHz
DR = 0.3 kbit/s, CHF = 1.7 kHz -129 -132 -129 -132
Sensitivity
DR = 1.2 kbit/s, CHF = 4 kHz -124 -127 -123 -127 dBm
BER @ OOK
DR = 38.4 kbit/s, CHF = 120 kHz -109 -112 -109 -112

Table 28. Blocking, selectivity and saturation at 169 MHz (SMPS clock frequency= 4 MHz)

Parameter Test condition HPM LPM Unit

Adjacent and Alternate channel rejection +12.5 kHz (adjacent channel) -35.5 -37.7
0.1% BER @ 2-GFSK BT=0.5 -12.5 kHz (adjacent channel) -35.4 -35.9
FDEV=2.4 kHz, DR = 2.4 kbit/s, CHF = +25 kHz (alternate channel) -35.3 -35.1
8 kHz
Wanted signal = 10LOG10(CHFkHz)-117+ dBm
3 dB = -105 dBm
Interferer CW -25 kHz (alternate channel) -35.5 -37.3
Channel spacing = 12.5 kHz
AFC OFF, GMC = 0x0A

Selectivity and blocking 0.1% -2 MHz -26.5 -28.9

BER @ 2-GFSK BT=0.5, FDEV=2.4 kHz, +2 MHz -21.0 -20.5
DR = 2.4 kbit/s, CHF = 8 kHz
-10 MHz -15.8 -16.1
Wanted signal = 10LOG10(CHFkHz)-117+ dBm
3 dB = -105 dBm +10 MHz -14.0 -14.7

AFC OFF, GMC = 0x0A -15 MHz -14.6 -14.9

Not modulated interferer signal +15 MHz -13.4 -14.0
Adjacent and Alternate channel rejection +12.5 kHz
-35.5 -37.8
0.1% BER @ 2-GFSK BT=0.5 (adjacent channel)
FDEV = 6.4 kHz, DR = 6.4 kbit/s, CHF = -12.5 kHz
20 kHz -35.5 -36.5
(adjacent channel) dBm
Wanted signal = 10LOG10(CHFkHz)-117+
3 dB = -101 dBm +25.5 kHz
-35.2 -39.8
Interferer CW (adjacent channel)

Channel spacing = 12.5 kHz -25 kHz -35.5 -38.5

DS14221 - Rev 5 page 47/91

 STM32WL33xx
Electrical characteristics

Parameter Test condition HPM LPM Unit

AFC OFF, GMC = 0x0A (adjacent channel) dBm
Selectivity and blocking -2 MHz -26.0 -26.6
0.1% BER @ 2-GFSK BT=0.5 +2 MHz -20.8 -20.5
FDEV = 6.4 kHz, DR = 6.4 kbit/s, CHF = -10 MHz -15.9 -16.0
20 kHz
+10 MHz -14.2 -14.5 dBm
Wanted signal = 10LOG10(CHFkHz)-117+
3 dB = -101 dBm -15 MHz -14.6 -15.0
Not modulated interferer signal
+15 MHz -13.4 -13.8
AFC OFF, GMC = 0x0A

Table 29. Saturation and image rejection at 169 MHz (SMPS clock frequency= 4 MHz)

Parameter Test condition HPM LPM Unit

ETSI Saturation at adjacent

channel
0.1% BER @ 2-GFSK BT=0.5
Wanted signal = - 65 dBm
DR = 2.4 kbit/s, FDEV =
Offset = ±12.5 kHz -4.4 -4.1
2.4 kHz, CHF = 8 kHz
(adjacent channel)
Wanted signal =
10LOG10(CHFkHz)-117+ 43
AFC ON, GMC 0x0A
ETSI Saturation at adjacent
channel
0.1% BER @ 2-GFSK BT=0.5
Wanted signal = - 61 dBm
DR = 6.4 kbit/s, FDEV =
Offset = ±12.5 kHz -5.2 -5.4
6.4 kHz, CHF = 20 kHz
(adjacent channel)
Wanted signal =
10LOG10(CHFkHz)-117+ 43
AFC ON, GMC = 0x0A
dBm
Image rejection
Interferer CW at image
frequency
0.1% BER @ 2-GFSK BT=0.5 Wanted signal = -105 dBm
-44.6 -44.6
DR = 2.4 kbit/s, FDEV = 2.4kHz, CW at -600 kHz of offset
CHF = 8 kHz
Wanted signal =
10LOG10(CHFkHz)-117+ 3 dB

Image rejection
Interferer CW at image
frequency
0.1% BER @ 2-GFSK BT=0.5 Wanted signal = -101 dBm
-41.1 -40.9
DR = 6.4 kbit/s, FDEV = CW at -600 kHz of offset
6.4 kHz, CHF = 20 kHz
Wanted signal =
10LOG10(CHFkHz)-117+ 3 dB

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 STM32WL33xx
Electrical characteristics

Table 30. Sensitivity at 433 MHz (SMPS clock frequency= 4 MHz)

SMPS OFF HPM/LPM SMPS ON

Parameter Test condition Unit
0.1% BER 1% BER 0.1% BER 1% BER

DR = 0.3 kbit/s, FDEV = 0.25 kHz,

-128 -130 -128 -130
CHF = 1.7 kHz AFC ON
DR = 1.2 kbit/s, FDEV = 1.2 kHz,
-124 -126 -124 -126
CHF = 4 kHz
DR = 38.4 kbit/s, FDEV = 20 kHz,
-112 -114 -112 -114
CHF = 74.8 kHz
Sensitivity
DR = 38.4 kbit/s, FDEV = 20 kHz, dBm
BER @ 2-GFSK,
CHF = 100 kHz (TX pin mode and -111.5 -113.5 -111.5 -113.5
BT = 0.5
10 dBm BOM)
DR = 38.4 kbit/s, FDEV = 20 kHz,
CHF = 100 kHz (TXHP mode and -111 -113 -111 -113
16 dBm BOM)
DR = 300 kbit/s, FDEV = 150 kHz,
-102 -104 -102 -104
CHF = 780 kHz
DR = 4.8 ks/s, DEV = 2.4 kHz, CHF
-112 -115 -112 -115
= 10 kHz
DR = 9.6 ks/s, DEV = 4.8 kHz, CHF
Sensitivity -109 -112 -109 -112
= 20 kHz
BER @ 4-GFSK, dBm
DR = 19.2 ks/s, DEV = 9.6 kHz,
BT = 0.5 -106 -109 -106 -109
CHF = 40 kHz
DR = 300 ks/s, DEV = 300 kHz,
-97 -100 -97 -100
CHF = 900 kHz
DR = 0.3 kbit/s, CHF = 1.7 kHz -129 -132 -129 -132

Sensitivity DR = 1.2 kbit/s, CHF = 4 kHz -124 -127 -124 -127

dBm
BER @ OOK DR = 38.4 kbit/s, CHF = 120 kHz -109 -112 -109 -112
DR = 125 kbit/s, CHF = 400 kHz -103 -106 -103 -106

Table 31. Blocking, selectivity and saturation at 433 MHz (SMPS clock frequency= 4 MHz)

Parameter Test condition HPM LPM Unit

+12.5 kHz (adjacent channel) -40 -42

-12.5 kHz (adjacent channel) -41 -43

Selectivity and blocking 0.1% BER @ 2- +25 kHz (alternate channel) -40 -43
GFSK, BT = 0.5, FDEV=1.2 kHz, DR = -25 kHz (alternate channel) -40 -43
1.2 kbit/s, CHF = 4 kHz.
Image rejection -47 -47 dBm
Wanted signal = ETSI sensitivity + 3 dB =
-108 dBm. +2 MHz -24 -24
Not modulated interferer signal. -2 MHz -29 -29
±10 MHz -17 -18
±15 MHz -16 -16
+100 kHz (adjacent channel) -38 -42
Selectivity and blocking 0.1% BER @ 2-
-100 kHz (adjacent channel) -38 -42
GFSK, BT = 0.5, FDEV = 20 kHz , DR =
38.4 kbit/s, CHF = 100 kHz. +200 kHz (alternate channel) -38 -41
dBm
Wanted signal = ETSI sensitivity + 3 dB = -200 kHz (alternate channel) -44 -44
-94 dBm.
Image rejection
Not modulated interferer signal. -38 -39
Offset = -600 kHz

DS14221 - Rev 5 page 49/91

 STM32WL33xx
Electrical characteristics

Parameter Test condition HPM LPM Unit

Selectivity and blocking 0.1% BER @ 2- ±2 MHz -23 -23
GFSK, BT = 0.5, FDEV = 20 kHz , DR =
38.4 kbit/s, CHF = 100 kHz. ±10 MHz -16 -17
dBm
Wanted signal = ETSI sensitivity + 3 dB =
-94 dBm. ±15 MHz -16 -16
Not modulated interferer signal.
ETSI saturation at adjacent channel 0.1% Wanted signal = -68 dBm
BER @ 2-GFSK, BT = 0.5, FDEV = -3 -6 dBm
1.2 kHz, DR = 1.2 kbit/s, CHF = 4 kHz. Offset = ±25 kHz (adjacent channel)

ETSI saturation at adjacent channel 0.1%.

BER @ 2-GFSK, BT = 0.5, FDEV = Wanted signal = - 54 dBm
-3 -6 dBm
20 kHz , DR = 38.4 kbit/s, CHF = Offset = ±100 kHz (adjacent channel)
100 kHz.

Table 32. Sensitivity at 868.5 MHz (SMPS clock frequency = 4.27 MHz)

SMPS OFF HPM/LPM SMPS ON

Parameter Test condition(1) Unit
0.1% BER 1% BER 0.1% BER 1% BER

DR = 0.3 kbit/s, FDEV = 0.25 kHz,

-126 -128 -126 -128
CHF = 1.7 kHz
DR = 1.2 kbit/s, FDEV = 1.2 kHz,
-122 -124 -122 -124
CHF = 4 kHz
DR = 38.4 kbit/s, FDEV = 20 kHz,
-110 -112 -110 -112
CHF = 74.8 kHz
Sensitivity BER @ 2- DR = 38.4 kbit/s, FDEV = 20 kHz,
GFSK, BT = 0.5 CHF = 100 kHz (TX pin connected -110 -112 -110 -112
10 dBm BOM)
DR = 38.4 kbit/s, FDEV = 20 kHz,
CHF = 100 kHz (TXHP pin -109 -111 -109 -111
connected and 16 dBm BOM)
DR = 300 kbit/s, FDEV = 150 kHz,
-101 -103 -101 -103
CHF = 780 kHz
dBm
DR = 4.8 ks/s, DEV = 2.4 kHz, CHF
-111 -114 -111 -114
= 10 kHz
DR = 9.6 ks/s, DEV = 4.8 kHz, CHF
-108 -111 -108 -111
Sensitivity BER @ 4- = 20 kHz
GFSK, BT = 0.5 DR = 19.2 ks/s, DEV = 9.6 kHz,
-105 -108 -105 -108
CHF = 40 kHz
DR = 300 ks/s, DEV = 300 kHz,
-96 -99 -96 -99
CHF = 900 kHz
DR = 0.3 kbit/s, CHF = 1.7 kHz -128 -131 -128 -131
DR = 1.2 kbit/s, CHF = 4 kHz -122 -125 -122 -125
Sensitivity BER @
OOK
DR = 38.4 kbit/s, CHF = 120 kHz -107 -110 -107 -110
DR = 125 kbit/s, CHF = 400 kHz -102 -105 -102 -105

1. For optimal results in 868 MHz sensitivity tests, the KRM feature needs to be used.

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 STM32WL33xx
Electrical characteristics

Table 33. Blocking, selectivity and saturation at 868 MHz (SMPS clock frequency = 4.27 MHz)

Parameter Test condition HPM LPM Unit

+12.5 kHz (adjacent channel) -44 -46

-12.5 kHz (adjacent channel) -44 -47
+25 kHz (alternate channel) -43 -48
Selectivity and blocking 0.1% BER @ 2-
GFSK, BT = 0.5, DR = 1.2 kbit/s, FDEV = -25 kHz (alternate channel) -44 -48
1.2 kHz, CHF = 4 kHz. Image rejection
-46 -46 dBm
Wanted signal = ETSI sensitivity + 3 dB = Offset = -600 kHz
-108 dBm
+2 MHz -26 -25
Not modulated interferer signal.
-2 MHz -29 -30
±10 MHz -22 -24
±15 MHz -17 -17
+100 kHz (adjacent channel) -43 -48
-100 kHz (adjacent channel) -43 -48
Selectivity and blocking 0.1%.
+200 kHz (alternate channel) -43 -46
BER @ 2-GFSK, BT = 0.5, FDEV =
20 kHz, DR = 38.4 kbit/s, CHF = 100 kHz, -200 kHz (alternate channel) -44 -45
channel separation 100 kHz. Image rejection dBm
-41 -41
Wanted signal = ETSI sensitivity + 3 dB = Offset = -600 kHz
-94 dBm,
±2 MHz -26 -27
Not modulated interferer signal.
±10 MHz -19 -21
±15 MHz -16 -17
ETSI saturation at adjacent channel 0.1% Wanted signal = -68 dBm
BER @ 2-GFSK, BT = 0.5, FDEV = -5 -9 dBm
1.2 kHz, DR = 1.2 kbit/s, CHF = 4 kHz. Offset = ±25 kHz (adjacent channel)

ETSI saturation at adjacent channel 0.1% Wanted signal = - 54 dBm

BER @ 2-GFSK, BT = 0.5 20 kHz FDEV, -4 -8 dBm
DR = 38.4 kbit/s, CHF = 100 kHz. Offset = ±100 kHz (adjacent channel)

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Electrical characteristics

Table 34. Sensitivity at 915 MHz (SMPS clock frequency= 4 MHz)

SMPS OFF HPM/LPM SMPS ON

Parameter Test condition
0.1% BER 1% BER 0.1% BER 1% BER

DR = 0.3 kbit/s, FDEV = 0.25 kHz,

-126 -128 -126 -128
CHF = 1.7 kHz
DR = 1.2 kbit/s, FDEV = 1.2 kHz,
-122 -124 -122 -124
CHF = 4 kHz
Sensitivity
DR = 38.4 kbit/s, FDEV = 20 kHz, dBm
0.1% BER @ 2-GFSK, -110 -112 -110 -112
CHF = 74.8 kHz
BT = 0.5
DR = 38.4 kbit/s, FDEV = 20 kHz,
-109 -111 -109 -111
CHF = 100 kHz
DR = 300 kbit/s, FDEV = 150 kHz,
-100 -102 -100 -102
CHF = 780 kHz
DR = 4.8 ks/s, DEV = 2.4 kHz, CHF
-110 -113 -110 -113
= 10 kHz
DR = 9.6 ks/s, DEV = 4.8 kHz, CHF
Sensitivity -107 -110 -107 -110
= 20 kHz
dBm
0.1% BER @ 4-GFSK
DR = 19.2 ks/s, DEV = 9.6 kHz,
BT = 0.5 -104 -107 -104 -107
CHF = 40 kHz
DR = 300 ks/s, DEV = 300 kHz,
-96 -99 -96 -99
CHF = 900 kHz
DR = 0.3 kbit/s, CHF = 1.7 kHz -128 -131 -128 -131

Sensitivity DR = 1.2 kbit/s, CHF = 4 kHz -122 -125 -122 -125

dBm
0.1% BER @ OOK DR = 38.4 kbit/s, CHF = 120 kHz -107 -110 -107 -110
DR = 125 kbit/s, CHF = 400 kHz -102 -105 -102 -105

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Table 35. Blocking, selectivity and saturation at 915 MHz

Parameter Test condition HPM LPM Unit

+12.5 kHz (adjacent channel) -45 -49

-12.5 kHz (adjacent channel) -45 -49

Selectivity and blocking 0.1% +25 kHz (alternate channel) -45 -51
BER @ 2-GFSK, BT = 0.5,
FDEV = 1.2 kHz , DR = -25 kHz (alternate channel) -45 -51
1.2 kbit/s, CHF = 4 kHz Image rejection
-52 -52 dB
Wanted signal = ETSI Offset = - 600 kHz
sensitivity + 3 dB = -108 dBm.
+2 MHz -29 -29
Not modulated interferer
signal. -2 MHz -30 -30
±10 MHz -19 -20
±15 MHz -17 -18
+100 kHz (adjacent channel) -44 -50
-100 kHz (adjacent channel) -44 -50
Selectivity and blocking 0.1%
BER @ 2-GFSK, BT = 0.5, +200 kHz (alternate channel) -45 -47
FDEV = 20 kHz, DR =
-200 kHz (alternate channel) -45 -48
38.4 kbit/s, CHF = 100 kHz.
Image rejection dB
Wanted signal = ETSI -41 -42
sensitivity + 3 dB = -94 dBm Offset = -600 kHz
Not modulated interferer ±2 MHz -26 -26
signal.
±10 MHz -18 -19
±15 MHz -17 -17
ETSI saturation at adjacent
channel 0.1% BER @ 2- Wanted signal = -68 dBm
GFSK, BT = 0.5, FDEV -8 -12 dBm
1.2 kHz, DR = 1.2 kbit/s, CHF Offset = ±25 kHz (adjacent channel)
= 4 kHz.
ETSI saturation at adjacent
channel 0.1% BER @ 2- Wanted signal = -54 dBm
GFSK, BT = 0.5, FDEV = -7 -11 dBm
20 kHz , DR = 38.4 kbit/s, Offset = ±100 kHz (adjacent channel)
CHF = 100 kHz.

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Electrical characteristics

6.3.6 RF transmitter
Characteristics measured over recommended operating conditions unless otherwise specified. All typical values
are referred to a temperature of 25 °C, VBAT = 3.3 V. All performance data is referred to the reference design with
a 50-ohm antenna connector.
Transmission measurements are performed for VDD = 3.3 V, TA = 25 °C, SMPS ON, SMPS frequency 4 MHz,
SMPS Vout value dependent on the desired output power =1.4V, 16 MHz system clock, HSIPLL mode, HSE GMC
setting 0x0A
TX measurements are given for HPM test conditions:
VDD = 3.3V, TA = 25o C, SMPS ON, SMPS frequency 4 MHz (unless otherwise stated), SMPS Vout according to
output power, 16 MHz system clock, HSI mode.

Table 36. RF transmitter characteristics

Parameter Test condition RF power Unit

TX mode, SMPS = 2 V 14
TX mode, SMPS = 1.4 V 10

Maximum output power TXHP mode, SMPS = 1.5 V dBm

16
PA_DEGEN_ON
TX+TXHP mode, SMPS = 2 V
20
PA_DEGEN_ON

Output power step (all modes) All BOMs, all frequencies 0.5 dB

Table 37. PA impedance

Parameter Test condition Typ Unit

433 MHz 10 dBm, TX mode, Vsmps = 1.4 V 52 Ω // 35 nH

433 MHz 14 dBm, TXHP mode, Vsmps = 1.4 V 37 Ω // 37 nH
433 MHz 16 dBm, TXHP mode, Vsmps = 1.6 V 37 Ω // 37 nH
868-929 MHz 10 dBm, TX mode, Vsmps = 1.4 V 40 Ω // 36 nH
Optimum load impedance Ω
868-929 MHz 14 dBm, TXHP mode, Vsmps = 1.4 V 32 Ω // 16 nH
868-929 MHz 16 dBm, TXHP mode,
44 Ω // 18 nH
PA_DEGEN_ON, Vsmps = 1.5 V
902-928 MHz 20 dBm, TX+TXHP mode,
20 Ω // 6 nH
PA_DEGEN_ON, Vsmps = 2.2 V

Table 38. Regulatory standards

Frequency band Suitable for compliance with:

ETSI EN300 220 category 1

413 - 479 MHz FCC part 15, FCC part 90
ARIB STD-T67
ETSI EN300 220-2 category 1
826 - 958 MHz FCC part 15
ARIB STD-T108

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 STM32WL33xx
Electrical characteristics

6.3.7 Harmonic emissions

TX measurements are given for HPM test conditions: VDD = 3.3 V, TA = 25 oC, SMPS ON, SMPS frequency
4 MHz, SMPS Vout according to output power, 16 MHz system clock, HSI mode.
• 10 dBm measurements conditions: SMPS ON Vout = 1.4 V, Continuous Wave (CW), TX pin connected,
TX mode, 10 dBm BOM.
• 16 dBm measurements conditions: Continuous Wave (CW), TXHP pin connected, TXHP mode, 16 dBm
BOM and PA_DGEN_ON:
– 433 MHz band: SMPS ON Vout = 1.6 V
– 868 MHz band: SMPS ON Vout = 1.5 V
– 915 MHz band: SMPS ON Vout = 1.5 V
• 20 dBm measurement conditions: Continuous Wave (CW), TX+TXHP pins connected, TX+TXHP mode,
20 dBm BOM, PA_DEGEN_ON and SMPS = 2 V for 868, 2.2 V for 915 MHz

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Electrical characteristics

6.3.7.1 Harmonic emission at 169 MHz

Table 39. 169 MHz Band +16 dBm RF transmitter characteristics

Parameter Test condition Min Typ Max Unit

RF test frequency range - 159.2 169.4 185 MHz

CW 16 dBm
Maximum TX power - 16 -
TXHP pin, TXHP mode
47-74 MHz, 87.5-118 MHz,
Unwanted emissions in spurious domain. - - -54
174-230 MHz, 470-862 MHz
ETSI EN 300-220-14
Frequencies below 1 GHz - - -36 dBm
POUT = 16 dBm, 169.4375 MHz
Frequencies above 1 GHz - - -30

Spurious emissions harmonics 47-74 MHz, 87.5-118 MHz,174-230 MHz, 470-862 MHz - - -54
ETSI EN 300-220-14 Frequencies below 1 GHz - - -36
POUT = 16 dBm 169.4375 MHz Frequencies above 1 GHz - - -30

Table 40. 169 MHz Band +10 dBm RF transmitter characteristics

Parameter Test condition Min Typ Max Unit

RF test frequency range - 159.2 169.4 185 MHz

CW 16 dBm
Maximum TX power - 10 -
TXHP pin, TXHP mode
47-74 MHz, 87.5-118 MHz,
Unwanted emissions in spurious domain. - - -54
174-230 MHz, 470-862 MHz
ETSI EN 300-220-14
Frequencies below 1 GHz - - -36 dBm
POUT = 10 dBm, 169.4375 MHz
Frequencies above 1 GHz - - -30

Spurious emissions harmonics 47-74 MHz, 87.5-118 MHz,174-230 MHz, 470-862 MHz - - -54
ETSI EN 300-220-14 Frequencies below 1 GHz - - -36
POUT = 10 dBm 169.4375 MHz Frequencies above 1 GHz - - -30

Table 41. Current consumption in transmission mode, fc = 169 MHz

Parameter Symbol Test condition Min

Measurements TX @ CW 10 dBm
11
TX pin connected, TX Mode
Supply current mA
Measurements TX @ CW 16 dBm
28
TXHP pin connected, TXHP mode

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 STM32WL33xx
Electrical characteristics

6.3.7.2 Harmonic emission at 433 MHz

Table 42. Harmonic emission at 433 MHz

Parameter Test condition 10 dBm 16 dBm Unit

H1 As detailed above 10 16

H2 As detailed above -57 -44

H3 As detailed above -44 -35
H4 As detailed above -56 -56 dBm

H5 As detailed above -63 -66

H6 As detailed above -61 -66
H7 As detailed above -53 -66

6.3.7.3 Harmonic emission at 868 MHz

Table 43. Harmonic emission at 868 MHz

Parameter Test condition 10dBm 16dBm 20dBm Unit

H1 As detailed above 10 16 20
H2 As detailed above -59 -42 -34
H3 As detailed above -60 -53 -43
H4 As detailed above -62 -62 -68 dBm
H5 As detailed above -60 -57 -52
H6 As detailed above -61 -44 -38
H7 As detailed above -62 -52 -68

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 STM32WL33xx
Electrical characteristics

6.3.7.4 Harmonic emission at 915 MHz

Table 44. Harmonic emission at 915 MHz

Parameter Test condition 10 dBm 16 dBm 20 dBm Unit

H1 As detailed above 10 16 20
H2 As detailed above -50 -42 -42
H3 As detailed above -58 -55 -52
H4 As detailed above -63 -59 -65 dBm
H5 As detailed above -61 -55 -46
H6 As detailed above -63 -34 -46
H7 As detailed above -61 -58 -68

6.3.8 Frequency synthesizer

Characteristics measured over recommended operating conditions. All typical values are referred to 25 °C
temperature, VBAT = 3.3 V, SMPS ON Vsmps = 1.4 V, SMPS clock frequency = 4 MHz, HSE ON, GMC 0x0A,
WFI mode. The whole performance is referred to the reference design with a 50-ohm antenna connector.

Table 45. Frequency synthesizer parameters

Parameter Test conditions HPM Unit

For 433 MHz 5.72

Frequency step size Hz
For 868-915 MHz 11.44
10 kHz -108
100 kHz -112
RF carrier phase noise 433.5 MHz
1 MHz -130
10 MHz -147
10 kHz -105
100 kHz -108
RF carrier phase noise 868 MHz dBc/Hz
1 MHz -124
10 MHz -142
10 kHz -104
100 kHz -108
RF carrier phase noise 915 MHz
1 MHz -121
10 MHz -140

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Electrical characteristics

6.3.9 Low-power autonomous wake-up receiver

Characteristics measured over recommended operating conditions unless otherwise specified. All typical values
are referred to 25 °C temperature, VBAT = 3.3 V. All performance data are referred to a 50 Ω antenna connector,
via the reference design.

Table 46. Low-power autonomous wake-up receiver electrical specification

Symbol Parameter Test conditions Min. Typ. Max. Unit

No input signal, circuit in

Global current
IVBAT_TOP deepstop mode internal - 4.2 - uA
consumption
32 kHz clock. AGC ON.
Manchester OOK
Maximal acceptable
Pmax signal(1), no external - - 18 dBm
input power
filtering
Maximal operating input
Pmax_operating Manchester OOK signal - - 15 dBm
power
Data rate Signal data rate - 950 1000 1050 bps
MDC Manchester duty cycle - 45 50 55 %

1/10 of symbol time for

TRF Signal rise/fall time - - 50 mS
1 kbit/s Manchester OOK
Maximum power for an
Pmax_int Maximal interferer power - - 0 dBm
interferer signal
Pin <= 10 dBm 40 - -
MD Modulation depth dBc
Pin=15 dBm 45 - -
Normal LPAWUR
ZIN input impedance operation, AGC not - 500 - Ω
active
LPAWUR not active,
ZIN_MIN DC input impedance SoC in active mode, - 2.2 2.5 Ω
AGC MAX
860 - 928 MHz
FRANGE Operating band - 860 - 928 MHz

PSENS Sensitivity BER < 10-3 - -53 - dBm

Wanted signal =
PSENS+3dB, BER<10-3
C/ICOCHANNEL Co-channel interferer - 10 - dBc
2 kbit/s OOK modulated
interferer signal
Wanted signal =
PSENS+ 3dB, BER<10-3
C/IINBAND CW inband interferer - -28 - dBc
CW interferer at Foffset
> +/-30 kHz
Wanted signal =
PSENS+3 dB, BER<10-3
Modulated inband
C/IOOK_40K - 0 - dBc
interferer 40 kbit/s OOK modulated
interferer signal at
Foffset > +/- 30 kHz
Wanted signal =
PSENS+3 dB, BER<10-3
Modulated inband
C/IOOK_1M - -10 - dBc
interferer 1 Mbit/s OOK modulated
interferer signal at
Foffset > +/- 30 kHz

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 STM32WL33xx
Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

2400 - 2483.5 MHz

FRANGE Operating band - 2400 - 2483.5 MHz

PSENS Sensitivity BER < 10-3 - -49 - dBm

Wanted signal =
PSENS+3 dB, BER<10-3
C/ICOCHANNEL Co-channel interferer - 10 - dBc
2 kbit/s OOK interferer
modulated signal
Wanted signal =
PSENS+3dB, BER<10-3
C/IINBAND CW inband interferer - -29 - dBc
CW interferer at Foffset
> +/-30kHz
413-479 MHz
FRANGE Operating band - 413 433 479 MHz

PSENS Sensitivity BER < 10-3 - -54 - dBm

Wanted signal =
PSENS+3 dB, BER<10-3
C/ICOCHANNEL Co-channel interferer - +5 - dBc
2 kbit/s OOK interferer
modulated signal
Wanted signal =
PSENS+3dB, BER<10-3
C/IINBAND CW inband interferer - -27 - dBc
CW interferer at Foffset
> +/-30 kHz

1. If not otherwise indicated, power values are given for Manchester OOK modulation: this means that the peak power is 3 dB
higher than the indicated average power.

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 STM32WL33xx
Electrical characteristics

6.3.10 High-speed external clock

The high-speed external oscillator must be supplied with an external 48 MHz crystal specified for a 6 to 8 pF
loading capacitor. The STM32WL33xx includes internal programmable capacitances that can be used to tune the
crystal frequency to compensate the PCB parasitic one.
These internal load capacitors are made by a fixed one, in parallel with a 6-bit binary weighted capacitor bank.
Thanks to low CL step size (1-bit is typically 0.12 pF), very fine frequency tuning is possible. With typical XTAL
sensitivity of -14 ppm/pF, it is possible to trim a 48 MHz crystal, with a resolution of 1 ppm (5 ppm max).
The STM32WL33xx guarantees a very low frequency drift due to 0.2 V supply variations, supporting long
transmission times at low data rate.

Table 47. HSE frequency drift versus power supply drop

Symbol Parameter Conditions Min. Typ. Max. Unit

Frequency drift versus

fDRIFT 200 mV VDD drop - ±40 - ppb
power-supply variation

Table 48. HSE crystal requirements

Symbol Parameter Conditions(1)(2) Min. Typ. Max. Unit

fnom Oscillator frequency - - 48 - MHz

Initial accuracy at 25 °C - +/-10 -

Over temperature -40 °C to +85 °C - +/-20 -
fTOL Frequency accuracy Over temperature +85 °C to ppm
- +/-32 -
+105 °C
Aging over 10 years - +/-10 -
Equivalent series
ESR - - - 80 Ω
resistance
CLOAD Load capaticance - - 8 -

Cshunt Shunt capacitance - -30% 0.71 30 pF

Cmotion Motional capacitance - -30% 2.03 30

Lmotion Motional inductance - -30% 5.41 30 µH

PD Drive level - - - 100 µW

1. A 48 MHz XTAL is specified for a specific reference: NX1612SA. A 48 MHz XTAL is specified for a specific reference:
NX1612SA.
2. For more information about the crystal selection, refer to the application note Oscillator design guide for STM8AF/AL/S,
STM32 MCUs and MPUs (AN2867).

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Electrical characteristics

Table 49. HSE oscillator characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

OSCIN OSCOUT
CHSE - 6.7(1) 10.6(2) 14.33(3) pF
internal capacitor

OSCIN OSCOUT VBAT = 3.3 V

CHSEstep internal capacitor 27 °C, - 0.12 - pF
granularity 1-bit value XOTUNE code between 32 and 33
HSE start- Startup time for From HSE enable to amplitude
- 155 - µs
up time amplitude stabilization ready
ISTARTUP = 00 - 5.1 -
Programmable trans-
Gm conductance of the ISTARTUP = 01 - 10.2 - mS
oscillator at start-up
ISTARTUP = 10 - 20.4 -

1. XOTUNE programmed at minimum code = 0

2. XOTUNE programmed at center code = 32
3. XOTUNE programmed at maximum code = 63

6.3.11 Low speed external clock

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. The
information provided in this section is based on design simulation results obtained with typical external
components specified in the table below. In the application, the resonator and the load capacitors have to be
placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time.
Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package,
accuracy).

Table 50. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

LSEDRV[1:0] =00 - Low drive capability - 250 -

LSEDRV[1:0] =01 - Medium-low drive capability - 315 -
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] =10 - Medium-high drive capability - 500 -
LSEDRV[1:0] =11 - High drive capability - 630 -
LSEDRV[1:0] =00 - low drive capability - - 0.50
LSEDRV[1:0] =01 - medium-low drive capability - - 0.75
Gmcritmax Maximum critical crystal gm µA/V
LSEDRV[1:0] =10 - medium-high drive capability - - 1.70
LSEDRV[1:0] =11 - high drive capability - - 2.70

tSU(LSE)(2) Startup time VDD stabilized - 2 - s

1. Guaranteed by design - not tested in production

2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) until a stable 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.

For more information onthe crystal selection, refer to application note Oscillator design guide for STM8AF/AL/S,
STM32 MCUs and MPUs (AN2867).

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 STM32WL33xx
Electrical characteristics

Figure 13. Typical application with a 32.768 kHz crystal

Resonator with integrated

capacitors
CL1

OSC32_IN fLSE

32.768 kHz Drive

resonator programmable
amplifier

OSC32_OUT
CL2

DT58413
Note: No external resistors are required between OSC32_IN and OSC32_OUT, and it is forbidden to add one.
In bypass mode, the LSE oscillator is switched off and the input pin is a standard GPIO. The external clocksignal
has to respect the I/O characteristics detailed in Section 6.3.15: I/O port characteristics. The recommend clock
input waveform is shown in the figure below.

Figure 14. Low-speed external clocksource AC timing diagram

tw(LSEH)
VLSEH
90%
10%
VLSEL
tr(LSE) t
tf(LSE) tw(LSEL)

DT58414
TLSE

Table 51. Low-speed external user clockcharacteristics(1) – Bypass mode

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fLSE_ext - 21.2 32.768 44.4 kHz
frequency
OSC32_IN input pin high- level
VLSEH - 0.7 x VDDx - VDDx
voltage
V
OSC32_IN input pin low- level
VLSEL - VSS - 0.3 x VDDx
voltage
tw(LSEH) tw(LSEL) OSC32_IN high or low time - 250 - - ns

Includes initialaccuracy,
ftolLSE Frequency tolerance stability over temperature, –500 - +500 ppm
aging and frequency pulling

1. Guaranteed by design - not tested in production.

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 STM32WL33xx
Electrical characteristics

6.3.12 Low-speed internal ring oscillator

Table 52. LSI oscillator characteristics

Symbol Parameter Conditions Min.(1) Typ.(1) Max.(1) Unit

VDD=3.3V
fLSI
LSI frequency TA = 30 °C 32.83 34.3 35.77 kHz
nominal
Typical corner
ΔfLSI /
Frequency variation
fLSI(TA) / Standard deviation - 140 - ppm/ºC
versus temperature
TRange

1. Evaluated by characterization - not tested in production

6.3.13 Flash memory characteristics

The characteristics below are specified by design and not tested in production.

Table 53. Flash memory characteristics

Symbol Parameter Test conditions Typ. Max. Unit

Tprog 32-bit programming time - 20 40

4x32-bit burst programming µs

Tprog_burst - 4x20 4x40
time
tERASE Page (2 kbyte) erase time - 20 40
ms
tME Mass erase time - 20 40

Write mode 3 -
Average consumption from
IDD Erase mode 3 - mA
VDD
Mass erase 5 -

Table 54. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

NEND Endurance TA= -40 to +105 ºC 10 kcycles

1 kcycle(2) at TA = 85 °C 30

1 kcycle(2) at TA = 105 °C 15

tRET Data retention 10 kcycles(2) at TA = 55 °C 30 Years

10 kcycles(2) at TA = 85 °C 15

10 kcycles(2) at TA = 105 °C 10

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

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 STM32WL33xx
Electrical characteristics

6.3.14 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each
sample according to each pin combination. The sample size depends on the number of supply pins in the device
(3 parts x (n + 1) supply pins). This test conforms to the ANSI/JEDEC standard.

Table 55. ESD absolute maximum ratings

Symbol Parameter Conditions Class Max. Unit

Electrostatic discharge TA= +25 ºC, conforming to ANSI/

VESD(HBM) 2 2000(1)
voltage (human body model) ESDA/JEDEC JS-001
Electrostatic discharge V
TA= +25 ºC, conforming to ANSI/
VESD(CBM) voltage (charge device C2a 500
ESDA/STM5.3.1 JS-002
model)

1. TX pin can sustain 700V, TXHP pin can sustain 1000 V

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6.3.15 I/O port characteristics

Unless otherwise specified, the parameters given in the tables below are derived from tests performed under the
conditions summarized in Section 6.3.1: Operating range.

Table 56. I/O static characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

I/O input low level

VIL - - 0.3 x VDD
voltage
1.62 V < VDD < 3.6 V V
I/O input high level
VIH 0.7 x VDD - -
voltage

0 <= VIN <= Max(VDDx)(1) - - ±100

Max(VDDx) (1) <= VIN <= Max(VDDx)

Ilkg Input leakage current - - 650 nA
(1) +1 V

Max(VDDx)(1) + 1V < VIN <= 5.5 V - - 200

RPU Pull up resistor VIN=GND 25 40 55

kΩ
RPD Pull down resistor VIN=VDD 25 40 55

CIO I/O pin capacitance - - 5 - pF

1. Max(VDDx) is the maximum value among all the I/O supplies

All I/Os are CMOS-compliant (no software configuration required).

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA and sink or source up to ±20 mA (with
a relaxed VOL / VOH).
In the user application, the number of I/O pins that can drive current must be limited to respect the absolute
maximum rating specified.
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum consumption of the MCU
sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD.
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on
GND, cannot exceed the absolute maximum rating ΣIVGND.

Table 57. Output voltage characteristics

Symbol Parameter Conditions Min. Max. Unit

Output low level voltage

VOL - 0.4
for an I/O pin
CMOS port(1) |IIO| = 8 mA VDD ≥ 2.7 V
Output high level voltage
VOH VDD - 0.4 -
for an I/O pin
Output low level voltage
VOL - 1.3
for an I/O pin
|IIO| = 20 mA VDD ≥ 2.7 V V
Output high level voltage
VOH VDD - 1.3 -
for an I/O pin
Output low level voltage
VOL - 0.4
for an I/O pin
|IIO| = 4 mA VDD ≥ 1.62 V
Output high level voltage
VOH VDD - 0.45 -
for an I/O pin

1. CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

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 STM32WL33xx
Electrical characteristics

6.3.16 RSTN pin characteristics

The RSTN pin input driver uses the CMOS technology. It is connected to a permanent pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests performed under the
ambient temperature and supply voltage conditions summarized in Section 6.3.1: Operating range.

Table 58. RSTN pin characteristics (specified by design - not tested in production)

Symbol Parameter Conditions Min. Typ. Max. Unit

RSTN input low level

VIL(RSTN) - - - 0.3 x VDD
voltage
V
RSTN input high level
VIH(RSTN) - 0.7 x VDD - -
voltage
RSTN Schmitt trigger
Vhys(RSTN) - - 200 - mV
voltage hysteresis
Weak pull up
RPU VIN=GND 25 40 55 kΩ
equivalent resistor

Figure 15. Recommended RSTN pin protection

Note: • The reset network protects the device against parasitic resets.
• The user must ensure that the level on the RSTN pin can go below the VIL(RSTN) maximum level
specified in Table 58, otherwise the reset is not taken into account by the device.
• The external capacitor on RSTN must be placed as close as possible to the device.

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6.3.17 ADC characteristics

Table 59. ADC characteristics (HSI must be set to PLL mode)

Symbol Parameter Conditions Min. Typ. Max Units

Number of channels for

Channels Diff VFQFPN48 , VFQFPN32 - - 4 -
differential mode
Number of channels for
Channels SE VFQFPN48 , VFQFPN32 - - 8 -
single ended mode
ADC biasing
IBATADCBIAS Biasing blocks turned on - 145 - µA
consumption at battery
ADC active consumption
IBATADCACTIVE ADC activated in differential mode - 185 - µA
at battery

RAIN Input impedance In DC - 250 - kΩ

Internal access
Rin VBOOST is enabled for VBAT < 2.7 V - - 550 Ω
resistance
Cin Input sampling capacitor - - 4 - pF
Ts Sampling period Default config - 1 - µs
Tsw Sampling time Default config - 125 - ns
DR Output data rate - - 200 - ksamples/s
FRMToutput Output data format - - 16 - bits

TL Latency time 200 ks/s - 5 - µs

TsTARTUP Start up time From ADC Enable to conversion start - - 1 µs

DNL Differential non -linearity - - +/-0.7 - LSB

INL Integral non-linearity - - +/-1 - LSB
Differential input
SNR Diff Signal to noise ratio @1 kHz, -1 dBFs, Fs = 800 kHz, - 72 - dB
DS=4
Differential input
Signal to THD ratio (10
STHD Diff @1 kHz, -1 dBFs, Fs = 800 kHz, - 75 - dB
harmonics)
DS=4
Differential input
ENOB Diff Effective number of bits @1 kHz, -1 dBFs, Fs = 800 kHz, - 11.5 - bits
DS=4
Single ended
SNR SE Signal to noise ratio @1 kHz, -1 dBFs, Fs = 800 kHz, - 70 - dB
DS=4
Single ended
Signal to THD ratio (10
STHD SE @1 kHz, -1 dBFs, Fs = 800 kHz, - 70 - dB
harmonics)
DS=4

Single ended
ENOB SE Effective number of bits @1 kHz, -1 dBFs, Fs = 800 kHz, - 11 - bits
DS=4
ADC_ERR_1V7 - 13 - mV
ADC_ERR_2V4 Absolute error when used for battery - 0 - mV
ADC ERROR measurement at 1.7 V, 2.4 V, 3.0 V,
ADC_ERR_3V0 3.6 V - -9 - mV
ADC_ERR_3V6 - -22 - mV

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 STM32WL33xx
Electrical characteristics

6.3.18 Temperature sensor characteristics

Table 60. Temperature sensor characteristics(1)

Symbol Parameter Conditions Min. Typ. Max. Unit

Temperature range =
TrERR Error in temperature - +/-2 - °C
-20 to 85 °C
TSLOPE Average temperature coefficient - - 10 - LSB/°C

Current consumption with

TICC - - 415 - µA
AUXADC
TTS-OUT Output code at 30 °C (+-5 °C) - - 2550 - LSB

1. Evaluated by characterization - not tested in production.

6.3.19 Timer characteristics

Table 61. TIM2/16 characteristics

Symbol Parameter Condition Min Typ Max Unit

tres(TIM) Timer resolution time fTIMxCLK = 64 MHz - 15.625 - ns

ResTIM Timer resolution - 16 - bit

16-bit counter clock

tCOUNTER fTIMxCLK = 64 MHz 0.015625 - 1024 μs
period
Maximum possible
tMAX_COUNT fTIMxCLK = 64 MHz - - 67.10 s
count time

Table 62. IWDG min/max timeout period at 32 kHz (LSE)

Prescaler
PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF Unit
divider

/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768

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 STM32WL33xx
Electrical characteristics

6.3.20 I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification for:
• Standard-mode (Sm): bit rate up to 100 kbit/s
• Fast-mode (Fm): bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): bit rate up to 1 Mbit/s.
The SDA and SCL I/O requirements are met with the following restriction: the SDA and SCL I/O pins are not “true”
open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but
is still present. The 20 mA output drive requirement in Fast-mode Plus is supported partially.
This limits the maximum load Cload supported in Fast-mode Plus, given by these formulas:
• tr(SDA/SCL) = 0.8473 x Rp x Cload
• Rp(min) = [VDD - VOL(max)] / IOL(max)
where Rp is the I2C line pull-up.
All I2C SDA and SCL I/Os embed an analog filter.

Table 63. I2C analog filter characteristics (specified by design - not tested in production)

Symbol Parameter Min Max Unit

Maximum pulse width of spikes that are suppressed

tAF 50 110 ns
by the analog filter.

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 STM32WL33xx
Electrical characteristics

6.3.21 SPI characteristics

The parameters given in Table 64 for SPI are derived from tests performed according to fPCLKx frequency and
supply voltage conditions summarized in Table 10. Operating range.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x VDD

Table 64. SPI characteristics

Symbol Parameter(1) Conditions Min. Typ. Max. Units

Master mode 32
fSCK SPI clock frequency - - MHz
Slave mode 32(1)
tsu(NSS) NSS setup time - 4 / fPCLK - - -

th(NSS) NSS hold time - 2 / fPCLK - - -

tw(SCKH)
SCK high and low time Master mode 1/ fPCLK -1.5 1/ fPCLK 1/ fPCLK + 1 -
tw(SCKL)

tsu(MI) Data input setup time Master mode 1 - -

tsu(SI) Data input setup time Slave mode 1 - -

th(MI) Master mode 3 - -

Data input hold time
th(SI) Slave mode 1 - -

ta(SO) Data output access time 5 - 40

Slave mode ns
tdis(SO) Data output disable time 5 - 38

tv(MO) Master mode - 2 8

Data output valid time
tv(SO) Slave mode - 12 39

th(MO) Master mode 2 - -

Data output hold time
th(SO) Slave mode 4 - -

1. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved .

Figure 16. SPI timing diagram - slave mode and CPHA = 0

DT57476V1

DS14221 - Rev 5 page 71/91

 STM32WL33xx
Electrical characteristics

Figure 17. SPI timing diagram - slave mode and CPHA = 1

DT57477V1
Figure 18. SPI timing diagram - master mode

DT57478V1

DS14221 - Rev 5 page 72/91

 STM32WL33xx
Electrical characteristics

6.3.22 LCD characteristics

Table 65. Current consumption in Deepstop mode with LCD clock source LSI, duty 1/4, bias 1/3

Condition
Symbol Parameter Unit
Clock source VDD (V) -40 °C -20 °C 0 °C 27 °C 50 °C 85 °C

1.8 1.5 1.58 1.72 2.23 3.59 11.37

IDD 2.5 1.48 1.63 1.77 2.24 3.69 11.37

Supply current Clock source
(Deepstop with in Deepstop LSI, duty 1/4, 3.0 1.58 1.65 1.8 2.3 3.72 11.75 µA
LCD) with LCD(1) bias 1/3
3.3 1.6 1.69 1.79 2.31 3.74 11.67
3.6 1.62 1.68 1.82 2.34 3.77 11.65

1. Guaranteed by characterization results.

Table 66. Current consumption in Deepstop mode with LCD clock source LSE, duty 1/4, bias 1/3

Condition
Symbol Parameter Unit
Clock source VDD (V) -40 °C -20 °C 0 °C 27 °C 50 °C 85 °C

1.8 1.27 1.34 1.47 1.96 3.35 11.16

IDD 2.5 1.25 1.38 1.51 2.02 3.44 11.06

Supply current Clock source
(Deepstop with in Deepstop LSE, duty 14, 3.0 1.35 1.42 1.53 2.05 3.44 11.2 µA
LCD) with LCD(1) bias 1/3
3.3 1.36 1.44 1.57 2.09 3.5 11.23
3.6 1.41 1.47 1.6 2.13 3.55 11.44

1. Guaranteed by characterization results.

Table 67. Current consumption in Deepstop with LCD clock source LSI, duty 1/8, bias 1/4

Condition
Symbol Parameter Unit
Clock source VDD (V) -40 °C -20 °C 0 °C 27 °C 50 °C 85 °C

1.8 1.52 1.58 1.73 2.19 3.65 11.62

IDD 2.5 1.5 1.6 1.76 2.26 3.68 11.3

Supply current Clock source
(Deepstop with in Deepstop LS1, duty 1/8, 3.0 1.59 1.66 1.78 2.28 3.74 11.56 µA
LCD) with LCD(1) bias 1/4
3.3 1.6 1.67 1.81 2.29 3.73 11.6
3.6 1.62 1.7 1.82 2.33 3.78 11.7

1. Guaranteed by characterization results.

Table 68. Current consumption in Deepstop with LCD clock source LSE, duty 1/8, bias 1/4

Condition
Symbol Parameter Unit
Clock source VDD (V) -40 °C -20 °C 0 °C 27 °C 50 °C 85 °C

1.8 1.26 1.33 1.46 1.97 3.36 11.22

IDD 2.5 1.26 1.37 1.53 2.01 3.47 11.44

Supply current Clock source
(Deepstop with in Deepstop LSE, duty 1/8, 3.0 1.36 1.41 1.56 2.07 3.45 11.26 µA
LCD) with LCD(1) bias 1/4
3.3 1.37 1.46 1.58 2.08 3.52 11.31
3.6 1.41 1.48 1.61 2.12 3.55 11.4

1. Guaranteed by characterization results.

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 STM32WL33xx
Electrical characteristics

6.3.23 LCSC characteristics

Table 69. Current consumption in Deepstop mode with LCSC

Comparator high speed Comparator in medium speed

configuration [µA] configuration [µA]
Symbol Parameter Condition
Typ Typ

25 °C 50 °C 70 °C 85 °C 25 °C 50 °C 70 °C 85 °C

Clock source LSI,

Supply current 3.0 4.3 6.9 11.1 1.9 3.1 5.8 9.9
VDD = 3.3 V
in Deepstop
with LCSC @ Clock source LSE
IDD 70 Hz(1) 2.8 4.1 6.8 11.0 1.7 2.9 5.6 9.8
VDD = 3.3 V
(Deepstop with
Clock source LSI
LCSC) Supply current 10.4 11.7 14.2 18.4 3.3 4.6 7.3 11.5
VDD = 3.3 V
in Deepstop
with LCSC @ Clock source LSE
300 Hz(1) 9.7 11.2 14.2 18.3 3.1 4.4 7.1 11.4
VDD = 3.3 V

1. Guaranteed by characterization results.

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 STM32WL33xx
Package information

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK2
packages, depending on their level of environmental compliance. ECOPACK2 specifications, grade definitions,
and product status are available at: www.st.com. ECOPACK2 is an ST trademark.

7.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers and microprocessors”
(TN1433 ) available on http://www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation
of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are not yet qualified and
therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to run a qualification
activity.

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 STM32WL33xx
Package information

7.2 VFQFPN48 package information (A0BE)

This VFQFPN is a 48 lead, 6 x 6 mm, 0.40 mm pitch, very fine pitch quad flat no lead package.

Figure 19. VFQFPN48 - Outline

Pin 1 index

E2

NX b
ddd
bbb
C
AB
fff C AB

L (48X) k

fff C AB
D2

BOTTOM VIEW

ccc C

A
SEATING PLANE
eee C A1
C

SIDE VIEW

A D aaa C 2X

aaa C 2X

E A0BE_F_VFQFPN48_ME_V1

PIN1 INDEX

B
TOP VIEW

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 STM32WL33xx
Package information

Table 70. VFQFPN48 - Mechanical data

Millimetres Inches(1)
Symbol Note
Min Typ Max Min Typ Max

A 0.80 0.85 1.00 0.0315 0.0335 0.0394 12

A1 0.00 - 0.05 0.0000 - 0.0020 9, 12
5, 6, 7,
b 0.17 0.21 0.25 0.0067 0.0083 0.0098
12, 13
D 6.00 BSC 0.2362 BSC 4, 12
D2 4.30 4.40 4.50 0.1693 0.1732 0.1772 4, 12
e 0.40 BSC 0.0157 BSC
E 6.00 BSC 0.2362 BSC 4, 12
E2 4.30 4.40 4.50 0.1693 0.1732 0.1772 4, 12
L 0.35 0.45 0.55 0.0138 0.0177 0.0217 12, 13
k 0.24 - - 0.0094 - - -
N 48 8
Tolerance of form and position
aaa 0.10 0.0039
bbb 0.10 0.0039
ccc 0.10 0.0039
15
ddd 0.05 0.0020
eee 0.08 0.0031
fff 0.10 0.0039

1. Values in inches are converted from mm and rounded to 3 decimal digits.

Notes (to be reported in Note column of Table 70).

1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters unless otherwise stated. Values in inches are converted from mm and
rounded to 3 decimal digits.
3. Terminal A1 identifier and terminal numbering convention shall conform to JEP95 SPP-002.
Terminal A1 identifier must be located within the zone indicated on the outline drawing. Topside terminal A1
indicator may be a molded, or metalized feature. Optional indicator on bottom surface may be a molded,
marked or metallized feature.
4. Outlines with “D” and “E” increments less than 0.5 mm should be registered as “stand alone” outlines. These
outlines should use as many of the algorithms and dimensions states in the design standard as possible to
insure predictability in manufacturing.
5. Dimension ‘b’ applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension ‘b’ should
not be measured in that radius area.
6. Inner edge of corner terminals may be chamfered or rounded in order to achieve minimum gap “k”.
This feature should not affect the terminal width “b”, which is measured L/2 from the edge of the package
body.
7. Exact shape of the leads at the edge of the package is optional.
8. “N” is the maximum number of terminal positions for the specified body size. Depopulation is allowed, but only
under the following conditions.
– Depopulation scheme must be consistent in each quadrant of the package.
– Non-symmetric variations should be broken out as separate mechanical outline variations, including
depopulation graphics.
9. A1 is defined as the distance from the seating plane to the lowest point on the package body (standoff).
10. Dimension D2 and E2 refer to exposed pad. For exposed pad dimensions see Variations Table 70.

DS14221 - Rev 5 page 77/91

 STM32WL33xx
Package information

11. For Tolerance of Form and Position see Table 70.

12. Critical dimensions:
12.1 A
12.2 A1
12.3 D & E
12.4 b & L
12.5 e
12.6 D2 & E2
13. Dimensions “b” and “L” are measured at terminal plating surface.
14. Depending on the method of lead termination at the edge of the package, pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3 mm.
15. For Symbols, Recommended Values and Tolerances see the Table below: (ACCORDING TO PACKAGE OR
JEDEC SPEC IF REGISTERED)

Table 71. Symbols, recommended values, and tolerances

Symbol Definition Notes

The bilateral profile tolerance that controls the position

aaa of the plastic body sides. The centers of the profile -
zones are defined by the basic dimensions D and E.
The tolerance that controls the position of the entire
terminal pattern with respect to Datums A and B. The
bbb center of the tolerance zone for each terminal is -
defined by the basic dimension “e” as related to
Datums A and B.
The tolerance located parallel to the seating plane in
ccc -
which the top surface of the package must be located.
The tolerance that controls the position of the terminals
This tolerance is normally compounded
ddd to each other. The centers of the profile zones are
with tolerance zone defined by bbb.
defined by basic dimension “e”.
The unilateral tolerance located above the seating This tolerance is commonly known as
eee plane where in the bottom surface of all terminals must the “coplanarity” of the package
be located. terminals.
The tolerance that controls the position of the exposed
metal heat feature. The center of the tolerance zone
fff -
will be the datum’s defined by the centerlines of the
package body.

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 STM32WL33xx
Package information

Figure 20. VFQFPN48- Footprint example

4.65

37
48
0.65
PIN 1 ID
0.25
0.20
1 36

4.50

4.65
0.40

12 25

A0BE_F_VFQFPN48_FP_V1
13 24

4.50

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 STM32WL33xx
Package information

7.3 VFQFPN32 package information (42)

This VFQFPN is a 32 lead, 5 x 5 mm, 0.50 mm pitch, very fine pitch quad flat no lead package.

Figure 21. VFQFPN32 - Outline

ddd C
SEATNG PLANE

A1
A3
SIDE VIEW

17 e
8

b
E2 E

24 L

42_VFQFPN32_CALAMBA_ME_V1
PIN #1 ID 32 25
CHAMFER 0.35
b L

D2

BOTTOM VIEW

1. Drawing is not to scale.

2. Package outline exclusive of any mold flashes dimensions and metal burrs.
3. Details of terminal 1 are optional but must be located on the top surface of the package by using either a mold
or marked features.

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 STM32WL33xx
Package information

Table 72. VFQFPN32 - Mechanical data

Millimetres Inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0 - 0.05 0 - 0.0020
A3 - 0.20 - - 0.008 -
b 0.18 0.25 0.30 0.0070 0.0098 0.0118
D 4.90 5.00 5.10 0.1929 0.19 0.2008
E 4.90 5.00 5.10 0.1929 0.19 0.2008
D2 3.60 3.70 3.80 0.1417 0.1457 0.1496
E2 3.60 3.70 3.80 0.1417 0.1457 0.1496
e - 0.50 - - 0.0197 -
L 0.30 0.40 0.50 0.0118 0.0157 0.0197
ddd - - 0.05 - - 0.0020

1. Values in inches are converted from mm and rounded to 3 decimal digits.

2. VFQFPN stands for thermally Enhanced very thin fine pitch quad flat package No lead . Very thin profile 0.80 < A ≤ 1.00
mm.

Figure 22. VFQFPN32 - Footprint example

3.50

0.80
0.25

0.25

0.50
3.50 5.70

42_VFQFPN32_CALAMBA_FP_V1

4.10
0.30

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 STM32WL33xx
Ordering information

8 Ordering information

Table 73. Ordering information scheme

Example: STM32 WL 33 K C V 6 TR
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
WL = wireless long-range
Device subfamily
33 = Cortex-M0+ full set of features
Pin count
C = 48
K = 32
Memory configuration
8 = 64 Kbyte flash/16 Kbyte RAM
B = 128 Kbyte flash/32 Kbyte RAM
C = 256 Kbyte flash/32 Kbyte RAM

Package(1)
V = VFQFPN
Temperature range
6 = -40 °C up to +85 °C
7 = -40 °C up to +105 °C
Frequency band options
No character = 413-479 MHz and 868-958 MHz
A = 159 -185 MHz
Packing
TR = tape and reel

1. ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimony oxide flame retardants).

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 STM32WL33xx
Ordering information

Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST
product(s) identified in this documentation may be certified by various security certification bodies and/or may
implement our own security measures as set forth herein. However, no level of security certification and/or built-in
security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the
customer needs both in relation to the ST product alone, as well as when combined with other components and/or
software for the customer end product or application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such as Platform
Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms
(www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received
security certification along with the level and current status of such certification, either visit the relevant
certification standards website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can change from time to
time, customers should re-check security certification status/level as needed. If an ST product is not shown
to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST
products. These certification bodies are therefore independently responsible for granting or revoking
security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations,
assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard
technologies which may be used in conjunction with an ST product are based on standards which were not
developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open
technologies or for any methods which have been or may be developed to bypass, decrypt or crack such
algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections
against all attacks, including, for example, against advanced attacks which have not been tested for,
against new or unidentified forms of attack, or against any form of attack when using an ST product outside
of its specification or intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance against such
attacks. As such, regardless of the incorporated security features and/or any information or support that
may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for
meets their needs, both in relation to the ST product alone and when incorporated into a customer end
product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like),
including but not limited to any enhanced security features added by ST, are provided on an "AS IS"
BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL
WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

DS14221 - Rev 5 page 83/91

 STM32WL33xx

Revision history
Table 74. Document revision history

Date Version Changes

31-Oct-2023 1 Initial release.

Updated:
• Cover-page features
• Figure 8. Fast clock tree generation
• Table 4. Alternate function port A
• Table 5. Alternate function port B
• Section 6.3.2: Thermal properties
• Table 14. Current consumption in Run and WFI mode with SMPS ON
(SMPS frequency 4 MHz, SMPS Vout =1.4 V)
• Table 15. Current consumption in Run and WFI mode with SMPS
bypassed
• Table 17. Current consumption in reception, fc = 915 MHz
21-May-2024 2
• Table 18. Current consumption in reception, fc = 868 MHz (SMPS clock
frequency = 4.27 MHz)
• Table 19. Current consumption in reception, fc = 433 MHz
• Table 48. HSE crystal requirements
• Table 49. HSE oscillator characteristics
• Section 6.3.11: Low speed external clock
• Table 54. Flash memory endurance and data retention
• Table 59. ADC characteristics (HSI must be set to PLL mode) (IBAT
units)
• Table 60. Temperature sensor characteristics1
• Table 73. Ordering information scheme
31-May-2024 3 Updated Table 3. Pin description.
Updated pin types in Table 3. Pin description.
Added in Section 6.3.5: RF receiver:
• Table 27. Sensitivity at 169 MHz (SMPS clock frequency= 4 MHz)
27-Jun-2024 4 • Table 28. Blocking, selectivity and saturation at 169 MHz (SMPS clock
frequency= 4 MHz)
• Table 29. Saturation and image rejection at 169 MHz (SMPS clock
frequency= 4 MHz)
Added Section 6.3.7.1: Harmonic emission at 169 MHz.
Updated:
• Document title
• Figure 8. Fast clock tree generation
• Section 3.24: Analog digital converter (ADC)
• Section 6.3.5: RF receiver including performance figures in:
– Table 26. RF receiver characteristics
13-Nov-2024 5
– Table 27. Sensitivity at 169 MHz (SMPS clock frequency= 4 MHz)
– Table 32. Sensitivity at 868.5 MHz (SMPS clock frequency =
4.27 MHz)
– Table 34. Sensitivity at 915 MHz (SMPS clock frequency= 4 MHz)
• Table 41. Current consumption in transmission mode, fc = 169 MHz
• Table 60. Temperature sensor characteristics1

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 STM32WL33xx
Contents

Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Arm Cortex-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.1 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.3 Embedded OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.4 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.1 RF front-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.2 TX and RX event alert. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.3 Low power autonomous wake up receiver (LPAWUR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.1 SMPS step-down converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.2 SMPS bypass on-the-fly (BOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3 Linear voltage regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.4 Power voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.2 Deepstop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6.3 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7 Reset management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8.1 System clock details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 General purpose inputs/outputs (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16 General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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3.16.1 General Purpose timer (TIM2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.16.2 General purpose timer (TIM16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.18 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.19 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . . . . . . . . . . . . . . . . . . 25
3.21 Low power universal asynchronous receiver transmitter (LPUART). . . . . . . . . . . . . . . . . . . . 26
3.22 Serial peripheral interface (SPI/I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.23 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.24 Analog digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.24.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.25 Analog comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.26 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.27 LC sensor controller (LCSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.28 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4 Pinouts and pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.1 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.2 Thermal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.4 RF general characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.5 RF receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3.6 RF transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.7 Harmonic emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.8 Frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.9 Low-power autonomous wake-up receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.10 High-speed external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.11 Low speed external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.12 Low-speed internal ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.13 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.14 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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6.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.3.16 RSTN pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.17 ADC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.18 Temperature sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.19 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.20 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.21 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.22 LCD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.23 LCSC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.2 VFQFPN48 package information (A0BE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.3 VFQFPN32 package information (42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

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List of tables

List of tables
Table 1. Definition of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. SMPS output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 4. Alternate function port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 5. Alternate function port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 6. Application circuit external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 8. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 9. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. Operating range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 12. Shutdown and Reset current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 13. Current consumption in Deepstop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 14. Current consumption in Run and WFI mode with SMPS ON (SMPS frequency 4 MHz, SMPS Vout =1.4 V) . . . . . 42
Table 15. Current consumption in Run and WFI mode with SMPS bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. Peripheral current consumption at VDD=3.3V, T=25°C System clock 32 MHz, SMPS ON . . . . . . . . . . . . . . . . . 43
Table 17. Current consumption in reception, fc = 915 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18. Current consumption in reception, fc = 868 MHz (SMPS clock frequency = 4.27 MHz) . . . . . . . . . . . . . . . . . . . 44
Table 19. Current consumption in reception, fc = 433 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 20. Current consumption in transmission, fc = 433 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 21. Current consumption in transmission mode, fc = 868 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 22. Current consumption in transmission mode, fc = 915 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 23. RF state transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. Data rate with different coding options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26. RF receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 27. Sensitivity at 169 MHz (SMPS clock frequency= 4 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 28. Blocking, selectivity and saturation at 169 MHz (SMPS clock frequency= 4 MHz) . . . . . . . . . . . . . . . . . . . . . . . 47
Table 29. Saturation and image rejection at 169 MHz (SMPS clock frequency= 4 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 30. Sensitivity at 433 MHz (SMPS clock frequency= 4 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 31. Blocking, selectivity and saturation at 433 MHz (SMPS clock frequency= 4 MHz) . . . . . . . . . . . . . . . . . . . . . . . 49
Table 32. Sensitivity at 868.5 MHz (SMPS clock frequency = 4.27 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 33. Blocking, selectivity and saturation at 868 MHz (SMPS clock frequency = 4.27 MHz) . . . . . . . . . . . . . . . . . . . . 51
Table 34. Sensitivity at 915 MHz (SMPS clock frequency= 4 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 35. Blocking, selectivity and saturation at 915 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 36. RF transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 37. PA impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 38. Regulatory standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 39. 169 MHz Band +16 dBm RF transmitter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 40. 169 MHz Band +10 dBm RF transmitter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 41. Current consumption in transmission mode, fc = 169 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 42. Harmonic emission at 433 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 43. Harmonic emission at 868 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 44. Harmonic emission at 915 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 45. Frequency synthesizer parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 46. Low-power autonomous wake-up receiver electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 47. HSE frequency drift versus power supply drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 48. HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 49. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 50. Low-speed external user clock characteristics(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 51. Low-speed external user clockcharacteristics(1) – Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 52. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 53. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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List of tables

Table 54. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 55. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 56. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 57. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 58. RSTN pin characteristics (specified by design - not tested in production). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 59. ADC characteristics (HSI must be set to PLL mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 60. Temperature sensor characteristics(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 61. TIM2/16 characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 62. IWDG min/max timeout period at 32 kHz (LSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 63. I2C analog filter characteristics (specified by design - not tested in production) . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 64. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 65. Current consumption in Deepstop mode with LCD clock source LSI, duty 1/4, bias 1/3 . . . . . . . . . . . . . . . . . . . 73
Table 66. Current consumption in Deepstop mode with LCD clock source LSE, duty 1/4, bias 1/3 . . . . . . . . . . . . . . . . . . 73
Table 67. Current consumption in Deepstop with LCD clock source LSI, duty 1/8, bias 1/4 . . . . . . . . . . . . . . . . . . . . . . . 73
Table 68. Current consumption in Deepstop with LCD clock source LSE, duty 1/8, bias 1/4 . . . . . . . . . . . . . . . . . . . . . . . 73
Table 69. Current consumption in Deepstop mode with LCSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 70. VFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 71. Symbols, recommended values, and tolerances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 72. VFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 73. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 74. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. STM32WL33xx system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Sub-1GHz IP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Wake up radio block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. LPAWUR frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Power supply configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Power supply domains overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Fast clock tree generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Pinout top view (QFN32 package - 5 mm x 5 mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Pinout top view (VFQFPN48 package - 6 mm x 6 mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. STM32WL33xx application circuit without SMPS, VFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. STM32WL33xx application circuit with SMPS, VFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 13. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 14. Low-speed external clocksource AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 15. Recommended RSTN pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 17. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 18. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 19. VFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 20. VFQFPN48- Footprint example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 21. VFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 22. VFQFPN32 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

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DS14221 - Rev 5 page 91/91