16 Channel Rearlight Driver - Standalone Version E522.

88
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Features General Description

• Supply voltage range from 5V up to 32V The E522.88 is a multi-channel PWM driver for lighting
• 16 programmable LED drivers up to 100mA applications. It provides 16 current sinks with an integrated
• LED driver current selection step size of 100uA 10bit PWM generator for each channel. Each of the channels
• 8 custom sequences to control LED's using up to 5 dis- can be digitally configured to drive up to 100mA with a
crete signals selectable slew rate.
• OTP memory for storing individual LED channel configura- The device provides a simple instruction set to control the
tion LED channels. The instruction set can be used to generate up
• 1832 bytes of OTP memory for storing sequences to to eight unique light functions. These light functions can be
implement dynamic signalling and animations triggered using up to five discrete pins. The device provides
• Sequences implemented using simple instructions OTP memory to store the application specific sequences of
• 10bit internal PWM generators for high brightness resolu- instructions. The customer application configuration can be
tion programmed into the device using the I²C bus interface.
• Individual LED channel bin class brightness correction An advanced device power management feature allows LED
• Optional binning with external resistors channel bundling with automatic current balancing with
• 10bit ADC for LED open, short and system diagnosis external resistors resulting in reduced device power dissipa-
• Advanced device power management by channel bund- tion.
ling option Various diagnostic features, like LED open, short condition
• Customizable supply and temperature dependent LED detection and temperature sensor, are provided to meet
current derating automotive requirements.
• Single lamp mode behavior option To protect the device from thermal damage, the device
• I²C interface for programming customer application con- implements a configurable LED supply and device temperat-
figuration and scenarios ure dependent automatic LED current derating.
• Developed according ISO 26262, supports safety require-
ments with ASIL B Ordering Information
• Automotive qualification according to AEC-Q100
Product ID Description Temperature Package
Applications Range
E52288A7 Standard -40°C to +125°C QFN32L6-SLP
• Automotive interior and exterior light systems 7B660
• General LED Applications
• Basic stand alone LED light dynamic animations
E52288A7 High PWM pre- -40°C to +125°C QFN32L6-SLP
7B661 cision
Please refer to section 5.6-1Electrical Parameters PWM for more details.

Typical Operating Circuit

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Functional Diagram

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Pin Configuration QFN32L6

Pin Description QFN32

No Name Type Description
1 LED15 HV_A_O LED15 current sink
2 IN_0 HV_D_I This signal is used to trigger Sequence 0 or Sequence 4 (based on status of the ANI_IN
pin) which control a group of LED's
3 IN_1 HV_D_I This signal is used to trigger Sequence 1 or Sequence 5 ( based on the status of the
ANI_IN pin) which control a group of LED's
4 ANI_IN HV_D_I This pin selects between main mode and animation mode
0: Main mode of operation
1: Animation mode of operation
5 NRESET HV_D_IO Open-drain active low reset pin
6 SCL HV_D_I I²C clock pin
7 SDA HV_D_IO I²C data pin
8 DG0_LED0 HV_AD_IO LED0 / DIAG0 current sink
9 DG1_LED1 HV_AD_IO LED1 / DIAG1 current sink
10 GND0 S Ground for channels DG0_LED0,DG1_LED1,IN2_LED2,IN3_LED3
11 IN_2_LED2 HV_AD_IO LED2 current sink / input 2 pin for triggering sequence
12 IN_3_LED3 HV_AD_IO LED3 current sink /input 3 pin for triggering sequence
13 LNK0_LED4 HV_A_O LED4 current sink / Link output pin related to IN_0 for multi device applications
14 LNK1_LED5 HV_A_O LED5 current sink / Link output pin related to IN_1 for multi device applications
15 GND1 S Ground for channels LNK0_LED4,LNK1_LED5,LNK2_LED6,LNK3_LED7
16 LNK2_LED6 HV_A_O LED6 current sink / Link output pin related to IN_2_LED2 for multi device applications

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No Name Type Description

17 LNK3_LED7 HV_A_O LED7 current sink /Link output pin related to IN_3_LED3 for multi device applications
18 VS HV_S Power supply pin for the device
19 N.C. not connected (unused)
20 GNDA S analog ground
21 GNDD S digital ground
22 VDD5 S Internal 5V supply, a decoupling capacitor has to be attached to this pin
23 PROG HV_D_I (terminate to GND in application)
active high device program mode pin
24 BIN0_LED8 HV_A_IO LED8 current sink / external resistor connection for binning option-1
25 BIN1_LED9 HV_A_IO LED9 current sink / external resistor connection for binning option-2
26 GND2 S Ground for BIN1_LED8,BIN2_LED9, OE_LED10, LED11
27 OE_LED10 HV_AD_IO LED10 current sink / output enable option
28 LED11 HV_A_O LED11 current sink
29 LED12 HV_A_O LED12 current sink
30 LED13 HV_A_O LED13 current sink
31 GND3 S Ground for channels LED12, LED13, LED14, LED15
32 LED14 HV_A_O LED14 current sink
33 EP S
Exposed die pad, connect to GND in application
analog ground
Note: A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage.

Pin Instruction Description

All LED channels ( DG0_LED0 to LED15),SCL, SDA, PROG Unused Pins should be connected to ground in an application
SCL,SDA I²C interface is only meant for user configuration programming.
These pins should be connected to ground and not used in
an application
SDA,NRESET Open drain output
VDD5 The VDD5 pin is not to be used for powering any other circuits in
an application
DG0_LED0,DG1_LED1,IN_2_LED2,IN_3_LED3,LNK0_LED4 The LED pins having alternate function can be configured via the
,LNK1_LED5,LNK2_LED6,LNK3_LED7,BIN0_LED8,BIN1_LE LED_ALT_CONFIG register in the OTP memory
D9,OE_LED10
Pin usage instructions

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1 Functional Safety
The development of this product is based on a process according to ISO 26262 which has been certified to be compliant to
ISO 26262 requirements and integrity levels up to ASIL D. Technical safety requirements for this product are rated ASIL B.
In order to achieve the IC target metrics for the appropriate ASIL, it is mandatory to consider the safety mechanisms and
recommendations mentioned in the safety manual.

1.1 Technical Safety Requirements

Table 1.1-1: Technical safety requirement
Property Description
ID TSR1
Brief description Provide predefined LED output signal corresponding to input data
ASIL B
Detailed description The state of the LED output channels shall be controlled, depending on input signals, in
accordance with the predefined LED output data. The IC shall provide diagnosis informa-
tion.
Safe State In case of any failure of the IC the device shall reset or give failure indication via Diag-Pin.

In case of a detected failure within external LED string the IC shall give failure information
via Diag-Pin.
Fault Tolerant Time Interval For single point faults a fault tolerant time of 300ms is assumed.
For latent faults, a detection within one driving cycle (i.e. during initial self test of the Item)
is assumed to be compliant to the multiple point fault detection interval requirements.

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2 Absolute Maximum Ratings

Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress
ratings only;
operation of the device at these or any other conditions beyond those listed in the operational sections of this document is
not implied.
Exposure to conditions beyond those listed in the operational sections of this document for extended periods may affect
device reliability.
All voltages with respect to ground. Currents flowing into terminals are signed as positive, those drawn out of a terminal are
negative.

Table 2-1: Absolute Maximum Ratings

No. Description Condition Symbol Min Max Unit
1 junction temperature TJ -40 150 °C
2 Storage temperature1) Max 100h for TSTG > TSTG -40 150 °C
85°C
3 Device internal power dissipation2) PDIS 2 W
4 power dissipation at any LED channel pin 3)
PLEDn QM 800 mW
5 voltage at pin VS Vmax_VS -0.3 40 V
6 voltage at pin VDD54) Vmax_VDD5 -0.3 6 V
7 voltage Difference VS - VDD55) Vmax_VS_VDD5 -0.3 40 V
8 voltage at pin NRESET Vmax_NRESET -0.3 40 V
9 voltage at pin PROG Vmax_PROG -0.3 40 V
10 voltage at pin SCL Vmax_SCL -0.3 40 V
11 voltage at pin SDA Vmax_SDA -0.3 40 V
12 voltage at pin IN_0 Vmax_IN_0 -0.3 40 V
13 voltage at pin IN_1 Vmax_IN_1 -0.3 40 V
14 voltage at pin ANI_IN Vmax_ANI_IN -0.3 40 V
15 voltage on any LED channel pin3) Vmax_LEDn -0.3 40 V
1)
Storage is not considering packing materials such as tapes, reels, dry packs, foils, etc. Please contact ELMOS for packing material specifications. Packaged
devices before soldering: For moisture sensitive devices refer to JEDEC standard J-STD-033 and JEDEC Publication JEP160 documents. Solderability of the
device may be affected, when the storage ratings or the according condition are exceeded.
2)
This parameter depends on the PCB design. In a real application, it can be lower than 2W
3)
All LED pins DG0_LED0,DG1_LED1,IN_2_LED2,IN_3_LED3,LNK0_LED4, LNK1_LED5, LNK2_LED6, LNK3_LED7, BIN0_LED8, BIN1_LED9, OE_LED10, LED11,
LED12, LED13, LED14, LED15
4)
Device has internal voltage regulator to generate this supply.
5)
This does not overrule Vmax_VS and Vmax_VDD5. They have to be respected in parallel.

Table 2-2: ESD Parameters

Description Condition Symbol Min Max Unit
ESD HBM Protection at all Pins 1)
VESD(HBM) -2 2 kV
ESD CDM Protection at all Pins 2)
VESD(CDM) -500 500 V
1)
According to AEC-Q100-002 (HBM) chip level test and CVDD5 >= 470nF/10V
2)
According to AEC-Q100-011 (CDM) chip level test

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3 Recommended Operating Conditions

Table 3-1: Recommended Operating Conditions
No. Description Condition Symbol Min Typ Max Unit
1 ambient temperature TA -40 125 °C
2 voltage at pin VS during startup, at Vstart_VS 5.5 32 V
least 1 ms
3 voltage at pin VS after startup Vfunc_VS 5 32 V
4 voltage at pin NRESET Vfunc_NRESET 0 32 V
5 voltage at pin PROG Vfunc_PROG 0 32 V
6 full functionality VDD5 working range1) Vfunc_VDD5 4.5 5.5 V
7 external capacitance at VDD5 pin2) CVDD5 470 nF
8 voltage at pin SCL Vfunc_SCL 0 32 V
9 voltage at pin SDA Vfunc_SDA 0 32 V
10 voltage at pin IN_0 Vfunc_IN_0 0 32 V
11 voltage at pin IN_1 Vfunc_IN_1 0 32 V
12 voltage at pin ANI_IN Vfunc_ANI_IN 32 V
13 voltage at pin LEDn, full functional working n=0..15 Vfunc_LEDn 1 32 V
range3)
14 tolerated voltage at pin LEDn, reduced func- n=0..15 Vred_func_LEDn 0 1 V
tionality working range4)
15 External Capacitance at each LEDx Pin5) Lext_LEDx < 400 nH Cext_LEDx 0 10 nF
16 External Capacitance at each LEDx Pin5) Lext_LEDx > 400 nH Cext_LEDx 10 10 nF
17 Serial inductance between LEDx Pad and slew=0 Lext_LEDx 0 5 μH
external LED
18 Serial inductance between LEDx Pad and slew=1 Lext_LEDx 0 10 μH
external LED
19 Serial inductance between LEDx Pad and slew=2 Lext_LEDx 0 17 μH
external LED
20 Serial inductance between LEDx Pad and slew=3 Lext_LEDx 0 23 μH
external LED
1)
VDD5 is intended to be driven by the integrated voltage regulator. It should not be driven or loaded externally
2)
Note: Ceramic capacitors derate over lifetime and bias voltage. It is therefore recommended to choose a part with higher nominal value to ensure the min
requirement, e.g. 680nF.
3)
All LED pins DG0_LED0,DG1_LED1,IN_2_LED2,IN_3_LED3,LNK0_LED4, LNK1_LED5, LNK2_LED6, LNK3_LED7, BIN0_LED8, BIN1_LED9, OE_LED10, LED11,
LED12, LED13, LED14, LED15
4)
Current sink works stable till resistive saturation. Saturation is below 1V for all currents below 100 mA. Some electrical parameters like settling time will be
violated when the output voltage is below 1V
5)
Maximum value(*) for external capacitance on LED Pin depends on various factors and has to be estimated by measurement in circuit.

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4 Thermal Characteristics
Table 4-1: Thermal Characteristics
No. Description Condition Symbol Min Typ Max Unit
1 QFN32L6 package junction to case thermal res- RTH_JC_QFN32L6 5 K/W
istance*) 1)
2 QFN32L6 package junction to ambient thermal RTH_JA_QFN32L6 28 K/W
resistance*) 1)
*)
Not tested in production
1)
Based on JEDEC standards JESD-51-2(still air), JESD-51-5(exposed pad soldered to PCB) and JESD-51-7(four layer PCB)

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5 Electrical Characteristics
(VVS = 5V to 32V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V VS = 12.0V and TA = +25°C. Positive cur-
rents flow into the device pins.)

5.1 Power Supply and Resets

5.1.1 Voltage regulator and references
5.1.1.1 Voltage Regulator 5V
Table 5.1.1.1-1: Electrical Parameters Voltage Regulator 5V
No. Description Condition Symbol Min Typ Max Unit
1 regulator output VVS = 12V VVDD5_REG 4.8 5.0 5.2 V
idle state minimal internal
current consump-
tion
2 dropout voltage VVS - VVDD5 minimal internal VVDD5_DROP 0 200 500 mV
current consump-
tion,
external:
IVDD5 = 0 .. 20mA,
VVS = 4.9V
3 VDD5 reset threshold, rising supply VVDD5_OK_LH 4.75 V
4 VDD5 reset threshold, falling supply VVDD5_OK_HL 4 V
5 VDD5 reset threshold, hysteresis VVDD5_OK_HYST 0.75 V
6 total VS functional current consumption IVS_TOT_FUNC 7 15 mA
VS does not have a powerwatch, but VS reset levels can be derived from VDD5.
As they are only implicit given, they are not tested in production:
VVS_OK_LH = VVDD5_OK_LH + VVDD5_DROP = 4.95 V (typ)
and:
VVS_OK_HL = VVDD5_OK_HL + VVDD5_DROP = 4.2 V (typ)

5.1.2 Overtemperature Module

Table 5.1.2-1: Thermal Shutdown

No. Description Condition Symbol Min Typ Max Unit
1 thermal shutdown threshold rising temperat- TTHERM_LH 155 175 °C
ure*)
2 thermal shutdown threshold falling temperat- TTHERM_HL 135 155 °C
ure*)
3 thermal shutdown hysteresis*) TTHERM_HYST 10 K
*)
Not tested in production

5.2 Device Startup

Table 5.2-1: Electrical Parameters Device Startup
No. Description Condition Symbol Min Typ Max Unit
1 device startup time*) 1) tDEVICE_STARTUP 30 ms
*)
Not tested in production
1)
time needed by the device to enter active mode after reset goes inactive

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5.3 Bus Interface

5.3.1 I²C Slave Bus Interface

Table 5.3.1-1: Electrical Parameters I²C Interface

No. Description Condition Symbol Min Typ Max Unit
1 SDA voltage against 3 mA load VI2C_OL_3 0.4 V
2 SDA voltage against 6 mA load VI2C_OL_6 0.6 V
3 SDA fall time 70% to 30% Vfunc_SDA1) 3V < Vfunc_SDA < tI2C_SDA_FALL 20 250 ns
5.5V *Vfunc_SD
40 pF< CBUS < 400 A / 5.5
pF
4 SDA, SCL debounce time*) tI2C_DEB 50 ns
5 Hysteresis CMOS level selec- VI2C_HYST_CMOS 0.25 V
ted
6 High level input voltage CMOS level selec- VI2C_CMOS_IH 3.5 V
ted
7 Low level input voltage CMOS level selec- VI2C_CMOS_IL 1.5 V
ted
8 Input current SDA, SCL CMOS level selec- II2C_I_CMOS -10 10 µA
ted
*)
Not tested in production
1)
Vfunc_SDA is the supply of the external pull-up resistor

5.4 Input Interface

Table 5.4-1: Timing Parameters Input interface
No. Description Condition Symbol Min Typ Max Unit
1 Internal timing interval at which the inputs are TSTEP 10 ms
sampled and the time in which individual
instructions within the Sequences are
executed*)
2 Time for applying currents/PWM to the LED TIN_TO_LF 9 ms
channels after input detection*) 1)
3 Minimum time for which the inputs have to be TIN_ACT_WIDTH TSTEP ms
held active for detection*)
4 Time for the input to be detected within the TDET_DEL TSTEP ms
device*)
*)
Not tested in production
1)
The application of PWM/currents depends on the user instructions in the triggered sequence

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5.5 Digital IOs

Table 5.5-1: Electrical Parameters Digital IOs
No. Description Condition Symbol Min Typ Max Unit
1 input voltage for digital "1" 1)
VDIG_IH 2 V
2 input voltage for digital "0" 1)
VDIG_IL 0.8 V
3 input hysteresis2) VDIG_HYST 0.3 V
4 positive supply of internal pull resistor 3)
VDIG_PULL 3.3 V
5 pull resistor2) RDIG_PULL 50 kΩ
6 PROG pin pull resistor to ground RDIG_PULL_PROG 10 kΩ
7 output voltage for digital "0"4) 4mA load VDIG_OL 0.5 V
8 analog low-pulse debounce filter for pins NRE- tDIG_DEB 3 μs
SET and PROG
9 digital low-pulse debounce filter for pins tDIG_DEB_ANI_DIAG 50 100 μs
ANI_IN, DIAG0 and DIAG1
10 High/Low pulses lower than this will be tDIG_DEB_INP 20 μs
filtered*) 5)
11 The pull down current when IN_2_LED2, IPULLDN_IN_2_3_OE 1500 μA
IN_3_LED3, OE_LED10 are used as input pins *)
*)
Not tested in production
1)
valid for DG0_LED0, DG1_LED1, IN_0, IN_1, ANI_IN, NRESET
IN_2_LED2, IN_3_LED3, OE_LED10 when used as inputs. This is not tested for pins IN_2_LED2, IN_3_LED3, OE_LED10 during production.
2)
valid for DG0_LED0, DG1_LED1, IN_0, IN_1, ANI_IN, NRESET
3)
please see pull current behavior figures 7.5-1 and 7.5-2 for details
4)
valid for open-drain NRESET pin
5)
These are valid for IN_0,IN_1, IN_2_LED2, IN_3_LED3 and OE_LED10

5.6 PWM System

Table 5.6-1: Electrical Parameters PWM
No. Description Condition Symbol Min Typ Max Unit
1 Permissible range for internal PWM frequency *)
fPWM 65 500 Hz
2 Internal frequency accuracy *) 1)
Standard fACC -4.2 +4.2 %
(Order Code
E52288A77B660)
3 Internal frequency accuracy*) High PWM preci- fACC -2.0 +2.0 %
sion
(Order Code
E52288A77B661)
*)
Not tested in production
1)
This parameter is derived from internal oscillator frequency and not measured explicitly

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5.7 LED Current Sinks

5.7.1 Current sinks

Table 5.7.1-1: Electrical Parameters Current Sinks

No. Description Condition Symbol Min Typ Max Unit
1 current below lower border *)
ILED <= 10 mA ISINK_MIN_SAT -0.01 10.5 mA
2 overall accuracy of selected current 10mA < ILED <= 20 ISINK_ACC_OVA_20 -5 5 %
mA
3 overall accuracy of selected current 20mA < ILED <= 55 ISINK_ACC_OVA_55 -3.5 3.5 %
mA
4 overall accuracy of selected current 55mA < ILED < 100 ISINK_ACC_OVA_100 -3 3 %
mA
5 channel matching accuracy 10mA < ILED <= 20 ISINK_ACC_CH_20 -4 4 %
mA
6 channel matching accuracy 20mA < ILED <= 55 ISINK_ACC_CH_55 -2.5 2.5 %
mA
7 channel matching accuracy 55mA < ILED < 100 ISINK_ACC_CH_100 -2 2 %
mA
8 Current above upper border*) 100 mA < ILED < ISINK_MAX 97 106 mA
102.3 mA
9 rise time 10% to 90% slew = 0 tSINK_RISE_0 0.1 0.75 us
10 fall time 90% to 10% slew = 0 tSINK_FALL_0 0.1 0.5 us
11 rise time 10% to 90% slew = 1 tSINK_RISE_1 5 us
12 fall time 90% to 10% slew = 1 tSINK_FALL_1 5 us
13 rise time 10% to 90% slew = 2 tSINK_RISE_2 10 us
14 fall time 90% to 10% slew = 2 tSINK_FALL_2 10 us
15 rise time 10% to 90% slew = 3 tSINK_RISE_3 20 us
16 fall time 90% to 10% slew = 3 tSINK_FALL_3 20 us
17 ADC MUX input resistance RSINK_ADC 500 kΩ
18 input current when OFF current sink dis- ISINK_LEAK 5 uA
abled or pwm
dutycycle = 0
*)
Not tested in production
Explanation:
• ILED describes the current which is digitally requested (incl. derating and binning). The register has a size of 10 bit. This corresponds to a maximum value of
1023 LSB or 102.3 mA.
• Channel matching accuracy describes the matching of an individual channel against the average value of all channels programmed to same output
current.
Overall accuracy describes matching of an individual channel against absolute value selected by its register.

• All accuracy values are valid when lower range is selected for currents below 40mA and upper range is selected for currents above 40mA. When using
analog channel bundling, the stated accuracy values are valid for current sums above 20mA of the two bundled channels.

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5.8 Measurement System

Table 5.8-1: Electrical Parameters Measurement System
No. Description Condition Symbol Min Typ Max Unit
1 gain factor of ADC Mux, VS AMEAS_VS 25 LSB/V
2 gain factor of ADC Mux, VS via sample and hold AMEAS_VS_SH 36 LSB/V
(S&H) buffer
3 gain factor of ADC Mux, LED pin voltage AMEAS_VLED 36 LSB/V
4 gain factor of ADC Mux, VDD5 AMEAS_VDD5 142 LSB/V
5 relative error fraction of measurement EMEAS_REL_ANY 2 %
6 uncertainty error fraction of measurement, EMEAS_UNC_VLED_SH 141 mV
channel VLED, VS (S&H)
7 uncertainty error fraction of measurement, EMEAS_UNC_VS_PWM 203 mV
channel VS
8 uncertainty error fraction of measurement, EMEAS_UNC_VDD5 35 mV
channel VDD5
9 saturated region, channel VLED EMEAS_SAT_VLED 281 mV
10 error of temperature sensor measurement *)
EMEAS_TEMP -15 15 K
*)
Not tested in production
See chapter 7.9.2.1 for correct interpretation of the accuracy specification.
Note that saturated region for VDD5 and VS measurement is not given, because it is below recommended operating voltage

5.8.1 SAR ADC

Table 5.8.1-1: Electrical Parameters SAR ADC

No. Description Condition Symbol Min Typ Max Unit
1 resolution *)
NADC - 10 - bit
2 differential non-linearity DNLADC -1 - 2 LSB
3 integral non-linearity INLADC -2 - 2 LSB
4 conversion rate*) ADC clock = 8/3 fADC_CONV 205 kS/s
MHz
1 cycle sample
extension
*)
Not tested in production

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6 Typical Operating Characteristics

120,0 120,00

IConf=100 mA IConf=100 mA
100,0 100,00

0°C

°C
5°C

25
T=-4

T=2

1
T=
80,0 IConf=75 mA 80,00 IConf=75 mA
Current into pin LEDx / mA

Current into pin LEDx / mA

60,0 60,00
IConf=50 mA IConf=50 mA

40,0 40,00

IConf=25 mA IConf=25 mA
20,0 20,00

0,0 0,00
0 3 6 9 12 15 18 21 24 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
Voltage at pin LEDx / V Voltage at pin LEDx / V

Figure 6-1: Output Current vs Output Voltage Figure 6-4: Output Current vs Output Voltage vs Temperature

6 104

5
103
4
max limit
max limit 102 LED00
3
LED0 LED01
LED1
2 LED02
LED2
101 LED03
LED3
1 LED4 LED04
LED5 LED05
Current / mA
Accuracy / %

0 LED6 100 LED06

LED7 LED07
-1 LED8 LED08
LED9 99 LED09
LED10 LED10
-2
LED11
LED11
LED12
-3 LED13 98 LED12
LED14 LED13
-4 LED15 LED14
min limit 97 LED15
-5 min limit

-6 96
10 20 30 40 50 60 70 80 90 100 -40 -20 0 20 40 60 80 100 120
IConf / mA Temperature / °C

Figure 6-2: Accuracy of LED-Current at Room Temperature Figure 6-5: Accuracy of 100 mA Current vs Temperature

8 7,15

7
7,1

6
7,05

5
Current Consumption / mA

Current Consumption / mA

7 VS = 6 V
VS = 8 V
4 VS = 10 V
VS = 12 V
6,95 VS = 14 V
3 VS = 16 V
VS = 18 V
VS = 20 V
6,9
2

6,85
1

0 6,8
Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -40 -20 0 20 40 60 80 100 120
Number of enabled LED-Channels Temperature / °C

Figure 6-3: Current Consumption at Nominal Condition Figure 6-6: Current Consumption vs. Condition

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60 0,6

50
0,5

40
0,4

30 t_rise, 100 mA
LED-Current / mA

t_rise, 75 mA

Time / µs
0,3 t_rise, 50 mA
PWM t_rise, 25 mA
20 LED-Current t_fall, 100 mA
t_fall, 75 mA
0,2 t_fall, 50 mA
t_fall, 25 mA
10

0,1
0

-10 0
-200 0 200 400 600 800 1000 1200 1400 1600 1800 0 0,5 1 1,5 2 2,5 3 3,5

Time / ns Voltage at LED-Pin in On-State / V

Figure 6-7: Rise- and Falltime of LED Driver with Slew=0 Figure 6-9: Rise- and Falltime with Slew=0 vs. Pin-Voltage

Note: Note:
• The overshoot after the fall-ramp is generated by the • Time was measured from 10% to 90% of final current
parasitic serial inductance of the measurement cables. • Fully settled current may be saturated when Pin-Voltage is
• Pin-Voltage in on-state is >1V. < 1.0V, according to Figure 6-4

120 120

100 100

80 80
slew=1 slew=1
slew=1 slew=1
current / mA

current / mA

slew=1 slew=1
60 60
slew=2 slew=2
slew=2 slew=2
slew=2 slew=2
slew=3 slew=3
40 40
slew=3 slew=3
slew=3 slew=3

20 20

0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
time / µs time / µs

Figure 6-8: Risetime of LED Driver with activated Slew-Rate Figure 6-10: Falltime of LED Driver with activated Slew Rate

Notes:
• Measurement done with Pin-Voltage > 1.0 V in on-state
• Swept over 3 different current settings
• As can be seen, Rise/Falltime is mostly independent of selected current value

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7 Functional Description
7.1 System Introduction
The E522.88 is a multi-channel PWM driver for lighting applications. It provides 16 current sinks with integrated 10bit PWM
generator for each channel. Each driver can be used to drive external loads up to 100mA with a selectable LED current slew
rate. All LED channels provide separate PWM duty cycle settings and high precision wide-range LED current configuration.
The device can support up to eight light functions using five discrete pins to trigger these light functions. There are two
modes, main mode and animation mode, differentiated by the ANI_IN signal. The light function can be implemented using
simple instructions. The device offers flexibility for light functions to be associated with available LED channels. A maximum
of four light functions can execute in parallel.
Various diagnostic features, like LED open and short condition detection, are provided to meet automotive requirements.
An advanced device power management feature makes it possible to bundle LED channels and use an automatic current bal-
ancing to reduce device thermal dissipation.
To protect the device from thermal damage, it implements a configurable, LED supply and device temperature dependent,
LED current derating.
The LED driver device can be used in a device group, configured to behave like a single lamp in case of an LED open or short
condition. For this reason two diagnosis groups can be defined and used to connect the grouped LED driver devices.
The device offers a wide range of operating modes to cover different use cases.

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7.2 Device Startup

7.2.1 Device States

Figure 7.2.1-1: Device State Diagram

The device implements the following states as shown in the figure above:

• START
1. Evaluates the reset resources.
• INIT-1
1. Initializes RAM code - Issues reset on CRC mismatch.
2. Checks calibration CRC - Issues reset on CRC mismatch.

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3. Applies OTP calibration values.

4. Applies ADC calibration values.
5. Checks Firmware CRC - Issues reset on CRC mismatch.
6. Copies part of OTP data into RAM registers.
7. Enters INIT-2 state on successful completion.
• INIT-2
1. Initializes all hardware units as per configuration data.
2. Enters ACTIVE state if user data is programmed, else enters PROG state.This is detected via the OTP_DONE bit in
the OTP.
• PROG
1. Programs the user data received from the I²C master into the OTP.
2. Power cycling is required to apply the programmed data.
3. This state is entered from INIT-2 only if OTP_DONE = 0.
• ACTIVE
1. Executes enabled sequences - reads PWM's and currents for active sequences (main or animation) from sequence
database.
2. overrides PWM's and currents from the I²C Master, if available.
3. Applies binning, bundling and derating.
4. Enters CONFIG state on receiving config start request from I²C master, if validation is not locked.
5. This state is entered only if OTP_DONE = 1.
• CONFIG
1. This state is only available for factory debug and is not available to the user.
2. Changes the configuration in RAM registers on request from I²C master.
3. Enters INIT-2 state on receiving config stop request from I²C master.

• Note : The device monitors health of internal circuit blocks and triggers a SOFT RESET in case of any malfunction. SOFT
RESET may be triggered from any of the device states.
The following table shows the status of the components based on the operating state of the device.

Table 7.2.1-1: Device Component Modes

system compon- START INIT-1 INIT-2 PROG ACTIVE CONFIG
ent
system clock running running running running running running
oscillator
LED current sinks OFF OFF OFF OFF usable OFF
ADC OFF OFF OFF OFF usable OFF
over-temperat- ON ON ON ON ON ON
ure comparator

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7.2.1.1 Device internal error detection and handling

The device implements the following fail safe states, which will be entered on the detected error:

• state START
This state will be entered when periodic resets are detected after reaching RESET_BEHAVIOUR.number_retries + 1
resets.
LED's disabled.
This state will be left automatically after a time defined in RESET_BEHAVIOUR.unresponsive_time.

7.2.2 Device data handling

The figure below shows the internal PWM pulse width and LED current configuration data handling. This data handling is
done using DMA functionality and the Device Control Module.

During device startup:

The BUS_CONFIG area is initialized using some of the OTP data

Every time derating factor or LED binning factor changes:

LED current data from sequences is adapted using derating, LED binning, IDAC range and LED bundled mode factors, and then
written to the IDAC current reload data area.

Active LED driver stages will be measured for diagnosis and the ADC result data is written to the BUS_STATUS area.

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Figure 7.2.2-1: Data handling structure

If no communication device address has been programmed , the bus interface is inactive and will not receive or interpret I²C
memory access frames. To switch such a device to an active I²C interface mode, the PROG pin has to be set to active high
level during device startup. The device will then be accessible using device address 31 and device group 1.

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To assign unique device addresses to all LED driver devices connected to a common bus, the following procedure can be
used:

1. Set one device PROG pin to active high level and restart at least this device via it's reset pin or a power cycle.
2. Access the device using the device address value 31 and device group 1.
3. Program a unique device address value (larger than 0, smaller than 31) to COM_DEV_ADDR.
4. Remove the PROG pin active high level and repeat these steps with all other devices.

Note: The last assigned device address can also be a 31.

Note: While PROG pin is set to "high", the LED channels 0 & 1 are switched off!

7.3 Bus Interface

7.3.1 I²C Slave Bus Interface
The I²C Slave Bus Interface allows access to the device configuration data and device status information. This is used to pro-
gram the user configuration in the device OTP memory. The I²C bus has direct access to the device RAM. The write to the OTP
areas is accomplished via a memory access protocol using read/write to these RAM areas. The I²C access is also used for
device testing. This interface is not designed to be used in an application and is only meant for end of line programming of
user configuration.

The following sections provide details of the protocol to configure user OTP area and the constraints that need to be fol-
lowed.

7.3.1.1 I²C Interface Features

• Serial bidirectional communication
• Standard-mode (100 kbit/s) support
• Fast-mode (400 kbit/s) support
• Single master only
• I²C standard START and STOP conditions
• I²C standard MSB first byte format, ACK and NACK

7.3.1.2 I²C Protocol

Protocol Features:

• frame based communication

• 7 bit device address
• upper 2 bits used as device group selector
• lower 5 bits used as device address
• 1 to 31 bus slave devices and broadcast access
• 8 bit device internal memory address space

Data words (10 bit words) are transferred in a compact byte manner. Data is always handled as 10 bit word values. If the bus
master sends a number of data word stream bits which is not a multiple of 8, the additional fill bits at the end of the data
stream will be ignored by the bus slave device.

Protocol components:

The following figure shows the components used by the protocol and their implementation.

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START
START 0-BIT 1-BIT ACK NACK STOP repeated
(S) (0) (1) (A) (NA) (P) (SR)

SCL

SDA

Figure 7.3.1.2-1: Protocol Components

In the following frame format figures some abbreviations are used:

• S : start condition
• P : stop condition
• SR : repeated start condition
• A : acknowledge
• NA : not acknowledge

S device address 0 A memory address A num CRC6 A

6 0 7 0 1 0 5 0

write data word 0 A ... ... A write data word M-1 A

9 0 9 0

CRC8 A
7 0

write data word 0 A ... ... A write data word M-1 A

9 0 9 0

CRC8 A P
7 0

Figure 7.3.1.2-2: Write Frame Format

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S device address 0 A memory address A num CRC6 A

6 0 7 0 1 0 5 0

S
device address 1 A
R
6 0

read data word 0 A ... ... A read data word M-1 A

9 0 9 0

writeCRC8
data word A
7 0

read data word 0 A ... ... A read data word M-1 A

9 0 9 0

N
writeCRC8
data word P
A
7 0

Figure 7.3.1.2-3: Read Frame Format

7.3.1.3 I²C Programming

Table 7.3.1.3-1: Accessible memory areas
Base address Area size(x 16 bits) Name Type Description
0x0000 0x40 BUS_CONFIG RESERVED Reserved not to be used
Address range : 0x00 to 0x3F
0x0040 0x40 BUS_CONFIG I2C_MEMACC_PRO- Address range : 0x40 to 0x7F
TOCOL 0x78 to 0x7F is used for memory
access protocol via the I²C. This
protocol supports OTP configur-
ation and debug access.

Remaining area is reserved and

not to be used.
0x0080 0x40 BUS_STATUS Address range : 0x80 to 0xBF
This area is accessible for debug
only. This allows read back of
ADC result and system status.
0x00C0 0x40 PAGING RESERVED Address range : 0xC0 to 0xFF
Reserved not be used
The Table shows the areas accessible via the I²C bus interface.

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7.3.1.3.1 OTP user data protocol

Figure 7.3.1.3.1-1: OTP access protocol

Packet structure to write user configuration into the OTP

Eight words (x10) of direct access memory (BUS_CONFIG :0x78 - 0x7F) area are used as protocol packets between host and
the device.

For writes, 8 word packets are used. The OTP address is specified as:
Target Address = PageNumber x 128 + Offset.

For an eight word I²C read/write frame with starting address 0x78, the packet details is mentioned below and shown in the
figure above.
*The PageNumber is provided as data at address 0x7C
*The Offset as data at address 0x7D
*The 32 bit data is provided as :
Bits 31:24 at address 0x7B
Bits 23:16 at address 0x7A
Bits 15:08 at address 0x79
Bits 07:00 at address 0x78
*The data at address 0x7E indicates write/read:
0x00 indicates a read and 0x01 a write. For a read frame the data from 0x78-0x7B is ignored.
*For any communication to the device the data at address 0x7F has to be set to 0x01 , by the master. This is used for
synchronization between I²C master and slave. The slave writes "0" to the address 0x7F on completion of the request. The
master has to poll the data at address 0x7F to return to "0". Once the read data at address 0x7F is "0", next frame can be sent
to the device. If this protocol is not followed, it may lead to unexpected behavior, inclusive of the device becoming unus-
able.

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For read requests, four word packets starting from 0x7C can also be used and 4 words starting from 0x78 have to be read for
the device data.

Any write has to be preceded and ended with special ram register writes. Reads can be carried out anytime.

7.3.1.3.2 OTP read/write steps

Steps for writing user data to OTP:
The following list details the steps to program the user configuration data into the OTP.

1. Force the PROG pin of the device to high

2. Read the I²C register 0x7F and wait until the data reads 0
3. Write 8 words starting from 0x78 (with REG = 0xFE) - Start of write cycle.
4. Read the I²C register 0x7F and wait until the data reads 0
5. Write I²C packet for OTP write, with Page no, offset and data words
6. For more writes, go to step 4
7. Write 8 words starting from 0x78 (with REG = 0xFF) - End of write cycle.
8. Force the PROG pin of the device to low

Steps for reading user data from OTP:

The following list details the steps to read the OTP.

1. Read the I²C register 0x7F and wait until it reads 0

2. Write 4 words starting from 0x7C with Page no, offset
3. Read the I²C register 0x7F and wait until it reads 0
4. Read 4 words starting from 0x78 for the data from the device

The OTP data can be read anytime.

Example for OTP write using Elmos controller

RI2C 1 1F 7F ; wait for return value of 0
WI2C8 1 1F 78 00 00 00 00 00 FE 03 01 ; Start of write cycle
RI2C 1 1F 7F ; wait for return value of 0
WI2C8 1 1F 78 01 02 03 04 6C 00 01 01 ; OTP address=0x00003600, data = 0x04030201
RI2C 1 1F 7F ; wait for return value of 0
WI2C8 1 1F 78 05 06 07 08 6C 04 01 01 ; OTP address=0x00003604, data = 0x08070605
RI2C 1 1F 7F ; wait for return value of 0
WI2C8 1 1F 78 09 0A 0B 0C 6C 08 01 01 ; OTP address=0x00003608, data = 0x0C0B0A09
RI2C 1 1F 7F ; wait for return value of 0
WI2C8 1 1F 78 00 00 00 00 00 FF 03 01 ; End of write cycle

Example for OTP read using Elmos controller

RI2C 1 1F 7F ; wait for return value of 0
WI2C4 1 1F 7C 6C 00 00 01 ; OTP address=0x00003600
RI2C 1 1F 7F ; wait for return value of 0
RI2C4 1 1f 78 ; should return 01 02 03 04

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7.4 Input Interface

The light functions are triggered using discrete pins. The input interface triggers the execution of sequences with different
priority within the device. The device uses three fixed pins IN_0, IN_1 and ANI_IN and two optional pins for this function. The
optional pins are multiplexed with LED channels and can be configured for input or as LED channel via LED_ALT_CONFIG
register. All these pins can be configured for active high or active low polarity using IO_CONFIG register.

7.4.1 Input Sampling

The input pins are sampled once every TSTEP interval serially. Once the trigger is detected, the sequences corresponding to the
pins are executed within TSTEP. For noise immunity the pins have voltage hysteresis and glitch filtering. The input sampling
details are shown in the figure below.

Figure 7.4.1-1: Input Sampling

The inputs are sampled serially as shown in the figure, at every T STEP interval. The digital pins (IN_0 and IN_1) are sampled first
followed by LED pins (IN_2_LED2, IN_3_LED3 and OE_LED10 ). In each sampling window an input is sampled thrice and the
value which is at least twice in that interval is selected as the input value. Once detected in this manner , the input is not
looked at till the next TSTEP. The sampling of input and software filtering ensures that glitches in the signal are ignored. To
ensure that an input signal is surely detected it has to be held active for at least T STEP interval.

The internal TSTEP is asynchronous with respect to the external input signals. The serial sampling and lack of sync means that
input signals triggered simultaneously can be detected with a delay of T STEP. This means that the input signal to sequence trig-
gering can have an uncertainty of TSTEP in addition to detection to trigger delay.

For a simultaneous excitation of triggers there can be a difference of T STEP in the respective sequence getting triggered. To
ensure consistent triggering of sequences follow the guidelines mentioned in the section: 7.6.1.3: Mode transition.

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7.4.2 OE PWM Masking

The OE_LED10 pin, in case it is being used for the output enable functionality, can be used to mask PWM signals.
When the OE_LED10 pin is inactive (low level in case of non-inverted OE usage), the PWM pulses of all LED channels are sup-
pressed, which sets the related LED channel driver stages to an off state. When the OE_LED10 pin is active (high level in case
of non-inverted OE usage), this mask is removed and PWM signals of LED channels are fed to the related LED driver stages.
The output enable signal does not block the internal sequence execution , only masks the application of the PWM signals to
the LED channels.

7.5 Digital IOs

The signal polarity of ANI_IN, IN_0,IN_1,IN_2_LED2,IN_3_LED3,OE_LED10 pins can be configured using the IO_CONFIG value.
This allows to connect inverted control signals to the device.

The description in the following chapters refers to the internal signal states, which represent the "default" control signal
polarity.

For LED pins configured as input pins ( IN_2_LED2, IN_3_LED3 and OE_LED10) there is pull-down current irrespective of the
active high or active low polarity. These pins do not have a pull resistor, but have the current sink configured for minimum
current.
ANI_IN, IN_0 and IN_1 show a pull-down behavior if active high polarity is selected. The pull direction changes with the selec-
ted polarity. It changes to pull-up if the active low polarity is selected.
The following figures show the pull-up and pull-down IO typical current behavior of the digital IOs. The internal pull resistor
voltage will be limited to approximately VDIG_PULL+0.2V. For this reason the pull current saturates above VDIG_PULL+0.2V IO input
voltage.

Figure 7.5-1: Digital IO Pull-up Typical Current Behavior

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Figure 7.5-2: Digital IO Pull-down Typical Current Behavior

7.6 User Sequence System

The User sequence system sets the current and generates the PWM pulse signals needed to control the LED driver stages.
The PWM duty cycle and current of each channel can be controlled using the instructions within a sequence.

7.6.1 Sequences
7.6.1.1 Sequence Trigger & mode of operation
The device offers up to eight sequences which are mapped to their corresponding input pins. At any point of time four
sequences can run in parallel. The device offers two modes of operation Main mode and Animation mode.
• Main mode
This mode is meant for the basic light functions which implement the regulatory requirements i.e., TAIL, BRAKE, TURN.
• Animation mode
This mode is meant for non-critical light functions i.e LEAVE HOME, COME HOME.
The mode selection allows the device to have two times the number of light functions with one additional mode selection
pin(ANI_IN). The only difference between the two modes is the priority. The Main mode has higher priority with respect to
Animation mode. This is described in more detail in the Mode transition section.
The sequence mapping to the trigger signals, mode of operation and priority is shown in the table below.

Table 7.6.1.1-1: Sequence priority & trigger signal mapping

Mode Sequence Trigger signal Priority
Main Mode 0 (0) IN_0 = Active 1
Main Mode 1 (1) IN_1 = Active 2
Main Mode 2 (2) IN_2_LED2 = Active 3
Main Mode 3 (3) IN_3_LED3 = Active 4
Animation Mode 0 (4) IN_0 = Active 1
Animation Mode 1 (5) IN_1 = Active 2
Animation Mode 2 (6) IN_2_LED2 = Active 3
Animation Mode 3 (7) IN_3_LED3 = Active 4
Main Mode is when ANI_IN = Inactive and Animation Mode is when AN_IN = Active
Sequences can be referred to in absolute or with respect to mode. The numbers in bracket in the Sequence column refer to the absolute reference.
For example : Animation mode sequence 0 or Sequence 4

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7.6.1.2 Sequence Configuration

Each sequence can be configured to control any of the 16 LED channels.
The LED channels configured for alternate function , i.e. Diagnosis,Link,Input, and Output enable, will not be considered for
binning and derating. In case a LED is shared between multiple sequences, in the event of parallel execution of the said
sequences, the sequence having higher priority will drive the LED channel.
A sequence configuration consists of :
1. Sequence to channel association
2. A bit to enable/disable the sequence
3. Start & end address of the instructions which are to be run on sequence triggering.
4. Diagnostic channel association
5. A bit to select Single lamp/ Multi lamp (SLM/MLM) mode
This can be programmed using the Configurator tool during application development. The following tables show
1. Sequence configuration area in OTP
2. Details of the configuration items

Table 7.6.1.2-1: Sequence configuration in OTP

Sequence Address Size (bytes)
Sequence 0 0x00003480 6
Sequence 1 0x00003486 6
Sequence 2 0x0000348C 6
Sequence 3 0x00003492 6
Sequence 4 0x00003498 6
Sequence 5 0x0000349E 6
Sequence 6 0x000034A4 6
Sequence 7 0x000034AA 6

Table 7.6.1.2-2: Sequence configuration details

Bits Name Description
47:32 LED_ASSOCIATION Each bit represents a channel.
Bit 47:32 -> Channel 15:Channel 0

The value of the bit indicates the association

0 : Not associated
1 : Associated with this sequence.
31:23 RESERVED Reserved
22:16 END_INSTR_PTR Address of the last instruction which is part of the sequence
15 RESERVED Reserved
14:8 START_INSTR_PTR Address of the first instruction which is part of the sequence
7:6 RESERVED Reserved
5:4 DIAG_ASSOCIATION Sequence association with DIAG pins
0 : INVALID - CANNOT BE USED
1 : associated with DIAG0
2 : associated with DIAG1
3 : associated with both DIAG0 and DIAG1

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Bits Name Description

3 SLM Single lamp mode
0 : Multi lamp mode
1 : Single lamp mode
2:1 RESERVED Reserved
0 ENABLE Enable the sequence
0 : Sequence disabled
1 : Sequence enabled
• The configuration details for all sequences is identical and is described in this table

7.6.1.3 Mode Transition

The modes are differentiated by the level of the ANI_IN signal. Active level of ANI_IN signal corresponds to animation mode
and inactive level corresponds to main mode.

For transition from Main mode to Animation mode, the following conditions have to be satisfied
1. All active main mode sequences should be de-activated
2. The ANI_IN signal has to be active
3. There has to be at-least once TSTEP of quiet period (no Sequence triggered) between Animation mode activation and trig-
gering of animation mode sequence.

Transition from Animation mode to Main mode happens as soon as the ANI_IN signal is de-activated. The active animation
sequences will be de-activated and corresponding Main mode sequences will be started.

To switch the device predictably between modes the recommended steps are

• For Main mode to animation mode transition

1. Deactivate all active triggers to ensure that none of the sequences are running.
2. 10ms after step 1, activate the ANI_IN signal to put the device in animation mode.
3. 10ms after step 2, any of the animation sequences can be triggered.
If any main mode sequence trigger is active when triggering the animation mode (step 2) , the device will continue to stay
in main mode. The device will switch from main mode to animation mode only after all the active trigger signals have
become inactive.
• For Animation mode to Main mode transition
1. Deactivate all active triggers to ensure that none of the sequences are running.
2. 10ms after step 1, deactivate the ANI_IN signal to put the device in main mode.
3. 10ms after step 2, any of the main mode sequences can be triggered.
If any animation mode sequence trigger is active when triggering the main mode (step 2) , the device will immediately
switch to main mode and execute the corresponding main mode sequence. The device switches to Main mode whenever
ANI_IN signal is inactive.
The device behavior with respect to the condition of the input signals is shown in the following figure.

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Figure 7.6.1.3-1: InputSignal behavior

Device response to input signals (IN_X, ANI_IN), where X can be ( 0, 1, 2_LED2, 3_LED3)

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7.6.1.4 Sequence Database

Sequence database holds the users instructions for the light function being implemented. It can hold a maximum of 128 com-
mands along with necessary parameters. This database is spread across multiple regions in OTP area as shown in the table
below. The total space available for sequence database is 1832 bytes (1340+376+116).

Table 7.6.1.4-1: Sequence database

Address Data Comments
0x34B0 SEQUENCE_DB_PARS_ADDRESS Hold starting address of Variable para-
(4 bytes) meters. This is to be filled by the Config-
urator / programming tool.
0x34B4 SEQUENCE_DB Sequence database
(1340 bytes)
0x39F0 RESERVED Reserved for DEVICE_VERSION and
(16 bytes) UDIN. This needs to be kept untouched
by the Configurator / programming tool.
0x3A00 SEQUENCE_DB Sequence database
(376 bytes)
0x3B78 RESERVED Reserved for DEVICE_INFO. This needs to
(8 bytes) be kept untouched by the Configurator /
programming tool.
0x3B80 SEQUENCE_DB Sequence database
(116 bytes)

The sequence database is split into two parts : fixed and variable. Fixed part occupies 4 bytes of space per entry and contains
instruction, index into variable parameter array as specified below.

Table 7.6.1.4-2: Sequence database details

Field Size(byte) Remark
Instruction 1 Command byte. It can be any one of the
following
0x3C - LNKOF
0x3D - LNKON
0x5C - SETLNKOF
0x5D - SETLNKON
0x6C - DIM
0x6D - DIMX
0x8C - WAIT
0xAC - GOTO
Operand_1 1 The interpretation is based on the
instruction.
Current value for SETLNKxx, DIMx and
jump address for GOTO.
No meaning for other commands.

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Field Size(byte) Remark

ParIndex 2 The interpretation is based on the
instruction.
Index into variable parameter array for
SETLNKxx, DIMx
Timer counter for WAIT
No meaning for other commands

The fixed part of sequence database starts at 0x34B4 and can grow up to 0x36B3, depending on number of instructions. The
variable part starts after the fixed part. The starting address of this variable part is placed at 0x34B0. The variable part of the
sequence database can grow up to 0x3BF3, leaving the reserved spaces in between. ParIndex in the fixed part is 2 byte
aligned. This variable part is used to store pwms (SETLNKxx) and pwm percentages (DIMx) for channels mentioned in the
sequence (main or animation) to which this sequence database entry is associated with.

Example with 4 sequences and 11 database entries

Sequence Configuration

{1,X,X,X,X,0, 1, 0x00E0}, // Seq 0 - LED5, LED6 and LED7 ; start index = 0, stop index = 1
{1,X,X,X,X,2, 3, 0x1800}, // Seq 1 - LED11 and LED12 ; start index = 2, stop index = 3
{1,X,X,X,X,4, 5, 0x2000}, // Seq 2 - LED13 ; start index = 4, stop index = 5
{1,X,X,X,X,6,10, 0xC000}, // Seq 3 - LED14 and LED15 ; start index = 6, stop index = 10

Sequence Database entries (11)

00{SETLNKON, 0x33,0x1234,0x00,0x00,0x00,0x00,0x00,0x7F,0x3F,0x2F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
01{GOTO, 0x00,0x0000,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
02{SETLNKOF, 0x19,0x5678,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x6F,0x1F,0x00,0x00,0x00}
03{GOTO, 0x02,0x0000,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
04{SETLNKOF, 0x22,0x9ABC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00}
05{GOTO, 0x04,0x0000,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
06{SETLNKOF, 0x40,0xDEF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x5F,0xD0}
07{DIM, 0x20,0x01F4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x02}
08{LNKON, 0x00,0x0000,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
09{WAIT, 0x00,0xFFFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
10{GOTO, 0x06,0x0000,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}

The figure below shows the organization of the above instructions in the OTP memory based on the given sequence configur-
ation.

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Figure 7.6.1.4-1: Sequence database details

Data highlighted is ignored and is considered "do not care".

7.6.2 Instructions
The sequences control the LED channels via the instructions. The instructions available to control the device behavior are lis-
ted in the table below. The state machine executing the instructions is driven by a clock with a period of T STEP. The instructions
allow the user to set a maximum current of 102.3mA / channel, however Elmos recommends to limit this to 100mA / chan-
nel.

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Table 7.6.2-1: Instruction set for E522.88

1. Instruction Operand 1 Operand 2 Operand 3 Operand N Operand Description
4 18
1 SETLNKON Current Wait Steps PWM - PWM - PWM - Sets the current , PWM for the channels.
(0x5D) (8 bits) (16 bits) Channel 0 Channel N Channel 15 If Link is configured then the correspond-
(1) (8 bits) (8 bits) (8 bits) ing link channel current source will be
(2) N = 1 to 14 turned ON.
(4)
2 SETLNKOF Current Wait Steps PWM - PWM - PWM - Sets the current , PWM for the channels.
(0x5C) (8 bits) (16 bits) Channel 0 Channel N Channel 15 If Link is configured the link channel cur-
(8 bits) (8 bits) (8 bits) rent source will be turned OFF.
N = 1 to 14 (4)
3 DIM Current Steps dPWM - dPWM - dPWM - Sets the current .
(0x6C) (8 bits) (16 bits) Channel 0 Channel N Channel 15 Changes the PWM for a channel by
(3) (8 bits) (8 bits) (8 bits) "dPWM" for "Steps + 1" units of time
N = 1 to 14 intervals.
dPWM :Can be configured from -12.5% to
+12.4% .
PWM's will be saturated at 0 and 1023.
0 in the dPWM field means the previous
PWM is maintained.
(4)
4 DIMX Current Steps dPWM - dPWM - dPWM - Sets the current .
(6D) (8 bits) (16 bits) Channel 0 Channel N Channel 15 Changes the PWM for a channel by
(8 bits) (8 bits) (8 bits) "dPWM" for "Steps + 1" units of time
N = 1 to 14 intervals.
dPWM :Can be configured from -50% to
+49.6%.
PWM's will be saturated at 0 and 1023
0 in the dPWM field means the previous
PWM is maintained.
(4)
5 WAIT Steps Waits for Steps + 1 time intervals
(0x8C) (16 bits)
6 GOTO Jump 7 bits are used to decide the jump
(0xAC) address address
(8 bits)
7 LNKON Turns the current source of the link chan-
(0x3D) nel associated with the sequence ON.
This is ignored if the LED channel is not
configured for alternate function.
8 LNKOF Turns the current source of the link chan-
(0x3C) nel associated with the sequence OFF.
This is ignored if the LED channel is not
configured for alternate function.
(1) 8 bit PWM is converted to 10 bit in the device as {(PWM x 1023) / 255}
(2) Each bit of the current is equal to 400uA current
(3) 1 time interval = 10ms
(4)For instructions which set PWM's or dPWM's, data has to be provided only for those channels which are associated with the sequence

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7.6.2.1 SETLNKON Instruction

This instruction sets the LED channel to defined PWM and current values. The instruction effect is restricted to LED channels
associated with this sequence. Other LED channels on the device will not be affected. The LED channel current is further
modified by binning and derating. This command also turns the current source of the link channel, associated with this
sequence, ON. The effect of the linking will be dependent on the pin configuration LED_ALT_CONFIG:LED_ALT_CONFIG. In
case the channel is not configured for linking, the link operation will be ignored.
The table below shows the details for this instruction.
Table 7.6.2.1-1: SETLNKON Instruction details
Field Bits Value Description
Micro-code 8 0x5D Opcode
Current 8 0xXX 0x00 : 0 mA
0xFF : 102.3mA
Current value applies to the LED's
who are associated with this sequence
Wait Steps 16 0xXXXX Waits in this state for t + 1 units.
where is t = decimal equivalent of 0xXXXX
PWM LED 0 - 15 8 (x 16) 0xXX 0x00 : 0%
0xFF : 100%
Only for the LED channels that are associated
with the sequence
SETLNKON instruction:
Opcode 1 byte, Current 1 byte, Wait Steps 2 bytes, Indexing 2 bytes, PWM 1 byte for every enabled channel, Padding to make the overall number of bytes
even.

7.6.2.2 SETLNKOF Instruction

This instruction sets the LED channel to defined PWM and current values. The instruction effect is restricted to LED channels
associated with this sequence. Other LED channels on the device will not be affected. The LED channel current is further
modified by binning and derating. This command also turns the current source of the link channel, associated with this
sequence, OFF. The effect of the linking will be dependent on the pin configuration LED_ALT_CONFIG. In case the channel is
not configured for linking, the link operation will be ignored.

The table below shows the details for this instruction.

Table 7.6.2.2-1: SETLNKOF Instruction details

Field Bits Value Description
Micro-code 8 0x5C Opcode
Current 8 0xXX 0x00 : 0 mA
0xFF : 102.3mA
Current value applies to the LED's
who are associated with this sequence
Wait Steps 16 0xXXXX Waits in this state for t + 1 units.
where is t = decimal equivalent of 0xXXXX
PWM LED 0 - 15 8 (x 16) 0xXX 0x00 : 0%
0xFF : 100%
Only for the LED channels that are associated
with the sequence
SETLNKOF instruction:
Opcode 1 byte, Current 1 byte, Wait Steps 2 bytes, Indexing 2 bytes, PWM 1 byte for every enabled channel, Padding to make the overall number of bytes
even.

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7.6.2.3 WAIT Instruction

This instruction has no effect on the current/PWM values for the LED channels. This instruction can be used to hold the LED
channel states for a fixed amount of time. The instruction details are provided in the table below.

Table 7.6.2.3-1: WAIT Instruction details

Field Bits Value Description
Micro-code 8 0x8C Code value identifying WAIT instruction
Steps 16 0xXXXX Wait for count + 1 times TStep.
0x0000: count = 1
0xFFFE: count = 65535
0xFFFF: count = 65536
WAIT Instruction (4 bytes)

7.6.2.4 DIM Instruction

This instruction changes the PWM by user specified delta values and steps. The PWM value is saturated at 0% or 100% if
reached within the defined time interval. The PWM of the channels is incremented/decremented from the previous PWM
value for the channel. If the PWM values of the channels are not set by any command before this, the PWM's for the chan-
nels are assumed to be zero. On deactivation of the sequence, the history information is lost and the next activation would
be a fresh cycle. The command also sets the current through the LED channels. The command effect is restricted to lighting
LED's belonging to this sequence. The details of this instruction are shown in table below.

• During PWM duty cycle ramp up the device increments PWM pulse length to larger values and reloads these values a short
time after a previous PWM pulse has been finished. The PWM channels may get active "again" to "finish" the new (just
loaded) PWM pulse length. This can result in the short pulses on the LED channel. This happens only during automatic
internal duty cycle transition and does not happen for steady state conditions.

Table 7.6.2.4-1: DIM Instruction details

Field Bits Value Description
Micro-code 8 0x6C Code value identifying DIM instruction
Steps 16 0xXXXX Applies the increment/decrement for Steps + 1 cycles.
Steps
0x0000 : 1 cycle
0x0001 : 2 cycles
0xFFFF : 65536 cycles
Current 8 0xXX 0x00 :0 mA
0xFF :102.3 mA
This value applies to the LED's that are associated with
the sequence

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Field Bits Value Description

dPWM LED 0 - 15 8 (x 16) 0xXX 0x00 : A value of 0 means that the PWM value will not be
changed.
0x01 : + 1/1023 % (~+ 0.1%)
0x02 : + 2/1023 % (~+ 0.2%)
..
0x7E : + 126/1023 % (~+ 12.3%)
0x7F : + 127/1023 % (~+ 12.4%)
0x80 : - 128/1023 % (~- 12.5%)
0x81 : - 127/1023 % (~- 12.4%)
..
0xFE : - 2/1023 % (~- 0.2%)
0xFF : - 1/1023 % (~- 0.1%)

Only for the LED channels that are associated with the
sequence
DIM instruction:
Opcode 1 byte, Current 1 byte, Steps 2 bytes, Indexing 2 bytes, PWM 1 byte for every enabled channel, Padding to make the overall number of bytes even.

7.6.2.5 DIMX Instruction

This instruction offers a higher change value as compared to the DIM command. This instruction changes the PWM by user
specified delta values and steps. The PWM of the channels is incremented/decremented from the previous PWM value for
the channel. If the PWM values of the channels are not set by any command before this, the PWM's for the channels are
assumed to be zero. On deactivation of the sequence, the history information is lost and the next activation would be a fresh
cycle. The PWM value is saturated at 0% or 100% if reached within the defined time interval. The command also sets the cur-
rent through the LED channels. The command effect is restricted to lighting LED's belonging to this sequence. The details of
this instruction are shown in table below.

• During PWM duty cycle ramp up the device increments PWM pulse length to larger values and reloads these values a short
time after a previous PWM pulse has been finished. The PWM channels may get active "again" to "finish" the new (just
loaded) PWM pulse length. This can result in the short pulses on the LED channel. This happens only during automatic
internal duty cycle transition and does not happen for steady state conditions.

Table 7.6.2.5-1: DIMX Instruction details

Field Bits Value Description
Micro-code 8 0x6D Code value identifying DIMX instruction
Steps 16 0xXXXX Applies the increment/decrement for Steps + 1 cycles.
Steps
0x0000 : 1 cycle
0x0001 : 2 cycles
0xFFFF : 65536 cycles
Current 8 0xXX 0x00 :0 mA
0xFF :102.3 mA
This value applies to the LED's associated with the
sequence

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Field Bits Value Description

dPWM LED 0 - 15 8 (x 16) 0xXX 0x00 : A value of 0 means that the PWM value will not be
changed.
0x01 : + 4/1023 % (~+ 0.4%)
0x02 : + 8/1023 % (~+ 0.8%)
..
0x7E : + 504/1023 % (~+ 49.2%)
0x7F : + 127/1023 % (~+ 49.6%)
0x80 : - 128/1023 % (~- 50.0%)
0x81 : - 127/1023 % (~- 49.6%)
..
0xFE : - 8/1023 % (~- 0.8%)
0xFF : - 4/1023 % (~- 0.4%)

Only for the LED channels that are associated with the
sequence
DIMX instruction :
Opcode 1 byte, Current 1 byte, Steps 2 bytes, Indexing 2 bytes, PWM 1 byte for every enabled channel, Padding to make the overall number of bytes even.

7.6.2.6 LNKON Instruction

This instruction switches the current sink of linking channel assigned to the specific sequence ON (main mode: sequence 0 ->
link 0, sequence 1 -> link 1, sequence 2 -> link 2, sequence 3 -> link 3; animation mode: sequence 4 -> link 0, sequence 5 ->
link 1, sequence 6 -> link 2, sequence 7 -> link 3)
The PWM value for the link channel is 100% and current is set to 10mA.

Table 7.6.2.6-1: LNKON Instruction details

Field Bits Value Description
Micro-code 8 0x3D Code value identifying LNKON
instruction.
Turns ON the link signal asso-
ciated with this sequence.
LNKON ( 4 bytes)
Link 0 is pin : LNK0_LED4, Link 1 is pin : LNK1_LED5, Link 2 is pin : LNK2_LED6, Link 3 is pin : LNK3_LED7

7.6.2.7 LNKOF Instruction

This instruction switches the current sink of linking channel assigned to the specific sequence OFF (main mode: sequence 0 ->
link 0, sequence 1 -> link 1, sequence 2 -> link 2, sequence 3 -> link 3; animation mode: sequence 4 -> link 0, sequence 5 ->
link 1, sequence 6 -> link 2, sequence 7 -> link 3)

Table 7.6.2.7-1: LNKOF Instruction details

Field Bits Value Description
Micro-code 8 0x3C Code value identifying LNKOF
instruction.
Turns OFF the link signal asso-
ciated with this sequence.
LNKOF (4 bytes)
Link 0 is pin : LNK0_LED4, Link 1 is pin : LNK1_LED5, Link 2 is pin : LNK2_LED6, Link 3 is pin : LNK3_LED7

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7.6.2.8 GOTO Instruction

This instruction allows the code to restart from any point within the sequence. The jump address can be any number from 0
to 127. The user has to ensure that the jump address is valid and belongs to the same sequence. There is no validation in the
device for an incorrect GOTO address. The details for this instruction are shown in the table below.

Table 7.6.2.8-1: GOTO Instruction details

Field Bits Value Description
Micro-code 8 0xAC Code value identifying GOTO
Instruction
Address 8 0xXX The MSB, bit 7, is reserved
and has to be 0. The 7 LSB's
indicate the address of the
next instruction to be
executed.
GOTO Instruction ( 4 Bytes )

7.6.3 Constraints
The E522.88 device can be configured as per the application requirement. There are constraints which need to be followed to
ensure that the device functions in a predictable manner.
The following constraints must be followed:
1. Sequences (main or animation) can contain channels configured for lighting function only.
2. Start and end index of any sequence should be within the range of sequence database.
3. Any instruction in the sequence database should be from the device instruction set.
4. No blank entry is allowed the within programmed sequence database.
5. Consecutive LIGHT channels (0 and 1, 2 and 3, ....) can only be analog bundled.
6. Analog bundled channels cannot be spread across multiple sequences and should be part of same sequence(s). For
example, if LED12 and LED13 are configured to be analog bundled, both or none can be part of any sequence.
7. Any channel configured for alternate function cannot be used for analog bundling.
If DG0_LED0/DG1_LED1 is used for alternate function (Diagnostic), bundling cannot be enabled on DG0_LED0 and
DG1_LED1
If IN_2_LED2/IN_3_LED3 is used for alternate function (Input), bundling cannot be enabled on IN_2_LED2 and
IN_3_LED3
If LNK0_LED4/LNK1_LED5 is used for alternate function (Linking), bundling cannot be enabled on LNK0_LED4 and
LNK1_LED5
If LNK2_LED6/LNK3_LED7 is used for alternate function (Linking), bundling cannot be enabled on LNK2_LED6 and
LNK3_LED7
If BIN0_LED8/BIN1_LED9 is used for alternate function (Binning), bundling cannot be enabled on BIN0_LED8 and
BIN1_LED9
If OE_LED10 is used for alternate function (Output enable), bundling cannot be enabled on OE_LED10 and LED11
8. A LIGHT channel cannot be associated with both the BIN pins.
9. BIN_CLASS_LEVEL's should be monotonic i.e. BIN_CLASS_LEVEL_3 > BIN_CLASS_LEVEL_2 > BIN_CLASS_LEVEL_1 >
BIN_CLASS_LEVEL_0.
10. Index in the GOTO command should be within the range of the corresponding sequences start and stop indices.
11. Parameter index in sequence database (for variable parameters) should be valid (within the user data space) and aligned
with a 2 byte boundary.
12. During configuration, following OTP memory addresses are not to be written by the user:
39F4 DEVICE_VERSION (4 bytes)
39F8 UDIN (4 bytes)
3B7A DEVICE_INFO (2 bytes)

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13. I²C addresses (0x00 - 0x77) should not be written. These addresses are used to define memory access protocol and incor-
rect data written to these registers may render the device unusable.
14. IDAC_REF_SEL_0_15 should be written with following data:
0 when configured as LED's
1 when configured as alternate function pin

7.7 PWM System

The PWM system generates the PWM pulse signals needed to control the LED driver stages. It consists of a common PWM
period generator (configured using PWM_PRESCALER and PWM_PERIOD values) and 16 independent PWM generator chan-
nels(configured using the PULSE_x values). The figure below shows the PWM generator structure.

PWM_PRESCALER PWM_PERIOD PULSE_x

16

system prescale prescaled common period counter PWM pulse PWM pulse
clock (8MHz) counter clock period counter value generation logic 16 signals

Figure 7.7-1: PWM Generator Structure

The timing figure below shows an example timing of the prescaler counter, the period counter and different pulse lengths
shown as LED channels a, b and c. In this example the prescaler is configured with a value of 5, resulting in a prescaler divid-
ing factor of 6 system clock cycles. The period counter in this example is configured with a value of 4 which results in count-
ing from 0 to 3. The period counter is incremented every time the prescaler counter is reset to 0 when reaching it's configura-
tion value. The period counter itself is reset to 0 every time it reaches it's period configuration value minus one. This results
in a PWM period length equal to the PWM_PERIOD configuration value, based on a prescaled increment clock. In the
example timing below, the pulse starting time stamps are equal and correspond to the period counter re-start event time
stamp. The channel a is configured to generate a 2 PWM cycle pulse, the channel b is configured to generate a 3 PWM cycle
pulse and the channels c generates a 100% duty cycle pulse. A channel PWM pulse length configured to be longer than the
PWM period will result in 100% duty cycle for this channel.

The firmware configures the PWM_PERIOD to 1023 and is not available for user configuration. The PWM_PRESCALER is avail-
able in the user OTP configuration area. The individual pulses for the LED channels are derived from the user sequences. The
instructions have operands which provide the PWM or delta PWM operands which are processed and provided to the
internal hardware by the device controller.

Each PWM pulse generation logic channel uses its own virtual PWM period and can be set up to generate a PWM signal with
duty cycles from 0% up to 100%. The PWM pulse starting points of the 16 channels are distributed equidistantly over the
PWM period
• *adjacent PWM channel pulse starting point distance = PWM period / 16

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The following figure shows an example of equidistantly distributed PWM channel starting time stamps with all PWM channels
set up with 75% duty cycle. The colored parts mark the virtual PWM period of the different PWM channels.

PWM channel 0

PWM channel 1

PWM channel 2

PWM channel 3

PWM channel 4

PWM channel 5

PWM channel 6

PWM channel 7

PWM channel 8

PWM channel 9

PWM channel 10

PWM channel 11

PWM channel 12

PWM channel 13

PWM channel 14

PWM channel 15

PWM period

PWM period

Figure 7.7-2: Equidistantly Distributed Timing Example

If LED PWM channels are analog bundled, the bundled channels are supplied with the same PWM pulse length value (taken
from the first channel inside the combined bundled group) and will start at the same time stamp, which means these PWM
channels are active during exactly the same time period.

The following figure shows an example of a analog bundled PWM channel timing. In this example 8 groups of 2 adjacent LED
PWM channels are combined.

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PWM channel 0

PWM channel 1

PWM channel 2

PWM channel 3

PWM channel 4

PWM channel 5

PWM channel 6

PWM channel 7

PWM channel 8

PWM channel 9

PWM channel 10

PWM channel 11

PWM channel 12

PWM channel 13

PWM channel 14

PWM channel 15

PWM period

PWM period

Figure 7.7-3: Combined PWM Channels Example

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7.8 LED Current Sinks

7.8.1 Current sinks
LEDx

100 mA
40 mA
Range ADC-
1 0
Mux
PWM
Digital
Control

Current ADC-
DAC
Mux

GND
Figure 7.8.1-1: ISINK Block Diagram

Each current sink is based on a DAC with selectable full scale range. The range can be selected per LED using the
IDAC_REF_SEL_x values.
The current sink gets current strength information and the PWM duty cycle from the digital part.
The output switch offers various slew rate settings, configurable using the IO_CONFIG.slew value, to improve EMC perform-
ance.
An internal ADC can be connected to monitor pad-voltage for diagnosis purpose.

In this device for any LED channel which is used for alternate configuration, the IDAC_REF_SEL_x has to be set for lower
range. For LED channel being used for lighting function, this has to be set for higher range.

The following figures show the relation between the current configuration value (digital set value) and the resulting LED cur-
rent. The LED current can saturate above the selected range maximum current value. Below the selected range minimum cur-
rent value the LED current behavior can be non-linear including a possible saturation of the driven LED current. For this
reason it's not recommended to select an LED current outside the selected range.

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Figure 7.8.1-2: LED Current Sink 40mA Range Behavior

Figure 7.8.1-3: LED Current Sink 100mA Range Behavior

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7.8.1.1 Advanced Power Management

Figure 7.8.1.1-1: Advanced Power Management

Eight pairs of LED pins offer the option to be configured in analog bundling mode (DG0_LED0 & DG1_LED1, IN_2_LED2 &
IN_3_LED3, ... LED14 & LED15). This option is intended for advanced thermal management (please see figure Advanced
Power Management), shifting power dissipation to an external power sink resistor, which reduces the driver power consump-
tion.
The channel current is regulated as a sum of currents in LED(x) and LED(x+1). The priority output LED(x) drives the current as
long as the voltage headroom allows to. The bypass output LED(x+1) is used to deliver the remaining current flow. In any case
the bypass output LED(x+1) drives at least 5% of the sum of currents preventing the LED(x+1) from regulation performance
lost. This implies, that the priority output LED(x) will drive at maximum 95% of the sum of currents.

The current sink analog bundling with prioritized current sum regulation can be enabled per LED driver pair using the
ISINK_BUNDLE configuration value. In case, an LED driver pair is configured to be bundled like described before, the phases of
both the channels will be aligned with equal pulse lengths for analog bundled LED channels.
For LED channels in analog bundling mode, the LED current, DAC range and PWM pulse length configuration will only be
taken from the lower channel configuration and will also be applied to the upper channel to provide a consistent behavior of

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analog bundled LED channel pairs. The upper channel LED current, DAC range and PWM pulse length configuration is ignored
in this special case.

The described distribution of current allows to share some of the linear regulator power with the external power-shunt.
Figure Advanced Power Management shows the basic power dissipation per channel as a function of the LED supply voltage
at:

• the driven LEDs (ILED = 60mA in this example)

• the external power shunt, given for exemplary values R1 = 68Ω, R2 = 100Ω, R3 = 150Ω
• and the remaining on-chip power dissipation of the bundled driver channels.

For further power-budget optimization, the chip offers the option to enable supply-voltage based derating of the LED cur-
rents, as well as core-temperature based derating. LED current derating is described in to following sub-chapter.

• Supply voltage based derating is displayed, starting at 20V, and decreasing the output current with 3.75mA/V up to 30V.
• Depending on ambient temperature and power dissipation in other channels, temperature derating can decrease the cur-
rent further. This is not displayed in this figure above.

7.8.1.2 LED Current Derating

To protect the device from thermal damage, an automatic LED current derating is implemented. Two independent types of
device internal (LED supply and device temperature) measurement based derating functions can be configured to derate the
LED current between a start and stop value as shown in the following figures. The derating is implemented as a nominal LED
current dependent percentage function, which means that larger currents are derated more than the smaller currents from
an absolute point of view. The LED supply and VT (device temperature) derating configuration values found below can be
used to configure the desired range and gain values.

Figure 7.8.1.2-1: LED Supply Voltage Based Derating Example

The figure above shows the LED supply voltage dependent LED current derating with the following example configuration val-
ues:

• derating start LED supply value = 10V

• derating stop LED supply value = 20V
• derating gain select value = 9

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This results in a percental LED derating by:

• 10V * 9 * 0.61%/V = 54.9%

Considering a nominal LED current of 100mA, the stop LED current will be at:

• 100mA * 45.1% = 45.1mA

Figure 7.8.1.2-2: Device Junction Temperature Based Derating Example

The figure above shows the device junction temperature dependent LED current derating with the following example config-
uration values:

• derating start VT value = 120°C

• derating stop VT value = 130°C
• derating gain select value = 15

This results in a percental LED derating by:

• 10K * 15 * 0.39%/K = 58.5%

Considering a nominal LED current of 100mA, the stop LED current will be at:

• 100mA * 41.5% = 41.5mA

The E522.88 device offers a possibility of using an external sensor to reduce the LED current. This reduction can be pro-
grammed as per application requirement. This derating feature can be used to control board thermals when used with an
external NTC/PTC resistor, sensing LED temperature.
A typical circuit that can be used to implement a thermistor based derating is shown in the figure below.

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Figure 7.8.1.2-3: Thermistor based derating

The device when configured for sensing external voltage, sinks a current through the BIN1_LED9 pin. This current is program-
mable through OTP register BIN_CLASS_CURRENT. To ensure a robust design, Elmos recommends that this current should be
>= 10mA. The device measures the differential voltage across the pin VS and BIN1_LED9. This measured voltage Vb is used to
determine the derating factor MVB_derate. Based on the configuration of the register TEMPSENSE_TYPE and
TEMPSENSE_NTCPTC, the derating algorithm applies a multiplier MVB_derate in range [0...1] to the LED current using the for-
mulas shown in the table below.

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Table 7.8.1.2-1: External derating formula

Tempsense Condition MVB_derate
NTC Vb >= VT_DERATE_START 1
NTC VT_DERATE_START > Vb > 1 - (vt_gain * (VT_DERATE_START – Vb) / 256)
VT_DERATE_STOP
NTC Vb <= VT_DERATE_STOP 1 - (vt_gain * (VT_DERATE_START - VT_DERATE_STOP) / 256)
PTC Vb <= VT_DERATE_START 1
PTC VT_DERATE_START < Vb < 1 - (vt_gain * (Vb - VT_DERATE_START ) / 256)
VT_DERATE_STOP
PTC Vb >= VT_DERATE_STOP 1 - (vt_gain * (VT_DERATE_STOP - VT_DERATE_START) / 256)
Vb is the differential voltage between pin VS and pin BIN1_LED9

The average LED current is given by ISET x DC, where ISET is the programmed channel current and DC is the duty cycle at
which the channel is operated. The user has an option of applying the derating factor on either of ISET or the DC. This is con-
trolled by the register DUTY_DERATE.
When using derating along with analog bundling of channels, it is recommended to use the DC based derating.

7.8.1.3 LED Binning

To support different LED bin classes per device, a general LED bin factor can be configured per LED using the BIN_GAIN_X val-
ues.

Separate to this fixed bin configuration, the voltage drop over an external resistor connected to BIN0_LED8 or BIN1_LED9 pin
can be evaluated for LED binning. These pins can be configured for bin evaluation using the LED_ALT_CONFIG register. Once
the pin is configured for BIN evaluation,the firmware configures it for 100 percent PWM duty cycle. The sink current configur-
ation value from BIN_CLASS_CURRENT register is used to drive this pin.

Note: the voltage over the external resistor is used for bin class evaluation. The class evaluation is done every PWM cycle.

A table of 4 bin class levels (BIN_CLASS_LEVEL_x values) can be used to distinguish between 5 bin classes with separate bin
gain values (BIN_0_CLASS_GAIN_x or BIN_1_CLASS_GAIN_x values). The ADC measurement value of the pin to be evaluated
is compared to the specified levels, the resistor value related bin class gain is determined and applied to the LEDs selected
using the BIN_0_CLASS_ENABLE_x or BIN_1_CLASS_ENABLE_x values.
When the BIN_0_CLASS_ENABLE_x or BIN_1_CLASS_ENABLE_x bit of an LED channel is configured as 1. The related general
LED bin factor and the evaluated bin class gain work independently on the selected channel. The actual gain factor would be
a multiplication of general bin factor and the resistor evaluated bin gain. Both the BIN pins should not be selected for a single
LED channel.

The following figure shows an example bin class table with resistor values selected from the E12 series.
In this example the external resistor is supplied with a current of 16mA.
The external resistor is evaluated once every LED PWM period and 3 adjacent sample values are filtered using a median filter
algorithm (the last 3 values including the current value are sorted and the middle value is taken) before bin class gain selec-
tion.

The bin adoption is implemented as a LED current factor to reduce or raise the LED current depending on the LED bin class to
achieve a uniform LED luminance of LEDs connected to a single driver device and between LEDs connected to different LED
driver devices.

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Figure 7.8.1.3-1: Example Bin Class Table

The following figure shows an LED binning example of the following parameter set:

• BIN_CLASS_LEVEL_0 = 1V
• BIN_CLASS_LEVEL_1 = 2V
• BIN_CLASS_LEVEL_2 = 3V
• BIN_CLASS_LEVEL_3 = 4V
• BIN_CLASS_GAIN_0 = -25%
• BIN_CLASS_GAIN_1 = -12.5%
• BIN_CLASS_GAIN_2 = +0%
• BIN_CLASS_GAIN_3 = +12.5%
• BIN_CLASS_GAIN_4 = +25%

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Figure 7.8.1.3-2: LED Binning Example

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7.8.1.4 Logical view of the current calculation steps

Figure 7.8.1.4-1: Logical view of the current calculation steps

Current calculation steps

The gain and offset correction are done to ensure that max code from the configuration results in a current close to 102.3mA,
while meeting the IC accuracy specification. The fixed binning correction is an additional factor provided. This is done along
with the gain & offset correction for the current sink as shown in the above figure. This can lead to the maximum current
exceeding 102.3 mA in case of fixed binning with factors > 1.0.

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7.9 Measurement System

7.9.1 Description

Figure 7.9.1-1: Measurement System

The centre of the measurement system is a 10 Bit SAR ADC.

With the ADC, it is possible to convert:

• LED voltage of each channel (prescaled and saturated)

• LED current of each channel
• Internal temperature-sensor voltage
• VDD5 voltage
• VS voltage (full range)
• IN_1 voltage (full range)
• IN_0 voltage (full range)
• A sample and hold (S&H) buffer voltage

3 inputs to the measurement system can be send to a sample and hold buffer. These are:

• VS voltage (prescaled and saturated)

• IN_1 voltage (prescaled and saturated)
• IN_0 voltage (prescaled and saturated)

LED(x) voltage and its supply can be sampled at the same time, and conversion of them can be done afterwards in series.
The diagnosis module will do a digital subtraction of the two results and compare it against the short detection threshold.

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For better resolution in normal supply scenarios, the LED resistor dividers will reach ADC full scale at approximately 28V (see
electrical parameter AMEAS_VLED). To implement a full scale VS derating up to 40V, another resistor divider for VS is added to the
measurement system (see electrical parameter A MEAS_VS).

7.9.2 SAR ADC

7.9.2.1 Accuracy of Measurement System

*2)

Legend

Ideal
Measurement Result

Accuracy

Notes:

1) saturated region =E MEAS_SAT_K

2) error band =±[ E MEAS_REL_K∗X in +E MEAS_UNC_K ]
K= ILED , VLED , VS , ...

*1)

Xin
*1)

Figure 7.9.2.1-1: Accuracy Diagram

Explanation of Electrical Parameters for Accuracy Estimation:

The figure above shows exemplary the tolerances of each measurement:

There are mainly two effects:
1) Very low input values may saturate.
2) Normal input values suffer a combination of linear errors, which are a percentage value of the input plus some uncertainty.
This sum includes temperature effects, non-linearities of the ADC and also noise.

7.10 Diagnosis
The device implements diagnosis features to detect open or short conditions of the connected LEDs.
An LED short condition means, that the LED driver pin is shorted with the LED supply net. An LED open condition means, that
the LED driver pin is open and does not sink a significant current, e.g. caused by a broken LED or LED connection.

This diagnosis is implemented using once per PWM period ADC measurements of all LED channel voltages and their related
supply voltages.

Every diagnosis result compare operation generates an event which is fed into an LED error filter.
Each LED channel implements it's own error filter using a counter and a common error level value (IO_CONFIG.diag_level).

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In case of a LED error condition, the filter counter value is incremented by 1 if the counter values is smaller than the IO_CON-
FIG.diag_level value. In case of an LED OK condition, the filter counter value is decremented by 1 if the error counter is larger
than 0.
When the filter counter value reaches the IO_CONFIG.diag_level value, an LED channel error flag is set and kept until the fil-
ter counter value reaches 0 again. When the filter counter value reaches 0, the LED channel error flag is cleared.

Figure 7.10-1: Open and Short Diagnosis Filter Behavior

The device implements two independent diagnosis groups with their related evaluation logic shown in the figure below.
Every sequence has to be associated with at least one of these diagnostic groups or can be associated with both. Diagnostic
group 0 is flagged on DG_0_LED0 pin and Diagnostic group 1 is flagged on DG_1_LED1 pin, if the pins are configured for dia-
gnostics using LED_ALT_CONFIG.
To ensure that the device is capable of listening to other errors on a multi IC system, at least one of the DG_x_LEDx (x in 0,1)
pins have to be configured for diagnostics and associated sequence/s should be configured for single lamp mode.

An LED pin short condition evaluation is only done and signaled in case of:

• LED supply is larger than the minimum LED supply level VS_TOO_LOW.
• LED related raw (non-offset-gain corrected) LED supply ADC measurement value is not saturated
• Short detection for the pin is enabled
• PWM was active and valid (LED current slewing has finished) during ADC measurement
In case of high LED supply voltage (VLED_supply_max) above 28V the supply measurement will saturate. This leads to lower
VDIF results than expected. If the short detection threshold has low margin to the forward voltage of the LED string this may
result in false SHORT diagnosis results.
For LED supply voltages above 28V it is recommended to maintain a margin from short detection threshold voltage to the for-
ward voltage of the LED string of at least (VLED_supply_max - 28V).

An LED pin voltage based open condition evaluation is only done and signaled in case of:

• LED supply is larger than the minimum LED supply level VS_TOO_LOW.
• Voltage based Open detection for the pin is enabled
• PWM was active and valid (LED current slewing has finished) during ADC measurement

The LED channel retry measurement state is used to recover LED channels from active error state. In this state the LED chan-
nel is switched ON for the minimum time needed to do LED channel retry ADC measurement. In case of analog bundling,
both the channels will be switched ON for retry measurement. The retry pulse width is the minimum required to ensure that
the measurement can be achieved. Since the error channel is switched ON there is a possibility of error channel glowing with
minimum intensity during retry measurements.

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Please note, that in SLM mode all LED channel drivers of a sequence are switched off, if at least one LED of this sequence is in
error state or off. The LEDs which cause this error state will be ON for retry measurements. This lowers the device current
consumption in OPEN/SHORT error state, which allows to detect this error state (if all device LED driver channels are com-
bined in a single diagnosis group) using a very low current consumption compare threshold.

7.10.1 Min PWM for diagnostic

The hardware monitors the LED pin voltage for performing the LED open/short diagnostics. The pin voltage takes a finite time
to settle to the final value. The internal measurement ADC has to wait until this time to ensure proper diagnostics. This set-
tling times depends on the Slew setting, PWM period and internal hardware parameters. The equation for calculation of the
minimum PWM pulse duration is shown below:

TSLEW + (TADCs + TADCc)*3*CHtype + (2 x TADCs + TADCc )

TSLEW : Slew dependent masking time ( 0 : 5us, 1 : 25us, 2 : 31us, 3 : 60us)

TADCs : ADC sampling time per sample 4us
TADCc : ADC conversion time per sample 5us
CHtype : Channel type( 0: normal channel, 1 : analog bundled)

The user has to ensure that the channel ON times are greater than the value calculated using the above equation. The device
uses the minimum value calculated as per the above equation for retry measurements in case of open/short errors.

7.10.2 Diagnostic & SLM logic

The diagnostic feature for the device is dependent on the pin configuration, sequence to diagnostic group association and the
single lamp mode configuration. The table below explains the effect of all these combinations on the device behavior.

Table 7.10.2-1: Diagnostic behaviour

DG1_LED1* DG0_LED0* SEQ-DIAG SLM mode Behaviour
CFG
X X 00 X INVALID : Sequence to diagnostic group association of 00 is not
allowed.
0 0 01 0 On internal error of any associated led -
retry enabled on error led
0 0 01 1 On internal error of any associated led -
retry enabled on error led
all leds associated with this sequence are turned off
0 0 10 0 On internal error of any associated led -
retry enabled on error led
0 0 10 1 On internal error of any associated led
retry enabled on error led
all leds associated with this sequence are turned off
0 0 11 0 On internal error of any associated led -
retry enabled on error led
0 0 11 1 On internal error of any associated led -
retry enabled on error led
all leds associated with this sequence are turned off

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DG1_LED1* DG0_LED0* SEQ-DIAG SLM mode Behaviour

CFG
0 1 01 0 On internal error of any associated led -
retry enabled on error led
asserts DG0_LED0
0 1 01 1 On internal error of any associated led -
retry enabled on error led
all leds associated with this sequence are turned off
asserts DG0_LED0

On external error from DG0_LED0 -

all leds associated with this sequence are turned off
0 1 10 0 On internal error of any associated led -
retry enabled on error led
0 1 10 1 On internal error of any associated led
retry enabled on error led
all leds associated with this sequence are turned off
0 1 11 0 On internal error of any associated led -
retry enabled on error led
asserts DG0_LED0
0 1 11 1 On internal error of any associated led -
retry enabled on error led
all leds associated with this sequence are turned off
asserts DG0_LED0

On external error from DG0_LED0 -

all leds associated with this sequence are turned off
1 0 01 0 On internal error of any associated led -
retry enabled on error led
1 0 01 1 On internal error of any associated led -
retry enabled on error led
all leds associated with this sequence are turned off
1 0 10 0 On internal error of any associated led -
retry enabled on error led
asserts DG1_LED1
1 0 10 1 On internal error of any associated led
retry enabled on error led
all leds associated with this sequence are turned off
asserts DG1_LED1

On external error from DG1_LED1 -

all leds associated with this sequence are turned off
1 0 11 0 On internal error of any associated led -
retry enabled on error led
asserts DG1_LED1

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DG1_LED1* DG0_LED0* SEQ-DIAG SLM mode Behaviour

CFG
1 0 11 1 On internal error of any associated led -
retry enabled on error led
all leds associated with this sequence are turned off
asserts DG1_LED1

On external error from DG1_LED1 -

all leds associated with this sequence are turned off
1 1 01 0 On internal error of any associated led -
retry enabled on error led
asserts DG0_LED0
1 1 01 1 On internal error of any associated led -
retry enabled on error led
all leds associated with this sequence are turned off
asserts DG0_LED0

On external error from DG0_LED0 -

all leds associated with this sequence are turned off
1 1 10 0 On internal error of any associated led -
retry enabled on error led
asserts DG1_LED1
1 1 10 1 On internal error of any associated led
retry enabled on error led
all leds associated with this sequence are turned off
asserts DG1_LED1

On external error from DG1_LED1 -

all leds associated with this sequence are turned off
1 1 11 0 On internal error of any associated led -
retry enabled on error led
asserts DG0_LED0 and DG1_LED1
1 1 11 1 On internal error of any associated led -
retry enabled on error led
all leds associated with this sequence are turned off
asserts DG0_LED0 and DG1_LED1

On external error from DG0_LED0 or DG1_LED1 -

all leds associated with this sequence are turned off
• These bits are part of LED_ALT_CONFIG register
X : Do not care, can be 0 or 1

7.11 Configuration and Status Memory

This OTP device requires configuration of the application to be programmed at the end of the production line. The user must
ensure that any unused and reserved registers/bits are programmed with the default values specified in the device's data-
sheet prior to deployment.

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PRODUCTION DATA – Feb 27, 2023

7.11.1 Configuration Memory (OTP)

Table 7.11.1-1: OTP configuration registers

Register Name Address Description
COM_DEV_ADDR 3400 Device address value for the communication interface 1)
IDAC_REF_SEL_0_15 3402 IDAC reference (range) selection for driver channels 0 to 15 2)
BIN_GAIN_0 3404 LED channel 0 binning gain
BIN_GAIN_1 3406 LED channel 1 binning gain
BIN_GAIN_2 3408 LED channel 2 binning gain
BIN_GAIN_3 340A LED channel 3 binning gain
BIN_GAIN_4 340C LED channel 4 binning gain
BIN_GAIN_5 340E LED channel 5 binning gain
BIN_GAIN_6 3410 LED channel 6 binning gain
BIN_GAIN_7 3412 LED channel 7 binning gain
BIN_GAIN_8 3414 LED channel 8 binning gain
BIN_GAIN_9 3416 LED channel 9 binning gain
BIN_GAIN_10 3418 LED channel 10 binning gain
BIN_GAIN_11 341A LED channel 11 binning gain
BIN_GAIN_12 341C LED channel 12 binning gain
BIN_GAIN_13 341E LED channel 13 binning gain
BIN_GAIN_14 3420 LED channel 14 binning gain
BIN_GAIN_15 3422 LED channel 15 binning gain
BIN_CLASS_CURRENT 3424 Current sink setting for BIN 0 and BIN 1 pins
BIN_CLASS_LEVEL_0 3426 Bin Class 0 evaluation level
BIN_CLASS_LEVEL_1 3428 Bin Class 1 evaluation level
BIN_CLASS_LEVEL_2 342A Bin Class 2 evaluation level
BIN_CLASS_LEVEL_3 342C Bin Class 3 evaluation level
BIN_0_CLASS_GAIN_0 342E Selected Gain when BIN 0 pin voltage (Vb) is : Vb < BIN_CLASS_LEVEL_0
BIN_0_CLASS_GAIN_1 3430 Selected Gain when BIN 0 pin voltage ( Vb ) is : Vb < BIN_CLASS_LEVEL_1
& Vb > BIN_CLASS_LEVEL_0
BIN_0_CLASS_GAIN_2 3432 Selected Gain when BIN 0 pin voltage (Vb)is : Vb < BIN_CLASS_LEVEL_2 &
Vb > BIN_CLASS_LEVEL_1
BIN_0_CLASS_GAIN_3 3434 Selected Gain when BIN 0 pin voltage (Vb) is: Vb < BIN_CLASS_LEVEL_3 &
Vb > BIN_CLASS_LEVEL_2
BIN_0_CLASS_GAIN_4 3436 Selected Gain when BIN 0 pin voltage (Vb) is: Vb > BIN_CLASS_LEVEL_3
BIN_1_CLASS_GAIN_0 3438 Selected Gain when BIN 1 pin voltage (Vb1) is: Vb1 < BIN_CLASS_LEVEL_0
BIN_1_CLASS_GAIN_1 343A Selected Gain when BIN 1 pin voltage (Vb1) is: Vb1 < BIN_CLASS_LEVEL_1
& Vb1 > BIN_CLASS_LEVEL_0
BIN_1_CLASS_GAIN_2 343C Selected Gain when BIN 1 pin voltage (Vb1) is: Vb1 < BIN_CLASS_LEVEL_2
& Vb1 > BIN_CLASS_LEVEL_1
BIN_1_CLASS_GAIN_3 343E Selected Gain when BIN 1 pin voltage (Vb1) is: Vb1 < BIN_CLASS_LEVEL_3
& Vb1 > BIN_CLASS_LEVEL_2
BIN_1_CLASS_GAIN_4 3440 Selected Gain when BIN 1 pin voltage (Vb1) is: Vb1 > BIN_CLASS_LEVEL_3

Elmos Semiconductor SE reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor SE Data Sheet CONFIDENTIAL QM No.: 25DS2288E.04

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Register Name Address Description

BIN_0_CLASS_ENABLE_0_15 3442 Bin 0 pin to channel association3)
BIN_1_CLASS_ENABLE_0_15 3444 Bin 1 pin to channel association3)
ISINK_BUNDLE 3446 Enable analog bundling for LED channels
PWM_PRESCALER 3448 Configure PWM frequency
LED_OPEN_THR 344C OPEN detection threshold level
LED_OPEN_SEL_0_15 344E Enable open diagnostics for LED channels
LED_SHORT_THR_1 3450 LED short detection threshold 1
LED_SHORT_THR_2 3452 LED short detection threshold 2
LED_SHORT_THR_3 3454 LED short detection threshold 3
LED_SHORT_SEL_0_7 3456 Short threshold selection for LED's 0 to 7
LED_SHORT_SEL_8_15 3458 Short threshold selection for LED's 8 to 15
VS_TOO_LOW 345A Threshold level for Vs too low.
VS_DERATE_RANGE 345C Supply Derating configuration settings
VT_DERATE_START 345E Start temperature threshold for Vt derating
VT_DERATE_STOP 3460 Stop temperature threshold for Vt derating
DERATE_GAIN 3462 VS & VT derate gain settings
IO_CONFIG 3464 Sets the IO polarity, LED channel slew , bin polling method and diag
counter level.
RESET_BEHAVIOR 3466 Reset Behavior setting for number of retries and unresponsive time 4)
LED_ALT_CONFIG 3468 LED alternate configuration
DUTY_DERATE 346A Select Derating on current or dutycle
TEMPSENSE_TYPE 346C Select internal die temperature sense or external thermistor for derating
TEMPSENSE_NTCPTC 346E Choose thermistor type as NTC or PTC
UNUSED_0 3470 Unused register
UNUSED_1 3472 Unused register
UNUSED_2 3474 Unused register
UNUSED_3 3476 Unused register
UNUSED_4 3478 Unused register
UNUSED_5 347A Unused register
UNUSED_6 347C Unused register
UNUSED_7 347E Unused register
RESERVED_0 3BF4 Reserved register5)
RESERVED_1 3BF8 Reserved register5)
OTP_DONE 3BFC Register which indicates that the sequence programming is done 6)
1)
This is for validation using single I²C bus , in case of multiple E52288 devices are being used.
2)
For any channel configured as LED this should be "0" and any channel used for alternate configuration this should be "1"
3)
A Led channel cannot be associated with both the BIN pins
4)
When an internal reset occurs the device clock is not trimmed. Hence the accuracy of the time value is not guaranteed.
5)
This is for internal use
6)
This data is to be written after the user light function has been programmed. After this the sequence information cannot be edited.
OTP can be written in multiple of 4 bytes via I²C

Elmos Semiconductor SE reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor SE Data Sheet CONFIDENTIAL QM No.: 25DS2288E.04

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Table 7.11.1-2: Register COM_DEV_ADDR (3400) Device address value for the communication interface 1)
Bit Name Delivery Access Description
State
15:7 - 0 R
6:5 Group 0 R Bus slave device group
address value 0 is used as broadcast address value
4:0 Address 0 R Address values 1 to 31 are used for explicit device access
1)
This is for validation using single I²C bus , in case of multiple E52288 devices are being used.

Table 7.11.1-3: Register IDAC_REF_SEL_0_15 (3402) IDAC reference (range) selection for driver channels 0 to 15 1)
Bit Name Default Access Description
15:0 IDAC_REF_SEL_0_15 0 R IDAC reference (range) selection for driver channels 0 to 15
Value of 0 selects IDAC upper range Max: 102.3 [mA]
Value of 1 selects IDAC lower range Max: 40 [mA]
1)
For any channel configured as LED this should be "0" and any channel used for alternate configuration this should be "1"

Table 7.11.1-4: Register BIN_GAIN_0 (3404) LED channel 0 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_0 0x0200 R LED channel 0 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-5: Register BIN_GAIN_1 (3406) LED channel 1 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_1 0x200 R LED channel 1 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-6: Register BIN_GAIN_2 (3408) LED channel 2 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_2 0x200 R LED channel 2 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Elmos Semiconductor SE reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor SE Data Sheet CONFIDENTIAL QM No.: 25DS2288E.04

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Table 7.11.1-7: Register BIN_GAIN_3 (340A) LED channel 3 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_3 0x200 R LED channel 3 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-8: Register BIN_GAIN_4 (340C) LED channel 4 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_4 0x200 R LED channel 4 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-9: Register BIN_GAIN_5 (340E) LED channel 5 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_5 0x200 R LED channel 5 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-10: Register BIN_GAIN_6 (3410) LED channel 6 binning gain

Bit Name Default Access Description
15:10 - 0
9:0 BIN_GAIN_6 0x200 R LED channel 6 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-11: Register BIN_GAIN_7 (3412) LED channel 7 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_7 0x200 R LED channel 7 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Elmos Semiconductor SE reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor SE Data Sheet CONFIDENTIAL QM No.: 25DS2288E.04

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Table 7.11.1-12: Register BIN_GAIN_8 (3414) LED channel 8 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_8 0x200 R LED channel 8 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-13: Register BIN_GAIN_9 (3416) LED channel 9 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_9 0x200 R LED channel 9 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-14: Register BIN_GAIN_10 (3418) LED channel 10 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_10 0x200 R LED channel 10 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-15: Register BIN_GAIN_11 (341A) LED channel 11 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_11 0x200 R LED channel 11 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-16: Register BIN_GAIN_12 (341C) LED channel 12 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_12 0x200 R LED channel 12 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Elmos Semiconductor SE reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor SE Data Sheet CONFIDENTIAL QM No.: 25DS2288E.04

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Table 7.11.1-17: Register BIN_GAIN_13 (341E) LED channel 13 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_13 0x200 R LED channel 13 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-18: Register BIN_GAIN_14 (3420) LED channel 14 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_14 0x200 R LED channel 14 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-19: Register BIN_GAIN_15 (3422) LED channel 15 binning gain

Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_GAIN_15 0x200 R LED channel 15 binning gain
gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-20: Register BIN_CLASS_CURRENT (3424) Current sink setting for BIN 0 and BIN 1 pins
Bit Name Default Access Description
15:10 - 0 R
9:0 Bin_pin_current_sink 0x00A0 R Current which will be drawn from external resistor to define voltage on
bin pin current [mA] = (current-sel x 0.1 [mA])
Default : 16mA

Table 7.11.1-21: Register BIN_CLASS_LEVEL_0 (3426) Bin Class 0 evaluation level

Bit Name Default Access Description
15:10 - 0 R
9:0 Bin Class 0 evaluation 0x0024 R Threshold voltage for level 0 [V] = (level x 0.0.02778)
level [Note : 36LSB's/V ]

Table 7.11.1-22: Register BIN_CLASS_LEVEL_1 (3428) Bin Class 1 evaluation level

Bit Name Default Access Description
15:10 - 0 R
9:0 Bin Class 1 evaluation 0x048 R Threshold voltage for level 1 [V] = (level x 0.0.02778)
level [Note : 36LSB's/V ]

Elmos Semiconductor SE reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

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Table 7.11.1-23: Register BIN_CLASS_LEVEL_2 (342A) Bin Class 2 evaluation level

Bit Name Default Access Description
15:10 - 0 R
9:0 Bin Class 2 evaluation 0x06C R Threshold voltage for level 2 [V] = (level x 0.0.02778)
level [Note : 36LSB's/V ]

Table 7.11.1-24: Register BIN_CLASS_LEVEL_3 (342C) Bin Class 3 evaluation level

Bit Name Default Access Description
15:10 - 0 R
9:0 Bin Class 3 evaluation 0x090 R Threshold voltage for level 3 [V] = (level x 0.0.02778)
level [Note : 36LSB's/V ]

Table 7.11.1-25: Register BIN_0_CLASS_GAIN_0 (342E) Selected Gain when BIN 0 pin voltage (Vb) is : Vb <
BIN_CLASS_LEVEL_0
Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_CLASS_GAIN_0 0x200 R gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-26: Register BIN_0_CLASS_GAIN_1 (3430) Selected Gain when BIN 0 pin voltage ( Vb ) is : Vb <
BIN_CLASS_LEVEL_1 & Vb > BIN_CLASS_LEVEL_0
Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_0_CLASS_GAIN_1 0x200 R gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-27: Register BIN_0_CLASS_GAIN_2 (3432) Selected Gain when BIN 0 pin voltage (Vb)is : Vb <
BIN_CLASS_LEVEL_2 & Vb > BIN_CLASS_LEVEL_1
Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_0_CLASS_GAIN_2 0x200 R gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-28: Register BIN_0_CLASS_GAIN_3 (3434) Selected Gain when BIN 0 pin voltage (Vb) is: Vb <
BIN_CLASS_LEVEL_3 & Vb > BIN_CLASS_LEVEL_2
Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_0_CLASS_GAIN_3 0x200 R gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Elmos Semiconductor SE reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor SE Data Sheet CONFIDENTIAL QM No.: 25DS2288E.04

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Table 7.11.1-29: Register BIN_0_CLASS_GAIN_4 (3436) Selected Gain when BIN 0 pin voltage (Vb) is: Vb >
BIN_CLASS_LEVEL_3
Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_0_CLASS_GAIN_4 0x200 R gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-30: Register BIN_1_CLASS_GAIN_0 (3438) Selected Gain when BIN 1 pin voltage (Vb1) is: Vb1 <
BIN_CLASS_LEVEL_0
Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_1_CLASS_GAIN_0 0x200 R gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-31: Register BIN_1_CLASS_GAIN_1 (343A) Selected Gain when BIN 1 pin voltage (Vb1) is: Vb1 <
BIN_CLASS_LEVEL_1 & Vb1 > BIN_CLASS_LEVEL_0
Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_1_CLASS_GAIN_1 0x200 R gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-32: Register BIN_1_CLASS_GAIN_2 (343C) Selected Gain when BIN 1 pin voltage (Vb1) is: Vb1 <
BIN_CLASS_LEVEL_2 & Vb1 > BIN_CLASS_LEVEL_1
Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_1_CLASS_GAIN_2 0x200 R gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-33: Register BIN_1_CLASS_GAIN_3 (343E) Selected Gain when BIN 1 pin voltage (Vb1) is: Vb1 <
BIN_CLASS_LEVEL_3 & Vb1 > BIN_CLASS_LEVEL_2
Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_1_CLASS_GAIN_3 0x200 R gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Elmos Semiconductor SE reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor SE Data Sheet CONFIDENTIAL QM No.: 25DS2288E.04

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Table 7.11.1-34: Register BIN_1_CLASS_GAIN_4 (3440) Selected Gain when BIN 1 pin voltage (Vb1) is: Vb1 >
BIN_CLASS_LEVEL_3
Bit Name Default Access Description
15:10 - 0 R
9:0 BIN_1_CLASS_GAIN_4 0x200 R gain 0.50 = 0x100
gain 1.00 = 0x200
gain 1.99 = 0x3FF

Table 7.11.1-35: Register BIN_0_CLASS_ENABLE_0_15 (3442) Bin 0 pin to channel association1)

Bit Name Default Access Description
15:0 BIN_0_CLASS_ENABLE 0 R Selects which LED pins (0 to 15) are associated to Bin 0 pin.
_0_15 Each position represents the associated channel. For e.g., Bit 15 ->
Channel 15.
A "1" at the bit position associates the channel with the BIN 0 pin.
1)
A Led channel cannot be associated with both the BIN pins

Table 7.11.1-36: Register BIN_1_CLASS_ENABLE_0_15 (3444) Bin 1 pin to channel association1)

Bit Name Default Access Description
15:0 BIN_1_CLASS_ENABLE 0 R Selects which LED pins (0 to 15) are associated to Bin 1 pin.
_0_15 Each position represents the associated channel. For e.g., Bit 15 ->
Channel 15.
A "1" at the bit position associates the channel with the BIN 1 pin.
1)
A Led channel cannot be associated with both the BIN pins

Table 7.11.1-37: Register ISINK_BUNDLE (3446) Enable analog bundling for LED channels
Bit Name Default Access Description
15:8 - 0 R
7 Analog_Bundle_14_15 0 R 0: Not bundled
1: Analog bundled
6 Analog_Bundle_12_13 0 R 0: Not bundled
1: Analog bundled
5 Analog_Bundle_10_11 0 R 0: Not bundled
1: Analog bundled
4 Analog_Bundle_8_9 0 R 0: Not bundled
1: Analog bundled
3 Analog_Bundle_6_7 0 R 0: Not bundled
1: Analog bundled
2 Analog_Bundle_4_5 0 R 0: Not bundled
1: Analog bundled
1 Analog_Bundle_2_3 0 R 0: Not bundled
1: Analog bundled
0 Analog_Bundle_0_1 0 R 0: Not bundled
1: Analog bundled

Elmos Semiconductor SE reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor SE Data Sheet CONFIDENTIAL QM No.: 25DS2288E.04

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Table 7.11.1-38: Register PWM_PRESCALER (3448) Configure PWM frequency

Bit Name Default Access Description
15:7 - 0 R
6:0 PWM_PRESCALER 0x19 R PWM frequency = system clock frequency / (1023 * (PWM_PRESCALER
+ 1))
Example:
8MHz/(1023 * (25+1))= 300.8Hz

Table 7.11.1-39: Register LED_OPEN_THR (344C) OPEN detection threshold level

Bit Name Default Access Description
15:10 - 0 R
9:0 LED_OPEN_THR 0x012 R Open THR [V] = (level x 0.02778)
OPEN error is flagged if the LED pin voltage sample value is smaller than
the selected detection threshold level.
[Note : 36LSB's/V ]

Table 7.11.1-40: Register LED_OPEN_SEL_0_15 (344E) Enable open diagnostics for LED channels
Bit Name Default Access Description
15:0 LED_OPEN_SEL_0_15 0xFFFF R Enable Open diagnostics for LED's
Bit position (X) corresponds to the LED channel. The value of the bit
determines if the channel is enabled for open detection.
0 : Open detection disabled
1 : Open detection enabled

Table 7.11.1-41: Register LED_SHORT_THR_1 (3450) LED short detection threshold 1

Bit Name Default Access Description
15:10 - 0 R
9:0 LED_SHORT_THR_1 0x062 R LED channel SHORT detection threshold level 1
Short THR [V] = (level x 0.02778V)
SHORT error is flagged if the difference between LED supply sample and
LED pin voltage sample is smaller than the detection threshold level.
[Note : 36LSB's/V ]

Table 7.11.1-42: Register LED_SHORT_THR_2 (3452) LED short detection threshold 2

Bit Name Default Access Description
15:10 - 0 R
9:0 LED_SHORT_THR_2 0x0C3 R LED short detection threshold 2
Short THR [V] = (level x 0.02778V)
SHORT error is flagged if the difference between LED supply sample and
LED pin voltage sample is smaller than the detection threshold level.
[Note : 36LSB's/V ]

Elmos Semiconductor SE reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor SE Data Sheet CONFIDENTIAL QM No.: 25DS2288E.04

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Table 7.11.1-43: Register LED_SHORT_THR_3 (3454) LED short detection threshold 3

Bit Name Default Access Description
15:10 - 0 R
9:0 LED_SHORT_THR_3 0x124 R LED short detection threshold 3
Short THR [V] = (level x 0.02778V)
SHORT error is flagged if the difference between LED supply sample and
LED pin voltage sample is smaller than the detection threshold level.
[Note : 36LSB's/V ]

Table 7.11.1-44: Register LED_SHORT_SEL_0_7 (3456) Short threshold selection for LED's 0 to 7
Bit Name Default Access Description
15:14 LED7-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
13:12 LED6-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
11:10 LED5-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
9:8 LED4-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
7:6 LED3-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
5:4 LED2-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
3:2 LED1-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
1:0 LED0-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level

Elmos Semiconductor SE reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor SE Data Sheet CONFIDENTIAL QM No.: 25DS2288E.04

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Table 7.11.1-45: Register LED_SHORT_SEL_8_15 (3458) Short threshold selection for LED's 8 to 15
Bit Name Default Access Description
15:14 LED15-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
13:12 LED14-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
11:10 LED13-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
9:8 LED12-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
7:6 LED11-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
5:4 LED10-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
3:2 LED09-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level
1:0 LED08-Short threshold 0x1 R 00: SHORT detection disabled
sel 01: LED_SHORT_THR_1 level
10: LED_SHORT_THR_2 level
11: LED_SHORT_THR_3 level

Table 7.11.1-46: Register VS_TOO_LOW (345A) Threshold level for Vs too low.
Bit Name Default Access Description
15:10 - 0 R
9:0 VS_TOO_LOW 0 R When the ADC result of VS measurement is smaller than this level value
"VS too low" will be signaled.
Vs too low [V] = (level x 0.04V)

Note: LED open and short evaluation of all LED channels will be dis-
abled
in case of "VS too low".
[Note : 25LSB's/V ]

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Table 7.11.1-47: Register VS_DERATE_RANGE (345C) Supply Derating configuration settings

Bit Name Default Access Description
15:10 - 0 R
9:5 Stop Level 0x14 R LED supply voltage level at which derating stops [V]
0 : derating stop disabled
n (n != 0) : derating stops at LED supply = n V
4:0 Start Level 0x0E R LED supply voltage level at which derating starts [V]
0 : derating disabled
n (n != 0) : derating starts at LED supply = n V

Table 7.11.1-48: Register VT_DERATE_START (345E) Start temperature threshold for Vt derating
Bit Name Default Access Description
15:10 - 0 R
9:0 VT_DERATE_START 0x189 R temperature level at which derating starts [K]
[Default = 120 degrees Celsius]
Note: start = 0 disables temperature derating

Table 7.11.1-49: Register VT_DERATE_STOP (3460) Stop temperature threshold for Vt derating
Bit Name Default Access Description
15:10 - 0 R
9:0 VT_DERATE_STOP 0x193 R Temperature level at which derating stops [K]
[Default = 130 degrees Celsius]

Table 7.11.1-50: Register DERATE_GAIN (3462) VS & VT derate gain settings

Bit Name Default Access Description
15:13 - 0 R
12:5 vt_gain 0x0F R VT derating multiplier in case VT derating is enabled:
if VT <= VTstart : MVT_derate = 1
if VTstart < VT < VTstop : MVT_derate = 1 - (vt_gain * (VT - VTstart) /
256)
This equals a derating by vt_gain * 0.39% of nominal LED current per
Kelvin
if VT >= VTstop : MVT_derate = 1 - (vt_gain * (VTstop - VTstart) / 256)
4:0 vs_gain 0x09 R VS derating multiplier in case VS derating is enabled:
if VS <= VSstart : MVS_derate = 1
if VSstart < VS < VSstop : MVS_derate = 1 - (vs_gain * (VS - VSstart) /
256)
This equals a derating by vs_gain * 0.61% of nominal LED current per
Volt
if VS >= VSstop : MVS_derate = 1 - (vs_gain * (VSstop - VSstart) / 256)

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Table 7.11.1-51: Register IO_CONFIG (3464) Sets the IO polarity, LED channel slew , bin polling method and diag counter
level.
Bit Name Default Access Description
15:11 diag_level 0x0A R DIAG error counter level which has to be reached before asserting a
diagnosis error
Note: If level is 0, the filter will block all diagnosis events received from
the measurement system and it's output will not show a diagnosis
error.
Set level at least to 1 to enable the filter.
10 - 0 R
9:8 Slew_setting 01 R 00 : please see tSINK_RISE_0 and tSINK_FALL_0 parameters
01 : please see tSINK_RISE_1 and tSINK_FALL_1 parameters
10 : please see tSINK_RISE_2 and tSINK_FALL_2 parameters
11 : please see tSINK_RISE_3 and tSINK_FALL_3 parameters
7:6 RESERVED 11 R These have to be set to "11"
5 OE_polarity 1 R 0 : Active Low
1 : Active High
4 ANI_IN_polarity 1 R 0 : Active Low
1 : Active High
3 IN_3_polarity 1 R 0 : Active Low
1 : Active High
2 IN_2_polarity 1 R 0 : Active Low
1 : Active High
1 IN_1_polarity 1 R 0 : Active Low
1 : Active High
0 IN_0_polarity 1 R 0 : Active Low
1 : Active High

Table 7.11.1-52: Register RESET_BEHAVIOR (3466) Reset Behavior setting for number of retries and unresponsive time 1)
Bit Name Default Access Description
15:4 time-sel 0 R Unresponsive time after reset.
0: Reserved, not to be used
Else :
time [ms] = (10 x time-sel)
3:0 retries 0x3 R 0000: Reserved, not to be used

0001: 1 time reset retry, after next reset go to unresponsive time

...
1110: 14 time reset retry, after next reset go to unresponsive time.

1111: reset retry loop, no unresponsive time, no matter how unre-

sponsive_time is configured.
1)
When an internal reset occurs the device clock is not trimmed. Hence the accuracy of the time value is not guaranteed.

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Table 7.11.1-53: Register LED_ALT_CONFIG (3468) LED alternate configuration

Bit Name Default Access Description
15:11 - 0 R
10 ALT_LED10 0 R 0: LIGHT
1: OE
9 ALT_LED9 0 R 0: LIGHT
1: BIN1
8 ALT_LED8 0 R 0: LIGHT
1: BIN0
7 ALT_LED7 0 R 0: LIGHT
1: LNK3
6 ALT_LED6 0 R 0: LIGHT
1: LNK2
5 ALT_LED5 0 R 0: LIGHT
1: LNK1
4 ALT_LED4 0 R 0: LIGHT
1: LNK0
3 ALT_LED3 0 R 0: LIGHT
1: IN_3
2 ALT_LED2 0 R 0: LIGHT
1: IN_2
1 ALT_LED1 0 R 0: LIGHT
1: DIAG_1
0 ALT_LED0 0 R 0: LIGHT
1: DIAG_0

Table 7.11.1-54: Register DUTY_DERATE (346A) Select Derating on current or dutycle

Bit Name Default Access Description
15:1 - 0 R
0 DUTY_DERATE 0 R 0: Derating applied to current
1: Derating applied to dutycycle

Table 7.11.1-55: Register TEMPSENSE_TYPE (346C) Select internal die temperature sense or external thermistor for derating
Bit Name Default Access Description
15:1 - 0 R
0 TEMPSENSE_TYPE 0 R 0 : Internal die temperature based derating
1 : External thermistor based derating

Table 7.11.1-56: Register TEMPSENSE_NTCPTC (346E) Choose thermistor type as NTC or PTC
Bit Name Default Access Description
15:1 - 0 R
0 TEMPSENSE_NTCPTC 0 R 0 : NTC
1 : PTC

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Table 7.11.1-57: Register UNUSED_0 (3470) Unused register

Bit Name Default Access Description
15:0 - 0 R

Table 7.11.1-58: Register UNUSED_1 (3472) Unused register

Bit Name Default Access Description
15:0 - 0 R

Table 7.11.1-59: Register UNUSED_2 (3474) Unused register

Bit Name Default Access Description
15:0 - 0 R

Table 7.11.1-60: Register UNUSED_3 (3476) Unused register

Bit Name Default Access Description
15:0 - 0 R

Table 7.11.1-61: Register UNUSED_4 (3478) Unused register

Bit Name Default Access Description
15:0 - 0 R

Table 7.11.1-62: Register UNUSED_5 (347A) Unused register

Bit Name Default Access Description
15:0 - 0 R

Table 7.11.1-63: Register UNUSED_6 (347C) Unused register

Bit Name Default Access Description
15:0 - 0 R

Table 7.11.1-64: Register UNUSED_7 (347E) Unused register

Bit Name Default Access Description
15:0 - 0 R

Table 7.11.1-65: Register RESERVED_0 (3BF4) Reserved register1)

Bit Name Default Access Description
31:0 RESERVED_0 0xB10CED R The content of this register has to be 0xB10CED55.
55
1)
This is for internal use

Table 7.11.1-66: Register RESERVED_1 (3BF8) Reserved register1)

Bit Name Default Access Description
31:0 - 0 R Do not write any value to this register.
1)
This is for internal use

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Table 7.11.1-67: Register OTP_DONE (3BFC) Register which indicates that the sequence programming is done 1)
Bit Name Default Access Description
31:0 OTP_DONE 0 R Writing 0x00ACCE55 at this location enables the device to start
sequence execution after following reset. This signifies to the firmware
that device is programmed with user data.
1)
This data is to be written after the user light function has been programmed. After this the sequence information cannot be edited.

7.11.2 Status Memory (SRAM)

Table 7.11.2-1: Status registers

Register Name Address Description
RESULT_VLED_0 0x80 LED channel 0 pin voltage 1)

RESULT_VLED_1 0x81 LED channel 1 pin voltage1)

RESULT_VLED_2 0x82 LED channel 2 pin voltage1)
RESULT_VLED_3 0x83 LED channel 3 pin voltage1)
RESULT_VLED_4 0x84 LED channel 4 pin voltage1)
RESULT_VLED_5 0x85 LED channel 5 pin voltage1)
RESULT_VLED_6 0x86 LED channel 6 pin voltage1)
RESULT_VLED_7 0x87 LED channel 7 pin voltage1)
RESULT_VLED_8 0x88 LED channel 8 pin voltage1)
RESULT_VLED_9 0x89 LED channel 9 pin voltage1)
RESULT_VLED_10 0x8A LED channel 10 pin voltage1)
RESULT_VLED_11 0x8B LED channel 11 pin voltage1)
RESULT_VLED_12 0x8C LED channel 12 pin voltage1)
RESULT_VLED_13 0x8D LED channel 13 pin voltage1)
RESULT_VLED_14 0x8E LED channel 14 pin voltage1)
RESULT_VLED_15 0x8F LED channel 15 pin voltage1)
RESULT_VDIF_0 0x90 Difference of VS (Supply) and LED channel 0 pin voltage 1)
RESULT_VDIF_1 0x91 Difference of VS (Supply) and LED channel 1 pin voltage 1)
RESULT_VDIF_2 0x92 Difference of VS (Supply) and LED channel 2 pin voltage 1)
RESULT_VDIF_3 0x93 Difference of VS (Supply) and LED channel 3 pin voltage 1)
RESULT_VDIF_4 0x94 Difference of VS (Supply) and LED channel 4 pin voltage 1)
RESULT_VDIF_5 0x95 Difference of VS (Supply) and LED channel 5 pin voltage 1)
RESULT_VDIF_6 0x96 Difference of VS (Supply) and LED channel 6 pin voltage 1)
RESULT_VDIF_7 0x97 Difference of VS (Supply) and LED channel 7 pin voltage 1)
RESULT_VDIF_8 0x98 Difference of VS (Supply) and LED channel 8 pin voltage 1)
RESULT_VDIF_9 0x99 Difference of VS (Supply) and LED channel 9 pin voltage 1)
RESULT_VDIF_10 0x9A Difference of VS (Supply) and LED channel 10 pin voltage 1)
RESULT_VDIF_11 0x9B Difference of VS (Supply) and LED channel 11 pin voltage 1)
RESULT_VDIF_12 0x9C Difference of VS (Supply) and LED channel 12 pin voltage 1)
RESULT_VDIF_13 0x9D Difference of VS (Supply) and LED channel 13 pin voltage 1)

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Register Name Address Description

RESULT_VDIF_14 0x9E Difference of VS (Supply) and LED channel 14 pin voltage 1)
RESULT_VDIF_15 0x9F Difference of VS (Supply) and LED channel 15 pin voltage 1)
RESULT_VT 0xB0 Device temperature ADC measurement result value
RESULT_VSUP 0xB1 Supply ADC meas result value2)
RESULT_VDD5 0xB2 VDD5 voltage ADC measurement result value 3)
LED_OPEN_0_7 0xB8 LED channels 0 to 7 open detection status value
LED_OPEN_8_15 0xB9 LED channels 8 to 15 open detection status value
LED_SHORT_0_7 0xBA LED channels 0 to 7 short detection status value
LED_SHORT_8_15 0xBB LED channels 8 to 15 short detection status value
EVENT_STATUS 0xBC Device events status value
PININ_STATUS 0xBD Device pin status
DIAG_STATUS 0xBE Diagnostic pin status
PROG_STATUS 0xBF OTP programming status
1)
36LSB's/V
2)
25LSB's/V
3)
142LSB's/V
These registers are only accessible during the device configuration

Table 7.11.2-2: Register RESULT_VLED_0 (0x80) LED channel 0 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_0 NA R LED0 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-3: Register RESULT_VLED_1 (0x81) LED channel 1 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_1 NA R LED1 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-4: Register RESULT_VLED_2 (0x82) LED channel 2 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_2 NA R LED2 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-5: Register RESULT_VLED_3 (0x83) LED channel 3 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_3 NA R LED3 pin voltage ADC measurement result value
1)
36LSB's/V

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Table 7.11.2-6: Register RESULT_VLED_4 (0x84) LED channel 4 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_4 NA R LED4 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-7: Register RESULT_VLED_5 (0x85) LED channel 5 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_5 NA R LED5 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-8: Register RESULT_VLED_6 (0x86) LED channel 6 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_6 NA R LED6 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-9: Register RESULT_VLED_7 (0x87) LED channel 7 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_7 NA R LED7 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-10: Register RESULT_VLED_8 (0x88) LED channel 8 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_8 NA R LED8 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-11: Register RESULT_VLED_9 (0x89) LED channel 9 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_9 NA R LED9 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-12: Register RESULT_VLED_10 (0x8A) LED channel 10 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_10 NA R LED10 pin voltage ADC measurement result value
1)
36LSB's/V

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Table 7.11.2-13: Register RESULT_VLED_11 (0x8B) LED channel 11 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_11 NA R LED11 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-14: Register RESULT_VLED_12 (0x8C) LED channel 12 pin voltage1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_12 NA R LED12 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-15: Register RESULT_VLED_13 (0x8D) LED channel 13 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_13 NA R LED13 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-16: Register RESULT_VLED_14 (0x8E) LED channel 14 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_14 NA R LED14 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-17: Register RESULT_VLED_15 (0x8F) LED channel 15 pin voltage 1)

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_15 NA R LED15 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-18: Register RESULT_VDIF_0 (0x90) Difference of VS (Supply) and LED channel 0 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_0 NA R LED0 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-19: Register RESULT_VDIF_1 (0x91) Difference of VS (Supply) and LED channel 1 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_1 NA R LED1 pin voltage ADC measurement result value
1)
36LSB's/V

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Table 7.11.2-20: Register RESULT_VDIF_2 (0x92) Difference of VS (Supply) and LED channel 2 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VLED_2 NA R LED2 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-21: Register RESULT_VDIF_3 (0x93) Difference of VS (Supply) and LED channel 3 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_3 NA R LED3 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-22: Register RESULT_VDIF_4 (0x94) Difference of VS (Supply) and LED channel 4 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_4 NA R LED4 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-23: Register RESULT_VDIF_5 (0x95) Difference of VS (Supply) and LED channel 5 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_5 NA R LED5 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-24: Register RESULT_VDIF_6 (0x96) Difference of VS (Supply) and LED channel 6 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_6 NA R LED6 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-25: Register RESULT_VDIF_7 (0x97) Difference of VS (Supply) and LED channel 7 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_7 NA R LED7 pin voltage ADC measurement result value
1)
36LSB's/V

Table 7.11.2-26: Register RESULT_VDIF_8 (0x98) Difference of VS (Supply) and LED channel 8 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_8 NA R LED8 pin voltage ADC measurement result value
1)
36LSB's/V

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Table 7.11.2-27: Register RESULT_VDIF_9 (0x99) Difference of VS (Supply) and LED channel 9 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_9 NA R Differential of LED9 pin voltage with respect to VS measured by the
ADC
1)
36LSB's/V

Table 7.11.2-28: Register RESULT_VDIF_10 (0x9A) Difference of VS (Supply) and LED channel 10 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_10 NA R Differential of LED10 pin voltage with respect to VS measured by the
ADC
1)
36LSB's/V

Table 7.11.2-29: Register RESULT_VDIF_11 (0x9B) Difference of VS (Supply) and LED channel 11 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_11 NA R Differential of LED11 pin voltage with respect to VS measured by the
ADC
1)
36LSB's/V

Table 7.11.2-30: Register RESULT_VDIF_12 (0x9C) Difference of VS (Supply) and LED channel 12 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_12 NA R Differential of LED12 pin voltage with respect to VS measured by the
ADC
1)
36LSB's/V

Table 7.11.2-31: Register RESULT_VDIF_13 (0x9D) Difference of VS (Supply) and LED channel 13 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_13 NA R Differential of LED13 pin voltage with respect to VS measured by the
ADC
1)
36LSB's/V

Table 7.11.2-32: Register RESULT_VDIF_14 (0x9E) Difference of VS (Supply) and LED channel 14 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_14 NA R Differential of LED14 pin voltage with respect to VS measured by the
ADC
1)
36LSB's/V

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Table 7.11.2-33: Register RESULT_VDIF_15 (0x9F) Difference of VS (Supply) and LED channel 15 pin voltage 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDIF_15 NA R Differential of LED15 pin voltage with respect to VS measured by the
ADC
1)
36LSB's/V

Table 7.11.2-34: Register RESULT_VT (0xB0) Device temperature ADC measurement result value
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VT NA R VT (temperature) ADC channel result data value in Kelvin Example: T =
25C -> data = 273 + 25 = 298

Table 7.11.2-35: Register RESULT_VSUP (0xB1) Supply ADC meas result value1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VSUP NA R Supply ADC meas result value
1)
25LSB's/V

Table 7.11.2-36: Register RESULT_VDD5 (0xB2) VDD5 voltage ADC measurement result value 1)
Bit Name Default Access Description
15:10 - 0 R Unused
9:0 RESULT_VDD5 NA R VDD5 voltage ADC measurement result value
1)
142LSB's/V

Table 7.11.2-37: Register LED_OPEN_0_7 (0xB8) LED channels 0 to 7 open detection status value
Bit Name Default Access Description
15:8 - 0 R Unused
7:0 LED_OPEN_0_7 NA R bit0:LED channel 0 open detection status value
bit1:LED channel 1 open detection status value
bit2:LED channel 2 open detection status value bit3:LED channel 3 open
detection status value
bit4:LED channel 4 open detection status value
bit5:LED channel 5 open detection status value
bit6:LED channel 6 open detection status value
bit7:LED channel 7 open detection status value

0 means- CH OK 1 means- CH OPEN

Table 7.11.2-38: Register LED_OPEN_8_15 (0xB9) LED channels 8 to 15 open detection status value
Bit Name Default Access Description
15:8 - 0 R Unused
7:0 LED_OPEN_8_15 NA R bit0:LED channel 8 open detection status value
bit1:LED channel 9 open detection status value
bit2:LED channel 10 open detection status value

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Bit Name Default Access Description

bit3:LED channel 11 open detection status value
bit4:LED channel 12 open detection status value
bit5:LED channel 13 open detection status value
bit6:LED channel 14 open detection status value
bit7:LED channel 15 open detection status value

0 means- CH OK 1 means- CH OPEN

Table 7.11.2-39: Register LED_SHORT_0_7 (0xBA) LED channels 0 to 7 short detection status value
Bit Name Default Access Description
15:8 - 0 R Unused
7:0 LED_SHORT_0_7 NA R bit0:LED channel 0 short detection status value
bit1:LED channel 1 short detection status value
bit2:LED channel 2 short detection status value
bit3:LED channel 3 short detection status value
bit4:LED channel 4 short detection status value
bit5:LED channel 5 short detection status value
bit6:LED channel short detection status value
bit7:LED channel short detection status value

0 means- CH OK 1 means- CH SHORT

Table 7.11.2-40: Register LED_SHORT_8_15 (0xBB) LED channels 8 to 15 short detection status value
Bit Name Default Access Description
15:8 - 0 R Unused
7:0 LED_SHORT_8_15 NA R bit0:LED channel 8 short detection status value
bit1:LED channel 9 short detection status value
bit2:LED channel 10 short detection status value
bit3:LED channel 11 short detection status value
bit4:LED channel 12 short detection status value
bit5:LED channel 13 short detection status value
bit6:LED channel 14 short detection status value
bit7:LED channel 15 short detection status value

0 means- CH OK 1 means- CH SHORT

Table 7.11.2-41: Register EVENT_STATUS (0xBC) Device events status value

Bit Name Default Access Description
15:10 - 0 R Unused
9:0 EVENT_STATUS NA R bit0:reset flag
bit1:communication timeout flag
bit2:LED current derating active flag
bit3:VS too low flag
bit4:reserved
bit5:reserved

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Bit Name Default Access Description

bit6:LED short condition flag
bit7:LED open condition flag
bit8:reserved
bit9:communication CRC error flag

Table 7.11.2-42: Register PININ_STATUS (0xBD) Device pin status

Bit Name Default Access Description
15:6 - 0 R Unused
5:0 PININ_STATUS NA R bit0:IN_0 pin state
bit1:IN_1 pin state
bit2:IN_2 pin state
bit3:IN_3 pin state
bit4:ANI_IN pin state
bit5:OE pin state

Table 7.11.2-43: Register DIAG_STATUS (0xBE) Diagnostic pin status

Bit Name Default Access Description
15:4 - 0 R Unused
3:0 DIAG_STATUS NA R bit0:
0:DIAG0 internal (outgoing) state
1 : if an LED of device diagnosis group 0 shows an error
bit1:
0:DIAG1 internal (outgoing) state
1: if an LED of device diagnosis group 0 shows an error
bit2
0:DIAG0 input (incoming) state
1: if DIAG0 pin is active and DIAG0 input path is enabled
bit3
0:DIAG1 input (incoming) state
1: if DIAG0 pin is active and DIAG1 input path is enabled

Table 7.11.2-44: Register PROG_STATUS (0xBF) OTP programming status

Bit Name Default Access Description
15:1 - 0 R Unused
0 PROG_STATUS NA R bit0: programming progress/busy flag
bit1: programming successful/failed flag

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8 Additional Information
The following hardware, software and additional information as well as calculation tools are available on request. Please get
in contact with your responsible key account manager or ask via Elmos Inside Sales. The following documents are available:

• Evaluation kit
• GUI tool for configuring the device
• Calculation tool for dimension'ing external resistors for thermal power distribution
• GUI tool for simulating the device configuration

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9 Typical Applications

Figure 9-1: VS Supplied LEDs , 2 main mode groups with bin and diagnostic
Device and connected LEDs are supplied by VS.
Device is controlled by IN_0 and IN_1 along with ANI_IN pin.
Device is connected with other devices via diagnosis (DIAG) network.
Device can be configured to drive mixed LED structures.

Figure 9-2: VS Supplied LEDs, with 4 inputs and channels extended by linking with another device
Device and connected LEDs are supplied by VS.
Device is controlled by IN_0,IN_1, IN_2_LED2, IN_3_LED3 and ANI_IN pins.
Device is connected with other devices via diagnosis (DIAG) network.
Device can be configured to drive mixed LED structures.

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Figure 9-3: LED Channel Bundling and Current Balancing

Device and connected LEDs are supplied by VS.
Device is controlled by external pins IN_0, IN_1 and ANI_IN.
Device is connected with other devices via diagnosis (DIAG) network.
Device can be configured to drive analog bundled LED to reduce device power dissipation.

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10 Package Reference
The package and land pattern drawing(s) and dimensions in this data sheet may not reflect the most current specifications.
For the latest package outline specification 08SP0640S contact your local Elmos representative.

10.1 Package Outline QFN32L6, 0.6mm - SLP

The E522.88 is available in a Pb free, RoHs compliant, QFN32L6 plastic package according to JEDEC MO-220-K VJJC-2, except
the dimensions of the exposed pad. The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-
020 with a soldering peak temperature of 260°C.

Figure 10.1-1: Package Outline QFN32L6, 0.6mm - SLP

Table 10.1-1: Package Characteristics QFN32L6, 0.6mm - SLP

Description Symbol mm
min typ max
Package height A 0.8 0.9 1
Stand off A1 0.00 0.02 0.05
Thickness of terminal leads, including lead finish A3 0.15 0.2 0.25
Width of terminal leads b 0.25 0.3 0.35
Package length / width D/E 5.85 6.00 6.15
Length /width of exposed pad D2 / E2 3.6 3.75 3.9

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Description Symbol mm
Lead pitch e 0.6 0.65 0.7
Length of terminal for soldering to substrate L 0.35 0.4 0.45
Step cut depth (incl. plating layer) SCD 0.100 0.135 0.170
Step cut width (incl. plating layer) SCW 0.01 0.05 0.075
Number of terminal positions N 32

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10.2 Recommended Land Pattern for QFN32L6, 0.6mm - SLP

The dimensions are intended as an example. They depend mainly on the PCB requirements and the corresponding assembly
process.
The pattern below is based on IPC-7371 and may have alternate designs.

Figure 10.2-1: Land Pattern Outline QFN32L6, 0.6mm option - SLP

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Table 10.2-1: Land Pattern Recommended Characteristics QFN32L6, 0.6mm option - SLP
unit [mm] D8/E8 b3 L3 d1 d2
typ 6.80 0.33 0.85 0.40 0.05

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11 General
11.1 WARNING - Life Support Applications Policy
Elmos Semiconductor SE is continually working to improve the quality and reliability of its products. Nevertheless, semicon-
ductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing Elmos Semiconductor SE products, to observe standards of safety, and to
avoid situations in which malfunction or failure of an Elmos Semiconductor SE Product could cause loss of human life, body
injury or damage to property. In development your designs, please ensure that Elmos Semiconductor SE products are used
within specified operating ranges as set forth in the most recent product specifications.

11.2 General Disclaimer

Information furnished by Elmos Semiconductor SE is believed to be accurate and reliable. However, no responsibility is
assumed by Elmos Semiconductor SE for its use, nor for any infringements of patents or other rights of third parties, which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Elmos Semi-
conductor SE. Elmos Semiconductor SE reserves the right to make changes to this document or the products contained
therein without prior notice, to improve performance, reliability, or manufacturability .

11.3 Application Disclaimer

Circuit diagrams may contain components not manufactured by Elmos Semiconductor SE, which are included as means of
illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily
given. The information in the application examples has been carefully checked and is believed to be entirely reliable. How-
ever, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of Elmos Semiconductor SE or others.

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12 Contact Info
Table 12-1: Contact Information
Headquarters
Elmos Semiconductor SE
Heinrich-Hertz-Str. 1
D-44227 Dortmund (Germany)
Phone: +49(0)231/7549-100
sales-germany@elmos.com
www.elmos.com

Sales and Application Support Office North America

Elmos NA. Inc.
sales-usa@elmos.com

Sales and Application Support Office China

Elmos Semiconductor Technology (Shanghai) Co., Ltd.
sales-china@elmos.com

Sales and Application Support Office Korea

Elmos Korea
sales-korea@elmos.com

Sales and Application Support Office Japan

Elmos Japan K.K.
sales-japan@elmos.com

Sales and Application Support Office Singapore

Elmos Semiconductor Singapore Pte Ltd.
sales-singapore@elmos.com

© Elmos Semiconductor SE, 2023. Reproduction, in part or whole, without the prior written consent of Elmos Semiconductor SE, is prohibited.

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13 Contents
Table of Content
Features...........................................................................................................................................................................................1
Applications......................................................................................................................................................................................1
General Description.........................................................................................................................................................................1
Ordering Information.......................................................................................................................................................................1
Typical Operating Circuit..................................................................................................................................................................1
Functional Diagram..........................................................................................................................................................................2
Pin Configuration QFN32L6..............................................................................................................................................................3
Pin Description QFN32.....................................................................................................................................................................3
1 Functional Safety..........................................................................................................................................................................5
1.1 Technical Safety Requirements...........................................................................................................................................5
2 Absolute Maximum Ratings.........................................................................................................................................................6
3 Recommended Operating Conditions..........................................................................................................................................7
4 Thermal Characteristics................................................................................................................................................................8
5 Electrical Characteristics..............................................................................................................................................................9
5.1 Power Supply and Resets....................................................................................................................................................9
5.1.1 Voltage regulator and references...............................................................................................................................9
5.1.1.1 Voltage Regulator 5V.........................................................................................................................................9
5.1.2 Overtemperature Module..........................................................................................................................................9
5.2 Device Startup.....................................................................................................................................................................9
5.3 Bus Interface......................................................................................................................................................................10
5.3.1 I²C Slave Bus Interface..............................................................................................................................................10
5.4 Input Interface...................................................................................................................................................................10
5.5 Digital IOs...........................................................................................................................................................................11
5.6 PWM System.....................................................................................................................................................................11
5.7 LED Current Sinks..............................................................................................................................................................12
5.7.1 Current sinks.............................................................................................................................................................12
5.8 Measurement System.......................................................................................................................................................13
5.8.1 SAR ADC....................................................................................................................................................................13
6 Typical Operating Characteristics...............................................................................................................................................14
7 Functional Description...............................................................................................................................................................16
7.1 System Introduction..........................................................................................................................................................16
7.2 Device Startup...................................................................................................................................................................17
7.2.1 Device States.............................................................................................................................................................17
7.2.1.1 Device internal error detection and handling..................................................................................................19
7.2.2 Device data handling................................................................................................................................................19
7.3 Bus Interface......................................................................................................................................................................21
7.3.1 I²C Slave Bus Interface..............................................................................................................................................21
7.3.1.1 I²C Interface Features.......................................................................................................................................21
7.3.1.2 I²C Protocol.......................................................................................................................................................21
7.3.1.3 I²C Programming..............................................................................................................................................23
7.3.1.3.1 OTP user data protocol...........................................................................................................................24
7.3.1.3.2 OTP read/write steps..............................................................................................................................25
7.4 Input Interface...................................................................................................................................................................26
7.4.1 Input Sampling..........................................................................................................................................................26
7.4.2 OE PWM Masking.....................................................................................................................................................27
7.5 Digital IOs...........................................................................................................................................................................27
7.6 User Sequence System......................................................................................................................................................28
7.6.1 Sequences.................................................................................................................................................................28
7.6.1.1 Sequence Trigger & mode of operation..........................................................................................................28

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7.6.1.2 Sequence Configuration...................................................................................................................................29

7.6.1.3 Mode Transition...............................................................................................................................................30
7.6.1.4 Sequence Database..........................................................................................................................................32
7.6.2 Instructions...............................................................................................................................................................34
7.6.2.1 SETLNKON Instruction......................................................................................................................................36
7.6.2.2 SETLNKOF Instruction.......................................................................................................................................36
7.6.2.3 WAIT Instruction..............................................................................................................................................37
7.6.2.4 DIM Instruction................................................................................................................................................37
7.6.2.5 DIMX Instruction..............................................................................................................................................38
7.6.2.6 LNKON Instruction............................................................................................................................................39
7.6.2.7 LNKOF Instruction............................................................................................................................................39
7.6.2.8 GOTO Instruction.............................................................................................................................................40
7.6.3 Constraints................................................................................................................................................................40
7.7 PWM System.....................................................................................................................................................................41
7.8 LED Current Sinks..............................................................................................................................................................44
7.8.1 Current sinks.............................................................................................................................................................44
7.8.1.1 Advanced Power Management........................................................................................................................46
7.8.1.2 LED Current Derating.......................................................................................................................................47
7.8.1.3 LED Binning......................................................................................................................................................50
7.8.1.4 Logical view of the current calculation steps...................................................................................................53
7.9 Measurement System.......................................................................................................................................................54
7.9.1 Description................................................................................................................................................................54
7.9.2 SAR ADC....................................................................................................................................................................55
7.9.2.1 Accuracy of Measurement System..................................................................................................................55
7.10 Diagnosis..........................................................................................................................................................................55
7.10.1 Min PWM for diagnostic.........................................................................................................................................57
7.10.2 Diagnostic & SLM logic............................................................................................................................................57
7.11 Configuration and Status Memory..................................................................................................................................59
7.11.1 Configuration Memory (OTP).................................................................................................................................60
7.11.2 Status Memory (SRAM)..........................................................................................................................................76
8 Additional Information...............................................................................................................................................................85
9 Typical Applications....................................................................................................................................................................86
10 Package Reference...................................................................................................................................................................88
10.1 Package Outline QFN32L6, 0.6mm - SLP.........................................................................................................................88
10.2 Recommended Land Pattern for QFN32L6, 0.6mm - SLP...............................................................................................90
11 General.....................................................................................................................................................................................92
11.1 WARNING - Life Support Applications Policy..................................................................................................................92
11.2 General Disclaimer..........................................................................................................................................................92
11.3 Application Disclaimer.....................................................................................................................................................92
12 Contact Info..............................................................................................................................................................................93
13 Contents...................................................................................................................................................................................94
Illustration Index
Figure 6-1: Output Current vs Output Voltage..............................................................................................................................14
Figure 6-2: Accuracy of LED-Current at Room Temperature.........................................................................................................14
Figure 6-3: Current Consumption at Nominal Condition...............................................................................................................14
Figure 6-4: Output Current vs Output Voltage vs Temperature....................................................................................................14
Figure 6-5: Accuracy of 100 mA Current vs Temperature.............................................................................................................14
Figure 6-6: Current Consumption vs. Condition............................................................................................................................14
Figure 6-7: Rise- and Falltime of LED Driver with Slew=0..............................................................................................................15
Figure 6-8: Risetime of LED Driver with activated Slew-Rate........................................................................................................15
Figure 6-9: Rise- and Falltime with Slew=0 vs. Pin-Voltage...........................................................................................................15

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Figure 6-10: Falltime of LED Driver with activated Slew Rate.......................................................................................................15

Figure 7.2.1-1: Device State Diagram............................................................................................................................................17
Figure 7.2.2-1: Data handling structure.........................................................................................................................................20
Figure 7.3.1.2-1: Protocol Components.........................................................................................................................................22
Figure 7.3.1.2-2: Write Frame Format...........................................................................................................................................22
Figure 7.3.1.2-3: Read Frame Format............................................................................................................................................23
Figure 7.3.1.3.1-1: OTP access protocol........................................................................................................................................24
Figure 7.4.1-1: Input Sampling.......................................................................................................................................................26
Figure 7.5-1: Digital IO Pull-up Typical Current Behavior..............................................................................................................27
Figure 7.5-2: Digital IO Pull-down Typical Current Behavior.........................................................................................................28
Figure 7.6.1.3-1: InputSignal behavior...........................................................................................................................................31
Figure 7.6.1.4-1: Sequence database details.................................................................................................................................34
Figure 7.7-1: PWM Generator Structure.......................................................................................................................................41
Figure 7.7-2: Equidistantly Distributed Timing Example...............................................................................................................42
Figure 7.7-3: Combined PWM Channels Example.........................................................................................................................43
Figure 7.8.1-1: ISINK Block Diagram...............................................................................................................................................44
Figure 7.8.1-2: LED Current Sink 40mA Range Behavior...............................................................................................................45
Figure 7.8.1-3: LED Current Sink 100mA Range Behavior.............................................................................................................45
Figure 7.8.1.1-1: Advanced Power Management..........................................................................................................................46
Figure 7.8.1.2-1: LED Supply Voltage Based Derating Example.....................................................................................................47
Figure 7.8.1.2-2: Device Junction Temperature Based Derating Example....................................................................................48
Figure 7.8.1.2-3: Thermistor based derating.................................................................................................................................49
Figure 7.8.1.3-1: Example Bin Class Table......................................................................................................................................51
Figure 7.8.1.3-2: LED Binning Example..........................................................................................................................................52
Figure 7.8.1.4-1: Logical view of the current calculation steps.....................................................................................................53
Figure 7.9.1-1: Measurement System............................................................................................................................................54
Figure 7.9.2.1-1: Accuracy Diagram...............................................................................................................................................55
Figure 7.10-1: Open and Short Diagnosis Filter Behavior..............................................................................................................56
Figure 9-1: VS Supplied LEDs , 2 main mode groups with bin and diagnostic...............................................................................86
Figure 9-2: VS Supplied LEDs, with 4 inputs and channels extended by linking with another device..........................................86
Figure 9-3: LED Channel Bundling and Current Balancing.............................................................................................................87
Figure 10.1-1: Package Outline QFN32L6, 0.6mm - SLP................................................................................................................88
Figure 10.2-1: Land Pattern Outline QFN32L6, 0.6mm option - SLP.............................................................................................90

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