1.
7 MOS Family
It does not use bipolar transistors but just Enhancement-only MOSFETs
There are two kinds of digital MOS circuits.
a) One which uses MOSFETs of one polarity either all of N-type called NMOS or all of P-
type called PMOS but not both on the same chip
b) The other which employs both N-type and P-type MOSFETSs on the same chip. It is
called complementary MOS (CMOS).
The MOS family may be subdivided as under:
Since a FET requires small area, it is possible to fabricate a large number of MOS ciruits
on a single small chip. Gating arrays with thousands of gates and flip-flops are
manufactured in standard containers and are often used in IC memories and
microprocessors.
Followings are some of the advantages of MOS ICs over the bipolar ICs (i.e. TTL, ECL etc.)
1. The MOS IC is relatively simple and inexpensive to fabricate.
2. The MOS device size is small and it consumers less power. Because of the small size,
the MOS ICs can accommodate a much larger number of circuit elements on a single
chip than bipolar IC in the area of large scale integration. This makes them especially
well- suited for complex ICs such as microprocessor, memory chips etc.
3. MOS digital ICs normally do not use the IC resistor elements that take up so much of
the chip area of bipolar ICs.
CMOS logic circuits use both PMOS and NMOS devices in the same circuit. It gives
the advantage of:
drastic decrease in power dissipation (12 nW per gate)
Increase in speed of operation.
It has the lowest power dissipation amongst different logic families.
very high packing density i.e. larger number of circuits can be placed on a single chip.
As a result, it is extensively used in VLSI circuits such as on-chip computers and memory
systems. The recent silicon-onsaphire MOS (SOSMOS) is 2 to 4 times faster than the
21
standard CMOS. Hence, they are being widely used for everything from electronic watches
and calculators to microprocessors.
CMOS handling precautions
CMOS devices are easily damaged by static charges, making them electrically delicate and
hence the following precautions should be taken when working with these devices:
Do not handle CMOS ICs unless your body is connected with a wrist strap to
earth ground.
Tools used to straighten pins should be grounded.
Do not remove or replace a CMOS IC in a socket with power ON
All unused CMOS gate inputs must be connected to an active gate input, V CC or
ground. If allowed to float, an input can take on enough static charges to damage
the IC.
CMOS Subfamilies
The popular CMOS subfamilies include the 4000A, 4000B, 4000UB, 54/74C, 54/74HC,
54/74HCT, 54/74AC and 54/74ACT families. The 4000A CMOS family has been replaced
by its high-voltage versions in the 4000B and 4000UB CMOS families, with the former having
1.7.1 Comparison between TTL and CMOS
(a) Power Consumption: In TTL devices, power is consumed at constant rate. CMOS devices
have a low power consumption since they only consume a significant amount of power
when switching (HIGH to LOW or LOW to HIGH) − very little power is consumed when
the gate is in a stable HIGH or stable LOW state. (Note that among all logic families, ECL
has the highest power consumption.)
(b) Noise Margin: With a supply voltage of VCC = 5 V, TTL devices have a noise margin of
about 0.8 V. CMOS devices have a noise immunity 3c 1 VCC , which is generally higher
than that of TTL devices. (ECL has the lowest noise margin among the logic families.)
(c) Power Supply Voltage: TTL devices should be powered with a supply voltage of
5V±5%. The 4XXX and 74C series of CMOS devices can be powered with voltages
between 3 V and 15 V, while the 74HC and the 74HCT CMOS series can operate with
power supply voltages of 2 V to 6 V. CMOS devices are therefore less sensitive to
power supply voltages.
(d) Speed: TTL devices have higher speed than CMOS devices. TTL devices have an av-
erage propagation delay of about 10 ns, compared to about 50 ns for the 4XXX CMOS
series. (ECL has the highest speed among the logic families − used where speed is the main
22
consideration.)
(e) Fan-Out: CMOS devices have a higher fan-out than TTL devices.
Assignment I
a) What do you understand by the term logic family? What is the significance of the
logic family with reference to digital integrated circuits (ICs).
b) Briefly describe propagation delay, power dissipation, speed–power product, fan-
out and noise margin parameters, with particular reference to their significance as
regards the suitability of the logic family for a given application.
c) What is the totem-pole output stage? What are its advantages?
d) Why is ECL called nonsaturating logic? What is the main advantage accruing from
this? With the help of a relevant circuit schematic, briefly describe the operation of
ECL OR/NOR logic.
e) What is the main criterion for the suitability of a logic family for use in fabricating
LSI and VLSI logic functions? Name any two popular candidates and compare their
features.
f) Why is it not recommended to leave unused logic inputs floating? What should we
do to such inputs in the case of TTL and CMOS logic gates?
g) What special precautions should we observe in handling and using CMOS ICs?
h) Fig. 1.21 shows a CMOS inverter. Explain its operation.
Figure 1.21: CMOS inverter
23
A Brief History of MOS Technology
An MOS (Metal-Oxide-Silicon) structure is created by superimposing several layers of conducting,
insulating, and transistor forming materials. After a series of processing steps, a typical structure might
consists of levels called diffusion, polysilicon, and metal that are separated by insulating layers. CMOS
technology provides two types of transistors, an n-type transistor (n MOS) and a p-type transistor (p
MOS). These are fabricated in silicon by using either negatively doped silicon that is rich in electrons
(negatively charged) or positively doped silicon that is rich in holes (the dual of electrons and positively
charged). For the n-transistor, the structure consists of a section of p-type silicon separating two diffused
areas of n-type silicon. The area separating the n regions is capped with a sandwich consisting of an
insulator and a conducting electrode called the GATE. Similarly, for the p-transistor the structure
consists of a section of n-type silicon separating two p-type diffused areas. The p-transistor also has a
gate electrode. The gate is a control input and it affects the flow of electrical current between the drain
and source. The drain and source may be viewed as two switched terminals.
MOS transistors conduct electrical current by using an applied voltage to move charge from the
source side to the drain side of the device. An MOS transistor is termed a majority-carrier device, in
which the current in a conducting channel between the source and drain is modulated by a voltage
applied to the gate. In an n-type MOS transistor (i.e.,nMOS), the majority carriers are electrons. A
positive voltage applied on the gate with respect to the substrate enhances the number of electrons in
the channel (region immediately under the gate) and hence increases the conductivity of the channel.
The operation of a p-type transistor is analogous to the nMOS transistor, with the exception that the
majority carriers are holes and the voltages are negative with respect to the substrate. The switching
behavior of an MOS device is characterized by threshold voltage, Vt. This is defined as the voltage at
which an MOS device begins to conduct. For gate voltage less than a threshold value, the channel is
cut-off, thus causing a very low drain- to-source current. Those devices that are normally cut-off (i.e.,
non-conducting) with zero gate bias are further classed as enhancement mode devices, whereas those
devices that conduct with zero gate bias are called depletion mode devices.
MOS TRANSISTOR
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
THE MOSFET
THE MOSFET AS A SWITCH
The Metal Oxide Semiconductor Field Effect Transistor (or MOSFET) has proved over the past
15 years to be a very attractive alternative to the BJT. In recent years the MOSFET has become
the preferred technology mainly because manufacturing improvements have advanced further
with FET processes compared to bipolar processes. A cross-section of an N-channel MOSFET is
shown in Fig. (a) below. We shall study the device at this level since this will help in our
understanding of how memory devices operate.
The transistor has four terminals: gate(G); source(S); drain (D); and substrate. Just as in the BJT
the MOSFET is composed of three semiconductor layers. However, for the FET the middle
terminal (the gate) is separated from the P-type semiconductor substrate by a thin gate oxide of
approximately 0.05 µm in thickness. The drain and source are connected to the N-type regions
either side of the gate. The original MOSFETs used a metal gate but now all MOSFETs are
manufactured with a polysilicon gate. One symbol for an N-channel MOSFET is shown in Fig.
(b).
The device operates by using the voltage on the gate to control the current flowing between
source and drain. When 𝑉𝐺𝑆 is zero, application of a positive voltage between the drain and
source (𝑉𝐷𝑆 ) will result in a negligible current flow since the drain to substrate is reverse biased.
When 𝑉𝐺𝑆 is increased in a positive direction electrons are attracted to the gate oxide-
semiconductor interface. When 𝑉𝐵𝑆 is greater than a voltage called the threshold voltage (𝑉𝑇 ) the
P-type material close to the gate oxide changes to N-type and hence the source and drain are
connected together by a very thin channel. Now, when a positive voltage, 𝑉𝐷𝑆 , is applied a
current, 𝐼𝐷𝑆 , will flow from drain to source and the transistor is said to be turned on. The
transistor can be turned on even more by further increasing the gate voltage. This is because
more electrons are attracted to the oxide-semiconductor interface and the depth of the channel
increases. Consequently the resistance between source and drain reduces thus increasing the
current "𝐼𝐷𝑆 "
The current-voltage relationship of the MOS transistor can be modeled approximately with two
equations depending upon the value of 𝑉𝐷𝑆 :
If 𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑇 then the device is in the linear region and
(1)
If 𝑉𝐷𝑆 > 𝑉𝐺𝑆 − 𝑉𝑇 then the device is in the saturation region and
(2)
Where 𝐾 = (𝑊⁄𝐿)𝜇𝐶𝑜𝑥 and 𝑊 and 𝐿 are the width and length of the gate; 𝜇 is the mobility of
carriers (this is a measure of the ease at which a carrier can pass through a semiconductor
material); and 𝐶𝑜𝑥 is the oxide capacitance per unit area of the thin gate oxide region. Physically,
the length of the gate is the distance between the drain and source and is marked as L in Fig. (a)
above, whilst the width 𝑊 is the dimension into the page. Since increasing 𝐾 increases 𝐼𝐷𝑆 then
𝐾 is sometimes referred to as the gain of the transistor even though it has dimensions of 𝜇𝐴𝑉 2 .
These MOS equations thus allow the voltages around the transistor to be calculated.
Let us look at a simple N-channel MOSFET inverter (illustrated in Fig. (a) below) as a means of
illustrating the application of this type of transistor. Here, the transistor can be thought of as a
switch such that when 𝑉𝐺𝑆 is greater than the threshold voltage, 𝑉𝑇 (typically 1 V), then the
transistor will turn on.
Therefore current flows from the supply through the load resistor RL, through the transistor
to ground (𝑉𝑠𝑠 ). As 𝑉𝐺𝑆 increases the current flowing will increase and by choosing the
appropriate value of RE then the voltage at the output will be pulled down towards 0 V. If on the
other hand the gate-source voltage is less than 𝑉𝑇 then the transistor is turned off (i.e. the switch
is open) and the output is pulled up to 𝑉𝑑𝑑 (usually 5 V). This circuit thus operates as an inverter
or a NOT gate. From the bipolar section we can see that the NMOS device operates as an active
pull-down, whilst the resistor RE is called a passive pull-up.
THE MOSFET AS A LOGIC GATE
Apart from the inverter shown above it is possible to use the NMOS transistor to form other
logic gates
Example 1
For the circuits in Fig. (a) and (b) below determine the functions implemented.
Solution
Fig. (a): if either or both of the inputs A and B are low (i.e. less than 𝑉𝑇 ) then one of the NMOS
transistors will be off and hence the output voltage will be pulled up to 𝑉𝑑𝑑 . The only way for the
output to go low is for both A and B to be high. The circuit thus operates as a two-input NAND
gate.
Fig. (b): if either A or B or both are high then the output is pulled to ground. The only way for
the output to go high is for both A and B to be low. The circuit thus operates as a two-input NOR
gate.
This type of logic is called NMOS logic. Historically the first MOS logic that appeared was in
1970 and used PMOS transistors. It was not possible at the time to produce NMOS devices due
to problems with processing. However, in 1975 these problems were remedied and NMOS logic
gates were manufactured taking advantage of the higher mobility of the N-channel carriers in
NMOS transistors compared to the P-channel carriers in PMOS devices. We can see from 𝐾 =
(𝑊⁄𝐿)𝜇𝐶𝑜𝑥 that a higher mobility will result in a higher value of 𝐾 allowing a larger current to
be passed within the same size transistor. In addition the higher the mobility, the faster the
switching speed. In fact N-channel mobility is 2-3 times that of P-channel carriers and hence the
NMOS logic operates at 2-3 times the speed of PMOS.
One problem of the NMOS gates (and for that matter PMOS) is that the upper transistor load is
just acting as a resistor. When the lower transistor is on then current will flow from𝑉𝑑𝑑 to 𝑉𝑠𝑠 and
hence these types of devices consume a moderate amount of power. Consequently in 1978 both
PMOS and NMOS devices were combined on to the same chip to produce the Complementary
Metal Oxide Semiconductor family or CMOS as it is more commonly known.
CMOS Inverter
A CMOS inverter is shown in Fig. below. It consists of one NMOS and one PMOS transistor.
The PMOS device is indicated by the negation sign (i.e. a bubble) on its gate and has a negative
threshold voltage of typically-1V. To turn on a PMOS device we require a voltage, 𝑉𝐺𝑆 , more
negative than-1 V. Notice that the two drains of the two MOS transistors are connected together
and form the output whilst the two gates form the single input. Due to the difference in the
mobilities of the two devices the PMOS device is made with its 𝑊 ⁄𝐿 ratio 2-3 times larger than
the NMOS device. This results in the two transistors having the same value of 𝐾 so that both will
have the same electrical performance.
CMOS Inverter
The circuit operation depends upon the individual gate-source voltages. When the input voltage
is 5 V then the NMOS 𝑉𝐺𝑆 is 5 V and hence this device is on. However, the PMOS 𝑉𝐺𝑆 is 0 V
and so this device is turned off. The output voltage is thus pulled down to 0 V. Now with the
input at 0 V the NMOS 𝑉𝐺𝑆 is 0 V and hence is turned off. However, the PMOS 𝑉𝐺𝑆 is 5V and is
thus turned on (remember a voltage more negative than the threshold voltage is needed to turn
on a PMOS device). With the PMOS device on, the output voltage is pulled up to 𝑉𝑑𝑑 . The
circuit thus operates as an inverter or a NOT gate.
CMOS Design Methodology
The basic CMOS design methodology involves three steps:
n Given the Boolean expression, take its complement
n Design PDN by realizing
l AND terms using series-connected nMOSFETs
l OR terms using parallel-connected nMOSFETs
n Design PUN just reverse (or dual) of the PDN
Design of CMOS Inverter (NOT) Gate
A CMOS inverter is the simplest logic circuit that uses one nMOS and one pMOS
transistor. The nMOS is used in PDN and the pMOS is used in the PUN, as shown
in Figs 6.8(a)–(c).
VDD
A Y pMOS
(a) A Y
A Y nMOS Cload
0 1
1 0
(b) (c)
Fig. (a) Symbol for inverter; (b) truth table of inverter; (c) CMOS
realization of inverter
Operation When input is low, the nMOS is OFF and the pMOS is ON. Hence,
the output is connected to VDD through pMOS. When the input is high, the nMOS
is ON and the pMOS is OFF. Hence, the output is connected to the ground through
nMOS. We can connect a capacitor at the output node as shown in Fig. 6.8 to
represent the load seen by the inverter. The load capacitor is charged to VDD
through pMOS when the input is low and is discharged to the ground through
nMOS when the input is high.
Design of Two-input NAND Gate
To illustrate the design methodology, let us consider a simple example of a two-
input NAND gate design. The two-input NAND function is expressed by
Y = A⋅ B (6.1)
Step 1: Take complement of Y
Y = A⋅ B = A⋅ B (6.2)
Digital CMOS Logic Design 211
Step 2: Design the PDN
In this case, there is only one AND term. So there will be two nMOSFETs in se-
ries, as shown in Fig. 6.9.
Step 3: Design the PUN
In PUN, there will be two pMOSFETs in parallel, as shown in Fig. 6.10.
Fig. Pull-down network Fig. Pull-up network comprising
comprising nMOSFETs pMOSFETs
Now join the PUN and PDN as shown in Fig. 6.11(c). Note that we have realized
Y , rather than Y because the inversion is automatically provided by the nature of
the CMOS circuit operation.
A VDD
Y
B
A B
(a)
A B Y Y
A
0 0 1
0 1 1
1 0 1 B
1 1 0
(b) (c)
Fig. Two-input NAND gate: (a) symbol; (b) truth table; (c) CMOS realization
Operation When A = 0 and B = 0, both the nMOS transistors are OFF and both
pMOS transistors are ON. Hence, the output is connected to VDD and we get logic
high at the output.
When A = 1 and B = 0, the upper nMOS is ON and lower nMOS is OFF. So,
output cannot be connected to the ground. Under this condition, left pMOS is OFF
but right pMOS is ON. Hence, the output is connected to VDD, and we get logic
high at the output.
When A = 0 and B = 1, the upper nMOS is OFF and lower nMOS is ON. So,
output cannot be connected to ground. Under this condition, left pMOS is ON but
right pMOS is OFF. Hence, the output is connected to VDD, and we get logic high
at the output.
When A = 1 and B = 1, both nMOS transistors are ON and both pMOS transis-
tors are OFF. Hence, the output is connected to the ground, and we get logic low at
the output. This is illustrated in Figs 6.11(a) and (c). This proves by the truth table
of NAND gate shown in Fig. 6.11(b).
Design of Two-Input NOR Gate
Let us consider another example of a two-input NOR gate. The two-input NOR
function is expressed by
Y = A+ B (6.3)
Step 1: Take complement of Y
Y = A+ B= A+ B (6.4)
Step 2: Design the PDN
Here, there is only one OR term. Hence, there will be two nMOSFETs connected
in parallel, as shown in Fig. 6.12.
Step 3: Design the PUN
In the PUN, two pMOSFETs will be connected in series, as shown in Fig. 6.13.
Fig. Pull-down network Fig. Pull-up network
comprising nMOSFETs comprising pMOSFETs
Now, join the PUN and PDN as shown in Fig. 6.14(c).
VDD
A
Y
B A
(a)
B
Y
A B Y
A B
0 0 1
0 1 0
1 0 0
1 1 0
(b) (c)
Fig. Two-input NOR gate: (a) symbol; (b) truth table; (c) CMOS realization
Operation When A = 0 and B = 0, both nMOS transistors are OFF and both
pMOS transistors are ON. Hence, the output is connected to VDD and we get logic
high at the output.
When A = 1 and B = 0, the upper pMOS is OFF and lower pMOS is ON. So,
output cannot be connected to the VDD. Under this condition, left nMOS is ON and
right nMOS is OFF. Hence, the output is connected to the ground and we get logic
low at the output.
When A = 0 and B = 1, the upper pMOS is ON and lower pMOS is OFF. So,
output cannot be connected to VDD. Under this condition, left nMOS is OFF and
right nMOS is ON. Hence, the output is connected to the ground and we get logic
low at the output.
When A = 1 and B = 1, both nMOS transistors are ON and both pMOS transis-
tors are OFF. Hence, the output is connected to VDD and we get logic low at the
output. This proves the truth table of NOR gate as shown in Fig. 6.14(b).
Classification of CMOS Digital Logic Circuit
CMOS logic circuits are mainly classified into two categories as follows:
n Combinational logic circuit
n Sequential logic circuit
In the combinational logic circuit, the output is determined by the present logic
inputs. However, in the sequential logic circuit, the output is determined by the
present inputs and past outputs. The examples of combinational logic circuits are
Inverter, NAND gate, NOR gate, multiplexer, demultiplexer, decoder, encoder,
half-adder, full-adder, etc. The examples of sequential logic circuits are flip-flops,
latches, registers, counters, etc.
There are other CMOS design styles as given below:
n CMOS transmission logic
n Complementary pass-transistor logic
n Dynamic CMOS logic
n Domino CMOS logic
n NORA CMOS logic
n Zipper CMOS logic
CMOS logic gates
In CMOS the process of implementing gates is just the same as NMOS except that the
complementary PMOS transistors are added.
Example 2
What function is implemented by the circuits shown in Fig. (a) and (b) below? Although not
shown you should assume that the gate inputs labeled A are connected together (similarly for
gate input B).
Complex gates with CMOS
We can implement many complex combinational functions by connecting together the basic
gates NAND and NOR. However, the result is not an efficient use of transistors. If we introduce
some basic rules we can produce a more efficient CMOS transistor implementation. Consider for
example Fig. (a) below which shows a CMOS circuit which implements the function:
The basic rules are as follows.
1. Concentrate on the NMOS network and note that from the function '𝑓' we can see that
terms OR'd are represented as transistors in parallel and those AND'd are transistors in
series, i.e. A is in parallel with B and C is in parallel with D, whilst these two networks
are in series with each other.
2. To produce the PMOS network we just replace series networks with parallel networks
and parallel with series.
Notice that the number of transistors needed for this function is 8. If we try to implement this
function directly with a NAND/NOT/NOR gate approach the circuit the number of transistors
required would be 16.
CMOS 4000 series Logic
The 4000 series was the first CMOS logic family marketed. It was basically the raw CMOS logic
gates shown in Figs above directly driving external load capacitances or other loads such as TTL
gates. The circuit impedance seen looking back into the output depends upon which transistors
are on or off. For example the two-input NOR gate when the output is low will present a
different output impedance depending upon whether one transistor is on or both are on.
This will result in differing propagation delays and variable output drive capability.
Nevertheless, these devices had very low static power dissipation and with a wide power supply
range of 3-15 V had good noise immunity. The 4000 series was eventually replaced by the
4000B series. This logic family is essentially the original 4000 series but with the outputs double
buffered. This double buffering was quite simply two inverter stages with W/L ratios increasing
at each stage so that the last stage is able to drive the off chip capacitances and other TTL loads
without compromising logic levels. A transistor circuit diagram illustrating the double buffering
(with approximate WIL ratios in microns) is shown in the Fig. below for a two-input NOR gate in
the 4000B series. These devices have a transfer characteristic which changes more abruptly from
one logic level to the other compared to the 4000 series. This is due to the two extra stages at the
output which also results in a much better noise margin. Delays of the order of 50-100ns are
obtainable with this process.
CMOS 74 series logic
Many digital electronic systems were designed at first with the 74 series TTL devices. Since the
4000B series were not pin-for-pin compatible with the TTL devices then replacement with
CMOS was only possible if a complete board redesign was implemented. Hence, in order to take
advantage of the low static power consumption of CMOS logic the TTL series has been
gradually replaced with CMOS equivalents that have the same pin out. These CMOS logic gates
all have outputs that arc double buffered and buffers on the inputs which result in a good noise
margin. A plethora of logic gate families now exist under the 74 CMOS series and we shall look
chronologically at most of these.
74C series
The 74C family was the first CMOS version of the TTL 74XXX series on the market. It used
5µm technology with all outputs double buffered, as in the 4000B series, so that they can drive
other TTL logic gates as well as large off-chip capacitances. This family is now obsolete being
replaced by the HC and HCT versions.
74HC/HCT series
The 74 HC series are fabricated with 3µm CMOS and an increased value of 𝐾. This results in a
shorter propagation delay and increased output drive capability. These devices have a speed
performance similar to the 74LS series but with a greatly reduced power consumption. Unloaded
the output voltages are guaranteed to be within 100mV of the supply. However, under a load
such as driving a TTL input the voltage across the MOS output transistors will increase as
current passes through them. The value of K of the output stage is therefore designed such that
the output voltage will still produce a legal logic 1 or 0.
Although the HC series have the same speed as 74LS parts (see comparison Table above) they
cannot be driven by LS parts. This is because the minimum 𝑉𝐼𝐻 (called 𝑉𝐼𝐻𝑚𝑖𝑛 ) of the HC is
approximately 3.5 V whilst the minimum 𝑉𝑂𝐻 for the LS part is 2.7 V and hence will not be
recognized by the HC series device as a legal logic 1. To avoid this problem the 74HCT was
introduced. This series again uses CMOS technology but the inputs are designed to be TTL input
voltage level compatible i.e. 𝑉𝐼𝐻𝑚𝑖𝑛 = 2.0𝑉 and 𝑉𝐼𝐿𝑚𝑎𝑥 = 0.8𝑉. This is achieved by adjusting
the W/L ratios of the two MOS transistors in the input buffers so as to move the switching point.
In the HC series the PMOS width is 2-3 times that of the NMOS (to compensate for the
difference in mobilities) and the device switches at 𝑉𝑑𝑑 ⁄2. However, for the HCT devices the
NMOS width is approximately ten times that of the PMOS device such that the value of 𝑉𝐼𝐻 is
reduced to 2 V and 𝑉𝐼𝐿 to 0.8 V - compatible with TTL logic levels.
74 AC/ACT series
Continual improvements in CMOS processing have led to the introduction of an improved high-
speed CMOS family called the advanced CMOS logic designated as 74AC and 74ACT. They are
direct replacements for the 74AS and 74ALS series and in some cases the 74F series. These
devices use 1.5µm CMOS technology with a very thin gate oxide of approximately 400Å (1Å =
10−10 𝑚). This results in very high speed CMOS devices with delays of typically 5 ns. This
range of devices also has a very high output current drive of 24 mA (see comparison Table) due
to the higher 𝐾 caused by the thin gate oxide and large W/L ratios at the output. The
ACT series is TTL input voltage level compatible and can be mixed with ALS and AS devices. It
has the added advantage of a very low power consumption as with all CMOS devices. This range
of devices is sometimes referred to as advanced CMOS logic (ACL) by Texas Instruments or
FACT by National and Fairchild.
Undoubtedly more and more logic families will become available to the designer. Currently we
are at the advanced, advanced stage of high-speed CMOS devices, the latest being the 74VHC
series offered by National Semiconductors and the 74AHC/AHCT series marketed by Texas
Instruments. We may well be approaching the limit of CMOS and the use of BiCMOS could
well be the next technology choice on offer to the logic designer.
BiCMOS
The advances in integrated circuit processing have led to ever decreasing transistor sizes.
However, for the same quality process a MOS transistor consumes considerably less space than a
bipolar transistor. Hence CMOS chips are much smaller than bipolar equivalents and hence
internal capacitances are greatly reduced resulting in ever decreasing propagation delays and
manufacturing costs. However, the CMOS families are limited when driving large capacitive
loads such as off-chip capacitances present on data buses, and even oscilloscope leads. The
bipolar transistor is much better at driving these large capacitances since for the same size device
the bipolar transistor has a larger effective 𝐾 than the MOS device. A new technology has
therefore emerged called BiCMOS that combines the best of both worlds, i.e. CMOS and
bipolar. It contains the small CMOS logic gates but in any places where it is necessary to drive
large capacitive loads then the bipolar totem-pole stage is used. A typical BiCMOS inverter is
shown in the Fig. below.
The device operates as follows. When the input is high then the base of T1 is low and is turned
off. Transistor MN is turned on and since MN2 is off then T2 turns on and the output is low.
When the input switches to zero volts then the base of T1 goes high and turns on T1. Since the
base ofT1 is high then MN2 is turned on and the base of T2 is low and is thus turned off and the
output goes high. Notice that when T1 turns off then MN1 provides a base discharge path, whilst
when T2 turns off the base discharge path is provided by MN2. The bipolar output thus allows
large capacitances to be driven, whilst the CMOS part implements the desired function
internally. A typical BiCMOS logic family is the 74BCT series which tends to have devices that
are only for bus driving such as octal buffers and octal latches. These have similar speeds to the
74F family but with greatly reduced power consumption (see comparison Table).
