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Subject Code: KCS302

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B TECH
(SEM-III) THEORY EXAMINATION 2020-21
COMPUTER ORGANIZATION AND ARCHITECTURE
Time: 3 Hours Total Marks: 100
Note: 1. Attempt all Sections. If require any missing data; then choose suitably.

SECTION A
1. Attempt all questions in brief. 2 x 10 = 20
Q no. Question Marks CO
a. Define the term Computer architecture and Computer organization. 2 1
b. What is mean by bus arbitration? List different types of bus arbitration. 2 1
c. Discuss biasing with reference to floating point representation. 2 2
d. What is restoring method in division algorithm? 2 2
e. Define micro operation and micro code. 2 3
f. Write short note on RISC. 2 3
g. Define hit ratio. 2 4
h. What do you mean by page fault? 2 4
i. Explain the term cycle stealing. 2 5
j. What do you mean by vector interrupt? Explain. 2 5

P
SECTION B
0Q

1
2. Attempt any three of the following: 3 x 10 = 30

13
29

Q no. Question Marks CO

2.
a. i. Draw a diagram of bus system using MUX which has four registers of size 4 bits 10 1
0E

24
each.
P2

ii. Evaluate the arithmetic statement.

5.
X = A + B * [C * D + E * (F + G)]
_Q

using a stack organized computer with zero address operation instructions.

.5
17
TU

b. Explain in detail the principle of carry look ahead adder and design 4-bit CLA adder. 10 2
|1

c. Draw the flowchart for instruction cycle with neat diagram and explain. 10 3
AK

d. Discuss 2 D RAM and 2.5D RAM with suitable diagram. 10 4

6
:0

e. Draw and explain the block diagram of typical DMA controller. 10 5

57

SECTION C
:
13

3. Attempt any one part of the following:

Q no. Question Marks CO
1
02

a. An instruction is stored at location 400 with its address field at location 401.The 10 1
address field has the value 500.A processor register R1 contains the number 200.
-2

Evaluate the effective address if the addressing mode of the instruction is (i) direct (ii)
ar

immediate (iii) relative (iv) register indirect (v) index with R1 as index register
M

b. What do you mean by processor organization? Explain various types of processor 10 1

5-

organization.
|1

4. Attempt any one part of the following:

Q no. Question Marks CO
a. Show the systemic multiplication process of (20) X (-19) using Booth’s algorithm 10 2
b. Explain IEEE standard for floating point representation. Represent the number (- 10 2
1460.125)10 in single precision and double precision format.

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Subject Code: KCS302
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5. Attempt any one part of the following:

Q no. Question Marks CO
a. What is a micro program sequencer? With block diagram, explain the working of 10 3
micro program sequencer.
b. Differentiate between hardwired and micro programmed control unit. Explain each 10 3
component of hardwired control unit organization.

6. Attempt any one part of the following:

Q no. Question Marks CO
a. Calculate the page fault for a given string with the help of LRU & FIFO page 10 4
replacement algorithm, Size of frames = 4 and string 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1
236
b. A computer uses RAM chips of 1024*1 capacity. 10 4
i) How many chips are needed & how should their address lines be connected to
provide a memory capacity of 1024*8?
ii) How many chips are needed to provide a memory capacity of 16 KB?

P
7. Attempt any one part of the following: 0Q
Q no. Question Marks CO

1
a. What do you mean by asynchronous data transfer? Explain strobe control and hand 10 5

13
29

shaking mechanism.

2.
0E

b. Discuss the different modes of data transfer. 10 5

24
P2

5.
_Q

.5
17
TU

|1
AK

6
:0
:57
13
1
02
-2
ar
M
5-
|1

2|Page
AKTU_QP20E290QP | 15-Mar-2021 13:57:06 | 117.55.242.131
 Printed Page: 1 of 2
Subject Code: KCS302
0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

BTECH
(SEM III) THEORY EXAMINATION 2021-22
COMPUTER ORGANIZATION AND ARCHITECTURE

Time: 3 Hours Total Marks: 100

Note: Attempt all Sections. If you require any missing data, then choose suitably.

SECTION A
1. Attempt all questions in brief. 2x10 = 20
Qno Questions CO
(a) List and briefly define the main structural components of a computer. CO1
(b) Differentiate between horizontal and vertical microprogramming. CO3
(c) Represent the following conditional control statements by two register CO1
transfer statements with control functions.
If(P=1) then (R1 R2) else if (Q=1) then (R1R3)
(d) Design a 4-bit combinational incremental circuit using four full adder CO2
circuits.
(e) Differentiate between Daisy chaining and centralized parallel CO5
arbitration.
(f) What is the transfer rate of an eight-track magnetic tape whose speed is CO5
120 inches per second and whose density is 1600 bits per inch?
(g) Register A holds the binary values 10011101.What is the register value CO2

1
0

13
after arithmetic shift right? Starting from the initial number 10011101,
29

determine the register value after arithmetic shift left, and state whether

2.
2_

there is an overflow.

24
(h) What is an Associative memory? What are its advantages and CO4
2P

5.
disadvantages?

.5
P2

(i) Differentiate between static RAM and Dynamic RAM. 17 CO4

(j) What are the different types of instruction formats? CO3
Q

|1

SECTION B
6

2. Attempt any three of the following: 10x3 = 30

:4

Qno Questions CO
30

(a) A digital computer has a common bus system for 8 registers of 16 bit CO1
:

each. The bus is constructed using multiplexers.

13

I. How many select input are there in each multiplexer?

II. What is the size of multiplexers needed?
2
02

III. How many multiplexers are there in the bus?

(b) Explain destination-initiated transfer using handshaking method. CO5
r-2

(c) Explain 2-bit by 2-bit Array multiplier. Draw the flowchart for divide CO2
Ap

operation of two numbers in signed magnitude form.

(d) A digital computer has a memory unit of 64K X 16 and a cache CO4
2-

memory of 1K words. The cache uses direct mapping with a block size
|0

of four words.
I. How many bits are there in the tag, index, block, and word
fields of the address format?
II. How many bits are there in each word of cache, and how
they are divided into functions? Include a valid bit.
III. How many blocks can the cache accommodate?
(e) Explain with neat diagram, the address selection for control memory. CO3

QP22P2_290 | 02-Apr-2022 13:30:46 | 117.55.242.131

 Printed Page: 2 of 2
Subject Code: KCS302
0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

BTECH
(SEM III) THEORY EXAMINATION 2021-22
COMPUTER ORGANIZATION AND ARCHITECTURE

SECTION C
3. Attempt any one part of the following: 10x1 = 10
Qno Questions CO
(a) A binary floating-point number has seven bits for a biased exponent. CO2
The constant used for the bias is 64.
I. List the biased representation of all exponents from -64 to +63.
II. Show that after addition of two biased exponents, it is necessary
to subtract 64 in order to have a biased exponent’s sum.
III. Show that after subtraction of two biased exponents, it is
necessary to add 64 in order to have a biased exponent’s
difference.
(b) Show the multiplication process using Booth algorithm, when the CO2
following binary numbers, (+13) x (-15) are multiplied.

4. Attempt any one part of the following: 10x1 = 10

Qno Questions CO
(a) Draw a diagram of a Bus system in which it uses 3 state buffers and a CO1
decoder instead of the multiplexers.

1
0

13
(b) Explain in detail multiple bus organization with the help of a diagram. CO1
29

2.
2_

5. Attempt any one part of the following: 10x1 = 10

24
Qno Questions CO
2P

5.
(a) The logical address space in a computer system consists of 128 CO4

.5
P2

segments. Each segment can have up to 32 pages of 4K words each.

17
Physical memory consists of 4K blocks of 4K words each. Formulate
Q

the logical and physical address formats.

|1

(b) How is the Virtual address mapped into physical address? What are the CO4
6

different methods of writing into cache?

:4
30

6. Attempt any one part of the following: 10x1 = 10

:

Qno Questions CO
13

(a) Explain how the computer buses can be used to communicate with CO5
2

memory and I/O. Also draw the block diagram for CPU-IOP
02

communication.
r-2

(b) What are the different methods of asynchronous data transfer? Explain CO5
in detail.
Ap

7. Attempt any one part of the following: 10x1 = 10

2-

Qno Questions CO
|0

(a) Write a program to evaluate arithmetic expression using stack CO3

organized computer with 0-address instructions.
X = (A-B) * (((C - D * E) / F) / G)
(b) List the differences between hardwired and micro programmed control CO3
in tabular format. Write the sequence of control steps for the following
instruction for single bus architecture.
R1  R2 * (R3)

QP22P2_290 | 02-Apr-2022 13:30:46 | 117.55.242.131

Printed Pages:02 Sub Code: KCS-302
Paper Id: 233647 Roll No.

B. TECH.
(SEM III) THEORY EXAMINATION 2022-23
COMPUTER ORGANIZATION AND ARCHITECTURE
Time: 3 Hours Total Marks: 100
Note: Attempt all Sections. If require any missing data; then choose suitably.

SECTION A

1. Attempt all questions in brief. 2 x 10 = 20

(a) List the steps involved in an instruction cycle.

(b) How memory read and write operations are performed in computer system?
(c) Define bus and memory transfer?
(d) Define HIT and MISS ratio in memory with an example.
(e) Define instruction cycle.
(f) Differentiate between RISC and CISC.
(g) List the difference between static RAM and dynamic RAM.
(h) Define Virtual memory.

2
90

13
(i) List down the functions performed by an Input/Output unit.
_2

(j) Why does the DMA get priority over CPU when both request memory transfer?

2.
P2

24
SECTION B

5.
3D

.5
2. Attempt any three of the following: 10x3=30
P2

17
Q

|1
(a) Explain functional units of computer system in detail.
(b) Explain IEEE-754 standard for floating point representation. Express (314.175) 10
7

in all the IEEE-754 models.

:1

(c) Explain the concept of pipelining and also explain types of pipelining.
28

(d) Consider a cache consisting of 256 blocks of 16 words each for a total of 4096
:
13

words and assume that the main memory is addressable by a 16 bits address and
it consists of 4K blocks. How many bits are there in each of TAG, SET, WORD
3

field for 2-way set associative technique?

02

(e) Define interrupt. Also discuss different types of interrupt.

-2
04

SECTION C
1-
|0

3. Attempt any one part of the following: 10x1=10

(a) Explain about stack organization used in processors. What do you understand by
register stack?
(b) What is an effective address? How it is calculated in different types of addressing
modes? Explain.

QP23DP2_290 | 01-04-2023 13:28:17 | 117.55.242.132

4. Attempt any one part of the following: 10x1=10

(a) Describe the derivation procedure of look ahead carry adder by an example with
the help of block diagram.
(b) Show the systematic multiplication process of (-15) × (-16) using Booth’s
Algorithm.

5. Attempt any one part of the following: 10x1=10

(a) Write a program to evaluate the arithmetic statement.

P = ((X − 𝑌 + 𝑍) ∗ (A ^ B))/( C ^ D ∗ E)
By using (i) Two address instructions (ii) One address instructions (iii) Zero address
instructions
(b) What are the differences between hardwired and micro-programmed control unit?

6. Attempt any one part of the following: 10x1=10

(a) Discuss the Memory Hierarchy in computer system with regard to Speed, Size
and Cost.
(b) Write a short notes on magnetic disk, magnetic tape and optical disk.

2
90

13
_2

2.
7. Attempt any one part of the following: 10x1=10
P2

24
(a) With a neat schematic diagram, explain about DMA controller and its mode of

5.
3D

data transfer.

.5
P2

(b) Discuss the design of a typical input or output interface.

17
Q

|1
7
:1
: 28
13
3
02
-2
04
1-
|0

QP23DP2_290 | 01-04-2023 13:28:17 | 117.55.242.132

 Printed Page: 1 of 2
Subject Code: BCS302
0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

BTECH
(SEM III) THEORY EXAMINATION 2023-24
COMPUTER ORGANIZATION AND ARCHITECTURE
TIME: 3HRS M.MARKS: 70

Note: 1. Attempt all sections. If require any missing data; then choose suitably.
SECTION A

1. Attempt all questions in brief.

Q no. Question Marks
a. What are the different types of Buses used in computer architecture? 2
b. Name the different types of multipliers. 2
c. What are the different phases of an instruction cycle? 2
d. How does control unit of a computer works? 2
e. Write a short not on locality of reference. 2
f. Define 2 ½ D memory organization. 2
g. In what way synchronous and asynchronous serial modes of data transfer differ? 2
SECTION B

2. Attempt any three of the following:

a. What is meant by the term BUS arbitration? Why is it needed? How can bus 7
90

2
arbitration be implemented in Daisy changing scheme?

13
_2

b. Show the multiplication process using Booth’s algorithm when the following 7

2.
numbers are multiplied: -
P2

24
(-12) *(-18).
4D

c. What is pipelining? What are the different stages of pipelining? Explain in detail. 7

5.
d. Give classification of memory based on the method of access. Also discuss 7
.5
P2

construction and working of magnetic disk and various components of disk access
17
Q

time.
|1

e. What are the basic differences between interrupt initiated I/O and programmed 7
I/O? Explain in detail.
5 6

SECTION C
2:

3. Attempt any one part of the following:

:2
13

a. What do you mean by processor organization? Explain various types of processor 7

organization with suitable example.
4

b. Differentiate between Memory stack and register stack. 7

02

4. Attempt any one part of the following:

-2

a. Explain in detail the principle of carry looks ahead adder and design 4-bit CLA 7
03

adder.
1-

b. Represent the following decimal number in IEEE standard floating-point format in 7

|2

a single precision method (32 bit) representation method.

(i) (85.125)10
(ii) (-307.1875)10
5. Attempt any one part of the following:
a. Explain the different cycles of an instruction execution. 7
b. Differentiate between hardwired and micro programmed control unit. Explain each 7
component of hardwired control unit organization.

1|Page
QP24DP2_290 | 21-03-2024 13:22:56 | 117.55.242.132
 Printed Page: 2 of 2
Subject Code: BCS302
0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

BTECH
(SEM III) THEORY EXAMINATION 2023-24
COMPUTER ORGANIZATION AND ARCHITECTURE
TIME: 3HRS M.MARKS: 70

6. Attempt any one part of the following:

a. Consider a cache (M1) and memory (M2) hierarchy with following characteristics: 7
-
M1 : 16K word, 50 ns Access time
M2 : 1M word, 400 ns Access time
Assume 8-word cache blocks and set size 256 words with set associative mapping.
(i) Show and explain the mapping between M2 and M1.
(ii) Calculate the effective memory access time with cache hit ratio=0.95.
b. Explain the direct mapping technique. Consider a digital computer has a memory 7
unit of 64k*16 and cache memory of 1k words. The cache uses direct mapping with
4 block size of four words.
(i) How many bits are there in the tag, block and word fields of the address
format?
(ii) How many blocks can the cache accommodate?
7. Attempt any one part of the following: 7x1=7
a. What do you mean by asynchronous data transfer? Explain strobe control and 7
90

2
handshaking mechanism.

13
_2

b. Explain the various modes of data transfer and discuss direct memory access mode 7

2.
in detail. Also explain how DMA is superior to other modes.
P2

24
4D

5.
.5
P2

17
Q

|1
56
2:
:2
13
4
02
-2
03
1-
|2

2|Page
QP24DP2_290 | 21-03-2024 13:22:56 | 117.55.242.132