SEVDGITAL CIRCUITS

BCD weighted DAC. The soOurce -b V,so tha

This expressäon i eqzal to the output-voitage of a 2-decade
is connected to -V
value o the attenuating resistor can be found out as follows :
K=10
R
W or, 1 + 15r 10
SR
or. r 48R
Ww If three 4-bit weighted resistor DACS are SW
resistors r, and
connected using attenuating

I, as shown in Fig. 17.14. Then, can be eingting

Rasster

15r,
SR -100andr,
caleulate using 1+ can be
Most
for the
signicant calculated as before. Therefore,
decode
r, - 4.8R and r,
of BCD DAC cascaded DAC in Fig.17.14,
oftree deccder
Fe 17.14 Cascoding =52.2R.

Difficulties in the Weighted Resistor DACs:The major disadvantage of the weighted

is concemed with the wide-range of resistor
values necessary for a reasonabie
restor DAC
using IC technology,to have all the resistors with
size converter. It isalso difficult to fabricate The equivalent ci
For example, a 4bit DAC with o.1 aceurNg for the resistor connected to the Op-ar
same preision. output of

the MSB would require 0.1/2 =

0.0125% for the resistor in LSB position. Another problem
for the weighted resistor DAC is that the current through
R is largest and that through the
Thus, the thermal ratings of the resistors depends on their positional
resistor SR is the smallest.
thermal increases as the numnber of the
weights, and the spread of the
values of the rating

resistor inreases in the weighted resistor DAC.

DAC used which will be discussed next.
To ovecomethese difficulties a new tvpe of is

uses R-2R ladder network.

This tvpe of DAC resistor

R-2R Ladder NetworkDAC

this tvpe of converter, it is essential to be
Ia order to understand the operation of

R-2R ladder network as shown

familiar with the basic operation of the
in Fig.17.15. In this To the left o
instead of
two values of resistors R and 2R for each input-bit we look back te
arangementthere are only DAC.
lf

a new resistor for each bit as we saw in case of binary weighted

resistor-type
line AA',then by
ratio (R:2R = 1:2) it is much easier to fabricate resistor
we may
Because of this small resistance theorem re
the wide spread resistor

,
tolerance compared to the left of
IC technology with much better Grcuit to
t
using the Switches
DAC. Fig.17.15 shows that the electronic series combinatio
values in binary weighted resistor-type
bits b,y
voltages of the input-binary 2R) and voltage so
SW are controled by logic-level
(SPDT)sW,Sw,, the resistor 2R to
Logic-0 then the switch sw, connects
b.,b- When the bit b, is at
voltage -V, when b, is at Logic
shown

connected
in Fig.17.17(a

to the n
is connected to the reference
ground and the same resistor
redrawn in Fig.17.16. replacing the switch sw, by the voltage scalled terminating
L The crcuit in Fig.17.15 is
 DATACONVERTERS S79

eighted DAC The source -b, V so that when b,-0 and 1, the resistor 2R of the switch sw, is grounded and
is connected to -V, respectively.

10 N RN, W

26
resistor DACS are
Sw Sw, SW SW.
ng resistors r, and
4. Thenr, can be. Termingting
Resister

100 andr,can be

nerefore, for the

4, r, - 4.8R and r,
b(LSB) b, b,(MS8
b
geof the weighted
v for a reasonable
Fig. 17.15:R-2R Ladder-type DAC.
the resistors with
connected to
The equivalent circuit in Fig.17.16 can be analvzed to obtain the output-voltage V,at the
stor

Another problem
outputof the Op-amp by using the Thevenin's theorem in the following way :

that through the A

n their DOsitional

ne number of the Na R R N, RN
e discussed next. 2R

b
|b,V,

A'
B
iessential to be Fig. 17.16:Equivdlent circuit for the circuit in Fig.17.15.

Fig.17.15. In this

of
TU the left of the dotted line AA
ut-bit instead
we look back to the left of the dotted
If
istor-type DAC.
abricate resistor
lineAA, then by applying Thevenin's R

theorem we may replace the portion of w

spread resistor
circuit to the left of the dotted line AA' by 2R 2R
ctronic switches
a series combination of resistor R (2R I 2
It-binary bits by
2R) and voltage source b,V/2. This b,,
is A
e resistor 2R to A'

shown in Fig.17.17(a). Here the 2R resistor

n b, is at Logic
connected to the node N, and ground
by the voltage
iscalled terminating resistor. Fig. 17.17() :Equivalent circuit for theportion left to AA.
880 VDIGITAL CIRCUITS

Grauit is show
To the left of the dotted line BB
If back to the left of the dotted line in Fig 17.16 ther by applying Thevenin's
we look BB
is shown ín Fig 17.17(b).The circuit is
theorem one mav get an equivalent círcuiít whích

to a resistor R in series with a voltage source DoV2De

equivalent 2

A
B

29

cirauit for the postion left ko BE,

Fig. 17.17(b)Equivalent IÉ the pol
tesistors is
To the ieftof the dotted line CC The abov

to the circuit left of the dotted líne CC, then the decimal val
When Thevenins theorem is applied
source
to a resistor R (=2R |12R) in series with a voltage The total
circuit becomesequivalent
Following a
ladder DAC
8 4 2
To find-out

This is shown in Fig.17.17(c).

R
C

Due to
CC
Fig. 17.17c) Equivolentcircuit
for the portion let to
ground p
be applied several times to the lader upto
the
node is L
the Thevenin theorem
carn
In this way is connected.The net equivalent
the Op-armp
inverting ínput of
dotted line EE' where the DG Cartaits
 DATA CONVERTERS 881

Op-amp =
current at the inverting input of the
is.I,
crcuit is shown in Fig.,17.17(d). The
voltage V,can now be written as
(Vgo)/R and the analog-output
Thevenin's
g
is
he circuit
R

2N

circuit for R-2Rlader to EE'

left
Fig.17.17d) :Equivalent

RVEQ=
R R2N -[b,+2b,+22
b,? +.+2n-2b,+2n-b
RV (decimal value of the binary input) RVD
2NR 2NR
current through the
of the flow of
If the polarity of V, is reversed then the direction

resistors is reversed and hence the sign of V, would be negative.

the analog-output voltage V, is proportional to the

The above expression shows that
CC,then the and R are constarnt.
decimal value (D) of the binary input becatuse R V

Source branches of R-2R ladder network.

The total current I, is divided among the different

For simplicity we assume a 4-bit R-2R

will give us the branch currents.
Following analysis
with the reference voltage shown in this figure.
ladder DAC as
of
shown in Fig.17.18 polarity

To find-out the current components I,, I,, and I, we may do the following analysis.
I,
R R R N,
No

2R
2R

b,V, b,V, b,v,

b,V
(LSB) (MSB)

Fig. 17.18:4-bit R-2R ladder DAC.

at
Due to virtual grounding effect of the Op-amp,the node N, of the ladder network is

ground potential and hence the current I flowing through the resistor 2R connected to this

ader upto the = Vg/R.

node is I, - b,V /2R. - b,/2,where I

net equivaient
DG Cicuits (111-111
882 DIGITALCIRCUITS

From Fig. 17.21

This current contributes completely to the net current Ir As b, is the most signíficant
bit in the 4-bit binary-input, then for, b, = 1 the contribution from the most
significant bit is

I,towards L

To get the contribution only from the bit b,, we assume b, =b, =b,=0 and b, =1. The

equivalent circuit of the R-2R ladder under this condition is shown in Fig.17.19.
N, R
2R

N, RN, R NA X RN, R N, R
N,
2
W

NZNI R
2R

b,V, b,v,

A
A
(b
(c

Fig. 17:19

From the Fig. 17.19.(c) we get

b, VR 3b,Vg
1, = 2R + (2RIIR) 8R

From Fig.17.19.(b)we get

IN;N 2R
This current In,
R and I, = NNgt
Ng through the re

or, NNg
Ib, Tofind out the
or,
4
where = V/R I
b, =0 and bo =

1.
Fig.17.21(e) giv
Ib,
and
8
For the bit b, the contribution of current towards I, is IN-N, It may be noted that the

contribution towards the net current I, by the bit b, is half of I3

To find out the contribution of bit b, towards the current L, we assumeb,= b, =b,-0 and
b,-1. The equivalent circuit for this input is shown in Fig.17.20.
From Fig 17.21
From Fig. 17.20(c) we get

b;Vg 11b;V
1= 32R or,

2R +2RI5R3
 DATA CONVERTERS 883

most significant From Fig. 17.20.(b) we get Iy,N which is a part of current I, flowing to the node N,, as
significant bit is

2R I,63b, Ve 3b,1
2R + [R +(RIl2R)] | 11 16R 16
D and b,=1. The
5.17.19.
R

2R N RN, R N, R N, R N N,

NN2
2R

b,V,

I N, W2R

b,Ve

(c)

Fig. 17.20

This current IN,Na is again splitted at the node N, and the current which flows to the node
N, through the resistor R is

2R 2lNNabl
R+2R 3 8
To find out the contribution of the bit b towards the net current I,we assume b, =b,=
b, = and
0 b =1. The equivalent circuit for the situation is shown in Fig.l7.21.

Fig.17.21(e) gives us

b,Vg 43b,Vg
the
128R
be noted that 2R +

e b,-b,-b,-0 and 2R 2R
From Fig 17.21 (c) we get, I, =Ih+ INN, and NoNI
10R 21R
R+
11
11

2R 2R 22b,I
or, INN, =
or,
2R + 21R l
2R + 11 21R -6/22
|43 128
11
884 V DIGITALCIRCUITS

A fraction of this current which flows towards the node N, is

To overa
2R
N,N, =NgN; 2R+2R+2RIRI connected

R-2R ladde:

input of the

No R
NgNs
R N,
W R N, N

'NgN
N,
P
Op-amp.Th
right of N,
'N,Ng
2R 2R is 2R (Fig.17

2RR2
N

I 21R
(b) 21R

2R
R N, N, 11 Ww
No
W W
2R
2R
2R

b,e

I (e

Fig. 17.21

A fraction of this current which flows towards the node N, is

2R b!
R+2R 16

This amount of current is the contribution by the bit b, towards the total current I,.

by the
But the sour
Thus, from the derived expressions, the currents contributed to the net current I,
But the impedance seen N,. As the switd
four input bits b, b,, b, arnd b, are according to their weights.
by
the source
each input-bit is different which is evident from the current expression of l, l, h and , V/3R.
V,

No R
W R

W W
2R
R
To get the
invérting-input
co

W -Vo
finding the cont
be obtained
2R
,12R by u

Consider the

(LSB)
b,V, from the switche
into two halves
because the resist

N,, the incoming

Fig.17.22,: 3-Bit R-2R ladder DAC with two terminating resistors. because the resista
from it towards n:
 885
DATA CONVERTERS
to be
of value
2R is requireda 3-bit
resistor for
Fig.17.22
one extra
terminating
This is shown in atthe inverting
ths preblem significant position. 2R connected of the
To overcome node of most terminating
resistance
grounding
effect
at the of the extra virtual to the
end to the looking
connected
DAC. The grounded
due 2R (Fig.17.23); is
R-2R ladder b,V, the resistance
the Op-amp
is effectively
the left
of N the resistance
node N, towards
input of to
looking
also looking down
Op-amp. Therefore, is 2R and
right of
Ny the resistance
is 2R (Fig. 17.23.(b)). 2R

A
P
Now
Ng
R

W 2R
W 2R

2
2R 2R

2R
2R
2F
2R b,e
2R

(b)
R
A
2R
(o)
b, 2R

2R

(c)

circuit for b = 1, b, =b,0

17.23Equivalent node
true for any
Fig.
This is
of value 3R [Fig.17.23(c)].
from
current source b,V, looks
a resistance
3R,hence the current drawn
If.
But

,
the
voltage V,faces a resistance
connected to that
bit- is
rent I,by the
Asthe switched
reference 2R
N,. b, through the resistance
dance seen by source V, from
the bit position
the
the
I, and I, input-bit towards
V/3R. the individual binary du to After
of current purpose.
To get the contribution at a time for this
of the Op-amp
we assume one high input-bit at the inverting input
can
inverting-input total current I,
for each bit the
separately
finding the contribution
theorem.
by using the superposition node N,
be obtained I, flowing to the
where b, -1, b, = b, =0. The current
Consider the Fig.17.24(a) b, Vp) is divided
(i.e. equivalent voltage
voltage V by the bit b,
from the switched reference of No This happens
and Iy2 flowing right
flowing left of the node N,
into two halves-I,y2 is the same.At the node
the node N, in these two directions
because the resistance seen by
again divided into two equal
halves
N,, the incoming current
I/2 from the node N, is 2R seen
to ground is 2R and it is also
because the resistance seen from the node N, down
N, through 2R and I/4
I/4 goes down to ground from
from it towards right. So, a current
S86 DIGITAL CIRCUITS

goes towards the node N,. The current I/4 at N, from N,is divided equally at N, in two
But I, =I, -,=
Therefore, the tota
halves. Iy/8 goes towards ground from N, through 2R and the other half goes towards the

I, = b,V1
Rp 3R

WW R
N

R
N,
W8
2R
W

(2)3R
2R 2R
In general for

b, tnb,=0
b,=1, b =b,=0

Fig. 17.24(a)

inverting- input of Op-amp. Therefore, the current contribution due to Logic-1 state of the

I/S of the Op-amp. Similarly, if b,= 1, bo=b,= 0, then using Therefore, the
bit b, is equal to to the input

Fig.17.24(b) we get a currentI,/4 at the inverting -input of the Op-amp and for b, = 1, b,=b, =0

R,

N
4
N

W
W W

2R 2R The sign of th
W Virtual

b, V,
ground
17.4.1 Sw
The R-2R ladc
b,=b, -0, b,=)
From the Fig.17.2

Fig. 17.24(b) VR is effectively

Switch isgrounc
and using the Fig. 17.24(c) the contributed current at the Op-amp is I,/2. The net current I,
becomes slower.
at the input of the Op-amp is
0 and Vg or -V;
I, = 1J8 + I,/4 + I/2 Currents can be s
current Switchin
R

DACS the binar

N summing them i

W Wh
R Fig.17.25 shor
w
R 2R

2 2R with that in Fig.

Vitual
voltage source V
b,ve
ground
Ladder DAC. In

current distribut
b,=1, b, =0, b, =0 in the inverted
l.
Fig.17.24(c) delay. Therefore,
 |DATACONVERTERS y 887

ly at
Des
N, in two
towards the
But ,
Therefore, the
=I,-L-V/3R, as each
total
input-bit sees equal resistance of value
curent for this 3-bit R-2R type is - DAC
3R (see Fig.17.23c).

3R 3R 3R

V Vg (decimal value equivaient to 3 bit binary)

(2b, + 2'b,+ 2°b,) =
(2)3R (2)3R
In generalfor on N-bit R-2R DAC of this kind we may write

[2n-'b+2n-"b2t + b,2 + 20b,]

(2" )3R

Vg(decimal value input equivalent to n binary - bits)

C-1 state of the (2)3R
-0, then using
Therefore, the analog-voltage output V, from the Op-amp is

',=1,b,=b,= 0
V;RE (Digital Input)
2"(3R)

V,(Digi'alInput)
2
,when R,= 3R.
The sign of this output voltage can be changed to positive if V, is negative.

1741| Switched Current DAC

The R-2R ladder type DAC so far discussed can also be called switched voltage DAC.
From the Fig. 17.25 it may be noted that when a binary-input goes high, the reference voltage
V, is effectively switched into the circuit and for logic-low input of the binary-input the

2 net current L switch is grounded.Due to the presence of the stray capacitance the voltage switching
becomesslower. This happens because the switching occurs between two unequal potential
0 and V or -Vg Because of the technology used to construct integrated-circuit DACs,
currents can be switched in and out of a circuít faster than voltages can. For this reason the
current switching is preferred in the commercially available DACs. In the current switched
DACs the binary-inputs are used to connect the weighted currents to Op-ampinputs for
summing them up according to the bit position of binary inputs.

Fig17.25 shows an example of a 4-bit current switched DAC. If we compare this circuit
with that ín Fig.17.15, then we can see that the position of the Op-amp and the
reference
voltage source V have been interchanged. Therefore, this type of DAC is called Inverted
Ladder DAC. In the circuit shown in Fig.17.15, the reference voltage is switched and the
current distríbution changes the ladder network and propagates towards
in the Op-amp. But
in the inverted ladder DAC the currents are directly switched to the Op-amp without any
delay. Therefore, the inverted ladder DAC is faster in operation.
920 DIGITAL CIRCUITS

The SAR is
Example 13
control sequen
Find out the maximum frequency of the analog-input which can be accuralely control sequen
converted to its §-bit digital equivalent using a tracking ADC which is run by a clock
Step-1.
of frequency 1 MHz.
8-bit SAR). Thi:
Solution:For its reference vC
this example

tek=1MHZ Step-2.Vp
n=8 by the voltage

Therefore, the maximum allocable frequency of the analog-input is (i) V, >V,

106 be furt

2x 2.653 KHz.
tCLK
max signific
2
V,, < V,
Successive Approximation Type ADC
(ii)
17.2.3 be decr

Whe technique approximationtype ADC is equivalent to the Binary

used in the successive
bit of tt

search nmethod of finding an unknown number trom a set of sorted numbers. In this ADC, Step-2 is rej
searched-out from the set of 2N
the N-bit digital code; equivalent to an analog input V.n,
is
For this particu
(0- to-2N-) possible codes. fron
one signal
Like the binary search, the search in this ADCstarts with the trial-value
of the digital
this EOC sign
code which falls at the middle of the set of 2N(-0-to-2N-1) possible codes. The Fig. 17.43(a)
Table17.8 is

shows the circuit for an 8-bit ADC. The circuit'can be extended to N-bit ADC by using for an 8-bit su
Approximation Register (SAR)and N-bit DAC.
N-bit Successive DAC and SAR
SOC EOC Bit of

Comparator the SAIR Di,

Successive Approxmation Clock

Reqister (SAR)

1
(LSB)

goin colibrator
VoAC R,

Q
(MSB)

D, D, D, D, D,D, D, Do
8bit DAC

Fig. 17.43(o): Circuit diagrom of an8-Bit succassive approximation ADC.

From this
t
The alogrithm of the trial conversion by the binary-searching method is described below.
be exact but it

The hardware required for this ADC is (i) one N-bit Successive Approximation Registor
the analog-iny
(SAR)(Gi) one N-bit DAC and (iii)one voltage comparator,

DG Circuits (l]-1
 Crcu it

921

CONVERTERS
DATA
to a specific
The
according
or reset coparator.
be set ofthe voltage
bit can : of an
individual atthe
is as
output follows
of
Q,=1)
the SAR
whose (i.e.
logic-value to 1 behalf
is set
aregister onthe resetting of SAR will
Ihe SAR
is
depending and of the (Vo)
sequence,for the setting the'MSB DAC-output
Control
sequence
starts,
0000
and the V
conversion 1000 voltage
Control the
accurately When
the SAR-input to an
analog-input
comnparison.
by aclock Step-1.
This
nakes
is compared out ofthis can
SAR). (Vo). arising Voac
8-bit voltage
of the amplifier
tes that the lower
its reference twosituations indica the next
the output mav be This
VDAcat There is "HIGH". by setting
Step-2.
comparator. output is done
V.. This to
voltage unchanged.
by the the VnAchas
the comparator with
> Vpac and for matching the already
set-bits
that
(i) V,, increased keeping This indicates lowersignificant
be further bit of the SAR, is "LOW". the next
output and setting
SAR.
the comparator bits of
significant set-bit
Vac and the currently all the
V,, < of
(ii) by
resetting finished,
and resetting the trials are
be decreasedSAR. of setting Using
the the trial After all or EOC.
bit of of SAR.
until we
finish Convesion
the &-bits of
tto the
Binary repeated try with the End latch.
ADC, Step-2 is circuit
we should indicating
in asuitable
gneratedbe
In this particular be latched approximation
of2N For this SAR should SAR should the
of the successive 9.5V and
1the set
one signal
from the
the content
of the
explain
the process
V= 12V, V. =
signal ref
EOC will
ADC. We assume
this which
of the digital an illustration
is type
Table 17.8
approximation Accumulated
e Fig. 17.43(a)
an 8-bit
successive
8-bit
wide. Comparator Value
ADC by using for
SAR are all
of VinVDAC Digital
DAC and Analog Equivalent
Output
New Input(VDA 1000 0000
Bit of the Digital Yes
1

Digital Value
the SAR 6V 1
11000000
Yes
10000000
6+3-9v 0 1100 0000
11000000
No
6+3+1.5=10.5 1100 0000
11100000 No
(LSB))
6+3+0.75-9.75V 1
1100 1000
11010000 Yes
1100 1000
o 6+3+0:375-9.375V
0
lotch
Q. 11001000 No
6+3+0.375+0.1875-9.5625 1100 1010
1
11001100 Yes
(MSB)
6+3+0.375+0.09375-9.46875 11001010
11001010 No
6+3+0.375+0.09375+0.046875-9.515625
Q 11001011
approximation
register.
8-bit succesive
TABLE 8: Table for the
17.
analog-output may not
equivalent of the
it may be noted
that the digital
increased. This difference of
From this table bits of the SAR is
be closer if the number
below. of
scribed
be exact but it will called the Quantization
Error.

(V,) and the Vpac

ation Registor iS
the analog-input

DG Circuits (111-116
 circu it

t
transferred 1
are
This 3docks
CIRCUITS con parator-output
with time.
from QQ difa
922 DIGITAL andthe by trials. for
V flops
of
variation the digital-output
shows the ADCgenerates
Fig.17.43(b) how this
explains 946875
figureclearly 9.375 95625-| 9515625

12
102975
9.5V=V,
VoAcVolt)
tíme
tttt

CLK
output
7 8
Comparator
3 5
e comparator
1
and the
of VoA
Waveform and V =9.5V
Fig. 17.43(b): V12V
SAR ADC
with

output
ofo 8-Bit
type and
ADCare
approximation time is fixed
successive The conversion SAR.
of the ADC.(ii) of the
If

The advantages counter type depends on the size

to other period
conmpared time is the tme T
be NT. where
i) Itis faster conversion
of V, The sothat
of the size time will synchronized
short, regardless conversion be
the SAR then the the output to
in time allows
there are
N-bits
constant conversion
(iii)The
of the
it can
clock.
be read at known
intervals.

Register (SAR) The circuit shown can extended

the same circuit
:
in Fig. 17.43(c)

Approximation of a SAR but

O Successive the behaviour
SAR to understand
is for a 3-bit
of bits. (may beJK or
flip-flops) D
any number (ii) three Flip-flops
for
DAC gates, (vi) one invertor
For this 3-bit SAR
weneed (i) one 3-bit (v)three AND
comparator
(iv) one voltage
ring counter 111
(iii)one 4-bit the
latch. signal Vy using
and (vii) one
3-bit
with the input analog
The output V,,
of the 3-bit DAC
is compared
and the output
of the ring
Q,QQ
The output Ve of the comparator when clock is applied.
voltage comparator. JK flip-flops
counter decides the output Q Q,
of the
and Q, of the three
flip-flops in
turn produces anew form the
Will
for further
reach near
V. Vt
DAC
In this way
These three outputs the
give a new output for Q,Q,@,. 3 clock cycles. The
V,
reach this output we
to
comparison with need only 17.43
error of 1LSB. To
Fig.
to V,with a maximum applied. At 4th clock the Q,=1is
in a 3-bit latch when
4th clock
output Q,Q,Q, is latched
 DATA CONVERTERS V 923

is

transferred to Q, of the ring counter. Therefore, we need four clocks and out of 4 clocks
3clocksare used to A-to-D conversion and the 4th clock is used latching and to restart again
ITOm QQQ= 1000. Fig. 17.43(d) shows the variation of the Q,Q, and Q, output of Flip
flops for different conditionsof the comparator output Ve

Ref V
3-bit DAC
D. D,

1
PREQT
>CK
-CIK

Lotch

MSB
D,

D
LSB

CLK
CLK

4-Bit Ring counter

ed and
SAR. If Approximotion Register (SAR)
Fig. 17.43(c):3-bit Successive
period
so that
QQ,Q, of Flip-Flops
Q,QQ,Q, = 1000
100
17.43(c)
V =0
ztended
|Clock (), Q,Q,Q,0,-0100
010
110
p-flops) Clock (),
V=l Ve= 0
nvertor Ve =0
=0010

sing the 1 101 |011| 001

the ring
V= 0 V= 1
V=0V= Clock (),

applied. 0001
further
100 011 O10 001 000
ach near 111 |110 101
les.. The
of the ring counterwith 100.
17 43(d) :Output of the JK flip-flops with clocks oter iniialisotion
Fig.
Q-1 is