Department of Electronics and Computer Science

FE(CMPN) SEM-II
Computer Organization & Architecture
By
Amaya Pethe

Amaya Pethe
 Module 3 : Processor Organization and Architecture

• Typical CPU Register Organization, Instruction Cycle, instruction

sequencing, Instruction Formats, instruction addressing modes, ,
instruction Interpretation

• CPU Architecture:

Amaya Pethe
Amaya Pethe
Amaya Pethe
 Module 3 : Processor Organization and Architecture

Register Organization in Computer

User Visible Register Control and Status Register

• General Purpose Register • Program counter (PC)
• Data Register • Instruction Register (IR)
• Address Register • Memory Address Register (MAR)
• Flag/Condition Code Register • Memory Data Register (MDR) or
Memory Buffer Register
Amaya Pethe
 Module 3 : Processor Organization and Architecture

• User-Visible Registers
These registers are visible to the assembly or machine language
programmers, and they use them effectively to minimize the memory
references in the instructions. These registers can be referenced
using the machine or assembly language.

Amaya Pethe
 Module 3 : Processor Organization and Architecture
• User-Visible Registers ……
1. General Purpose Register
The general-purpose registers detain both the addresses or the data.
Although we have separate data registers and address registers. The
general-purpose registers also accept the intermediate results during
program execution.
2. Data Register
The term itself describes that these registers are employed to hold the data.
But the programmers can’t use these registers for calculating operand
address.
3. Address Register
The address registers contain the address of an operand, or it can also act as
a general-purpose register. An address register may be dedicated to a
certain addressing mode. Amaya Pethe
 Module 3 : Processor Organization and Architecture
• User-Visible Registers ……
(a) Segment Pointer Register
A memory divided in segments, requires a segment register to hold the base
address of the segment. There can be multiple segment registers. As one
segment register can be employed to hold the base address of the segment
occupied by the operating system. The other segment register can hold the
base address of the segment allotted to the processor.
(b) Index Register
The index register is employed for indexed addressing and it’s initial
value is 0. Generally, it is used for traversing the memory locations. After
each reference, the index register is incremented or decremented by 1,
depending upon the nature of the operation. Sometime the index register
may be auto indexed.
Amaya Pethe
 Module 3 : Processor Organization and Architecture

• User-Visible Registers ……

(c) Stack Pointer Register

The stack register has the address that points to the stack top.

4. Flag/Condition Code Register

Condition codes are the flag bits which are the part of the control register.
The condition codes are set by the processor as a result of an operation, and
they are implicitly read through the machine instruction.
The programmers are not allowed to alter the conditional codes. Generally,
the condition codes are tested during conditional branch operation.

Amaya Pethe
 Module 3 : Processor Organization and Architecture

• Control and Status Registers

The control and status register holds the address or data that is
important to control the processor’s operation. The most important
thing is that these registers are not visible to the users.

Amaya Pethe
 Module 3 : Processor Organization and Architecture

• Control and Status Registers ......

1. Program Counter (PC)
The program counter is a processor register that holds the address of the
instruction that is to be executed next. It is a processor which updates the
program counter with the address of the next instruction to be fetched for
the execution.
2. Instruction Register (IR)
Instruction register has the instruction that is currently fetched. It helps in
analysing the opcode and operand present in the instruction.
3. Memory Address Register (MAR)
Memory address register holds the address of a memory location.

Amaya Pethe
 Module 3 : Processor Organization and Architecture

• Control and Status Registers ……

4. Memory Data Register (MDR)
The memory data register holds the data that is to be written to a memory
location or it holds the data that is recently been read. The memory address
registers (MAR) and memory data registers (MDR) are used to move the
data between processor and memory.
Apart from the above registers, several processors have a register termed
as Program Status Word (PSW). As the word suggests it contains the status
information.
The fields included in Program Status Word (PSW):
Sign: This field has the resultant sign bit of the last arithmetic
operation performed.
Amaya Pethe
 Module 3 : Processor Organization and Architecture

• Control and Status Registers ……

Zero: This field is set when the result of the operation is zero.
Carry: This field is set when an arithmetic operation results in a carry
out or borrow in.
Overflow: This bit indicates the arithmetic overflow.
Interrupt Enable: This bit is set to enable or disable the interrupts.
Parity: This bit indicates whether the result of the arithmetic/logic
operation has even/odd number of ones.

The processor designer organizes these registers according to the

requirement of the processor.
Amaya Pethe
 Module 3 : Processor Organization and Architecture

Instruction Cycle
The structure of the instruction cycle defines the processing of a single
instruction. The processing of instruction takes various forms during the
occurrence of an interrupt or if there is indirect addressing present in the
instruction. The processing involved in the execution of a single instruction
is termed as Instruction Cycle. This processing is done in three steps i.e.
fetch, decode and execute.
• Fetch cycle: In this cycle, the processor reads the instruction that is to be
executed, from the memory.
• Decode cycle: In this cycle, the processor decodes the fetched instruction
• Execute cycle: In this cycle, the processor performs the operation
according to the decoded information
Amaya Pethe
 Module 3 : Processor Organization and Architecture

Instruction Cycle ……
Basic Instruction Cycle

Instruction Cycle State Diagram

Amaya Pethe
 Module 3 : Processor Organization and Architecture

Instruction Cycle ……

Instruction Cycle flow diagram

4
Amaya Pethe
 Module 3 : Processor Organization and Architecture

Instruction Format
Computer perform task on the basis of instruction provided. An instruction
in computer comprises of groups called fields. The most common fields
are:
• Operation (Opcode) field which specifies the operation to be performed
like add/sub/mul/div.
• Operand/Address field which contain the location of operand, i.e.,
register or memory location.
• Mode field which specifies how operand is to be found.

Opcode Operand/Address of operand Mode

Amaya Pethe
 Module 2 : Processor Organization and Architecture

Instruction Format
On the basis of number of addresses, instruction are classified as:
1. Zero Address Instructions
2. One Address Instructions
3. Two Address Instructions
4. Three Address Instructions

Amaya Pethe
 Module 3 : Processor Organization and Architecture

Instruction Format
Formats Example Operation of Instruction Which type of
Instruction processor supports
the format
Zero Address ADD ST(0) ST(0)+ST(1) STACK BASED
Instructions PROCESSOR

One Address ADD B A A+B Accumulator Based

Instructions LOAD A Processors
STORE B

Two Address ADD BL,CL BL BL+CL Non-Accumulator

Instructions based Processors

Three Address ADDA1,A2,A3 M[A1] M[A1]+M[A2] First Generation

Instructions Processors

Amaya Pethe