IJSART - Volume 5 Issue 4 –April 2019 ISSN [ONLINE]: 2395-1052
A CMOS Design of 64 bit ALU using Mentor Tools
Kishore Prabhala1, Prof. Prabhandhakam Sangameswara Raju2
1
Research Scholar, EEE PhD, Rayalaseema University, Senior Member IEEE, 2Research Guide,
1
Principal, PLNM Degree College, Opposite Acharya Nagarjuna University Mens Hostel, Nagarjuna Nagar – 522 510,
Guntur Dist., AP, India
2
Dept. of Electrical and Electronics Engineering, SVU Engineering College, Sri Venkateswara Univeristy, Tirupati – 517
502, Chitoor Dist., AP
1
MSEE – Georgia Institute of Technlogy, GA, USA-1989, BSEE-Purdue University, W.Lafatette, IN, USA-1981,
1
prabhalakishore@gmail.com
Abstract new devices called mobile later smart phone but
ALU has been key aspect with memory in any
Data processing has been driven by an advanced design of these devices.
Arithmetic Logic Unit, ALU in any computer. A The key aspect is the technology scaling
four bit ALU began by Intel Corporation in 1971 in down from 250 nm of CMOS gate to 180 nm to
the design of 4004 microprocessor, first of kind. 130 nm with more transistors can be packed in
The basis of any logic gate is a transistor which can same area but bigger chips can be made. So 64 and
raise to a logic 1 or Logic 0 in less than 100 pico 128 bit data processing have taken place since
seconds (Ps) which translates 10 Giga Hertz, GHz. 2015. Mass production of integrated circuits (IC) in
16 Giga bit memory chip has been in production semiconductor technology of fabrication is a
since 2012 but 64 bit microprocessor have been complex, costly, and deals with yield. As
produced only at end of 2015 simple because of propagation delay approached 100 Ps in 180 nm
arithmetic operation and software development of technology with 10 GB memory development led
course with cost. The time delay of a 64 bit to 64 bit microprocessor based devices in 2015
operation of addition or subtraction may take with billions of devices. Operating system
twenty or fifty times more than a clock cycle and advancements and application of many types in
multiplication would take more than hundred clock millions made a 64 bit processing a key aspect of
cycles. So the design with reduction in area to design. Area, Delay, Power and Reliable
make faster processing has been pushing fabrication have become the key design constraints.
semiconductor technology with 180 nano meter Any ALU has to add or subtract or bit wise
(nm) to 90 nm to 65 nm or even 45 nm but the cost operations or increment or decrement.
or power or time to delivery has to evaluated. The
2. Addition
Electronic Design Automation (EDA) tools have
Fundaments design of any ALU is based
been heavily used to make front end design with
on addition and bit wise comparisons. So an adder
netlist with rapid strides along backend design of
plays a critical role in Very Large Scale Integration
layout with tape out also. This paper show the
(VLSI) design of 64 bit addition which require over
usage of Mentor EDA tools in the front design of
5000 gates to be simulated. An adder can also
64 bit ALU at 130 nm technology with simulation.
convert to do subtraction. There are two adders.
The full adder performs addition of two
inputs from A and B and another input called carry
Keywords: Arithmetic Logic Unit, Microprocessor,
in, Cin. There are two outputs are Sum and Carry
Giga Hertz, Electronic Design Automation and
Out, Co. Since there are three inputs there will be
Mentor Tools.
eight combinations in binary and the input
combinations would generate the output as truth
table for a full adder shown in the table 1.
1. Introduction
Data processing has been driven by an Table 1: Truth table for Full Adder
ALU in any computer which began by the 4004, A B Cin Sum Co
first microprocessor by Intel with Metal Oxide 0 0 0 0 0
Silicon (MOS) technology with 2300 transistors 0 0 1 1 0
using 4 bit processing in 1971.But 8 bit processing 0 1 0 1 0
in 1974 and 16 bit processing by 1978 created a 0 1 1 0 1
glorious technology diffusion of Personal 1 0 0 1 0
Computers led by IBM, Intel and Microsoft thought 1 0 1 0 1
Apple, Atari, Tandy, and others made big strides 1 1 0 0 1
but IBM model continued with faster speed and 32 1 1 1 1 1
bit processing by middle of 1990s. Millions of PC
have led to huge number of applications as well as
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IJSART - Volume 5 Issue 4 –April 2019 ISSN [ONLINE]: 2395-1052
When one transpose these values into a 7. Top Level Design in Mentor using Verilog
Karnaugh map and with simplification of sum of We have used Mentor tools to create the
products one get equation for Sum and Carry Out, top design with five blocks. Each block has been
Co. This is shown in figure 1. coded and compiled to verify logically there are
correct. There is a Logic_unit_64 for 64 bit wise
Figure 1: Full Adder operations with AND, OR, XOR, and XNOR using
sel(1:0) as control. A block with “a_logic” to
perform increment or decrement operation on input
ain. Another block with “b_logic” to perform
increment or decrement operation on input bin.
Two bit control operators used with “sel” along
anther operator “m” to select bit wise AND, OR,
XOR, XNOR when 0 and else other when 1. When
“Co” = 0, add will be done in the adder_64 block
and subtraction when “Co” = 1.
Sum = A’B’Cin + A’BCin’ + AB’Cin’ + ABCin = A block by name “mux_2by1” used to
(A XOR B) XOR Cin select the output from the adder block vs logic
block and control is “m”. When m=0, output at
Carry Out = AB + ACin + BCin or AB + (A XOR “result(63:0)” will from the logical operations
B)Cin defined by sel(1:0), if m=1 then the output of
adder_64 will be passed to “result(63:0)” .
3. Subtraction
A subtraction can be performed using a Figure 3: Top level 64 bit ALU
modification to a Full Adder. A – B can be written
as A + (2’s complement of B). A 2’s Complement
needs a XOR with control input when 0 passes B
and inverts bits when 1. This control input will be
connected to Carry in when 1 it will added to A
with complement of B. This is shown in figure 2.
A - B = A + (-B) = A + ~B + 1
Figure 2: Adder as a Subtractor
A A Sum
B Full
B Adder
Cin
The following table shows the mode of operation of
Co
ALU with four control variables ”sel0”, “sel1”,
Cin “m” and “Co”.
4. Logical Operations
A bitwise operation of AND is good for IP Table 1: Operations for ALU
address identification with 64 NANDs with INV. Mode Sel Sel Co Function Operations
There is OR operation, XOR (Parity Check), M 1 0
XNOR (Equivalency) of 64 bits. 0 0 0 x A AND B AND
0 0 1 x A OR B OR
5. Incrementing and decrementing 0 1 0 x A XOR B XOR
The input ain can be incremented it can be 0 1 1 x A XNOR B XNOR
incremented or decrement with 1’s or 2’s 1 0 0 0 A Pass A
complement. 1 0 0 1 A+1 Inc A
1 0 1 0 A+B Add
6. Flags 1 0 1 1 A+B+1 Add + Inc
A carry occurs when the final addition or 1 1 0 0 A + B’ A + 1’sB
subtraction is too big to fit into 64 bits which 1 1 0 1 A + B’ + 1 A + 2’sB
comes out of final carry out of 64 bit adders. A 1 1 1 0 A’ + B 1’sA + B
Zero is done with AND gate to signify the zero
value at the output of the ALU. Parity of One is 1 1 1 1 A’ + B + 1 2’sA + B
also checked.
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IJSART - Volume 5 Issue 4 –April 2019 ISSN [ONLINE]: 2395-1052
The coding is done in verilog using mentol Figure 5: 64 bit Adder in ALU
tool as shown in figure 4 with two inputs ain and
bin defined to have 64 bits. Two inputs of control
are m and co and other two are sel(1:0). Output of
64 bits is defined as result with flags as parity, cout,
z, n, c, and v.
Figure 4: Verilog coding of Top level 64 bit ALU
7.1 Adder Block
This block has 64 inputs of ain and bin
which are used to create add logic with XOR and
passed to a AND gate. Then carry out is identified
with a OR logic with one input from AND of ain
and bin. The second input is from ANDing XOR of
ain and bin with cin. Carry out of ain0 and bin0
will be carry in “cin” for ain1 and bin1. At bit 31,
this will be carry flag. This is shown in figure 5.
There is a second level of XOR output is
Sum. One input of this XOR is from the output of
ain XOR bin with other input will be driven by
Carry out from addition of each bit. The verilog
coding for sum and carry is
// full adder: <str> (\/)
module full_adder(cout,sum,ain,bin,cin); For addition of 64 bits there are 64 full
input ain,bin,cin; adder references in verilog from the above full
output cout,sum; adder definition as
wire w1,w2,w3; //64 bit adder : <str> (\/)
half_adder ha1(w1,w2,ain,bin), module adder_64 (cp,cout,sum,ain,bin,cin);
ha2(w3,sum,w2,cin); input [63:0] ain,bin;
or or1(cout,w1,w3); input cin;
endmodule output [63:0] sum;
output cp,cout;
//half adder <str> (\/) wire [62:0] c;
module half_adder(carry,sum,ain,bin); full_adder
input ain,bin; fulla0(c[0],sum[0],ain[0],bin[0],cin),
output sum,carry;
xor xor11(sum,ain,bin); fulla1(c[1],sum[1],ain[1],bin[1],c[0]),
and and11(carry,ain,bin); fulla2(c[2],sum[2],ain[2],bin[2],c[1]),
endmodule this continues for 63rd bit from bit zero.
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IJSART - Volume 5 Issue 4 –April 2019 ISSN [ONLINE]: 2395-1052
7.2 Logical Block
There are four logical implementations in
this block. One is AND all 64 bit ain with bin.
Second is OR all 64 bit ain with bin. Third is XOR
all 64 bit ain with bin and fourth is XNOR. The
verilog code that generates the logic is
module logic_low_unit
(and_out,or_out,xor_out,xnor_out,ain,bin);
input ain,bin;
output and_out,or_out,xor_out,xnor_out;
wire w1,w2;
//wire and_out,xnor_out;
nand aand1(w1,ain,bin);
not nnot1(and_out,w1);
nor oor1(w2,ain,bin);
not nnot11(or_out,w2);
or oor2(xnor_out,and_out,w2);
not nnot2(xor_out,xnor_out);
endmodule
module logic_unit_64(res_out,sel,ain,bin);
input [63:0] ain,bin;
input [1:0]sel; 8. Gate Count
output [63:0] res_out; There are two 64 bit inputs, four control
wire[63:0] inputs (m, sel0, sel1, Co), one 64 bit output results
and_out,or_out,xor_out,xnor_out; and six output as flags, so total 202 ports as show
logic_low_unit in figure 7.
llu0(and_out[0],or_out[0],xor_out[0],xnor_o The total number gates And, Or, Inv,
ut[0],ain[0],bin[0]), XOR, are 6125.
llu1(and_out[1],or_out[1],xor_out[1],xnor_o
ut[1],ain[1],bin[1]), continues for 63 rd bit. Figure 7: Gate for all the five blocks designed
for 64 bit ALU
Figure 6: 64 bitwise Logic implementation
9. Simulation
The first wave form shown is the 64 bit
input “ain” and next is input “bin”. The third wave
form is the control input “m” when it is 1 it select
addition and subtraction as seen going 1 at 1375ns
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IJSART - Volume 5 Issue 4 –April 2019 ISSN [ONLINE]: 2395-1052
on x-axis. When m is ZERO logical bit operations
are performed. Fourth wave form is carry in “co”
which goes from low to high at 2500 ns. Next is
two input “sel(1:0)” and also each input sel1 and
sel0 is shown figure 8.
Figure 8: Results of Logical verification of 64 bit
ALU
Eight waveform is the 64 bit output of “result” Figure 9: Propagation Values of Logical
which goes to all Ones at 1000 ns along with the Comparisons and Adders of 64 bit ALU
outputs parity and carryout too. By 1300 ns another
pattern is checked and the flags change too as per
the operation.
10. Results
A propagation delay for adder from stage
zero was identified and given in figure 9. A NOR
gate has a worst case delay of 0.26 ns and a NAND
gate has a worst delay of 0.32 ns. A logical OR
output took 0.62ns, a logical AND took 0.97ns, a
XOR took 1.79ns and a XNOR took 2.21ns at the
end of the mux shown in the top level logic
diagram.
A 64 bit addition has 39.36 ns delay from
input “ain” and “bin” to output “result_out” for
adding 64 bits at 130 nm technology library of
Leonardo Spectrum Level 3 of Mentor tool. This is
shown in figure 9 and figure 10 shows results for
last adders.
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IJSART - Volume 5 Issue 4 –April 2019 ISSN [ONLINE]: 2395-1052
12. References
1. Mukesh P. Mahajan, P.G. Salunke, Y.M.
Gaikwad, V.P. Jagtap, “Design And Simulation
of 64 bit ALU”, IJARECE Volume 4, Issue 4,
January 2015.
2. Kishore Prabhala, Haritha Dasari, and Thrinadh
Komatipalli, “Performance Comparison of 64-
Bit Adders”, IJEDR 2018 | Volume 6, Issue 2 |
ISSN: 2321-9939
3. Pragati Nagdeote and Prof. Manisha Waje,
“Design of 64-bit Arithmetic Logic Unit (ALU)
Based on BSIM4 Model Using Tanner”,
IJSART - Volume 2 Issue 10-October-2016
ISSN [ONLINE]: 2395-1052
4. Rajib Partha Bhattacharyya, Bijoy Kundu, Sovan
Ghosh, Vinay Kumar, and Anup Dandapat,
“Performance Analysis of a Low-Power High-
Speed Hybrid 1-bit Full Adder Circuit” IEEE
transactions on very large scale integration
(VLSI) systems, vol. 23, no. 10, October 2015.
5. Chetia, Kaushik Chandra Deva Sarma, Gaurab
Baruah, “Behavioral Design and Synthesis of 64
Bit ALU using Xilinx ISE”. IOSR Journal of
Electronics and Communication Engineering
(IOSR-JECE), Volume 7, Issue 4 (Sep. - Oct.
2013), PP 37-41, e-ISSN: 2278-2834,p- ISSN:
Figure 10: Propagation Values for the last stage 2278-8735.
Adders of 64 bit ALU 6. N. Ravindran, R. Mary Lourdes, “An Optimum
VLSI, Design Of A 16-Bit ALU”,978-1-4799-
8966-9/15/$31.00 ©2015 IEEE
7. Sakshi Samaiya and Anupreksha Jain, “A
Review Article of ALU Unit Design based on
FPGA”, International Journal of Scientific
Research & Engineering Trends, Volume 4,
Issue 4, July-Aug-2018, ISSN (Online): 2395-
566X.
About Authors
Kishore Prabhala is a research Scholar in EEE PhD,
Rayalaseema University and also Senior Member
IEEE. He published six papers in CMOS VSLI
design in India after leaving USA in 1994 working
at Motorola, MMI and National Semiconductor
from 1981. Currently, he is the Principal, PLNM
Degree College, Opposite Acharya Nagarjuna
University Mens Hostel, Nagarjuna Nagar – 522
510, Guntur Dist., AP, India. He received a MSEE
from Georgia Institute of Technology, GA, USA in
11. Conclusions
1989 and BSEE from Purdue University,
This is a CMOS VLSI design of 64 bit
W.Lafatette, IN, USA in 1981.
ALU with addition, subtraction, bit wise operations
Prof. Prabhandhakam Sangameswara Raju is a
of AND, OR, XOR and XNOR verified with
Professor in Dept. of Electrical and Electronics
mentor tools at 130 nm technology at room
Engineering, SVU Engineering College, Sri
temperature. The efficiency design time increases
Venkateswara Univeristy, Tirupati – 517 502,
for three or four fold with EDA tools and the
Chitoor Dist., AP. He received M.Tech. and Ph.D.
blocks can be reused. Addition can be reduced with
from SVU Engineering College. He has been
a carry look ahead adder and in future will do at the
teaching PG course for last 25 years and guided
cold and hot temperatures as well as scaling down
ove 52 projects. He published over 70 papers.
the technology too.
Currently there are 8 students pursuing Ph.D.
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