SN74ALVCH16952

16-BIT REGISTERED TRANSCEIVER

WITH 3-STATE OUTPUTS
www.ti.com SCES011E – JULY 1995 – REVISED SEPTEMBER 2004

FEATURES DGG, DGV, OR DL PACKAGE

• Member of the Texas Instruments Widebus™ (TOP VIEW)
Family
• EPIC™ (Enhanced-Performance Implanted 1OEAB 1 56 1OEBA
CMOS) Submicron Process 1CLKAB 2 55 1CLKBA
• ESD Protection Exceeds 2000 V Per 1CLKENAB 3 54 1CLKENBA
MIL-STD-883, Method 3015; Exceeds 200 V GND 4 53 GND
Using Machine Model (C = 200 pF, R = 0) 1A1 5 52 1B1
• Latch-Up Performance Exceeds 500 mA Per 1A2 6 51 1B2
JESD 17 VCC 7 50 VCC
1A3 8 49 1B3
• Bus Hold on Data Inputs Eliminates the Need
1A4 9 48 1B4
for External Pullup/Pulldown Resistors
1A5 10 47 1B5
• Package Options Include Plastic 300-mil GND 11 46 GND
Shrink Small-Outline (DL), Thin Shrink 1A6 12 45 1B6
Small-Outline (DGG), and Thin Very 1A7 13 44 1B7
Small-Outline (DGV) Packages 1A8 14 43 1B8
2A1 15 42 2B1
DESCRIPTION 2A2 16 41 2B2
This 16-bit registered transceiver is designed for 2A3 17 40 2B3
1.65-V to 3.6-V VCC operation. GND 18 39 GND
2A4 19 38 2B4
The SN74ALVCH16952 contains two sets of D-type
flip-flops for temporary storage of data flowing in 2A5 20 37 2B5
either direction. This device can be used as two 8-bit 2A6 21 36 2B6
transceivers or one 16-bit transceiver. Data on the A VCC 22 35 VCC
or B bus is stored in the registers on the low-to-high 2A7 23 34 2B7
transition of the clock (CLKAB or CLKBA) input, 2A8 24 33 2B8
provided that the clock-enable (CLKENAB or GND 25 32 GND
CLKENBA) input is low. Taking the output-enable 26 31
2CLKENAB 2CLKENBA
(OEAB or OEBA) input low accesses the data on 27 30
2CLKAB 2CLKBA
either port.
2OEAB 28 29 2OEBA
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16952 is characterized for operation from -40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004

FUNCTION TABLE (1)

INPUTS OUTPUT
CLKENAB CLKAB OEAB A B
H X L X B0 (2)
X L L X B0 (2)
L ↑ L L L
L ↑ L H H
X X H X Z

(1) A-to-B data flow is shown; B-to-A data flow is similar, but uses
CLKENBA, CLKBA, and OEBA.
(2) Level of B before the indicated steady-state input conditions were
established

2
 SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
www.ti.com
WITH 3-STATE OUTPUTS
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004

LOGIC SYMBOL(1)
56
1OEBA EN3
54
1CLKENBA G1
55
1CLKBA 1C5
1
1OEAB EN4
3
1CLKENAB G2
2
1CLKAB 2C6
29
2OEBA EN9
31
2CLKENBA G7
30
2CLKBA 7C11
28
2OEAB EN10
26
2CLKENAB G8
27
2CLKAB 8C12

5 52
1A1 3 5D 1B1
6D 4
6 51
1A2 1B2
8 49
1A3 1B3
9 48
1A4 1B4
10 47
1A5 1B5
12 45
1A6 1B6
13 44
1A7 1B7
14 43
1A8 1B8
15 42
2A1 9 11D 2B1
12D 10
16 41
2A2 2B2
17 40
2A3 2B3
19 38
2A4 2B4
20 37
2A5 2B5
21 36
2A6 2B6
23 34
2A7 2B7
24 33
2A8 2B8

(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

3
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004

LOGIC DIAGRAM (POSITIVE LOGIC)

3 54
1CLKENAB 1CLKENBA
2 55
1CLKAB 1CLKBA
56 1
1OEBA 1OEAB

One of Eight
C1
Channels CE
5 52
1A1 1D 1B1

C1
CE
1D

To Seven Other Channels

26 31
2CLKENAB 2CLKENBA
27 30
2CLKAB 2CLKBA
29 28
2OEBA 2OEAB

One of Eight
C1
Channels CE
15 42
2A1 1D 2B1

C1
CE
1D

To Seven Other Channels

4
 SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
www.ti.com
WITH 3-STATE OUTPUTS
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range -0.5 4.6 V
Except I/O ports (2) -0.5 4.6
VI Input voltage range V
I/O ports (2) (3) -0.5 VCC + 0.5
VO Output voltage range (2) (3) -0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 -50 mA
IOK Output clamp current VO < 0 -50 mA
IO Continuous output current ±50 mA
Continuous current through each VCC or GND ±100 mA
DGG package 81
θJA Package thermal impedance (4) DGV package 86 °C/W
DL package 74
Tstg Storage temperature range -65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51.

RECOMMENDED OPERATING CONDITIONS (1)

MIN MAX UNIT
VCC Supply voltage 1.65 3.6 V
VCC = 1.65 V to 1.95 V 0.65 × VCC
VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × VCC
VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V
VCC = 2.7 V to 3.6 V 0.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 1.65 V -4
VCC = 2.3 V -12
IOH High-level output current mA
VCC = 2.7 V -12
VCC = 3 V -24
VCC = 1.65 V 4
VCC = 2.3 V 12
IOL Low-level output current mA
VCC = 2.7 V 12
VCC = 3 V 24
∆t/∆v Input transition rise or fall rate 10 ns/V
TA Operating free-air temperature -40 85 °C

(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

5
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004

ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
IOH = -100 µA 1.65 V to 3.6 V VCC - 0.2
IOH = -4 mA 1.65 V 1.2
IOH = -6 mA 2.3 V 2
VOH 2.3 V 1.7 V
IOH = -12 mA 2.7 V 2.2
3V 2.4
IOH = -24 mA 3V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
IOL = 6 mA 2.3 V 0.4
VOL V
2.3 V 0.7
IOL = 12 mA
2.7 V 0.4
IOL = 24 mA 3V 0.55
II VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V 1.65 V 25
VI = 1.07 V 1.65 V -25
VI = 0.7 V 2.3 V 45
II(hold) VI = 1.7 V 2.3 V -45 µA
VI = 0.8 V 3V 75
VI = 2 V 3V -75
VI = 0 to 3.6 V (2) 3.6 V ±500
IOZ (3) VO = VCC or GND 3.6 V ±10 µA
ICC VI = VCC or GND, IO = 0 3.6 V 40 µA
∆ICC One input at VCC - 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
Ci Control inputs VI = VCC or GND 3.3 V 3.5 pF
Cio A or B ports VO = VCC or GND 3.3 V 8.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) For I/O ports, the parameter IOZ includes the input leakage current.

TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 2.5 V VCC = 3.3 V
VCC = 1.8 V VCC = 2.7 V
± 0.2 V ± 0.3 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency (1) 150 150 150 MHz
CLKEN high (1) 3.3 3.3 3.3
tw Pulse duration ns
CLK high or low (1) 3.3 3.3 3.3
Data before CLK (1) 1.7 1.9 1.5
tsu Setup time ns
CLKEN before CLK (1) 1.2 1 1
Data after CLK (1) 0.6 0.6 0.8
th Hold time ns
CLKEN after CLK (1) 1.1 0.9 1.1

(1) This information was not available at the time of publication.

6
 SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
www.ti.com
WITH 3-STATE OUTPUTS
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 2.5 V VCC = 3.3 V
FROM TO VCC = 1.8 V VCC = 2.7 V
PARAMETER ± 0.2 V ± 0.3 V UNIT
(INPUT) (OUTPUT)
MIN TYP MIN MAX MIN MAX MIN MAX
fmax (1) 150 150 150 MHz
tpd CLK A or B (1) 1 4.1 4.6 1 3.9 ns
ten OEBA or OEAB A or B (1) 1 5.4 5.3 1 4.4 ns
tdis OEBA or OEAB A or B (1) 1 5.3 4.4 1.1 4 ns

(1) This information was not available at the time of publication.

OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP
Outputs enabled (1) 53 71
Power dissipation
Cpd CL = 0, f = 10 MHz pF
capacitance Outputs disabled (1) 34 40

(1) This information was not available at the time of publication.

7
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004

PARAMETER MEASUREMENT INFORMATION

VCC = 1.8 V
2 × VCC
1 kΩ S1 Open
From Output TEST S1
Under Test GND
tpd Open
CL = 30 pF
1 kΩ tPLZ/tPZL 2 × VCC
(see Note A) tPHZ/tPZH GND

LOAD CIRCUIT
tw
VCC
VCC Input VCC/2 VCC/2
Timing
VCC/2 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
VCC Output
Data VCC
VCC/2 VCC/2 Control
Input VCC/2 VCC/2
0V (low-level
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output VCC
VCC Waveform 1
Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.15 V
0V (see Note B) VOL

tPLH tPHL tPZH tPHZ

Output VOH
VOH
Waveform 2 VOH − 0.15 V
Output VCC/2 VCC/2 VCC/2
S1 at GND
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

8
 SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
www.ti.com
WITH 3-STATE OUTPUTS
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004

PARAMETER MEASUREMENT INFORMATION

VCC = 2.5 V ± 0.2 V
2 × VCC
500 Ω S1 Open
From Output TEST S1
Under Test GND
tpd Open
CL = 30 pF
500 Ω tPLZ/tPZL 2 × VCC
(see Note A) tPHZ/tPZH GND

LOAD CIRCUIT
tw
VCC
VCC Input VCC/2 VCC/2
Timing
VCC/2 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
VCC Output
Data VCC
VCC/2 VCC/2 Control
Input VCC/2 VCC/2
0V (low-level
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output VCC
VCC Waveform 1
Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.15 V
0V (see Note B) VOL

tPLH tPHL tPZH tPHZ

Output VOH
VOH
Waveform 2 VOH − 0.15 V
Output VCC/2 VCC/2 VCC/2
S1 at GND
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.

Figure 2. Load Circuit and Voltage Waveforms

9
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS www.ti.com
SCES011E – JULY 1995 – REVISED SEPTEMBER 2004

PARAMETER MEASUREMENT INFORMATION

VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1 TEST S1
500 Ω Open
From Output tpd Open
Under Test GND tPLZ/tPZL 6V
CL = 50 pF tPHZ/tPZH GND
(see Note A) 500 Ω

tw
LOAD CIRCUIT
2.7 V
Input 1.5 V 1.5 V
2.7 V
Timing 1.5 V 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
2.7 V
Data Output
1.5 V 1.5 V 2.7 V
Input Control
0V 1.5 V 1.5 V
(low-level
VOLTAGE WAVEFORMS enabling)
0V
SETUP AND HOLD TIMES
tPZL tPLZ

Output 3V
2.7 V Waveform 1
Input 1.5 V
1.5 V 1.5 V S1 at 6 V VOL + 0.3 V
0V (see Note B) VOL
tPZH tPHZ
tPLH tPHL
Output VOH
VOH Waveform 2 VOH − 0.3 V
Output 1.5 V
1.5 V 1.5 V S1 at GND
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.

Figure 3. Load Circuit and Voltage Waveforms

10
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74ALVCH16952DGGR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH16952

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALVCH16952DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALVCH16952DGGR TSSOP DGG 56 2000 367.0 367.0 45.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DGG0056A SCALE 1.200
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
8.3 SEATING PLANE
TYP
7.9
PIN 1 ID 0.1 C
A
AREA 54X 0.5
56
1

14.1 2X
13.9 13.5
NOTE 3

28
29
0.27
6.2 56X 1.2 MAX
B 0.17
6.0
0.08 C A B

(0.15) TYP

0.25
SEE DETAIL A GAGE PLANE

0.15
0 -8 0.75 0.05
0.50

DETAIL A
TYPICAL

4222167/A 07/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGG0056A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

56X (1.5) SYMM

1
56

56X (0.3)

54X (0.5)

(R0.05)
TYP
SYMM

28 29
(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4222167/A 07/2015
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGG0056A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

56X (1.5) SYMM

1
56

56X (0.3)

54X (0.5)

(R0.05) TYP
SYMM

28 29

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4222167/A 07/2015
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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