Chapter 4

Analog Integrated Circuits

IC 555 timer
IC 555 timer
• First monolithic integrated circuit timer introduced
Signetics Corporation in 1972
• Precision timing, Pulse generation, Sequential timing,
Time delay generation, Pulse width/position
modulation, measurement and control signal
generation, and linear ramp signal generation.
• Features:
• Operate in both astable and monostable modes
• Adjustable duty cycle
• High current output.
• Flexibility and reliability
• Easy to use and low cost
Pin diagram
• Ground (Pin 1):
• Trigger (Pin 2): The external trigger pulse is applied
to determine the output of timer.
• Output (Pin 3):
• Reset (Pin 4): To reset (disable) IC 555, active low or
negative pulse must be applied
• Control Voltage (Pin 5): Changes the output of
threshold and trigger comparators.
• Threshold (Pin 6): Threshold input is applied to
control the output
• Discharge (Pin 7): Connected with the external
timing capacitor
• VCC (Pin 8): +5V to +18V
Block diagram:
• IC 555 timer consists of two comparators, an RS flip-
flop, an output buffer and a transistor.
• The comparator outputs drive RS flip-flop, output
buffer, and a transistor.
• The transistor is used as a discharging circuit to
discharge the timing capacitor.
• The inverting input of comparator-1 and non-
inverting input of comparator-2 is driven by a voltage
divider that is energized by a supply voltage VCC.
• The voltage divider is controllable by a control
voltage applied across terminal 5.
• Comparator-1 is called as threshold comparator
• Comparator-2 is called a trigger comparator.
• The threshold comparator compares the threshold
voltage with the reference internal voltage (2/3)V.
• High vth produce high R and produce low Q.
• The high drives the transistor in saturation to
discharge the external timing capacitor.
• The time period of reference level can be controlled
by modifying an external control voltage.
• The trigger comparator compares the trigger input
with the reference internal voltage (1/3)V
• High Q drives the transistor in cutoff to turn off
discharging the external timing capacitor.
• Reset input applied to the flip-flop at terminal 4, it
overrides all other inputs
Astable multivibrator
Astable multivibrator
• In the 555 timer, pin 2 and pin 6 are connected together
allowing the circuit to retrigger itself on each and every cycle
• It allows operating as a free running oscillator.
• During each cycle capacitor, C charges up through both
timing resistors, R1 and R2 but discharges itself only
through resistor, R2 as the other side of R2 is connected to the
discharge terminal, pin 7.
• Then the capacitor charges up to 2/3Vcc (the upper
comparator limit) which is determined by the 0.693(R1+R2)C
combination.
• And discharges itself down to 1/3Vcc (the lower comparator
limit) determined by the 0.693(R2.C) combination.
• This results in an output waveform whose voltage
level is approximately equal to Vcc - 1.5V and whose
output "ON" and "OFF" time periods are determined
by the capacitor and resistors combinations.
• The individual times required completing one charge
and discharge cycle of the output is therefore given as:
Monostable multivibrator
• It has one stable and one quasi stable state.
• The circuit is useful for generating single output pulse
of time duration in response to a triggering signal.
• The width of the output pulse depends only on
external components connected to the op-amp.
• The diode gives a negative triggering pulse.
• When the output is +Vsat, a diode clamps the capacitor
voltage to 0.7V then, a negative going triggering
impulse magnitude Vi passing through RC and the
negative triggering pulse is applied to the positive
terminal.
• Let us assume that the circuit is in stable state.
• The output V0i is at +Vsat.
• The diode D1 conducts and Vc the voltage across the
capacitor ‘C’ gets clamped to 0.7V, the voltage at the
positive input terminal through R1R2 potentiometer
divider is +ßVsat.
• Now, if a negative trigger of magnitude Vi is applied
to the positive terminal so that the effective signal is
less than 0.7V.
• The output of the Op-Amp will switch from +Vsat to
–Vsat.
• The diode will now get reverse biased and the
capacitor starts charging exponentially to –Vsat.
• When the capacitor charge Vc becomes slightly more
negative than –ßVsat, the output of the op-amp
switches back to +Vsat.
• The capacitor ‘C’ now starts charging to +Vsat through
R until Vc is 0.7V.
Phase-Locked Loop
(PLL)
Phase-Locked Loop (PLL)
• Introduction to Phase-locked loop
(PLL)
• Historical Background
• Basic PLL System
• Phase Detector (PD)/comparator
• Loop Filter (LPF)
• An error Amplifier
• Voltage Controlled Oscillator (VCO)
• PLL Applications
Phase-Locked Loop (PLL)
A Phase-Locked Loop (PLL) is a negative
feedback system consists of a
phase detector,
low pass filter and
voltage controlled oscillator (VCO)
Its purpose is to synchronize an output
signal with a reference or input signal in
frequency as well as in phase.
Phase-Locked Loop (PLL)

• In the synchronized or “locked” state, the phase error

between the oscillator’s output signal and the reference

signal is zero, or it remains constant.

• If a phase error builds up, a control mechanism acts on

the oscillator to reduce the phase error to a minimum so

that the phase of the output signal is actually locked to

the phase of the reference signal. This is why it is called

a PLL.
PLL-Applications
The majority of PLL applications fall into four main
categories:
• Frequency synthesis (Most widely used so PLL is also
referred as frequency synthesizer).
• Frequency (FM), phase (PM) Amplitude (AM) and
modulation and demodulation.
• Radar Synchronization & Communication
• Data and carrier recovery.
• Tracking filters.
PLL- Classification

Classification of PLLs:
• Analog or Linear PLL (LPLL)
• Digital PLL (DPLL) is Analog PLL with digital phase
detector
• All-Digital PLL (ADPLL) is a digital loop in two senses:
all digital components and all digital (discrete-time)
signals.
How Are PLLs Used?
 Brief Phase-Locked Loop (PLL) History
• 1932: Invention of “coherent communication” using vacuum tube,
(deBellescize)
• 1943: Horizontal and vertical sweep synchronization in television
(Wendt and Faraday)
• 1954: Color television (Richman)
• 1965: PLL on integrated circuit
• 1970: Classical digital PLL
• 1972: All-digital PLL
• PLLs today: in every cell phone, TV, radio, pager, computer, …
• Clock and Data Recovery
• Frequency Synthesis
• Clock Generation
• Clock-skew minimization
• Duty-cycle enhancement
 Block Diagram (PLL)

The VCO is the free running multivibrator and operates at the set
frequency F0 called free running frequency. F0 is determined by external
timing components RT and CT. It can be shifted in either side by applying
a DC controlled voltage to VCO.
The frequency deviation is directly proportional to the DC controlled
voltage therefore it is called “Voltage Controlled Oscillator”
 Block Diagram (PLL)

• The input signal Vs of the frequency Fs is applied to the PLL.

• The Phase Detector compares the phase and frequency of the Fs and
VCO output Fo.
• If the two signals are differ in frequency and/or phase an error voltage
Ve is generated.
• The phase detector is basically a signal multiplier and produces sum
(Fs+Fo) and difference (Fs-Fo)
 Block Diagram (PLL)

• The high frequency signal sum (Fs+Fo) is removed by LPF and low
frequency signal difference (Fs-Fo) is then passed by LPF and amplified
by an error amplifier which generates the DC control signal Vc for the
VCO to control the Fo.
• Vc shifts the VCO frequency in either direction so that to reduce the
difference between Fs and Fo.
• Once this action starts we say signal is captured.
• VCO continues to change the Fo till Fo=Fs. The circuit then said to be
Locked.
 PLL-Capture Transient
Once PLL is Locked, it tracks the frequency changes of the input signal
Fs. Thus it goes through three stages:
i) Free running
ii) Capture
iii) Locked or Tracking

• Above figure shows the capture transient, the LPF controls the
Capture range.
• If the difference signal (Fs-Fo) is too large to pass through the LPF the
PLL will not respond.
• It is said the signal is out of Capture range
• But once it is captured PLL can Lock/Track the signal well beyond the
capture range. Therefore Tracking Range > Capture Range
 PLL: Definitions
Lock In Range: Once the PLL is locked, it can track frequency changes in the
incoming signals. The range of frequencies over which the PLL can maintain the
lock with the incoming signal is called Lock-in Range or Tracking Range and it is
expressed as a percentage of Fo of VCO frequency.

Capture Range: The range of frequencies over which PLL can acquire the lock
with an input signal Fs called Capture range and it is expressed as a percentage of
Fo of VCO frequency.

Pull-in Time: The total time taken by PLL to establish the lock is called Pull-in
Time. This depends on the initial phase and frequency difference between Fs and
Fo, the overall loop gain and filter characteristics.
PLL: Characteristics
PLL: Phase Detector/Comparator (Analog)
 PLL: Phase Detector/Comparator (Digital)

• Figure shows the Digital (X-OR) phase detector. Output of X-OR is

HIGH only if one of the input signal Fs or Fo is HIGH.
• This type of Phase detector used only when both the inputs (Fs & Fo)
are square wave.
• The output waveforms when Fs=Fo are shown in above figure where
Fs is leading the Fo by Φ degrees.
 PLL: Phase Detector/Comparator (Digital)

Figure shows variation of the DC output voltage (Ve) with Phase

difference (Φ). It shows that the maximum DC output voltage occurs
when phase difference is c.
Slope of the curve gives the conversion ratio (KΦ) of the phase detector if
VCC=5V.
KΦ=5V/ π V/rad
 VCO- Voltage Controlled Oscillator
• A Voltage-Controlled Oscillator (VCO) is a circuit that provides
a varying output signal whose frequency can be adjusted over a
range controlled by an externally applied DC voltage.

• The VCO provides a linear relationship between the applied

voltage and the oscillation frequency. The applied voltage is
called control voltage.

• The control of frequency with the help of control voltage is

known as voltage to frequency conversion. Hence VCO is
otherwise known as Voltage to frequency converter.

• Practically VCO is available in IC form. IC 566 (LM566/SE566)

from Signetics is a popular VCO.

• IC 566 contains circuitry to generate both square-wave and

triangular-wave signals whose frequency is set by an external
resistor and capacitor and then varied by an applied dc voltage.
 PLL:VCO- Voltage Controlled Oscillator

• Figure (b) the timing capacitor CT is linearly charged or discharged by

a constant current source/sink.

• The amount of current can be controlled by changing the voltage VC at

the modulating input (Pin 5) or by changing the external timing
resistor RT.
 PLL:VCO- Voltage Controlled Oscillator

The voltage at pin 6 is held at same voltage as pin 5. (small capacitor

0.001µF connected between pin 5 & 6 to eliminate possible oscillations)
Thus, if VC at pin 5 increased, voltage at pin 6 also increases, results in less
voltage drop across RT and thereby decreasing the charging current.
VCO commonly used to convert low frequency signals such as ECGs and
EEGs into an audio frequency range to transmit over telephone line, 2
way radio communication system or can be recorded.
 PLL:VCO- Voltage Controlled Oscillator

The voltage at pin 6 is held at same voltage as pin 5. (small capacitor

0.001µF connected between pin 5 & 6 to eliminate possible oscillations)
Thus, if VC at pin 5 increased, voltage at pin 6 also increases, results in less
voltage drop across RT and thereby decreasing the charging current.
VCO commonly used to convert low frequency signals such as ECGs and
EEGs into an audio frequency range to transmit over telephone line, 2
way radio communication system or can be recorded.
Features:
1. Wide supply voltage range 10-24V
2. Very Linear Modulation characteristics
3. High temperature stability
4. Excellent power supply rejection
5. 10 to 1 Frequency range with fixed C1
6. The frequency can be controlled by means of current, voltage, resistor or capacitor.
 PLL: Low Pass Filter (LPF)

The LPF not only removes high frequency components and noise but also
controls the dynamic characteristics of the PLL includes Capture range,
Lock/Tracking range, Bandwidth and Transient response.
 PLL: Low Pass Filter (LPF)
Active or passive filters can be individually used of may be in
combination.
Active filters have following Advantages and Limitations:
Advantages:
1. They provide voltage gain and, therefore, can furnish wide control
voltage range to the VCO while still maintaining an optimum voltage
level for the detector to interface with.
2. As a loop filter, they are capable for providing the high DC gain and
low input current. This can result in zero static phase error between
Fs and Fo and thus very low error signal energy exist when the loop is
locked
Limitataions:
1. Active filter contributes noise components that can appear on VCO
signal, this troublesome, especially in narrowband FM radios.
PLL: IC LM565 Pin Configuration
PLL: IC LM565 Internal Block
PLL: IC LM565 Specifications
 PLL: Application-AM Detector

The PLL may be used to demodulate AM signal as shown in fig.

The PLL is locked to the Carrier frequency of the incoming AM
signal. Fo=Carrier Frequency (VCO output).
Since the un-modulated AM is fed to the Multiplier through 90º
phase shift network as VCO output (Fo) is always 90º phase
shifted with incoming AM signal under the locked condition.
This makes both the signal applied to the multiplier in same
phase.
 PLL: Application-AM Detector

The output of the multiplier contains both sum (AM+Fo) and

difference (AM-Fo) signals, the demodulated output is obtained
after filtering high frequency signal by LPF. Therefore,
Demodulated output =AM-Fo
AM=Fs+Fc
VCO locked to Fc therefore Fo=Fc
Therefore
Demodulated output =Fs+Fc-Fo=Fs
 PLL: Application-FM Detector

The Un-modulated FM signal (Fc+VmSinωt) and VCO frequency (Fo) which

is locked to the carried frequency (Fc) of the Un-modulated FM signal is
given to the Phase detector of PLL. The output of the Phase detector contains
both sum (Fo+Fc+VmSinωt) and difference (Fo-Fc+VmSinωt) signals, the
demodulated output is obtained after filtering high frequency signal by LPF.
Therefore,
Demodulated output = Fo-Fc+VmSinωt and VCO locked to Fc, therefore, Fo=Fc
Hence
Demodulated FM output =VmSinωt
 PLL: Application-Frequency translator

The Schematic for shifting the frequency of an oscillator by a

small factor is shown in the figure. It can be seen that the Mixer
(multiplier) and a LPF1 is connected externally to the PLL. The
signal Fs which has to be shifted and output frequency Fo of
VCO are applied as inputs to the mixer. The output of the mixer
contains sum (Fo+Fs) and difference (Fo-Fs). However, the LPF
passes only difference (Fo-Fs).
 PLL: Application-Frequency translator

The translation of offset frequency F1 (where F1<<Fs) is applied to the phase

comparator of the PLL. When PLL is in Locked State,
Output of Phase Comparator Sum (Fo-Fs+F1) and Difference (Fo-Fs-F1)
LPF2 passes difference component (Fo-Fs-F1) Therefore, Fo-Fs=F1 (Locked)
Fo=Fs+F1
Thus it is possible to shift incoming frequency Fs by small factor F1