LAPTOP POWER

Sequence

www.shriraminfotech.net
CHIP LEVEL LAPTOP REPAIR
 Laptop Voltage requirement

Supply requirement on motherboard

ADOPTER INPUT VOLT 18V
CPU 1V or
0.8v,1.05v(30amp) MCH 1.05v or
1.5v,1.8v
ICH 1.05 or 1.5v,1.8,3.3v,5v
Vin DDR 2 1.8v,3.3v,0.9v
SIO(KBC) 3.3v
Clock chip 3.3v
BIOS 3.3v
Network chip 3.3v
Batary Charging Voltage 10.8v Audio chip 3.3v
Audio amp 5v
Temp. sensor 3.3v
Card reader 3.3v
LCD supply 3.3v
Hard disk 5.0v
DVD writer 5.0v
USB 5.0
 Volt
In
sectio
n 18volt adopter or
battery supply
DCBAT B++

BEFORE POWER ON

LED
INVERT
ER STEP RUN
VOLTAGE
GFX CPU
CORE CORE
DOWN STEP DOWN VOLT VOLT
1 2

3.3VSUS 5VSUS
1.8V 1.05
1 TO
3.3VOLT 5VOLT 1.2VOLT 1VOLT
1.5V v APPROX APPROX
30AMP
Always voltage
 Laptop power sequence

Always voltage HD
5v D
MOSFET

Step
Down 1
DVD 5v suspend voltage
3.3v ICH W

BAT SIO
AM
T
BIO MOSFET
P
S
US

B
NETWOR LCD VDD AC97 AUDIOCON
Suspend volt
VOLT

K
1.05v 3.3volt suspend voltage
230volt
input

Step MCH ICH

AC Down
Adop 2
1.8v
0.9v DDR2
CPU CORE
volt CPU
(VRM) vcccore

inverter
 CORE i3 Laptop power sequence

Always voltage HD
5v D
MOSFET

Step
Down 1
DVD 5v suspend voltage
3.3v W

BAT SIO
AM
T
BIO MOSFET
P
S
US

B
NETWOR LCD VDD AC97 AUDIOCON
Suspend volt
VOLT

230volt 1.8V
input CPU CORE volt
1.05v (VRM)
AC Step PCH DDR3
Adop Down
2
CPU Core
1.5v
0.75v
GFX Core volt
3.3 volt
susp
end
volt
age

LED
BACKLIGHT
Normal resistance ON coil without CPU & RAM

Above 100
Vin voltage Battery ohm CPU Core
Charging supply
Above 100
ohm

GFX
Above
core
100
3.3volt ohm

1.5vo
Above
100 lt
ohm 1.05v
Above 15 ohm
olt

5volt Above
100
ohm
1.8vo
lt

6
 LAPTOP CHIPS VOLTAGES
2.5V (VDD)
CPU
VCORE (1V
Aprox 30Amp DDR 3.3V LAN 5V
1.25V (VTT ) HDD
current) 1
3.3V (SPD) 3.3V
1.05VCCP
Vtt CPU
1.8V (VDD)
BIO
5V FAN
0.9V (VTT DDR 3.3V S
1.05VCCP or DDR)
MCH 2 AUDIO
1.5v 3.3V (SPD)
Nort DVD
h 5V 5V
1.8V
bridg 1.5V US
3.3V e (VDD) B 3.3
0.75V
DDR V
(VTT ) 3 THERMA
3.3V CAR L
3.3V DDR D 3.3
RTC (SPD) REA
3L DER V
1.05VC
CP 1.35V 3.3V
LC
3.3V (VDD) D/
CLOC 5V
ICH 0.65V (VTT LE
5V ) K
Sou 3.3V
th
brid (SPD)
ge
V IN
3.3V

CORE
GFXCORE1.1V 3.3V
GP i3,i5,i7 1.05V
U
VCORE

3.3V
SI 1.8 GF P 1.05VC 1.5V
GFX
O X COR CP
(KB 1.5 V V CHI E
Core i3 CPU P
1.8V
C
RTC 1.5V
H

7
 CORE I CPU 1st Generation
CPUCORE 1.5volt

GFXCORE 1.05volt

CORE I CPU 2nd & 3rd Generation

CPUCORE
1.5volt
GFXCORE
1.05volt

CORE I CPU 4th & 5th Generation

CPUCORE 1.35volt
GFXCORE
3.3volt 1.05volt
 MOSFET

Drain

N-Channel
Gate
Source

Drain
P-Channel
Gate
Source
1,2
D1

D1
G1
8 1 G1
S1 S1,D2 S1,D2
5
D2
6 G2
G2 7 S2
3 2
S2
4
 Pulse Width Modulator
18 volt
5v DC

Switching AC voltage
Smooth DC voltage

18 volt DC
5 volt DC

A
B 18volt

PWM 5volt
Pulse-width modulation control works by
switching the power supplied on and off
very rapidly. The DC voltage is converted o
t
square-wave signal.
A
B
Sample pulse width modulator

+ve

enable
Output DC

PWM
Power good

-ve

feedback
Components in
power unit capacitor

coil

Mosfet

Diode
 Adopter Input
230volt AC

Batary
Chip manufacturer
Charging v ISL
MAXIM
10.8volt DC
TI
RICHTEK
Adapter Battery

18 volt DC

Volt in output

VIN
B++
 Voltage input and battery charging section VIN(DCBATB++)
Output

CURRENT SENSE RESISTER

1
18V DC 2 5
Adopter
MOSF MOSFET MOSFET
Dc input
ET

Ac ok CSSP CSSN
Dc Power for chip MOSFET
3 Battery
AC in
CELLS

PW
V in
ACPRESENT(AC OK) power MOSFET
4

CONTROL CIRCUIT

LI-ION CELLS
CHGLED SMD 10.8vDC
SIO SM BUS Bat
drv
AC IN SMC

Batt
BATLOW
SMDATA

SMCLOCK SM BUS
TEMP

PCH
 Voltage input and battery charging section
VIN(DCBATB++)
Output

18V DC 1 2 5
Adopter
Dc input MOSF MOSF MOSF
ET ET

Ac ok CSSP CSSN
Dc Power for chip MOSFET
3 Battery
AC in
CELLS

V in
ACPRESENT(AC OK) power MOSF
4

CONTROL CIRCUIT

LI-ION CELLS
CHGLED SMD 10.8vDC
ET
SIO SM BUS Bat
drv
AC IN SMC

Batt
BATLOW
SMDATA

SMCLOCK SM BUS
TEMP

PCH
 Not powering on
VIN(DCBATB++) battery
Output
1 2 5
Adopter 18V DC
Dc input MOSF MOSF MOSF
ET ET

Batt. drv
Ac ok CSSP CSSN

Not working on adopter

Dc Power for chip MOSFET
3 Battery
AC in

V in
ACPRESENT(AC OK) power MOSF
4

CONTROL CIRCUIT

LI-ION CELLS
CHGLED 10.8vDC
SMD ET
SIO SMC
Bat
drv

Batt

BATLOW
SMDATA

SMCLOCK SMBUS
TEMP

ICH
Battery not detecting
Communication between sio & battery Battery not charging
adopter

battery
Some sample chip
 Up to C2D CPU
3volt VCC 1
(cpu)
32.7KHZ
BIOS VR_ON (B

KBC_PWRBTN PWR_ON ( main_on, Run on)

SIO
3
6 SUSp_ON
2
4 5

PM_PWRBT

PM_SLP_

PM_SLP_
3 VOLT
RSMR

S3

S4
VCC

RSMRST

PWRBTN

ICH PM_PWRBTN

SLP_S3

SLP_S4
POWER ON BUTTON SEQ.
 STEP 2 TURN ON
CPU CORE ON
SLP_S4
SIO RSMRST

POWER BUTTON

ADOPTAR PRESENT

POWER BUTTON
TO PCH
SUSPEND ON
 3volt VCC
32.7KHZ
Pin No 8 1
EC BIOS

VR_ON (cpu)

PWR_ON (Bridge, Ram supply)

2 7
KBC_PWRBTN Main on(sys on)
SI
SUSP_ON
4 3
RSMR

PM_PWRBT
5 6

PM_SLP_
PM_SLP_S3
susb

S4

PC
POWER ON BUTTON SEQ.
 Presenter
2016-04-07 23:46:38
--------------------------------------------
Approved molly, ramey, morhardt,
bettencourt, tucker 3/25 Includes small
and large business

Core i3 power sequence

SW

1 SW

R304 Y1

C345
SIO R491 R490 R503
ITE-8518 R105

PCH
9
SUS_ON

RUN_ON
10
1
EC_PWROK313 HWPG
VR_ON
1211
 Step down 1 voltage(always voltage)

V+ vin
18
v
LD05
LD03(VREG3) (VREG5)
3v Linear 5v Linear
regulator regulator

18v 18v
Vcc 5V

MOSFET
UG v UG
MOSFET 5VALW
3VALW
3.3v 5v
3volt Osc Osc
LG PWM PWM LG
MOSFET
BIOS MOSFET

3 On 5 on

PG signal
SIO
Enable
 Step down 1 voltage(always voltage)

V+ vin
18
v
LD05
3volt LD03(VREG3) (VREG5)
3v Linear 5v Linear
regulator regulator
SIO 18v
Vcc 5V

su
MOSFET
v MOSFET
su

UG UG
3VS 3VALW 5VALW 5VS
MOSFET 3.3v 5v MOSFET
Osc Osc
LG PWM PWM LG
MOSFET
MOSFET

3 On 5 on

PG signal
VIN VOLTAGE Linear output
 Step down 1 voltage(always voltage)

V+ in

3v Out 5v Out LD05

LD03

Vcc

v 3VALW
5VALW
5v 3v
Osc Osc
PWM PWM

3 On 5 on

Microcontroll
PG signal

Enable
 Step down 2
1.8V & 1.05v voltage
V+ in

1.8 VOLT
OR
1.5 VOLT 0R
SIO ENABLE
1.05v 1.05V0LT

osc
Power Good
 RAM VTT Voltage
1.8V OR 1.5V 0.9V or 0.75

VTT Enable
 CPU Core voltage
5Volt

V IN
1v 30Amp

VR_ON PWM

SIO

CPU VCORE
VRM PWRGD VRM CCPPUU
V INV

PWM

CLK ENABLE

VID signal
Core i3 VRM 1 Vin voltage

section
5vo
lt
VCC CPU core

2
3
From SIO 1 v to 1.5v
VR_ON

6 VRM
5
To SIO Clock Core v
enable
4
6
VRM
power Core i3
good CPU
VID signal from

GFX Core
GND
32
 230v AC
Power Block Diagram
CPU Core
volt
0.8 v or 1v VCORE

Battery Adopter 17
18
1

0.9 v
Volt In
Step down
2
1.8v
1.05v
14
SM

2 15
CHG_ENAB

MOSFET 3.3vSUS

On\off
VR_ON
12
switch 16 5vSUS
13 MOSFET
SYS_ON
Enab

8 11
SUSP

(SIO) 4 SLP_S5 Step 3.3VALWS

Enab VRMPWRGD down 5 5VALWS
1
sig
KBC
PG

3v supply 3VL
6 3
ICH
32.7khz

PG 9 19 P3,SLP4,
P W RB T
si
N
l g n a EC_PWRGD(PWRGD)
S
1 0
3 vo lt L
 RSMRST 7
PWRBTN
 SUS_PWRGD
MAIN_PWRGD Power Block Diagram
GFX_PWRGD 230v AC
CPU Core 0.8v or 1v VCORE
volt
18
Battery Adopte
r
1
GFX 15
Volt In
1.8v
CHG_ENABLE

Step down
2 1.05v 13
SM

0.9v
AC

2 15

MOSFET 3.3vSUS
VR_ON 17

14
16
GFX_ON
11
5vSUS
SYS_on(Run1o
MOSFET
Enab

HWPG
2n) SUSP 10
SIO Step 3.3VALWS
Enab 19 VRMPWRGD down 5 5VALWS
1
KBCsig
SLP_S5 4 3
ICH
32.7khz

3v supply
RSMRST 6
On\off
PG 8 9
P W RB T 3 vo lt
switch si
l g n a
N
20
SLP3,SLP4,
7
ECP PM_PWRBTN
WRO
K(PW
R_GD
)
battery

Li-ion 3.6V 4500 Times charge/discharge

3.6v 3.6v 3.6v

2Amp

2Amp
3.6v 3.6v 3.6v

10.8volt 4amp
Battery connector

1 2 3456
Pin Signal Description Type
1 GND Ground

2 Temp Temperature I
monitor
3 Clock SM Bus I/O
4 Data SM Bus I/O
5 NC No Connection
6 BAT_S Positive voltage power
In side the battery
clock
SM Bus data
Interface
Temp sense

Dis-charging

Battery +ve
Sense &
control
-ve
charging

Battery
connector

Li-ion cell
 Laptop Power
ALWAYS ON SUS_POWER POWER ON VRON

5V_AUX 5V
ICH ICH FAN
USB HDD
DVDW AUDIO
AC
ADOPTER
V IN 3.3V_AUX 3.3V

BATTARY ICH ICH BIOS CLOCK

LAN LCD
THERMAL HDD
DDR2
1.8V
3.3V_ALWS
0.9V
MICOM
DDR2 VTT
5V_ALWS

1.05V
ICH MCH

CPU CORE

S4 / S5 S3 S0
 POWER RAIL

INPUT SUPPPLY VIN

BATT 0r ADOPT B+
Linear output 3VL
pwm always voltage out 5VALW/3VALW
RSMRST from kcb to ich RSMRST

user press on button ON/OFF

pwrbtn signal to ich PWRBTN

ich to SIO SLP_S5

ich to SIO SLP_S4
SIO to power SYSON
1.8V
ich to SIO SLP_S3
kbc to power SUSP
5VS/3VS/1.05VS
kbc to power VR_ON
CPU_CORE
VRM Chip to KBC VRMPWRGD

KBC TO ICH CLPWROK) M_PWROK

Clock reset CL_RST
Clock power good CL_PWRGD
KBC TO MCH PM_PWROK
ICH TO CPU H_PWRGOOD
ich to mch PLT_RST (PCI_RST)
mch to cpu RESET
 POWER ON AND RESET SEQUENCE

18v adopter 10.8 Battary

Input Input 8
ON/OFF SLP4
SW 10
SLP3
Clock start

V In
PM_PWRBTN Clock 20
ACIN 9
CPU 23
SIO RSMRST
19
CORE_V
17 CPU_PWRGD

16 7

CK_PWR
HWPG 15 22 M_PWRGD

1 SYS_ON (MAIN ON) 13 25

CPU
21 ECPWORK

CPU_PWR
RST
CKT KBC_RST
PLTRST
3

VRMPW MCH
KBC_3D3_AL

RGD North Bridge

6
BIOS
SUS

2 RSTIN CL_RST
(VGATE)
4
SLP_
PWR

11
Step 6 24
down 12 PLTRST
3.3v_ALWS 3.3V_SUSP
1 5 CL_RST
5V_ALWS 5v_SUSP CLK_PWRGD

SLP4/ 5
1.8v SLP3
Step To DDR
Down 0.9v 14
PWROK
15
2 1.05V 7 RSMRST
PWROK
ICH 23
South Bridge
3.3V

VR_ON 1.05V
w.shriraminfo CPU
tech.net Core
ww
17 CPU_CORE

VRMPWRGD 18
VRMP
WRG
D
WIFI Card Test Point

CLJ 33MHZ
11

16
22
PLTRST
SM BUS
30,32
 CPU RESET
R322

CPU
SIO

R313

R605

PCH
ECPWROK
ADOPTER Battery
ALWS PWRGD
CLOCK
MAIN PWRGD
SUS PWRGD HWPG

PWRBTN 18
ACIN
13
3
Slp _S5
Ste

PLTR
20

DRAM
2 ECPWORK 19 21

CPU
1
p
do
3.3VAL 22
EC BIOS
wn SUSB, SLP_S3
5V SUSC, SLP_S4 8 PCH
4 PM_PWRBTN 7
SUS

MOSFET

MOSFET
RSMRST
6
3.3V
5V
5
9 MAINON
Ste 10 1.05V(PCH, CPU)
p 1.5V(DDR3)
Do
wn 1.8V
14
11 GFX ON

15
VR_PWRG

GFX
CORE GFXCORE V
16
12
VR_ON
CK_PWRGD
CPUCORE V
 BIOS
CS
23
CLOCK CHIP
ADOPTER Battery
ALWS
CLOCK
PWRGD MAIN PWRGD HWP
SUS PWRGD G
PWRBT
N
ACIN 13
SLP _S5
3 21 20
Step

DRAM
PLT
dow
19

CPU
ECPWORK
1 n1 3.3VAL 2 2
SUSB, SLP_S3

5V SUSC, SLP_S4 8 PCH

4
SUS

MOSFET
PM_PWRBTN 7

MOSFET
RSMRST
6
Step
Dow
5 3.3V

n2
9 MAINON
1.05V(PCH,
CPU)
10

1.5V(DDR3)

GFX ON 14
 11 16
GFX

VR_PW
COR GFXCORE V
E 12
VR_ON
CPUCORE
CP V
U 15 1
Cor
7
e 47
CK_PWRGD
from
COMPAL 4TH GEN. CPU POWER ON SEQ.

Adopter present
ACIN
3volt linear
+3VLP
SIO turn on
EC_ON

3VALW 3.3volt

5volt
5VALW
Always voltage power good to SIO
SPOK

1VALW 1volt

1.8volt
1.8VALW

ON\OFF BTN
POWER BTN

SIO RSMRST Resume & Reset siganl

Power button out from SIO to PCH

PBTN_OUT

CPU Power on s4 state from PCH to SIO

SLP_S4

CPU SLP_S3 Power on s4 state from PCH to SIO

SYSON System on signal from SIO

1.35V 1.35 volt
 DDR_PWROK VR_ON
+SOC_VCC
Core volt turn on

+SOC_VNN VGATE
SUSP#

Suspend voltage enable

+1.0VS
+1.05VS

+1.35VS

+1.5VS

+1.8VS

+3VS

+5VS
KBRST#

PMC_CORE_PWROK

DDR_CORE_PWROK DDR POWER OK

PLTRST# Platform Reset

 Volt IN 14.3MHZ CRYSTAL

Charging
Tem
p

CPU SENSE

230v AC CP
1v
U Clock
CPU CORE
V

CPU_Re
5 VOLT
STEP
DOWN Analog
3.3 VOLT VOLT RGB o/p

3.3V MCH
1.05v
Step down 2
1.8v

Reset m/b
3.3v Cmos

PLT_Re
Bat

32.7khz crystal

res
ICH
PG Signal

CPU
FAN

AMP

camera Netwo
BIOS USB