Central

Processing unit:-

- A central processing unit, also called a central processor or main processor, is the electronic circuitry
within a computer that executes instructions that make up a computer program.
- The CPU performs basic arithmetic, logic, controlling, and input/output operations specified by the
instructions.

Features of Central Processing Unit (CPU):

1. CPU is considered as the brain of the computer.
2. CPU performs all types of data processing operations.
3. It stores data, intermediate results, and instructions (program).
4. It controls the operation of all parts of the computer.
CPU has three components.
i. Memory or Storage Unit
ii. Control Unit
iii. ALU(Arithmetic Logic Unit)
General Register organization:

Bus organizations for seven CPU register. The output of each register is connected to two
multiplexer from the two buses A and B. the selection lines in each multiplexer select one
register or the input data for the particular bus. The A and B buses from the inputs to a common
ALU.The control unit must provide binary selection variables have following selector variable.

1. MUX A selector(SELA):- to place the content of of R2 into BUS A

2. MUX B selector(SELB):- to place the content of R3 into BUS B
3. ALU Operation selector (OPR): to provide the arithmetic addition A+B
4. Decoder (3x8) destination selector (SELD): to transfer the content of the output bus R1.

Example: R1 <- R2 + R3
i. MUX A selector (SELA): BUS A R2
ii. MUX B selector (SELB): BUS B R3
iii. ALU operation selector (OPR): ALU to ADD
iv. Decoder destination selector (SELD): R1 Out Bus

Encoding of register selection fields

 CPU Organizations
There are three types of CPU organization based on the instruction format
1. Single accumulator organization
- In this type of organization all the operations are performed with an implied/indirect
accumulator register.
- Basic computer is the good example of single accumulator organization.
- The instruction of this type of organization has an address field
E.g. ADD X AC←AC+M[X] where X is the address of the operand
2. General register organization
- When a large number of processor registers are included in the CPU, it is most efficient
to connect them through a common bus system. The registers communicate with each
other not only for direct data transfer, but also while performing various microoperations.
Hence, it is necessary to provide a common unit that can perform all the arithmetic, logic
and shift microoperations in the processor.
- In this type of organization the instruction has two or three address field.

3. Stack organization
- A stack is a storage device that stores information in such a manner that the item stored
last is the first item retrieved.
- In stack the data can be operate Last-in, first-out (LIFO) mechanism/process.
- In this type of organization of CPU, all the operations are performed with stack.
- The PUSH and POP instruction only need address field. The operation-type instructions
do not need address field.
- Stack is an ordered collection of items in to which new items may be
inserted and from which items may be delete at one end, called tope of the
stack.
 - PUSH X
Pros: Easy to implement. Memory is saved as pointers are not involved.
Cons: It is not dynamic. It doesn’t grow and shrink depending on needs at
runtime.
Mainly the following three basic operations are performed in the stack:
- Push: Adds an item in the stack. If the stack is full, then it is said to be an
Overflow condition.
- Pop: Removes an item from the stack. The items are popped in the
reversed order in which they are pushed. If the stack is empty, then it is
said to be an Underflow condition.

Push Operation:-
If (top == (arraysize-1)]
Printf(“stack over flow”);
Else
{
Top == top + 1;
Stack_arr[top] = pushed –item;
}
Pop Operation:-
If (top ==-1)
Printf(“stack underflow”);
Else
{
Printf(“Poped element is %d”,stack_arr[top]);
}

E.g. PUSH X TOS←M[X]

POP X M[X] ←TOS
ADD
Register Stack/Stack organization:-
 - A stack is a storage device that stores information in such a manner that the item stored
last is the first item retrieved.
- The stack in digital computers is essentially a memory unit with an address register that
can count only. The register that holds the address for the stack is called a stack pointer
(SP) because its value always points at the top item in the stack.
- The physical registers of a stack are always available for reading or writing. It is the
content of the word that is inserted or deleted.

Fig:Block diagram of a 64-word stack

- A stack can be placed in a portion of a large memory or it can be organized as a
collection of a finite number of memory words or registers. The above Figure shows the
organization of a 64- word register stack.
- The stack pointer register SP contains a binary number whose value is equal to the
address of the word that is currently on top of the stack. Three items are placed in the
stack: A, B, and C, in that order. Item C is on top of the stack so that the content of SP is
now 3.
- To remove the top item, the stack is popped by reading the memory word at address 3
and decrementing the content of SP. Item B is now on top of the stack since SP holds
address 2.
- To insert a new item, the stack is pushed by incrementing SP and writing a word in the
next-higher location in the stack.
- In a 64-word stack, the stack pointer contains 6 bits because 26 = 64. Since SP has only
six bits, it cannot exceed a number greater than 63 (111111 in binary).
- When 63 are incremented by 1, the result is 0 since 111111 + 1 = 1000000 in binary, but
SP can accommodate only the six least significant bits.
- DR is the data register that holds the binary data to be written into or read out of the
stack.
PUSH:
 - If the stack is not full (FULL =0), a new item is inserted with a push operation. The push
operation consists of the following sequences of microoperations:
SP ← SP + 1 Increment stack pointer
M [SP] ← DR WRITE ITEM ON TOP OF THE STACK
IF (SP = 0) then (FULL ← 1) Check is stack is full
EMPTY ← 0 Mark the stack not empty
- The stack pointer is incremented so that it points to the address of next-higher word. A
memory write operation inserts the word from DR into the top of the stack.
- SP holds the address of the top of the stack and that M[SP] denotes the memory word
specified by the address presently available in SP.
POP:
- A new item is deleted from the stack if the stack is not empty (if EMTY = 0). The pop
operation consists of the following sequences of micro-operations:
DR ← M [SP] Read item on top of the stack
SP ← SP - 1 Decrement stack pointer
IF (SP = 0) then (EMPTY ← 1) Check if stack is empty
FULL ← 0 Mark the stack not full

Memory Stack:-

Fig: Memory Stack

- The program counters PC points at the address of the next instruction in the program
which is used during the fetch phase to read an instruction.
 - The address registers AR points at an array of data which is used during the execute
phase to read an operand.
- The stack pointer SP points at the top of the stack which is used to push or pop items into
or from the stack.
- The three registers are connected to a common address bus, and either one can provide
an address for memory.

Instructions Format:-

The most common fields are found in instructions formats are:

1. OP-code field - specifies the operation to be performed

2. Address field - designates memory address(s) or a processor register(s)
3. Mode field - specifies the way the operand or the effective address is determined.
The number of address fields in the instruction format depends on the internal organization of
CPU

Three Address Instructions format:-

The three address instructions formats can used each address field to specify a processor register
or a memory operand. The program of assembly level language that evaluates x=(A+B)*(C+D):

[See copy]

Addressing Modes
- The method of calculating or finding the effective address of the operand in the
instruction is called addressing mode.
- Effective address means the memory address where the required operand is located.
- The addressing mode specifies the rule interpreting or modifying the address field of the
instruction before the operand is actually referenced. The various addressing modes are:
i. Implied Mode
ii. Immediate Mode
iii. Register Mode
iv. Register Indirect Mode
v. Auto increment or Auto decrement Mode
vi. Direct Address Mode
vii. Indirect Address Mode
viii. Relative Address Mode
ix. Base Register Addressing Mode

Implied Mode
- In this type of addressing mode, operands specified implicitly in the definition of
instruction.
 - All the register reference instructions that use an accumulator and zero-address
instruction in a stack organized computer are implied mode instruction.
- E.g. CMA (complement accumulator)
Immediate Mode
- In this addressing mode, the operand is specified in the instruction itself i.e. there is no
any address field to represent the operand
- Immediate mode instructions are useful for initializing register to a constant value.
- E.g. LD #NBR / ACNBR
Register Mode
- In this type of addressing mode, the operands are in the register which is within the CPU
- E.g. LD R1 / ACR1
Register Indirect Mode
- In this addressing mode, the content of register present in the instruction specifies the
effective address of operand.
- The advantage of this addressing mode is that the address field of the instruction uses
fewer bits to select a register than would have been required to specify a memory address
directly. E.g. LD (R1) / ACM[R1]
Auto Increment or Auto Decrement Mode
- In auto increment mode, the content of CPU register is incremented by 1, which gives
the effective address of the operand in memory.E.g.LD (R1)+ / ACM[R1], R1R1 + 1
- In auto decrement mode, the content of CPU register is decremented by 1, which gives
the effective address of the operand in memory. E.g. LD (R1)- / ACM[R1 - 1]
Direct Address Mode
- In this addressing mode, the address field of an instruction gives the effective address of
operand. E.g. LD ADR / ACM[ADR]
Indirect Address Mode
- In this addressing mode, the address field of the instruction gives the address of effective
address. E.g. LD @ADR / ACM[M[ADR]]
Relative Address Mode
- In this addressing mode, the content of program counter is added to the address part of
the instruction which gives the effective address of the operand.
- Assume that the PC is 500 and the address part of instruction is 50. The instruction at
location 500 is read from memory during fetch phase and PC is then incremented by 1.
Hence, PC is 501, then effective address is 501+50=551. E.g. LD $ADR / ACM[PC +
ADR]
Base Register Addressing Mode
- In this addressing mode, the content of the base register is added to the address part of the
instruction which gives the effective address of the operand.
- E.g. LD ADR(B) / ACM[ADR + BR]

Data Transfer Instructions.

- Data transfer instructions move data from one place in the computer to another without
changing the data content.
- The most common transfers are between memory and processor registers, between
processor registers and input or output, and between the processor registers themselves.
- The load instruction has been used mostly to designate a transfer from memory to a
processor register, usually an accumulator.
- The store instruction designates a transfer from a processor register into memory.
- The move instruction has been used in computers with multiple CPU registers to
designate a transfer from one register to another. It has also been used for data transfers
between CPU registers and memory or between two memory words.
- The exchange instruction swaps information between two registers or a register and a
memory word.
- The input and output instructions transfer data among processor registers and input or
output terminals.
- The push and pop instructions transfer data between processor registers and a memory
stack.
RISC and CISC characteristics
RISC (reduced instruction set computer) characteristics
- Relatively few instructions
- Relatively few addressing modes
- Memory access limited to load and store instructions
- All operations done within the registers of the CPU
- Fixed-length, easily decoded instruction format
- Single-cycle instruction execution
- The control unit is hardwired rather than micro programmed
- Relatively large number of registers in the processor unit
- Efficient instruction pipeline
CISC (complex instruction set computer) characteristics
- A large number of instructions - typically from 100 to 250 instructions
- Some instructions that perform specialized tasks and are used infrequently
- A large variety of addressing modes – typically from 5 to 20 different modes
- Variable-length instruction format
- Uses memory to load and store instruction and operand as well
- Instructions that manipulate operands in memory

PROGRAM INTERRUPT:
 - The concept of program interrupt is used to handle a variety of problems that arise out of
normal program sequence.
- Program interrupt refers to the transfer of program control from a currently running
program to another service program as a result of an external or internal generated
request. Control returns to the original program after the service program is executed.
- After a program has been interrupted and the service routine been executed, the CPU
must return to exactly the same state that it was when the interrupt occurred.
- Only if this happens will the interrupted program be able to resume exactly as if nothing
had happened.
- The state of the CPU at the end of the execute cycle (when the interrupt is recognized) is
determined from:
1. The content of the program counter
2. The content of all processor registers
3. The content of certain status conditions
- The interrupt facility allows the running program to proceed until the input or output
device sets its ready flag. Whenever a flag is set to 1, the computer completes the
execution of the instruction in progress and then acknowledges the interrupt.
- The result of this action is that the retune address is stared in location 0. The instruction
in location 1 is then performed; this initiates a service routine for the input or output
transfer. The service routine can be stored in location 1.
- The service routine must have instructions to perform the following tasks:
1. Save contents of processor registers.
2. Check which flag is set.
3. Service the device whose flag is set.
4. Restore contents of processor registers.
5. Turn the interrupt facility on.
6. Return to the running program
Types of interrupts.:
There are three major types of interrupts that cause a break in the normal execution of a program.
They can be classified as:
1. External interrupts
2. Internal interrupts
3. Software interrupts
1. External interrupts:
- External interrupts come from input-output (I/0) devices, from a timing device, from a
circuit monitoring the power supply, or from any other external source.
- External interrupts are asynchronous. External interrupts depend on external conditions
that are independent of the program being executed at the time.
2. Internal interrupts:
- Internal interrupts arise from illegal or erroneous use of an instruction or data. Internal
interrupts are also called traps.
- Internal interrupts are synchronous with the program. . If the program is rerun, the
internal interrupts will occur in the same place each time.
3. Software interrupts:
 - A software interrupt is a special call instruction that behaves like an interrupt rather than
a subroutine call. It can be used by the programmer to initiate an interrupt procedure at
any desired point in the program.
- The most common use of software interrupt is associated with a supervisor call
instruction.
- This instruction provides means for switching from a CPU user mode to the supervisor
mode.

Computer Organization | Hardwired v/s Micro-programmed Control Unit

To execute an instruction, the control unit of the CPU must generate the required control signal
in the proper sequence. There are two approaches used for generating the control signals in
proper sequence as Hardwired Control unit and Micro-programmed control unit.
Hardwired Control Unit –
The control hardware can be viewed as a state machine that changes from one state to another in
every clock cycle, depending on the contents of the instruction register, the condition codes and
the external inputs. The outputs of the state machine are the control signals. The sequence of the
operation carried out by this machine is determined by the wiring of the logic elements and
hence named as “hardwired”.
 Fixed logic circuits that correspond directly to the Boolean expressions are used to generate
the control signals.
 Hardwired control is faster than micro-programmed control.
 A controller that uses this approach can operate at high speed.
 RISC architecture is based on hardwired control unit

Micro-programmed Control Unit –

 The control signals associated with operations are stored in special memory units
inaccessible by the programmer as Control Words.
 Control signals are generated by a program are similar to machine language programs.
 Micro-programmed control unit is slower in speed because of the time it takes to fetch
microinstructions from the control memory.
Some Important Terms –
 1. Control Word : A control word is a word whose individual bits represent various control
signals.
2. Micro-routine : A sequence of control words corresponding to the control sequence of a
machine instruction constitutes the micro-routine for that instruction.
3. Micro-instruction : Individual control words in this micro-routine are referred to as
microinstructions.
4. Micro-program : A sequence of micro-instructions is called a micro-program, which is
stored in a ROM or RAM called a Control Memory (CM).
5. Control Store : the micro-routines for all instructions in the instruction set of a computer
are stored in a special memory called the Control Store.

Types of Micro-programmed Control Unit – Based on the type of Control Word stored in the
Control Memory (CM), it is classified into two types :
1. Horizontal Micro-programmed control Unit :
The control signals are represented in the decoded binary format that is 1 bit/CS. Example: If 53
Control signals are present in the processor than 53 bits are required. More than 1 control signal
can be enabled at a time.
 It supports longer control word.
 It is used in parallel processing applications.
 It allows higher degree of parallelism. If degree is n, n CS are enabled at a time.
 It requires no additional hardware(decoders). It means it is faster than Vertical
Microprogrammed.
 It is more flexible than vertical microprogrammed
2. Vertical Micro-programmed control Unit :
The control signals re represented in the encoded binary format. For N control signals- Log2(N)
bits are required.
  It supports shorter control words.
 It supports easy implementation of new conrol signals therefore it is more flexible.
 It allows low degree of parallelism i.e., degree of parallelism is either 0 or 1.
 Requires an additional hardware (decoders) to generate control signals, it implies it is
slower than horizontal microprogrammed.
 It is less flexible than horizontal but more flexible than that of hardwired control unit.
Interrupts
Interrupt is a signal emitted by hardware or software when a process or an event needs
immediate attention. It alerts the processor to a high priority process requiring interruption of the
current working process. In I/O devices one of the bus control lines is dedicated for this purpose
and is called the Interrupt Service Routine (ISR).
When a device raises an interrupt at lets say process i, the processor first completes the execution
of instruction i. Then it loads the Program Counter (PC) with the address of the first instruction
of the ISR. Before loading the Program Counter with the address, the address of the interrupted
instruction is moved to a temporary location. Therefore, after handling the interrupt the processor
can continue with process i+1.
While the processor is handling the interrupts, it must inform the device that its request has been
recognized so that it stops sending the interrupt request signal. Also, saving the registers so that
the interrupted process can be restored in the future, increases the delay between the time an
interrupt is received and the start of the execution of the ISR. This is called Interrupt Lattency.

Hardware Interrupts:
In a hardware interrupt, all the devices are connected to the Interrupt Request Line. A single
request line is used for all the n devices. To request an interrupt, a device closes its associated
switch. When a device requests an interrupts, the value of INTR is the logical OR of the requests
from individual devices.
Sequence of events involved in handling an IRQ:
1. Devices raise an IRQ.
2. Processor interrupts the program currently being executed.
3. Device is informed that its request has been recognized and the device deactivates the
request signal.
4. The requested action is performed.
5. Interrupt is enabled and the interrupted program is resumed.
Handling Multiple Devices:
When more than one device raises an interrupt request signal, then additional information is
needed to decide which which device to be considered first. The following methods are used to
decide which device to select: Polling, Vectored Interrupts, and Interrupt Nesting. These are
explained as following below.
1. Polling:
In polling, the first device encountered with with IRQ bit set is the device that is to be
serviced first. Appropriate ISR is called to service the same. It is easy to implement but a
lot of time is wasted by interrogating the IRQ bit of all devices.
 2. Vectored Interrupts:
In vectored interrupts, a device requesting an interrupt identifies itself directly by sending a
special code to the processor over the bus. This enables the processor to identify the device
that generated the interrupt. The special code can be the starting address of the ISR or
where the ISR is located in memory, and is called the interrupt vector.
3. Interrupt Nesting:
In this method, I/O device is organized in a priority structure. Therefore, interrupt request
from a higher priority device is recognized where as request from a lower priority device is
not. To implement this each process/device (even the processor). Processor accepts
interrupts only from devices/processes having priority more than it.
Processors priority is encoded in a few bits of PS (Process Status register). It can be changed by
program instructions that write into the PS. Processor is in supervised mode only while executing
OS routines. It switches to user mode before executing application programs.