CS212

Computer Organization

UNIT-2
Processor Organization & Control Design
CENTRAL PROCESSING UNIT

• Introduction
• Single Accumulator Organization
• General Register Organization
• Stack Organization
• Instruction Formats
• Addressing Modes
• Single Bus Architecture
• Computer Instructions
• Instruction Cycle
• Hardwired Control Unit
 Introduction
• The part of computer that performs bulk of data processing operations is called the
central processing unit and is referred to as the CPU.
• It consists of 3 major parts:
i) ALU (Arithmetic and Logical Unit)
ii) CU (Control Unit)
iii) Register Set
• Register set stores intermediate data used
during the execution of instructions.
• ALU performs the required microoperations for executing the instructions.
• Control unit supervises the transfer of information among registers and instructs the ALU
as to which operation to perform.
 Different types of registers
We assume that we are having a computer with a memory of 4096 words of 16 bits each-

• Accumulator Register(AC): The accumulator register is located inside the ALU, It is used during
arithmetic & logical operations of ALU. The control unit stores data values fetched from main
memory in the accumulator for arithmetic or logical operation. This register holds the initial data
to be operated upon, the intermediate results, and the final result of operation. Size of AC is 16
bits.
• Program Counter (PC): Program Counter register is also known as Instruction Pointer Register.
This register is used to store the address of the next instruction to be fetched for execution. When
the instruction is fetched, the value of IP is incremented. Thus this register always points or holds
the address of next instruction to be fetched. Size of PC is 12 bits.
• Instruction Register (IR): Once an instruction is fetched from main memory, it is stored in the
Instruction Register. The control unit takes instruction from this register, decodes and executes it
by sending signals to the appropriate component of computer to carry out the task. Size of IR is
16 bits.
 Different types of registers contd..

• Address Register (AR): This register holds the address of memory where CPU wants to read or
write data. When CPU wants to store some data in the memory or reads the data from the
memory, it places the address of the required memory location in the AR. Size of AR is 12 bits.
• Data Register(DR): This register is used to store memory operands. Size of this register is 16 bits.
• Temporary Register(TR): It is used to store the temporary data at the time of the execution. Size
of this register is 16 bits.
• Input Register(INPR): It is holds the data from an input device. Size of this register is 8 bits.
• Output Register(OUTR): It holds the data that needs to be sent to an output device. Size of this
register is 8 bits.
 Different types of CPU organization

The number of address fields in the instruction format of a computer depends on

the internal organization of its registers. Most computers fall into one of the three
types of CPU organizations:
1. Single Accumulator Organization
2. General Register Organization
3. Stack Organization
 1. Single Accumulator Organization
The computers, present in the early days of computer history, had accumulator based CPUs. In this
type of CPU organization, the accumulator register is used implicitly for processing all instructions of
a program and store the results into the accumulator. The instruction format that is used by this
CPU Organization is One address field. Due to this the CPU is known as One Address Machine.
The main points about Single Accumulator based CPU Organization are:
• In this CPU Organization, the first ALU operand is always stored into the Accumulator and the
second operand is present either in Registers or in the Memory.
• Accumulator is the default address thus after data manipulation the results are stored into the
accumulator.
• One address instruction is used in this type of organization.
• It uses LOAD and STORE instructions for data transfer: e.g. LOAD X, STORE Y

Here LOAD is memory read operation that is data is transferred from memory location X to accumulator and
STORE is a memory write operation that is data is transferred from accumulator to memory location Y.
 2. General Register Organization
When we are using multiple general purpose registers, instead of single accumulator register, in the
CPU Organization then this type of organization is known as General register based CPU
Organization.
• In this type of organization, computer uses two or three address instruction format. Each address
field may specify a general register or a memory word.
Following components are used to design a general register organization circuit:
• Seven CPU registers R0,R1………..R7
• Two multiplexer sets of size 8x1 named as MUX A and MUX B are used to form two buses, BUS A
and BUS B
• ALU is used for calculation of arithmetic and logical operations. Output of BUS A and BUS B is
connected to ALU
• A 3x8 decoder is used to activate the load lines of seven registers for storing purpose
• Combination of SEL A, SEL B, SEL D and OPR fields is known as control word. Size of control word
is 14 bits(3+3+3+5)
 General Register Organization Circuit
Input
Clock

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB

3x8
A bus B bus
decoder

SELD
OPR ALU

Output
General Register Organization Contd..
 Operation of Control Unit
Example: R1 <- R2 + R3
[1] MUX A selector (SELA):
BUS A  R2
[2] MUX B selector (SELB):
BUS B  R3
[3] ALU operation selector
3
(OPR):
3 3 5
ALU to ADD
Control Word
[4] Decoder destination
SELA selector
SELB (SELD):
SELD R1  Out Bus
OPR
 3. Stack Organization
• The computers which use Stack-based CPU Organization are based on a data structure
called stack.
• The stack is a list of data words. It uses Last In First Out (LIFO) access method which is the most
popular access method in most of the CPU. A register is used to store the address of the topmost
element of the stack which is known as Stack pointer (SP).
• In this organization, ALU operations are performed on stack data. It means both the operands are
always required on the stack. After manipulation, the result is placed in the stack.
• The main two operations that are performed on the operators of the stack are Push and Pop.
These two operations are performed from one end only.
• Stack organization uses zero address instruction format.
• Stack can be formed in two ways:
i. Register Stack
ii. Memory Stack
 Register Stack
• A stack can be placed in a portion of a large memory or it can be organized as a collection of a finite
number of memory words or registers.
• Figure shows the organization of a 64-word register stack.
• The stack pointer register SP contains a binary number whose value is equal to the address of the word
that is currently on top of the stack. Three items are placed in the stack: A, B, and C, in that order. Item C
is on top of the stack so that the content of SP is now 3.
PUSH Operation Underflow(Initial Condition)
SP ← SP + 1 Increment stack pointer FULL  0
M[SP] ← DR Write item on top of the stack EMTY  1
If (SP = 0) then (FULL ←1) Check if stack is full
EMTY ← 0 Mark the stack not empty

POP Operation Overflow condition

DR ← M[SP] Read item from the top of stack FULL  1
SP ← SP - 1 Decrement stack pointer EMTY  0
If (SP = 0) then (EMTY ← 1) Check if stack is empty
FULL ← 0 Mark the stack not full
 Memory Stack
• A stack can exist as a stand-alone unit as in or can be implemented in a random-access memory attached to
a CPU. The implementation of a stack in the CPU is done by assigning a portion of memory to a stack
operation and using a processor register as a stack pointer.
• Figure shows a portion of computer memory partitioned into three segments: program, data, and stack. The
program counter PC points at the address of the next instruction in the program. The address register AR
points at an array of data.
• No provisions are available for stack limit checks.
• The stack pointer SP points at the top of the stack.
• The three registers are connected to a common address bus,
and either one can provide an address for memory.
• The initial value of SP is 4001 and the stack grows with decreasing
addresses. The first item is stored at 4000.

PUSH Operation POP Operation

SP  SP – 1 DR  M[SP]
M[SP]  DR SP  SP + 1
 Instructions Formats

• The format of an instruction is usually depicted in a rectangular box symbolizing the bits of the
instruction as they appear in memory words or in a control register. The bits of the instruction are
divided into groups called fields. The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor registers.
3. A mode field that specifies the way the operand or the effective address is determined.
Based on number of address fields used in the instruction, there can be 4 types of instruction
formats:
• Zero Address Instruction (Stack Organization)
• One Address Instruction (Single Accumulator Organization)
• Two Address Instruction (General Register Organization)
• Three Address Instruction (General Register Organization)
 One-address Instructions
• One-address instructions use an implied accumulator (AC) register for all data manipulation. For
multiplication and division there is a need for a second register. However, here we will neglect the
second and assume that the AC contains the result of all operations.

Opcode Address

• The program to evaluate X = (A + B) ∗ (C + D) is as follows:

LOAD A AC ← M [A]
ADD B AC ← A [C] + M [B]
STORE T M [T] ← AC
LOAD C AC ← M [C]
ADD D AC ← AC + M [D]
MUL T AC ← AC ∗ M [T]
STORE X M [X] ← AC
 Two-address Instructions
• The MOV instruction moves or transfers the operands to and from memory and processor registers.
• The first symbol listed in an instruction is assumed to be both a source and the destination where the
result of the operation is transferred.
• Each address field can specify either a processor register or a memory word.
Opcode Address Address

• The program to evaluate X = (A + B) ∗ (C + D) is as follows:

MOV R1, A R1 ← M [A]
ADD R1, B R1 ← R1 + M [B]
MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
MUL R1, R2 R1 ← R1∗R2
MOV X, R1 M [X] ← R1
 Three-address Instructions
• Computers with three-address instruction formats can use each address field to specify either a
processor register or a memory operand.

Opcode Address Address Address

• First address field the destination for result.
• The program to evaluate X = (A + B) ∗ (C + D) is as follows:

ADD R1, A, B R1 ← M [A] + M [B]

ADD R2, C, D R2 ← M [C] + M [D]
MUL X, R1, R2 M [X] ← R1 ∗ R2
 Zero-address Instructions
• A stack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH
and POP instructions, however, need an address field to specify the operand that communicates with
the stack.
• The name zero-address is given to this type of computer because of the absence of an address field in
the computational instructions
• To evaluate arithmetic expressions in a stack computer, it is necessary to convert the expression into
reverse Polish notation(Postfix Notation).
Ex:- X = (A + B) ∗ (C + D) Postfix Notation : AB+CD+*
PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A + B)
PUSH C TOS ← C
PUSH D TOS ← D
ADD TOS ← (C + D)
MUL TOS ← (C + D) ∗ (A + B)
POP X M [X] ← TOS
 Addressing Modes

• The operation field of an instruction specifies the operation to be performed.

• The way the operands are chosen during program execution in dependent on the addressing mode of
the instruction.
• The addressing mode specifies a rule for interpreting or modifying the address field of the instruction
before the operand is actually referenced.

Op code Mode Address

Fig: Instruction format with mode field

• Although most addressing modes modify the address field of the instruction, there are two modes that
need no address field at all. These are the implied and immediate modes.

Types of Addressing modes:

1. Implied Mode:
In this mode the operands are specified implicitly in the definition of the instruction. Zero-address
instructions in a stack-organized computer are implied-mode instructions since the operands are implied
to be on top of the stack. Ex: Push , POP, Load A
 Addressing Modes
2. Immediate Mode:
In this mode the operand is specified in the instruction itself. In other words, an immediate- mode
instruction has an operand field rather than an address field. The operand field contains the actual
operand to be used in conjunction with the operation specified in the instruction.
opcode Address1 Address2
Add R1 #50 Memory
100 Add R1 #50
101
Add R1 #50 R1  R1 + 50
102
Effective address EA = 100 (for operand 2)
operand value OV = 50 (for operand 2)
 Addressing Modes
3. Register Mode:
In this mode the operands are in registers that reside within the CPU. The particular register is selected
from a register field in the instruction. A k-bit field can specify any one of 2k registers.
Ex: Load R1 AC  R1
EA = R1
OV = content of R1
4. Register Indirect Mode:
In this mode the instruction specifies a register in the CPU whose contents give the address of the
operand in memory. In other words, the selected register contains the address of the operand rather
than the operand itself.
Ex: Load (R1) AC  M[R1]
EA = content of R1
OV = M[R1] = data at memory location given in R1
 Addressing Modes
5. Direct Address Mode: In this mode the effective address is equal to the address part of the instruction. The
operand resides in memory and its address is given directly by the address field of the instruction. In a branch-
type instruction the address field specifies the actual branch address.
Ex : Add 102 AC  AC + M[102]
EA = 102
Memory
OV = M[102] = 500 100 ADD 102
101
6. Indirect Address Mode: In this mode the address field of the instruction gives 102 500
The address where the effective address is stored in memory. Control fetches -
-
the instruction from memory and uses its address part to access memory again -
-
to read the effective address.
Ex : Add @102 AC  AC + M[M[102]]
499 250
EA = M[102] = 500
90
OV = M[M[102]] = M[500] = 90 500
 Addressing Modes
7. Relative Address Mode: In this mode the content of the program counter is added to the address part of
the instruction in order to obtain the effective address. XR
PC 396
Ex: Add $102 AC  AC + M[PC + 102]
100 Base
EA = PC + 102 = 101 + 102 = 203 (PC’s value is incremented ) 398
OV = M[203] = 350 Memory
8. Indexed Addressing Mode: In this mode the content of an index register is 100 ADD 102

added to the address part of the instruction to obtain the effective address. 101
102 500
The index register is a special CPU register that contains an index value.
-
The address field of the instruction defines the beginning address of a data array -
in memory. Each operand in the array is stored in memory relative to the 203 350
-
-
beginning address.
Ex: Add 102(XR) AC  AC + M[102 + XR] 498
250
499
EA = 102 + XR = 102 + 396 = 498 90
500
OV = M[102 +XR] = M[498] = 250
 Addressing Modes
9. Base Register Addressing Mode: In this mode the content of a base register is added to the address part of
the instruction to obtain the effective address. This is similar to the indexed addressing mode except that the
register is now called a base register instead of an index register.
Ex: Add 102(Base) AC  AC + M[102 + Base]
EA = 102 + Base = 102 + 398 = 500
OV = M[102 + 398] = M[500] = 90
10. Autoincrement mode
The address of an operand is contained in a register. With autoincrement mode the contents of the register
is incremented each time the instruction is executed. When an instruction that uses autoincrement mode is executed, the
following happens:
1. The address of the operand is in Rn (previously executing instructions put it there.)
2. The operand at that address is used.
3. THEN the address in Rn is incremented (by 1, 2, 4, 8, or 16 depending on the opcode).
The last letter of the mnemonic for the instruction designates the size of the operands, and the amount by which to
increment:
Ex: Add #26, (R4)+ ; add 26 to one byte at (R4), increment R4 by 1
 Addressing Modes
11. Autodecrement mode:
1. FIRST the address in Rn is decremented (by 1, 2, 4, 8, or 16 depending on the opcode).
2. The address of the operand is NOW in Rn.
3. The operand at that address is used.
Ex: Add #26, -(R4) ; decrement R4 by 1, now add 26 to one byte at (R4)
Numerical Example:
Single Bus Architecture
 Single Bus Architecture

• The basic computer has eight registers, a memory unit, and a control unit . Paths must be provided to transfer
information from one register to another and between memory and registers.
• The connection of the registers and memory of the basic computer to a common bus system. The outputs of seven
registers and memory are connected to the common bus.
• The specific output that is selected for the bus lines at any given time is determined from the binary value of the
selection variables S2, S1, and S0.
• The number along each output shows the decimal equivalent of the required binary selection. For example, the
number along the output of DR is 3.
• The 16-bit outputs of DR are placed on the bus lines when S2 S1 S0 = 011 since this is the binary value of decimal 3.
• The lines from the common bus are connected to the inputs of each register and the data inputs of the memory. The
particular register whose LD (load) input is enabled receives the data from the bus during the next clock pulse
transition.
• The memory receives the contents of the bus when its write input is activated. The memory places its 16-bit output
onto the bus when the read input is activated and S2 S1 S0 = 111.
• Note that the content of any register can be applied onto the bus and an operation can be performed in the adder
and logic circuit during the same clock cycle. The clock transition at the end of the cycle transfers the content of the
bus into the designated destination register and the output of the adder and logic circuit into AC
 Computer Instructions
• The basic computer has three instruction code formats. Each format has 16 bits.

• The operation code (opcode) part of the instruction contains three bits and the meaning of the remaining 13 bits depends on the
operation code encountered.
• A memory-reference instruction uses 12 bits to specify an address and one bit to specify the addressing mode I. I is equal to 0 for
direct address and to 1 for indirect address.
 Computer Instructions

• The register reference instructions are recognized by the operation code 111 with a 0 in the leftmost bit (bit
15) of the instruction.
• A register-reference instruction specifies an operation on or a test of the AC register. An operand from
memory is not needed; therefore, the other 12 bits are used to specify the operation or test to be executed.
• Similarly, an input-output instruction does not need a reference to memory and is recognized by the
operation code 111 with a 1 in the leftmost bit of the instruction. The remaining 12 bits are used to specify
the type of input-output operation or test performed.
• The type of instruction is recognized by the computer control from the four bits in positions 12 through 15 of
the instruction. If the three opcode bits in positions 12 though 14 are not equal to 111, the instruction is a
memory-reference type and the bit in position 15 is taken as the addressing mode I.
• If the 3-bit opcode is equal to 111, control then inspects the bit in position 15. If this bit is 0, the
instruction is a register-reference type. If the bit is 1, the instruction is an input-output type. Note that the
bit in position 15 of the instruction code is designated by the symbol I but is not used as a mode bit when
the operation code is equal to 111.
 Instruction Cycle
• A program residing in the memory unit of the computer consists of a sequence of instructions. The program
is executed in the computer by going through a cycle for each instruction. Each instruction cycle in turn is
subdivided into a sequence of subcycles or phases. In the basic computer each instruction cycle consists of
the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.
• Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and execute the next
instruction. This process continues indefinitely unless a HALT instruction is encountered.
• Initially, the program counter PC is loaded with the address of the first instruction in the program.
• The sequence counter SC is cleared to 0, providing a decoded timing signal T0. After each clock pulse, SC is
incremented by one, so that the timing signals go through a sequence T0, T1, T2, and so on. The
microoperations for the fetch and decode phases can be specified by the following register transfer
statements.
T0: AR ← PC
T1: IR ← M[AR], PC ← PC + 1
T2: D0, .... , D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)
Instruction Cycle
 Instruction Cycle
• It is necessary to transfer the address from PC to AR during the clock transition associated with timing signal T0.
The instruction read from memory is then placed in the instruction register IR with the clock transition associated
with timing signal T1.
• At the same time(T1), PC is incremented by one to prepare it for the address of the next instruction in the
program. At time T2, the operation code in IR is decoded, the indirect bit is transferred to flip-flop I, and the
address part of the instruction is transferred to AR
• SC is incremented after each clock pulse to produce the sequence T0, T1, and T2.
• Decoder output D7 is equal to 1 if the operation code is equal to binary 111. From Fig. on basic computer formats
we determine that if D7 = 1, the instruction must be a register-reference or input-output type.
• If D7 = 0, the operation code must be one of the other seven values 000 through 110, specifying a memory-
reference instruction.
• Control then inspects the value of the first bit of the instruction, which is now available in flip-flop I. If D7 = 0 and I
= 1, we have a memory reference instruction with an indirect address.
• After decoding of these instructions, we need to determine the type of that we have just read from the memory.
At last the instruction has to be executed to perform the desired operation.
 Hardwired Control Unit
• There are two major types of control organization: hardwired control and microprogrammed control. In the
hardwired organization, the control logic is implemented with gates, flip-flops, decoders, and other digital circuits. It
has the advantage that it can be optimized to produce a fast mode of operation.
• In the microprogrammed organization, the control information is stored in a control memory. The control memory
is programmed to initiate the required sequence of microoperations.
• A hardwired control, as the name implies, requires changes in the wiring among the various components if the
design has to be modified or changed. In the microprogrammed control, any required changes or modifications can
be done by updating the microprogram in control memory.
• The block diagram of the hardwired control unit is shown in Fig(next slide).
• It consists of two decoders, a sequence counter, and a number of control logic gates. An instruction read from
memory is placed in the instruction register (IR).
• The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder. The eight outputs of the decoder are
designated by the symbols D0 through D7
• The subscripted decimal number is equivalent to the binary value of the corresponding operation code. Bit 15 of
the instruction is transferred to a flip-flop designated by the symbol I.
• Bits 0 through 11 are applied to the control logic gates. The 4-bit sequence counter can count in binary from 0
through 15. The. outputs of the counter are decoded into 16 timing signals T0 through T15
Hardwired Control Unit
 Hardwired Control Unit
• The sequence counter SC can be incremented or cleared synchronously
• Most of the time, the counter is incremented to provide the sequence of timing signals out of the 4 x 16 decoder.
Once in awhile, the counter is cleared to 0, causing the next active timing signal to be T0.
• As an example, consider the case where SC is incremented to provide timing signals T0, T1, T2, T3, and T4 in
sequence. At time T4, SC is cleared to 0 if decoder output D3 is active.