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Ec3352 Set2

The document outlines the practical end semester examination details for the EC3352 - Digital Systems Design course, scheduled for April/May 2024. It includes a list of questions focusing on designing and implementing various digital circuits using logic gates, with each question carrying a maximum of 100 marks. The exam will take place at Einstein College of Engineering, with a total duration of 3 hours.

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Prem Kumar J
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18 views3 pages

Ec3352 Set2

The document outlines the practical end semester examination details for the EC3352 - Digital Systems Design course, scheduled for April/May 2024. It includes a list of questions focusing on designing and implementing various digital circuits using logic gates, with each question carrying a maximum of 100 marks. The exam will take place at Einstein College of Engineering, with a total duration of 3 hours.

Uploaded by

Prem Kumar J
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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B.E / B.Tech.

PRACTICAL END SEMESTER EXAMINATIONS, APRIL/MAY 2024

Third Semester

EC3352 - DIGITAL SYSTEMS DESIGN

(Regulations 2021)

QUESTION SET

Time : 3 Hours Answer any one Question Max. Marks 100

VENUE: 9506-EINSTEIN COLLEGE OF ENGINEERING


DATE: 05.08.2024
TIME: 12.30 PM To 3.30 PM

Aim/Principle/Apparatus Tabulation/Circuit/ Calculation Viva-Voce Record Total


required/Procedure Program/Drawing & Results
20 30 30 10 10 100

1. Design and implement Half Adder and Full Adder circuit using logic gates and
verify its truth table. (100)

2. Design and implement a Full Adder using two Half Adders using logic gates and
verify its truth table. (100)

3. Design and implement Half Subtractor and Full Subtractor using logic gates and
verify its truth table. (100)

4. Design and implement a Full Subtractor using two Half Subtractor using logic gates
and verify its truth table. (100)

5. Design and implement a BCD to Excess-3 code converter using logic gates and
verify its truth table. (100)

6. Design and implement an Excess-3 code to BCD converter using logic gates and
verify its truth table. (100)

7. Design and implement a Binary to Gray Code and Gray to Binary Code converter
using logic gates and verify its truth table.
Page 1 of 2
(100)

8. a. Design and implement the truth table of 4x1 multiplexer using logic gates. (50)

b. Design and implement the truth table of 1x4 de-multiplexer using logic gates. (50)

INTERNAL EXAMINER EXTERNAL EXAMINER

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9. a. Design 4:2 encoder using logic gates and verify its truth table. (50)

b. Design 2:4 decoder using logic gates and verify its truth table. (50)

10. Design and implement a combinational circuit for 2 bit magnitude comparator using
basic gates.
(100)

11. Design and construct a 4 – bit mod-10 ripple counter and verify its truth table. (100)

12. Construct a 3-bit synchronous up / down counter and verify its truth table. (100)

13. Design and construct a Mod-5 synchronous counter using JK flip flops. (100)

14. Design and implement a sequential circuit for SISO and PIPO shift register. (100)

15. Design and implement a sequential circuit for SIPO and PISO shift register. (100)

16. Design and construct a 4 – bit mod-12 ripple counter and verify its truth table. (100)

17. Design a 4 bit Ripple counter using JK flip-flop and verify its truth table. (100)

18. Design a serial in serial out and serial in parallel out shift register and verify its truth table.
(100)

19. Design a Parallel in serial out and Parallel in parallel out shift register and verify its truth
table.
(100)

20. Design a 4-bit Magnitude Comparator to compare two 4-bit numbers and verify its truth
table.
(100)

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