Freescale Semiconductor MPC875EC

Rev. 3.0, 07/2004

MPC875/MPC870
Hardware Specifications

This hardware specification contains detailed information on Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
power considerations, DC/AC electrical characteristics, and AC
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
timing specifications for the MPC875/MPC870. The CPU on the 3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 7
MPC875/MPC870 is a 32-bit PowerPC™ core that incorporates 4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9
memory management units (MMUs) and instruction and data 5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
caches and that implements the PowerPC instruction set. This 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10
hardware specification covers the following topics: 7. Thermal Calculation and Measurement . . . . . . . . . . 11
8. Power Supply and Power Sequencing . . . . . . . . . . . 13
9. Mandatory Reset Configurations . . . . . . . . . . . . . . . 14

1 Overview 10.
11.
Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15
12. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44
The MPC875/MPC870 is a versatile single-chip integrated
13. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46
microprocessor and peripheral combination that can be used in a 14. USB Electrical Characteristics . . . . . . . . . . . . . . . . . 67
variety of controller applications and communications and 15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 67
networking systems. The MPC875/MPC870 provides enhanced 16. Mechanical Data and Ordering Information . . . . . . . 71
ATM functionality over that of other ATM-enabled members of 17. Document Revision History . . . . . . . . . . . . . . . . . . . 82
the MPC860 family.

© Freescale Semiconductor, Inc., 2004. All rights reserved.

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features

Table 1 shows the functionality supported by the members of the MPC875/MPC870.

Table 1. MPC875/870 Devices

Cache Ethernet
Security
Part SCC SMC USB
Engine
I Cache D Cache 10BaseT 10/100

MPC875 8 Kbyte 8 Kbyte 1 2 1 1 1 Yes

MPC870 8 Kbyte 8 Kbyte — 2 — 1 1 No

2 Features
The MPC875/870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system
integration unit (SIU), and a communications processor module (CPM).
The following list summarizes the key MPC875/870 features:
• Embedded MPC8xx core up to 133 MHz
• Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
— The 133-MHz core frequency supports 2:1 mode only.
— The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes.
• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit
general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch and without conditional execution.
— 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1)
– Instruction cache is two-way, set-associative with 256 sets in 2 blocks
– Data cache is two-way, set-associative with 256 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and
are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces
and 16 protection groups
— Advanced on-chip emulation debug mode
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank.
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line

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 Features

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
• General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting.
— Interrupt can be masked on reference match and event capture
• Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that
interface through MII and/or RMII interfaces
• System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 1149.1 test access port (JTAG)
• Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,
802.11i, and iSCSI processing. Available on the MPC875, the security engine contains a
crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
– Implements the Rinjdael symmetric key cipher
– ECB, CBC, and counter modes
– 128-, 192-, and 256-bit key lengths
— Message digest execution unit (MDEU)
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Master/slave logic, with DMA
– 32-bit address/32-bit data
– Operation at 8xx bus frequency
— Crypto-channel supporting multi-command descriptors
– Integrated controller managing crypto-execution units
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
• Interrupts
— Six external interrupt request (IRQ) lines

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Features

— 12 port pins with interrupt capability

— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
• Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and
RESTART TRANSMIT)
— Supports continuous mode transmission and reception on all serial channels
— 8-Kbytes of dual-port RAM
— Several serial DMA (SDMA) channels to support the CPM
— Three parallel I/O registers with open-drain capability
• On-chip 16 × 16 multiply accumulate controller (MAC)
— One operation per clock (two-clock latency, one-clock blockage)
— MAC operates concurrently with other instructions
— FIR loop—Four clocks per four multiplies
• Four baud-rate generators
— Independent (can be connected to any SCC or SMC)
— Allows changes during operation
— Autobaud support option
• SCC (serial communication controller)
— Ethernet/IEEE 802.3 optional on the SCC, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support point-to-point protocol (PPP)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
• SMC (serial management channel)
— UART (low-speed operation)
— Transparent
• Universal serial bus (USB)—Supports operation as a USB function endpoint, a USB host controller, or both
for testing purposes (loopback diagnostics)
— USB 2.0 full-/low-speed compatible
— The USB function mode has the following features:
– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers.

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 Features

– CRC16 generation and checking

– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
– Flexible data buffers with multiple buffers per frame
– Automatic retransmission upon transmit error
— The USB host controller has the following features:
– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data
rate configuration). Note that low-speed operation requires an external hub.
– Flexible data buffers with multiple buffers per frame
– Supports local loopback mode for diagnostics (12 Mbps only)
• Serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multiple-master operation on the same bus
• Inter-integrated circuit (I2C) port
— Supports master and slave modes
— Supports a multiple-master environment
• The MPC875 has a time-slot assigner (TSA) that supports one TDM bus (TDMb).
— Allows SCC and SMC to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
— Allows dynamic changes
— Can be internally connected to two serial channels (one SCC and one SMC)
• PCMCIA interface
— Master (socket) interface, release 2.1-compliant
— Supports one independent PCMCIA socket on the MPC875/MPC870
— 8 memory or I/O windows supported
• Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break point internally.
• Normal high and normal low power modes to conserve power
• 1.8-V core and 3.3-V I/O operation with 5-V TTL compatibility
• The MPC875/870 comes in a 256-pin ball grid array (PBGA) package.

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Features

The MPC875 block diagram is shown in Figure 1.

Instruction 8-Kbyte System Interface Unit (SIU)

Bus Instruction Cache
Instruction MMU Unified Memory Controller
Embedded 32-Entry ITLB Bus
MPC8xx Internal External
Processor Bus Interface Bus Interface
Core 8-Kbyte Unit Unit
Data Cache
System Functions
Load/Store Data MMU
Bus 32-Entry DTLB PCMCIA-ATA Interface
Slave/Master IF

Security Engine
Fast Ethernet
Controller Controller
AESU DEU MDEU
DMAs
DMAs Channel
DMAs
FIFOs
4 Interrupt 8-Kbyte
Parallel I/O Timers Controllers Dual-Port RAM
10/100
BaseT
Media Access 4 Baud Rate
32-Bit RISC Controller Virtual IDMA
Control Generators
and Program
and
Parallel Interface Port ROM
Timers Serial DMAs
MIII/RMII

USB SCC4 SMC1 SPI I2C

Time Slot Assigner
Serial Interface

Figure 1. MPC875 Block Diagram

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 Maximum Tolerated Ratings

The MPC870 block diagram is shown in Figure 2.

Instruction 8-Kbyte System Interface Unit (SIU)

Bus Instruction Cache
Instruction MMU Unified Memory Controller
Embedded 32-Entry ITLB Bus
MPC8xx Internal External
Processor Bus Interface Bus Interface
Core 8-Kbyte Unit Unit
Data Cache
System Functions
Load/Store Data MMU
Bus 32-Entry DTLB PCMCIA-ATA Interface
Slave/Master IF

Fast Ethernet
Controller

DMAs
DMAs
FIFOs
4 Interrupt 8-Kbyte
Parallel I/O Timers Controllers Dual-Port RAM
10/100
BaseT
Media Access 4 Baud Rate
32-Bit RISC Controller Virtual IDMA and
Control Generators
and Program
Serial DMAs
Parallel Interface Port ROM
Timers
MIII / RMII

USB SMC1 SPI I2C

Serial Interface

Figure 2. MPC870 Block Diagram

3 Maximum Tolerated Ratings

This section provides the maximum tolerated voltage and temperature ranges for the MPC875/870. Table 2
displays the maximum tolerated ratings, and Table 3 displays the operating temperatures.

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Maximum Tolerated Ratings

Table 2. Maximum Tolerated Ratings

Rating Symbol Value Unit

Supply voltage 1 VDDL (core –0.3 to 3.4 V

voltage)

VDDH (I/O –0.3 to 4 V

voltage)

VDDSYN –0.3 to 3.4 V

Difference <100 mV
between
VDDL and
VDDSYN

Input voltage 2 Vin GND – 0.3 to V

VDDH

Storage temperature range Tstg –55 to +150 °C

1 The
power supply of the device must start its ramp from 0.0 V.
2
Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum
ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power
up and normal operation (that is, if the MPC875/870 is unpowered, a voltage greater than 2.5 V must not be applied
to its inputs).

Table 3. Operating Temperatures

Rating Symbol Value Unit

Temperature 1 (standard) TA(min) 0 °C

Tj(max) 95 °C

Temperature (extended) TA(min) –40 °C

Tj(max) 100 °C
1 Minimum temperatures are guaranteed as ambient temperature, TA. Maximum temperatures are guaranteed as
junction temperature, Tj.

This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it
is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages
to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic
voltage level (for example, either GND or VDDH).

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 Thermal Characteristics

4 Thermal Characteristics
Table 4 shows the thermal characteristics for the MPC875/870.
Table 4. MPC875/870 Thermal Resistance Data

Rating Environment Symbol Value Unit

Junction-to-ambient 1 Natural convection Single-layer board (1s) RθJA 2 43 °C/W

3
Four-layer board (2s2p) RθJMA 29

Airflow (200 ft/min) Single-layer board (1s) RθJMA3 36

3
Four-layer board (2s2p) RθJMA 26

Junction-to-board 4 RθJB 20
5
Junction-to-case RθJC 10

Junction-to-package top 6 Natural convection ΨJT 2

Airflow (200 ft/min) ΨJT 2

1 Junction
temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
2 Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3 Per JEDEC JESD51-6 with the board horizontal.
4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

5
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed
pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated
value from the junction to the exposed pad without contact resistance.
6
Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2.

5 Power Dissipation
Table 5 provides information on power dissipation. The modes are 1:1, where CPU and bus speeds are
equal, and 2:1, where CPU frequency is twice bus speed.
Table 5. Power Dissipation (PD)

Bus
Die Revision Frequency Typical 1 Maximum 2 Unit
Mode

66 MHz 310 390 mW

1:1
0 80 MHz 350 430 mW

2:1 133 MHz 430 495 mW

1 Typical
power dissipation is measured at VDDL = VDDSYN = 1.8 V, and VDDH is at 3.3 V.

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DC Characteristics

2 Maximum power dissipation at VDDL = VDDSYN = 1.9 V, and VDDH is at 3.5 V.

NOTE
The values in Table 5 represent VDDL-based power dissipation and do not
include I/O power dissipation over VDDH. I/O power dissipation varies
widely by application due to buffer current, depending on external
circuitry.
The VDDSYN power dissipation is negligible.

6 DC Characteristics
Table 6 provides the DC electrical characteristics for the MPC875/870.
Table 6. DC Electrical Specifications

Characteristic Symbol Min Max Unit

Operating voltage VDDH (I/O) 3.135 3.465 V

VDDL (Core) 1.7 1.9 V

VDDSYN 1 1.7 1.9 V

Difference — 100 mV
between
VDDL and
VDDSYN

Input high voltage (all inputs except EXTAL and EXTCLK) 2 VIH 2.0 3.465 V

Input low voltage 3 VIL GND 0.8 V

EXTAL, EXTCLK input high voltage VIHC 0.7 × VDDH VDDH V

Input leakage current, Vin = 5.5 V (except TMS, TRST, DSCK and Iin — 100 µA
DSDI pins) for 5-V tolerant pins 1

Input leakage current, Vin = VDDH (except TMS, TRST, DSCK, and IIn — 10 µA
DSDI)

Input leakage current, Vin = 0 V (except TMS, TRST, DSCK and DSDI IIn — 10 µA
pins)

Input capacitance 4 Cin — 20 pF

Output high voltage, IOH = –2.0 mA, VDDH = 3.0 V VOH 2.4 — V
except XTAL and open-drain pins

Output low voltage VOL — 0.5 V

IOL = 2.0 mA (CLKOUT)
IOL = 3.2 mA 5
IOL = 5.3 mA 6
IOL = 7.0 mA (TXD1/PA14, TXD2/PA12)
IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET)
1 The
difference between VDDL and VDDSYN cannot be more than 100 mV.
2 The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], PE(14:31), TDI, TDO, TCK, TRST, TMS, MII1_TXEN, MII_MDIO

are 5-V tolerant. The minimum voltage is still 2.0 V.

3
VIL(max) for the I2C interface is 0.8 V rather than the 1.5 V as specified in the I2C standard.

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 Thermal Calculation and Measurement
4
Input capacitance is periodically sampled.
5
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), IRQ(2:4), IRQ6, RD/WR, BURST, IP_B(0:1), PA(0:4), PA(6:7), PA(10:11), PA15,
PB19, PB(23:31), PC(6:7), PC(10:13), PC15, PD8, PE(14:31), MII1_CRS, MII_MDIO, MII1_TXEN, MII1_COL.
6
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:7), WE(0:3), BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A,
OP(0:3) BADDR(28:30

7 Thermal Calculation and Measurement

For the following discussions, PD = (VDDL × IDDL) + PI/O, where PI/O is the power dissipation of the I/O
drivers.
NOTE
The VDDSYN power dissipation is negligible.

7.1 Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction temperature, TJ, in °C can be obtained from the following equation:
TJ = TA + (RθJA × PD)
where:
TA = ambient temperature ºC
RθJA = package junction-to-ambient thermal resistance (ºC/W)
PD = power dissipation in package
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated
that errors of a factor of two (in the quantity TJ–TA) are possible.

7.2 Estimation with Junction-to-Case Thermal Resistance

Historically, thermal resistance has frequently been expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (ºC/W)
RθJC = junction-to-case thermal resistance (ºC/W)
RθCA = case-to-ambient thermal resistance (ºC/W)
RθJC is device-related and cannot be influenced by the user. The user adjusts the thermal environment to
affect the case-to-ambient thermal resistance, RθCA. For instance, the user can change the airflow around
the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the
thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful
for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink
to the ambient environment. For most packages, a better model is required.

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Thermal Calculation and Measurement

7.3 Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model
consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case thermal resistance
covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the
package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages
and especially PBGA packages is strongly dependent on the board temperature. If the board temperature is known,
an estimate of the junction temperature in the environment can be made using the following equation:
TJ = TB + (RθJB × PD)
where:
RθJB = junction-to-board thermal resistance (ºC/W)
TB = board temperature ºC
PD = power dissipation in package
If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable
predictions of junction temperature can be made. For this method to work, the board and board mounting must be
similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a
power and a ground plane) and vias attaching the thermal balls to the ground plane.

7.4 Estimation Using Simulation

When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor
model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the
package can be used in the thermal simulation.

7.5 Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal
characterization parameter (ΨJT) can be used to determine the junction temperature with a measurement of the
temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
ΨJT = thermal characterization parameter
TT = thermocouple temperature on top of package
PD = power dissipation in package
The thermal characterization parameter is measured per the JESD51-2 specification published by JEDEC using a 40
gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the
package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.

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 Power Supply and Power Sequencing

7.6 References
Semiconductor Equipment and Materials International (415) 964-5111
805 East Middlefield Rd
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifications 800-854-7179 or
(Available from Global Engineering Documents) 303-397-7956
JEDEC Specifications http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its
Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

8 Power Supply and Power Sequencing

This section provides design considerations for the MPC875/870 power supply. The MPC875/870 has a
core voltage (VDDL) and PLL voltage (VDDSYN), which both operate at a lower voltage than the I/O voltage
VDDH. The I/O section of the MPC875/870 is supplied with 3.3 V across VDDH and VSS (GND).
The signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI,
TDO, TCK, TRST, TMS, MII_TXEN, and MII_MDIO are 5-V tolerant. No input can be more than 2.5 V
greater than VDDH. In addition, 5 V-tolerant pins cannot exceed 5.5 V, and remaining input pins cannot
exceed 3.465 V. This restriction applies to power up/down and normal operation.
One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp
up at different rates. The rates depend on the nature of the power supply, the type of load on each power
supply, and the manner in which different voltages are derived. The following restrictions apply:
• VDDL must not exceed VDDH during power up and power down.
• VDDL must not exceed 1.9 V, and VDDH must not exceed 3.465 V.

These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic
discharge (ESD) protection diodes are forward-biased, and excessive current can flow through these diodes.
If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 3
can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential
difference between the external bus and core power supplies on power up, and the 1N5820 diodes regulate
the maximum potential difference on power down.

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Mandatory Reset Configurations

VDDH VDDL

MUR420

1N5820

Figure 3. Example Voltage Sequencing Circuit

9 Mandatory Reset Configurations

The MPC875/870 requires a mandatory configuration during reset.
If hardware reset configuration word (HRCW) is enabled, the HRCW[DBGC] value needs to be set to binary X1 in
the HRCW and the SIUMCR[DBGC] should be programmed with the same value in the boot code after reset. This
can be done by asserting the RSTCONF during HRESET assertion.
If HRCW is disabled, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset by
negating the RSTCONF during the HRESET assertion.
The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR need to be configured with the
mandatory values in Table 7 in the boot code after the reset is negated.
Table 7. Mandatory Reset Configuration of MPC875/870

Value
Register/Configuration Field
(binary)

HRCW HRCW[DBGC] X1
(Hardware reset configuration word)

SIUMCR SIUMCR[DBGC] X1
(SIU module configuration register)

MBMR MBMR[GPLB4DIS} 0
(Machine B mode register)

PAPAR PAPAR[5:9] 0
(Port A pin assignment register) PAPAR[12:13]

PADIR PADIR[5:9] 0
(Port A data direction register) PADIR[12:13]

PBPAR PBPAR[14:18] 0
(Port B pin assignment register) PBPAR[20:22]

PBDIR PBDIR[14:8] 0
(Port B data direction register) PBDIR[20:22]

PCPAR PCPAR[4:5] 0
(Port C pin assignment register) PCPAR[8:9]
PCPAR[14]

MPC875/MPC870 Hardware Specifications, Rev. 3.0

14 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Layout Practices

Table 7. Mandatory Reset Configuration of MPC875/870 (continued)

Value
Register/Configuration Field
(binary)

PCDIR PCDIR[4:5] 0
(Port C data direction register) PCDIR[8:9]
PCDIR[14]

PDPAR PDPAR[3:7] 0
(Port D pin assignment register) PDPAR[9:5]

PDDIR PDDIR[3:7] 0
(Port D data direction register) PDDIR[9:15]

10 Layout Practices
Each VDD pin on the MPC875/870 should be provided with a low-impedance path to the board’s supply. Each GND
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups
of logic on chip. The VDD power supply should be bypassed to ground using at least four 0.1-µF bypass capacitors
located as close as possible to the four sides of the package. Each board designed should be characterized and
additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed
circuit traces connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. At a
minimum, a four-layer board employing two inner layers as VDD and GND planes should be used.
All output pins on the MPC875/870 have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching times.
This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches
are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to
the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads because these loads create higher transient currents in the VDD and GND circuits. Pull up all unused
inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins. For more information, please refer to Section 14.4.3, “Clock Synthesizer Power (VDDSYN,
VSSSYN, VSSSYN1),” of the MPC885 PowerQUICC Family User’s Manual.

11 Bus Signal Timing

The maximum bus speed supported by the MPC875/870 is 80 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC875/870 used at 133 MHz must be configured for a 66 MHz bus). Table 8
shows the frequency ranges for standard part frequencies in 1:1 bus mode, and Table 9 shows the frequency ranges
for standard part frequencies in 2:1 bus mode.
Table 8. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)

Part Frequency 66 MHz 80 MHz

Min Max Min Max

Core frequency 40 66.67 40 80

Bus frequency 40 66.67 40 80

MPC875/MPC870 Hardware Specifications, Rev. 3.0

15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Bus Signal Timing

Table 9. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)

Part Frequency 66 MHz 80 MHz 133 MHz

Min Max Min Max Min Max

Core frequency 40 66.67 40 80 40 133

Bus frequency 20 33.33 20 40 20 66

Table 10 provides the bus operation timing for the MPC875/870 at 33, 40, 66, and 80 MHz.
The timing for the MPC875/870 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum
delays. CLKOUT assumes a 100-pF load maximum delay
Table 10. Bus Operation Timings

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic Unit
Min Max Min Max Min Max Min Max

B1 Bus period (CLKOUT), see Table 8 — — — — — — — — ns

B1a EXTCLK to CLKOUT phase skew - If –2 +2 –2 +2 –2 +2 –2 +2 ns

CLKOUT is an integer multiple of
EXTCLK, then the rising edge of EXTCLK
is aligned with the rising edge of CLKOUT.
For a non-integer multiple of EXTCLK, this
synchronization is lost, and the rising
edges of EXTCLK and CLKOUT have a
continuously varying phase skew.

B1b CLKOUT frequency jitter peak-to-peak — 1 — 1 — 1 — 1 ns

B1c Frequency jitter on EXTCLK — 0.50 — 0.50 — 0.50 — 0.50 %

B1d CLKOUT phase jitter peak-to-peak — 4 — 4 — 4 — 4 ns

for OSCLK ≥ 15 MHz

CLKOUT phase jitter peak-to-peak — 5 — 5 — 5 — 5 ns

for OSCLK < 15 MHz

B2 CLKOUT pulse width low 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns
(MIN = 0.4 × B1, MAX = 0.6 × B1)
B3 CLKOUT pulse width high 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns
(MIN = 0.4 × B1, MAX = 0.6 × B1)

B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns

B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 4.00 ns

B7 CLKOUT to A(0:31), BADDR(28:30), 7.60 — 6.30 — 3.80 — 3.13 — ns

RD/WR, BURST, D(0:31) output hold
(MIN = 0.25 × B1)
B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP, 7.60 — 6.30 — 3.80 — 3.13 — ns
PTR output hold (MIN = 0.25 × B1)

B7b CLKOUT to BR, BG, FRZ, VFLS(0:1), 7.60 — 6.30 — 3.80 — 3.13 — ns
VF(0:2) IWP(0:2), LWP(0:1), STS output
hold (MIN = 0.25 × B1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

16 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic Unit
Min Max Min Max Min Max Min Max

B8 CLKOUT to A(0:31), BADDR(28:30) — 13.80 — 12.50 — 10.00 — 9.43 ns

RD/WR, BURST, D(0:31) valid
(MAX = 0.25 × B1 + 6.3)
B8a CLKOUT to TSIZ(0:1), REG, RSV, BDIP, — 13.80 — 12.50 — 10.00 — 9.43 ns
PTR valid (MAX = 0.25 × B1 + 6.3)
B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2), — 13.80 — 12.50 — 10.00 — 9.43 ns
IWP(0:2), FRZ, LWP(0:1), STS valid 2
(MAX = 0.25 × B1 + 6.3)

B9 CLKOUT to A(0:31), BADDR(28:30), 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns
RD/WR, BURST, D(0:31), TSIZ(0:1), REG,
RSV, PTR High-Z
(MAX = 0.25 × B1 + 6.3)
B11 CLKOUT to TS, BB assertion 7.60 13.60 6.30 12.30 3.80 9.80 3.13 9.13 ns
(MAX = 0.25 × B1 + 6.0)
B11a CLKOUT to TA, BI assertion (when driven 2.50 9.30 2.50 9.30 2.50 9.80 2.5 9.3 ns
by the memory controller or PCMCIA
interface) (MAX = 0.00 × B1 + 9.30 1)

B12 CLKOUT to TS, BB negation 7.60 12.30 6.30 11.00 3.80 8.50 3.13 7.92 ns
(MAX = 0.25 × B1 + 4.8)
B12a CLKOUT to TA, BI negation (when driven 2.50 9.00 2.50 9.00 2.50 9.00 2.5 9.00 ns
by the memory controller or PCMCIA
interface) (MAX = 0.00 × B1 + 9.00)

B13 CLKOUT to TS, BB High-Z 7.60 21.60 6.30 20.30 3.80 14.00 3.13 12.93 ns
(MIN = 0.25 × B1)
B13a CLKOUT to TA, BI High-Z (when driven by 2.50 15.00 2.50 15.00 2.50 15.00 2.5 15.00 ns
the memory controller or PCMCIA
interface) (MIN = 0.00 × B1 + 2.5)

B14 CLKOUT to TEA assertion 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
(MAX = 0.00 × B1 + 9.00)
B15 CLKOUT to TEA High-Z 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
(MIN = 0.00 × B1 + 2.50)

B16 TA, BI valid to CLKOUT (setup time) 6.00 — 6.00 — 6.00 — 6 — ns

(MIN = 0.00 × B1 + 6.00)
B16a TEA, KR, RETRY, CR valid to CLKOUT 4.50 — 4.50 — 4.50 — 4.50 — ns
(setup time) (MIN = 0.00 × B1 + 4.5)
B16b BB, BG, BR, valid to CLKOUT (setup time) 4.00 — 4.00 — 4.00 — 4.00 — ns
2 (4MIN = 0.00 × B1 + 0.00)

B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid 1.00 — 1.00 — 2.00 — 2.00 — ns
(hold time) (MIN = 0.00 × B1 + 1.00 3)
B17a CLKOUT to KR, RETRY, CR valid (hold 2.00 — 2.00 — 2.00 — 2.00 — ns
time) (MIN = 0.00 × B1 + 2.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic Unit
Min Max Min Max Min Max Min Max

B18 D(0:31) valid to CLKOUT rising edge 6.00 — 6.00 — 6.00 — 6.00 — ns
(setup time) 4 (MIN = 0.00 × B1 + 6.00)

B19 CLKOUT rising edge to D(0:31) valid (hold 1.00 — 1.00 — 2.00 — 2.00 — ns
time) 4 (MIN = 0.00 × B1 + 1.00 5)
B20 D(0:31) valid to CLKOUT falling edge 4.00 — 4.00 — 4.00 — 4.00 — ns
(setup time) 6(MIN = 0.00 × B1 + 4.00)
B21 CLKOUT falling edge to D(0:31) valid 2.00 — 2.00 — 2.00 — 2.00 — ns
(hold time) 6 (MIN = 0.00 × B1 + 2.00)

B22 CLKOUT rising edge to CS asserted 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns
GPCM ACS = 00 (MAX = 0.25 × B1 + 6.3)
B22a CLKOUT falling edge to CS asserted — 8.00 — 8.00 — 8.00 — 8.00 ns
GPCM ACS = 10, TRLX = 0
(MAX = 0.00 × B1 + 8.00)

B22b CLKOUT falling edge to CS asserted 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns
GPCM ACS = 11, TRLX = 0, EBDF = 0
(MAX = 0.25 × B1 + 6.3)
B22c CLKOUT falling edge to CS asserted 10.90 18.00 10.90 16.00 5.20 12.30 4.69 10.93 ns
GPCM ACS = 11, TRLX = 0, EBDF = 1
(MAX = 0.375 × B1 + 6.6)

B23 CLKOUT rising edge to CS negated 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns
GPCM read access, GPCM write access
ACS = 00, TRLX = 0 & CSNT = 0
(MAX = 0.00 × B1 + 8.00)
B24 A(0:31) and BADDR(28:30) to CS 5.60 — 4.30 — 1.80 — 1.13 — ns
asserted GPCM ACS = 10, TRLX = 0
(MIN = 0.25 × B1 – 2.00)

B24a A(0:31) and BADDR(28:30) to CS 13.20 — 10.50 — 5.60 — 4.25 — ns

asserted GPCM ACS = 11 TRLX = 0
(MIN = 0.50 × B1 – 2.00)
B25 CLKOUT rising edge to OE, — 9.00 9.00 9.00 — 9.00 ns
WE(0:3)/BS_B[0:3] asserted
(MAX = 0.00 × B1 + 9.00)
B26 CLKOUT rising edge to OE negated 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns
(MAX = 0.00 × B1 + 9.00)
B27 A(0:31) and BADDR(28:30) to CS 35.90 — 29.30 — 16.90 — 13.60 — ns
asserted GPCM ACS = 10, TRLX = 1
(MIN = 1.25 × B1 – 2.00)

B27a A(0:31) and BADDR(28:30) to CS 43.50 — 35.50 — 20.70 — 16.75 — ns

asserted GPCM ACS = 11, TRLX = 1
(MIN = 1.50 × B1 – 2.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

18 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic Unit
Min Max Min Max Min Max Min Max

B28 CLKOUT rising edge to — 9.00 — 9.00 — 9.00 — 9.00 ns

WE(0:3)/BS_B[0:3] negated GPCM write
access CSNT = 0
(MAX = 0.00 × B1 + 9.00)
B28a CLKOUT falling edge to 7.60 14.30 6.30 13.00 3.80 10.50 3.13 9.93 ns
WE(0:3)/BS_B[0:3] negated GPCM write
access TRLX = 0, CSNT = 1, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
B28b CLKOUT falling edge to CS negated — 14.30 — 13.00 — 10.50 — 9.93 ns
GPCM write access TRLX = 0, CSNT = 1
ACS = 10 or ACS = 11, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
B28c CLKOUT falling edge to 10.90 18.00 10.90 18.00 5.20 12.30 4.69 11.29 ns
WE(0:3)/BS_B[0:3] negated GPCM write
access TRLX = 0, CSNT = 1 write access
TRLX = 0, CSNT = 1, EBDF = 1
(MAX = 0.375 × B1 + 6.6)
B28d CLKOUT falling edge to CS negated — 18.00 — 18.00 — 12.30 — 11.30 ns
GPCM write access TRLX = 0, CSNT = 1,
ACS = 10, or ACS = 11, EBDF = 1
(MAX = 0.375 × B1 + 6.6)
B29 WE(0:3)/BS_B[0:3] negated to D(0:31) 5.60 — 4.30 — 1.80 — 1.13 — ns
High-Z GPCM write access, CSNT = 0,
EBDF = 0 (MIN = 0.25 × B1 – 2.00)
B29a WE(0:3)/BS_B[0:3] negated to D(0:31) 13.20 — 10.50 — 5.60 — 4.25 — ns
High-Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 0
(MIN = 0.50 × B1 – 2.00)
B29b CS negated to D(0:31) High-Z GPCM write 5.60 — 4.30 — 1.80 — 1.13 — ns
access, ACS = 00, TRLX = 0 & CSNT = 0
(MIN = 0.25 × B1 – 2.00)

B29c CS negated to D(0:31) High-Z GPCM write 13.20 — 10.50 — 5.60 — 4.25 — ns
access, TRLX = 0, CSNT = 1, ACS = 10,
or ACS = 11 EBDF = 0
(MIN = 0.50 × B1 – 2.00)
B29d WE(0:3)/BS_B[0:3] negated to D(0:31) 43.50 — 35.50 — 20.70 — 16.75 — ns
High-Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 0
(MIN = 1.50 × B1 – 2.00)
B29e CS negated to D(0:31) High-Z GPCM write 43.50 — 35.50 — 20.70 — 16.75 — ns
access, TRLX = 1, CSNT = 1, ACS = 10,
or ACS = 11, EBDF = 0
(MIN = 1.50 × B1 – 2.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic Unit
Min Max Min Max Min Max Min Max

B29f WE(0:3/BS_B[0:3]) negated to D(0:31) 5.00 — 3.00 — 0.00 — 0.00 — ns

High-Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 1
(MIN = 0.375 × B1 – 6.30)
B29g CS negated to D(0:31) High-Z GPCM write 5.00 — 3.00 — 0.00 — 0.00 — ns
access, TRLX = 0, CSNT = 1 ACS = 10 or
ACS = 11, EBDF = 1
(MIN = 0.375 × B1 – 6.30)
B29h WE(0:3)/BS_B[0:3] negated to D(0:31) 38.40 — 31.10 — 17.50 — 13.85 — ns
High-Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 1
(MIN = 0.375 × B1 – 3.30)
B29i CS negated to D(0:31) (0:3) High-Z GPCM 38.40 — 31.10 — 17.50 — 13.85 — ns
write access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF = 1
(MIN = 0.375 × B1 – 3.30)
B30 CS, WE(0:3)/BS_B[0:3] negated to 5.60 — 4.30 — 1.80 — 1.13 — ns
A(0:31), BADDR(28:30) invalid GPCM
write access 7 (MIN = 0.25 × B1 – 2.00)

B30a WE(0:3)/BS_B[0:3] negated to A(0:31), 13.20 — 10.50 — 5.60 — 4.25 — ns

BADDR(28:30) invalid GPCM, write
access, TRLX = 0, CSNT = 1, CS negated
to A(0:31) invalid GPCM write access
TRLX = 0, CSNT =1 ACS = 10, or
ACS == 11, EBDF = 0
(MIN = 0.50 × B1 – 2.00)
B30b WE(0:3)/BS_B[0:3] negated to A(0:31) 43.50 — 35.50 — 20.70 — 16.75 — ns
Invalid GPCM BADDR(28:30) invalid
GPCM write access, TRLX = 1, CSNT = 1.
CS negated to A(0:31) invalid GPCM write
access TRLX = 1, CSNT = 1, ACS = 10, or
ACS == 11 EBDF = 0
(MIN = 1.50 × B1 – 2.00)
B30c WE(0:3)/BS_B[0:3] negated to A(0:31), 8.40 — 6.40 — 2.70 — 1.70 — ns
BADDR(28:30) invalid GPCM write
access, TRLX = 0, CSNT = 1. CS negated
to A(0:31) invalid GPCM write access,
TRLX = 0, CSNT = 1 ACS = 10,
ACS == 11, EBDF = 1
(MIN = 0.375 × B1 – 3.00)
B30d WE(0:3)/BS_B[0:3] negated to A(0:31), 38.67 — 31.38 — 17.83 — 14.19 — ns
BADDR(28:30) invalid GPCM write access
TRLX = 1, CSNT =1, CS negated to
A(0:31) invalid GPCM write access TRLX
= 1, CSNT = 1, ACS = 10 or 11, EBDF = 1

MPC875/MPC870 Hardware Specifications, Rev. 3.0

20 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic Unit
Min Max Min Max Min Max Min Max

B31 CLKOUT falling edge to CS valid, as 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
requested by control bit CST4 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 6.00)
B31a CLKOUT falling edge to CS valid, as 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns
requested by control bit CST1 in the
corresponding word in the UPM
(MAX = 0.25 × B1 + 6.80)
B31b CLKOUT rising edge to CS valid, as 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
requested by control bit CST2 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 8.00)
B31c CLKOUT rising edge to CS valid, as 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns
requested by control bit CST3 in the
corresponding word in the UPM
(MAX = 0.25 × B1 + 6.30)
B31d CLKOUT falling edge to CS valid, as 13.30 18.00 11.30 16.00 7.60 12.30 4.69 11.30 ns
requested by control bit CST1 in the
corresponding word in the UPM EBDF = 1
(MAX = 0.375 × B1 + 6.6)
B32 CLKOUT falling edge to BS valid, as 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
requested by control bit BST4 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 6.00)
B32a CLKOUT falling edge to BS valid, as 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
B32b CLKOUT rising edge to BS valid, as 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
requested by control bit BST2 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 8.00)
B32c CLKOUT rising edge to BS valid, as 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns
requested by control bit BST3 in the
corresponding word in the UPM
(MAX = 0.25 × B1 + 6.80)
B32d CLKOUT falling edge to BS valid, as 13.30 18.00 11.30 16.00 7.60 12.30 4.49 11.30 ns
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 1
(MAX = 0.375 × B1 + 6.60)
B33 CLKOUT falling edge to GPL valid, as 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
requested by control bit GxT4 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 6.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic Unit
Min Max Min Max Min Max Min Max

B33a CLKOUT rising edge to GPL valid, as 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns
requested by control bit GxT3 in the
corresponding word in the UPM
(MAX = 0.25 × B1 + 6.80)
B34 A(0:31), BADDR(28:30), and D(0:31) to 5.60 — 4.30 — 1.80 — 1.13 — ns
CS valid, as requested by control bit CST4
in the corresponding word in the UPM
(MIN = 0.25 × B1 - 2.00)
B34a A(0:31), BADDR(28:30), and D(0:31) to 13.20 — 10.50 — 5.60 — 4.25 — ns
CS valid, as requested by control bit CST1
in the corresponding word in the UPM
(MIN = 0.50 × B1 – 2.00)
B34b A(0:31), BADDR(28:30), and D(0:31) to 20.70 — 16.70 — 9.40 — 6.80 — ns
CS valid, as requested by CST2 in the
corresponding word in UPM
(MIN = 0.75 × B1 – 2.00)
B35 A(0:31), BADDR(28:30) to CS valid, as 5.60 — 4.30 — 1.80 — 1.13 — ns
requested by control bit BST4 in the
corresponding word in the UPM
(MIN = 0.25 × B1 – 2.00)
B35a A(0:31), BADDR(28:30), and D(0:31) to 13.20 — 10.50 — 5.60 — 4.25 — ns
BS valid, as requested by BST1 in the
corresponding word in the UPM
(MIN = 0.50 × B1 – 2.00)
B35b A(0:31), BADDR(28:30), and D(0:31) to 20.70 — 16.70 — 9.40 — 7.40 — ns
BS valid, as requested by control bit BST2
in the corresponding word in the UPM
(MIN = 0.75 × B1 – 2.00)
B36 A(0:31), BADDR(28:30), and D(0:31) to 5.60 — 4.30 — 1.80 — 1.13 — ns
GPL valid, as requested by control bit
GxT4 in the corresponding word in the
UPM (MIN = 0.25 × B1 – 2.00)
B37 UPWAIT valid to CLKOUT falling edge 8 6.00 — 6.00 — 6.00 — 6.00 — ns
(MIN = 0.00 × B1 + 6.00)

B38 CLKOUT falling edge to UPWAIT valid 8 1.00 — 1.00 — 1.00 — 1.00 — ns
(MIN = 0.00 × B1 + 1.00)

B39 AS valid to CLKOUT rising edge 9 7.00 — 7.00 — 7.00 — 7.00 — ns

(MIN = 0.00 × B1 + 7.00)
B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid 7.00 — 7.00 — 7.00 — 7.00 — ns
to CLKOUT rising edge
(MIN = 0.00 × B1 + 7.00)

B41 TS valid to CLKOUT rising edge (setup 7.00 — 7.00 — 7.00 — 7.00 — ns
time) (MIN = 0.00 × B1 + 7.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

22 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic Unit
Min Max Min Max Min Max Min Max

B42 CLKOUT rising edge to TS valid (hold 2.00 — 2.00 — 2.00 — 2.00 — ns
time) (MIN = 0.00 × B1 + 2.00)

B43 AS negation to memory controller signals — TBD — TBD — TBD — TBD ns

negation (MAX = TBD)
1
For part speeds above 50 MHz, use 9.80 ns for B11a.
2
The timing required for BR input is relevant when the MPC875/870 is selected to work with the internal bus arbiter.
The timing for BG input is relevant when the MPC875/870 is selected to work with the external bus arbiter.
3
For part speeds above 50 MHz, use 2 ns for B17.
4
The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted.
5 For part speeds above 50 MHz, use 2 ns for B19.
6 The D(0:31) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read

accesses controlled by chip-selects under control of the user-programmable machine (UPM) in the memory
controller, for data beats where DLT3 = 1 in the RAM words. (This is only the case where data is latched on the falling
edge of CLKOUT.)
7 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
8 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in

B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 19.
9 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior

specified in Figure 22.

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Bus Signal Timing

Figure 4 provides the control timing diagram.

.

2.0 V 2.0 V
CLKOUT
0.8 V 0.8 V

A
B

2.0 V 2.0 V
Outputs 0.8 V 0.8 V

A
B

2.0 V 2.0 V
Outputs 0.8 V 0.8 V

D
C

2.0 V 2.0 V
Inputs 0.8 V 0.8 V

D
C

2.0 V 2.0 V
Inputs 0.8 V 0.8 V

A Maximum output delay specification

B Minimum output hold time

C Minimum input setup time specification

D Minimum input hold time specification

Figure 4. Control Timing

Figure 5 provides the timing for the external clock.

CLKOUT

B1 B3
B1 B2
B4 B5

Figure 5. External Clock Timing

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24 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Bus Signal Timing

Figure 6 provides the timing for the synchronous output signals.

CLKOUT

B8
B7 B9

Output
Signals

B8a
B7a B9

Output
Signals

B8b
B7b

Output
Signals

Figure 6. Synchronous Output Signals Timing

Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals.

CLKOUT

B13
B11 B12

TS, BB

B13a

B11 B12a

TA, BI

B14
B15

TEA

Figure 7. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing

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Bus Signal Timing

Figure 8 provides the timing for the synchronous input signals.

CLKOUT

B16
B17

TA, BI

B16a

B17a

TEA, KR,
RETRY, CR

B16b

B17

BB, BG, BR

Figure 8. Synchronous Input Signals Timing

Figure 9 provides normal case timing for input data. It also applies to normal read accesses under the control of the
user-programmable machine (UPM) in the memory controller.

CLKOUT

B16
B17

TA

B18
B19

D[0:31]

Figure 9. Input Data Timing in Normal Case

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Bus Signal Timing

Figure 10 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM
RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

CLKOUT

TA

B20
B21

D[0:31]

Figure 10. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1

Figure 11 through Figure 14 provide the timing for the external bus read controlled by various GPCM factors.

CLKOUT

B11 B12

TS

B8

A[0:31]

B22 B23

CSx

B25 B26

OE

B28

WE[0:3] B19

B18

D[0:31]

Figure 11. External Bus Read Timing (GPCM Controlled—ACS = 00)

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Bus Signal Timing

CLKOUT

B11 B12

TS

B8

A[0:31]

B22a B23

CSx

B24 B25 B26

OE

B18 B19

D[0:31]

Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)

CLKOUT

B11 B12

TS

B8 B22b

A[0:31]

B22c B23

CSx

B24a B25 B26

OE

B18 B19

D[0:31]

Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)

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Bus Signal Timing

CLKOUT

B11 B12

TS

B8

A[0:31]

B22a B23

CSx

B27 B26

OE B27a

B22b B22c B18 B19

D[0:31]

Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11)

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Bus Signal Timing

Figure 15 through Figure 17 provide the timing for the external bus write controlled by various GPCM factors.

CLKOUT

B11 B12

TS

B8 B30

A[0:31]

B22 B23

CSx

B25 B28

WE[0:3]

B26 B29b

OE B29

B8 B9

D[0:31]

Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)

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Bus Signal Timing

CLKOUT

B11 B12

TS

B8 B30a B30c

A[0:31]

B22 B28b B28d B23

CSx

B25 B29c B29g

WE[0:3]

B26 B29a B29f

OE B28a B28c

B8 B9

D[0:31]

Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)

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Bus Signal Timing

CLKOUT

B11 B12

TS

B8 B30b B30d

A[0:31]

B22 B28b B28d B23

CSx

B25 B29e B29i

WE[0:3]

B26 B29d B29h

OE B29b

B8 B28a B28c B9

D[0:31]

Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)

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Bus Signal Timing

Figure 18 provides the timing for the external bus controlled by the UPM.

CLKOUT

B8

A[0:31]

B31a

B31d B31c

B31 B31b

CSx

B34
B34a

B34b

B32a B32d B32c

B32 B32b

BS_A[0:3]

B35 B36
B35a B33a

B35b

B33

GPL_A[0:5],
GPL_B[0:5]

Figure 18. External Bus Timing (UPM Controlled Signals)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Bus Signal Timing

Figure 19 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3]

GPL_A[0:5],
GPL_B[0:5]

Figure 19. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing

Figure 20 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3]

GPL_A[0:5],
GPL_B[0:5]

Figure 20. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing

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Bus Signal Timing

Figure 21 provides the timing for the synchronous external master access controlled by the GPCM.

CLKOUT

B41 B42

TS

B40
A[0:31],
TSIZ[0:1],
R/W, BURST
B22

CSx

Figure 21. Synchronous External Master Access Timing (GPCM Handled ACS = 00)

Figure 22 provides the timing for the asynchronous external master memory access controlled by the GPCM.

CLKOUT

B39

AS

B40
A[0:31],
TSIZ[0:1],
R/W
B22

CSx

Figure 22. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)

Figure 23 provides the timing for the asynchronous external master control signals negation.

AS

B43
CSx, WE[0:3],
OE, GPLx,
BS[0:3]

Figure 23. Asynchronous External Master—Control Signals Negation Timing

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Bus Signal Timing

Table 11 provides the interrupt timing for the MPC875/870.

Table 11. Interrupt Timing

All Frequencies
Num Characteristic 1 Unit
Min Max

I39 IRQx valid to CLKOUT rising edge (setup time) 6.00 ns

I40 IRQx hold time after CLKOUT 2.00 ns

I41 IRQx pulse width low 3.00 ns

I42 IRQx pulse width high 3.00 ns

I43 IRQx edge-to-edge time 4xTCLOCKOUT —

1
The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have
no direct relation with the total system interrupt latency that the MPC875/870 is able to support.

Figure 24 provides the interrupt detection timing for the external level-sensitive lines.

CLKOUT

I39

I40

IRQx

Figure 24. Interrupt Detection Timing for External Level Sensitive Lines

Figure 25 provides the interrupt detection timing for the external edge-sensitive lines.

CLKOUT

I41 I42

IRQx

I43
I43

Figure 25. Interrupt Detection Timing for External Edge-Sensitive Lines

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Bus Signal Timing

Table 12 shows the PCMCIA timing for the MPC875/870.

Table 12. PCMCIA Timing

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic Unit
Min Max Min Max Min Max Min Max

A(0:31), REG valid to PCMCIA 20.70 — 16.70 — 9.40 — 7.40 — ns

P44 strobe asserted 1
(MIN = 0.75 × B1 – 2.00)
A(0:31), REG valid to ALE 28.30 — 23.00 — 13.20 — 10.50 — ns
P45 negation1
(MIN = 1.00 × B1 – 2.00)

CLKOUT to REG valid 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns
P46
(MAX = 0.25 × B1 + 8.00)
CLKOUT to REG invalid 8.60 — 7.30 — 4.80 — 4.125 — ns
P47
(MIN = 0.25 × B1 + 1.00)
CLKOUT to CE1, CE2 asserted 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns
P48
(MAX = 0.25 × B1 + 8.00)

CLKOUT to CE1, CE2 negated 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns
P49
(MAX = 0.25 × B1 + 8.00)
CLKOUT to PCOE, IORD, PCWE, — 11.00 — 11.00 — 11.00 — 11.00 ns
P50 IOWR assert time (MAX =
0.00 × B1 + 11.00)

CLKOUT to PCOE, IORD, PCWE, 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns
P51 IOWR negate time (MAX =
0.00 × B1 + 11.00)

CLKOUT to ALE assert time (MAX 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns
P52
= 0.25 × B1 + 6.30)

CLKOUT to ALE negate time (MAX — 15.60 — 14.30 — 11.80 — 11.13 ns

P53
= 0.25 × B1 + 8.00)
PCWE, IOWR negated to D(0:31) 5.60 — 4.30 — 1.80 — 1.125 — ns
P54
invalid1 (MIN – = 0.25 × B1 – 2.00)
WAITA and WAITB valid to 8.00 — 8.00 — 8.00 — 8.00 — ns
P55 CLKOUT rising edge1
(MIN = 0.00 × B1 + 8.00)

CLKOUT rising edge to WAITA and 2.00 — 2.00 — 2.00 — 2.00 — ns

P56 WAITB invalid1 (MIN = 0.00 × B1 +
2.00)
1 PSST
= 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.

These synchronous timings define when the WAITA signals are detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAITA assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.
See Chapter 16, “PCMCIA Interface,” in the MPC885 PowerQUICC Family User’s Manual.

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Bus Signal Timing

Figure 26 provides the PCMCIA access cycle timing for the external bus read.

CLKOUT

TS

P44

A[0:31]

P46 P45 P47

REG

P48 P49

CE1/CE2

P50 P51

PCOE, IORD

P52 P53 P52

ALE

B18 B19

D[0:31]

Figure 26. PCMCIA Access Cycles Timing External Bus Read

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Bus Signal Timing

Figure 27 provides the PCMCIA access cycle timing for the external bus write.

CLKOUT

TS

P44

A[0:31]

P46 P45 P47

REG

P48 P49

CE1/CE2

P50 P51 P54

PCWE, IOWR

P52 P53 P52

ALE

B8 B9

D[0:31]

Figure 27. PCMCIA Access Cycles Timing External Bus Write

Figure 28 provides the PCMCIA WAIT signals detection timing.

CLKOUT

P55
P56

WAITA

Figure 28. PCMCIA WAIT Signals Detection Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

39 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Bus Signal Timing

Table 13 shows the PCMCIA port timing for the MPC875/870.

Table 13. PCMCIA Port Timing

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic Unit
Min Max Min Max Min Max Min Max

CLKOUT to OPx valid — 19.00 — 19.00 — 19.00 — 19.00 ns

P57
(MAX = 0.00 × B1 + 19.00)

HRESET negated to OPx 25.70 — 21.70 — 14.40 — 12.40 — ns

P58
drive 1(MIN = 0.75 × B1 + 3.00)

IP_Xx valid to CLKOUT rising edge 5.00 — 5.00 — 5.00 — 5.00 — ns

P59
(MIN = 0.00 × B1 + 5.00)
CLKOUT rising edge to IP_Xx invalid 1.00 — 1.00 — 1.00 — 1.00 — ns
P60
(MIN = 0.00 × B1 + 1.00)
1 OP2
and OP3 only.

Figure 29 provides the PCMCIA output port timing for the MPC875/870.

CLKOUT

P57
Output
Signals

HRESET

P58

OP2, OP3

Figure 29. PCMCIA Output Port Timing

Figure 30 provides the PCMCIA input port timing for the MPC875/870.

CLKOUT

P59
P60

Input
Signals

Figure 30. PCMCIA Input Port Timing

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Bus Signal Timing

Table 14 shows the debug port timing for the MPC875/870.

Table 14. Debug Port Timing

All Frequencies
Num Characteristic Unit
Min Max

D61 DSCK cycle time 3 × TCLOCKOUT —

D62 DSCK clock pulse width 1.25 × TCLOCKOUT —

D63 DSCK rise and fall times 0.00 3.00 ns

D64 DSDI input data setup time 8.00 ns

D65 DSDI data hold time 5.00 ns

D66 DSCK low to DSDO data valid 0.00 15.00 ns

D67 DSCK low to DSDO invalid 0.00 2.00 ns

Figure 31 provides the input timing for the debug port clock.

DSCK

D61 D62
D61 D62
D63 D63

Figure 31. Debug Port Clock Input Timing

Figure 32 provides the timing for the debug port.

DSCK

D64
D65

DSDI

D66
D67

DSDO

Figure 32. Debug Port Timings

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Bus Signal Timing

Table 15 shows the reset timing for the MPC875/870.

Table 15. Reset Timing

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic Unit
Min Max Min Max Min Max Min Max

CLKOUT to HRESET high — 20.00 — 20.00 — 20.00 — 20.00 ns

R69 impedance (MAX = 0.00 × B1 +
20.00)

CLKOUT to SRESET high — 20.00 — 20.00 — 20.00 — 20.00 ns

R70 impedance (MAX = 0.00 × B1 +
20.00)

RSTCONF pulse width 515.20 — 425.00 — 257.60 — 212.50 — ns

R71
(MIN = 17.00 × B1)

R72 — — — — — — — — — —

Configuration data to HRESET 504.50 — 425.00 — 277.30 — 237.50 — ns

R73 rising edge setup time
(MIN = 15.00 × B1 + 50.00)

Configuration data to RSTCONF 350.00 — 350.00 — 350.00 — 350.00 — ns

R74 rising edge setup time
(MIN = 0.00 × B1 + 350.00)

Configuration data hold time after 0.00 — 0.00 — 0.00 — 0.00 — ns

R75 RSTCONF negation
(MIN = 0.00 × B1 + 0.00)

Configuration data hold time after 0.00 — 0.00 — 0.00 — 0.00 — ns

R76 HRESET negation
(MIN = 0.00 × B1 + 0.00)

HRESET and RSTCONF — 25.00 — 25.00 — 25.00 — 25.00 ns

R77 asserted to data out drive
(MAX = 0.00 × B1 + 25.00)

RSTCONF negated to data out — 25.00 — 25.00 — 25.00 — 25.00 ns

R78 high impedance
(MAX = 0.00 × B1 + 25.00)

CLKOUT of last rising edge — 25.00 — 25.00 — 25.00 — 25.00 ns

before chip three-states
R79 HRESET to data out high
impedance
(MAX = 0.00 × B1 + 25.00)

DSDI, DSCK setup 90.90 — 75.00 — 45.50 — 37.50 — ns

R80
(MIN = 3.00 × B1)

DSDI, DSCK hold time 0.00 — 0.00 — 0.00 — 0.00 — ns

R81
(MIN = 0.00 × B1 + 0.00)
SRESET negated to CLKOUT 242.40 — 200.00 — 121.20 — 100.00 — ns
R82 rising edge for DSDI and DSCK
sample (MIN = 8.00 × B1)

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42 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Bus Signal Timing

Figure 33 shows the reset timing for the data bus configuration.

HRESET

R71
R76

RSTCONF

R73
R74 R75

D[0:31] (IN)

Figure 33. Reset Timing—Configuration from Data Bus

Figure 34 provides the reset timing for the data bus weak drive during configuration.

CLKOUT

R69

HRESET

R79

RSTCONF

R77 R78

D[0:31] (OUT)
(Weak)

Figure 34. Reset Timing—Data Bus Weak Drive During Configuration

MPC875/MPC870 Hardware Specifications, Rev. 3.0

43 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
IEEE 1149.1 Electrical Specifications

Figure 35 provides the reset timing for the debug port configuration.

CLKOUT

R70
R82

SRESET

R80 R80
R81 R81

DSCK, DSDI

Figure 35. Reset Timing—Debug Port Configuration

12 IEEE 1149.1 Electrical Specifications

Table 16 provides the JTAG timings for the MPC875/870 shown in Figure 36 to Figure 39.
Table 16. JTAG Timing

All
Frequencies
Num Characteristic Unit
Min Max

J82 TCK cycle time 100.00 — ns

J83 TCK clock pulse width measured at 1.5 V 40.00 — ns

J84 TCK rise and fall times 0.00 10.00 ns

J85 TMS, TDI data setup time 5.00 — ns

J86 TMS, TDI data hold time 25.00 — ns

J87 TCK low to TDO data valid — 27.00 ns

J88 TCK low to TDO data invalid 0.00 — ns

J89 TCK low to TDO high impedance — 20.00 ns

J90 TRST assert time 100.00 — ns

J91 TRST setup time to TCK low 40.00 — ns

J92 TCK falling edge to output valid — 50.00 ns

J93 TCK falling edge to output valid out of high impedance — 50.00 ns

J94 TCK falling edge to output high impedance — 50.00 ns

J95 Boundary scan input valid to TCK rising edge 50.00 — ns

J96 TCK rising edge to boundary scan input invalid 50.00 — ns

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IEEE 1149.1 Electrical Specifications

TCK

J82 J83
J82 J83
J84 J84

Figure 36. JTAG Test Clock Input Timing

TCK

J85
J86

TMS, TDI

J87
J88 J89

TDO

Figure 37. JTAG Test Access Port Timing Diagram

TCK

J91
J90

TRST

Figure 38. JTAG TRST Timing Diagram

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45 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
CPM Electrical Characteristics

TCK

J92 J94
Output
Signals

J93

Output
Signals

J95 J96

Output
Signals

Figure 39. Boundary Scan (JTAG) Timing Diagram

13 CPM Electrical Characteristics

This section provides the AC and DC electrical specifications for the communications processor module (CPM) of
the MPC875/870.

13.1 Port C Interrupt AC Electrical Specifications

Table 17 provides the timings for port C interrupts.
Table 17. Port C Interrupt Timing

33.34 MHz
Num Characteristic Unit
Min Max

35 Port C interrupt pulse width low (edge-triggered mode) 55 — ns

36 Port C interrupt minimum time between active edges 55 — ns

Figure 40 shows the port C interrupt detection timing.

36

Port C
(Input)
35

Figure 40. Port C Interrupt Detection Timing

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CPM Electrical Characteristics

13.2 IDMA Controller AC Electrical Specifications

Table 18 provides the IDMA controller timings as shown in Figure 41 to Figure 44.
Table 18. IDMA Controller Timing

All
Frequencies
Num Characteristic Unit
Min Max

40 DREQ setup time to clock high 7 — ns

41 DREQ hold time from clock high 1 TBD — ns

42 SDACK assertion delay from clock high — 12 ns

43 SDACK negation delay from clock low — 12 ns

44 SDACK negation delay from TA low — 20 ns

45 SDACK negation delay from clock high — 15 ns

46 TA assertion to falling edge of the clock setup time (applies to external TA) 7 — ns
1 Applies to high-to-low mode (EDM=1)

CLKO
(Output)

41
40

DREQ
(Input)

Figure 41. IDMA External Requests Timing Diagram

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CPM Electrical Characteristics

CLKO
(Output)

TS
(Output)

R/W
(Output)

42 43

DATA

46

TA
(Input)

SDACK

Figure 42. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA

CLKO
(Output)

TS
(Output)

R/W
(Output)

42 44

DATA

TA
(Output)

SDACK

Figure 43. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

CLKO
(Output)

TS
(Output)

R/W
(Output)

42 45

DATA

TA
(Output)

SDACK

Figure 44. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA

13.3 Baud Rate Generator AC Electrical Specifications

Table 19 provides the baud rate generator timings as shown in Figure 45.
Table 19. Baud Rate Generator Timing

All
Frequencies
Num Characteristic Unit
Min Max

50 BRGO rise and fall time — 10 ns

51 BRGO duty cycle 40 60 %

52 BRGO cycle 40 — ns

50 50

BRGOX

51 51
52

Figure 45. Baud Rate Generator Timing Diagram

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CPM Electrical Characteristics

13.4 Timer AC Electrical Specifications

Table 20 provides the general-purpose timer timings as shown in Figure 46.
Table 20. Timer Timing

All
Frequencies
Num Characteristic Unit
Min Max

61 TIN/TGATE rise and fall time 10 — ns

62 TIN/TGATE low time 1 — clk

63 TIN/TGATE high time 2 — clk

64 TIN/TGATE cycle time 3 — clk

65 CLKO low to TOUT valid 3 25 ns

CLKO

60
61 63 62

TIN/TGATE
(Input)

61 64
65

TOUT
(Output)

Figure 46. CPM General-Purpose Timers Timing Diagram

13.5 Serial Interface AC Electrical Specifications

Table 21 provides the serial interface (SI) timings as shown in Figure 47 to Figure 51.
Table 21. SI Timing

All Frequencies
Num Characteristic Unit
Min Max

70 L1RCLKB, L1TCLKB frequency (DSC = 0) 1, 2 — SYNCCLK MHz

/2.5

71 L1RCLKB, L1TCLKB width low (DSC = 0) 2 P + 10 — ns

3
71a L1RCLKB, L1TCLKB width high (DSC = 0) P + 10 — ns

72 L1TXDB, L1ST1 and L1ST2, L1RQ, L1CLKO rise/fall time — 15.00 ns

73 L1RSYNCB, L1TSYNCB valid to L1CLKB edge (SYNC setup time) 20.00 — ns

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

Table 21. SI Timing (continued)

All Frequencies
Num Characteristic Unit
Min Max

74 L1CLKB edge to L1RSYNCB, L1TSYNCB, invalid (SYNC hold time) 35.00 — ns

75 L1RSYNCB, L1TSYNCB rise/fall time — 15.00 ns

76 L1RXDB valid to L1CLKB edge (L1RXDB setup time) 17.00 — ns

77 L1CLKB edge to L1RXDB invalid (L1RXDB hold time) 13.00 — ns

78 L1CLKB edge to L1ST1 and L1ST2 valid 4 10.00 45.00 ns

78A L1SYNCB valid to L1ST1 and L1ST2 valid 10.00 45.00 ns

79 L1CLKB edge to L1ST1 and L1ST2 invalid 10.00 45.00 ns

80 L1CLKB edge to L1TXDB valid 10.00 55.00 ns

80A L1TSYNCB valid to L1TXDB valid 4 10.00 55.00 ns

81 L1CLKB edge to L1TXDB high impedance 0.00 42.00 ns

82 L1RCLKB, L1TCLKB frequency (DSC =1) — 16.00 or MHz

SYNCCLK
/2

83 L1RCLKB, L1TCLKB width low (DSC =1) P + 10 — ns

83a L1RCLKB, L1TCLKB width high (DSC = 1)3 P + 10 — ns

84 L1CLKB edge to L1CLKOB valid (DSC = 1) — 30.00 ns

85 L1RQB valid before falling edge of L1TSYNCB4 1.00 — L1TCLK

86 L1GRB setup time2 42.00 — ns

87 L1GRB hold time 42.00 — ns

88 L1CLKB edge to L1SYNCB valid (FSD = 00) CNT = 0000, BYT = 0, — 0.00 ns
DSC = 0)
1 The ratio SyncCLK/L1RCLKB must be greater than 2.5/1.
2 These
specs are valid for IDL mode only.
3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
4 These strobes and TxD on the first bit of the frame become valid after the L1CLKB edge or L1SYNCB, whichever

comes later.

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51 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
CPM Electrical Characteristics

L1RCLKB
(FE=0, CE=0)
(Input)
71 70 71a
72
L1RCLKB
(FE=1, CE=1)
(Input)
RFSD=1
75

L1RSYNCB
(Input)

73
74 77

L1RXDB
(Input) BIT0

76
78 79

L1ST(2-1)
(Output)

Figure 47. SI Receive Timing Diagram with Normal Clocking (DSC = 0)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

52 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
CPM Electrical Characteristics

L1RCLKB
(FE=1, CE=1)
(Input)
72 83a
82
L1RCLKB
(FE=0, CE=0)
(Input)
RFSD=1
75

L1RSYNCB
(Input)

73
74 77

L1RXDB
(Input) BIT0

76
78 79

L1ST(2-1)
(Output)

84

L1CLKOB
(Output)

Figure 48. SI Receive Timing with Double-Speed Clocking (DSC = 1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

53 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
CPM Electrical Characteristics

L1TCLKB
(FE=0, CE=0)
(Input)
71 70
72
L1TCLKB
(FE=1, CE=1)
(Input)
73
TFSD=0
75
L1TSYNCB
(Input)

74
80a 81

L1TXDB
(Output) BIT0

80
78 79

L1ST(2-1)
(Output)

Figure 49. SI Transmit Timing Diagram (DSC = 0)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

L1RCLKB
(FE=0, CE=0)
(Input)
72 83a
82
L1RCLKB
(FE=1, CE=1)
(Input)
TFSD=0
75

L1RSYNCB
(Input)

73
74 81

L1TXDB
(Output) BIT0

80
78a 79

L1ST(2-1)
(Output)

78
84

L1CLKOB
(Output)

Figure 50. SI Transmit Timing with Double Speed Clocking (DSC = 1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

55 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
56
L1RCLKB
(Input) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

73
71
CPM Electrical Characteristics

L1RSYNCB
(Input)
80 71
74
L1TXDB
(Output) B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M

72 81
77
L1RXDB
(Input) B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M

76
78

Figure 51. IDL Timing

L1ST(2-1)
(Output)

85

MPC875/MPC870 Hardware Specifications, Rev. 3.0

L1RQB
(Output)

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

86
87
L1GRB
(Input)

Freescale Semiconductor
CPM Electrical Characteristics

13.6 SCC in NMSI Mode Electrical Specifications

Table 22 provides the NMSI external clock timing.
Table 22. NMSI External Clock Timing

All Frequencies
Num Characteristic Unit
Min Max

100 RCLK3 and TCLK3 width high 1 1/SYNCCLK — ns

101 RCLK3 and TCLK3 width low 1/SYNCCLK +5 — ns

102 RCLK3 and TCLK3 rise/fall time — 15.00 ns

103 TXD3 active delay (from TCLK3 falling edge) 0.00 50.00 ns

104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 50.00 ns

105 CTS3 setup time to TCLK3 rising edge 5.00 — ns

106 RXD3 setup time to RCLK3 rising edge 5.00 — ns

107 RXD3 hold time from RCLK3 rising edge 2 5.00 — ns

108 CD3 setup time to RCLK3 rising edge 5.00 — ns

1 The
ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1.
2 Also
applies to CD and CTS hold time when they are used as external sync signals.

Table 23 provides the NMSI internal clock timing.

Table 23. NMSI Internal Clock Timing

All Frequencies
Num Characteristic Unit
Min Max

100 RCLK3 and TCLK3 frequency 1 0.00 SYNCCLK/3 MHz

102 RCLK3 and TCLK3 rise/fall time — — ns

103 TXD3 active delay (from TCLK3 falling edge) 0.00 30.00 ns

104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 30.00 ns

105 CTS3 setup time to TCLK3 rising edge 40.00 — ns

106 RXD3 setup time to RCLK3 rising edge 40.00 — ns

107 RXD3 hold time from RCLK3 rising edge 2 0.00 — ns

108 CD3 setup time to RCLK3 rising edge 40.00 — ns

1 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1.
2 Also
applies to CD and CTS hold time when they are used as external sync signals

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CPM Electrical Characteristics

Figure 52 through Figure 54 show the NMSI timings.

RCLK3

102 102 101

106 100

RxD3
(Input)

107
108

CD3
(Input)

107

CD3
(SYNC Input)

Figure 52. SCC NMSI Receive Timing Diagram

TCLK3

102 102 101

100

TxD3
(Output)

103
105

RTS3
(Output)

104 104

CTS3
(Input)

107

CTS3
(SYNC Input)

Figure 53. SCC NMSI Transmit Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

TCLK3

102 102 101

100

TxD3
(Output)

103

RTS3
(Output)

104 107 104

105

CTS3
(Echo Input)

Figure 54. HDLC Bus Timing Diagram

13.7 Ethernet Electrical Specifications

Table 24 provides the Ethernet timings as shown in Figure 55 to Figure 57.
Table 24. Ethernet Timing

All
Frequencies
Num Characteristic Unit
Min Max

120 CLSN width high 40 — ns

121 RCLK3 rise/fall time — 15 ns

122 RCLK3 width low 40 — ns

1
123 RCLK3 clock period 80 120 ns

124 RXD3 setup time 20 — ns

125 RXD3 hold time 5 — ns

126 RENA active delay (from RCLK3 rising edge of the last data bit) 10 — ns

127 RENA width low 100 — ns

128 TCLK3 rise/fall time — 15 ns

129 TCLK3 width low 40 — ns

130 TCLK3 clock period1 99 101 ns

131 TXD3 active delay (from TCLK3 rising edge) — 50 ns

132 TXD3 inactive delay (from TCLK3 rising edge) 6.5 50 ns

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CPM Electrical Characteristics

Table 24. Ethernet Timing (continued)

All
Frequencies
Num Characteristic Unit
Min Max

133 TENA active delay (from TCLK3 rising edge) 10 50 ns

134 TENA inactive delay (from TCLK3 rising edge) 10 50 ns

138 CLKO1 low to SDACK asserted 2 — 20 ns

2
139 CLKO1 low to SDACK negated — 20 ns
1
The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.

CLSN(CTS1)
(Input)
120

Figure 55. Ethernet Collision Timing Diagram

RCLK3

121 121
124 123

RxD3
(Input) Last Bit

125 126
127
RENA(CD3)
(Input)

Figure 56. Ethernet Receive Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

TCLK3

128 128 129

131 121

TxD3
(Output)

132
133 134
TENA(RTS3)
(Input)

RENA(CD3)
(Input)
(NOTE 2)
NOTES:
1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is negated before TENA or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.

Figure 57. Ethernet Transmit Timing Diagram

13.8 SMC Transparent AC Electrical Specifications

Table 25 provides the SMC transparent timings as shown in Figure 58.
Table 25. SMC Transparent Timing

All
Frequencies
Num Characteristic Unit
Min Max

150 SMCLK clock period 1 100 — ns

151 SMCLK width low 50 — ns

151A SMCLK width high 50 — ns

152 SMCLK rise/fall time — 15 ns

153 SMTXD active delay (from SMCLK falling edge) 10 50 ns

154 SMRXD/SMSYNC setup time 20 — ns

155 RXD1/SMSYNC hold time 5 — ns

1
SyncCLK must be at least twice as fast as SMCLK.

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CPM Electrical Characteristics

SMCLK

152 152 151 151

150

SMTXD
(Output)
NOTE
154 153
155

SMSYNC

154
155

SMRXD
(Input)

NOTE:
1. This delay is equal to an integer number of character-length clocks.

Figure 58. SMC Transparent Timing Diagram

13.9 SPI Master AC Electrical Specifications

Table 26 provides the SPI master timings as shown in Figure 59 and Figure 60.
Table 26. SPI Master Timing

All
Frequencies
Num Characteristic Unit
Min Max

160 MASTER cycle time 4 1024 tcyc

161 MASTER clock (SCK) high or low time 2 512 tcyc

162 MASTER data setup time (inputs) 15 — ns

163 Master data hold time (inputs) 0 — ns

164 Master data valid (after SCK edge) — 10 ns

165 Master data hold time (outputs) 0 — ns

166 Rise time output — 15 ns

167 Fall time output — 15 ns

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CPM Electrical Characteristics

SPICLK
(CI=0)
(Output)
161 167 166
161 160
SPICLK
(CI=1)
(Output)
163 167
162 166

SPIMISO
(Input) msb Data lsb msb

165 164
167 166

SPIMOSI
(Output) msb Data lsb msb

Figure 59. SPI Master (CP = 0) Timing Diagram

SPICLK
(CI=0)
(Output)
161 167 166
161 160
SPICLK
(CI=1)
(Output)
163 167
162 166

SPIMISO
(Input) msb Data lsb msb

165 164
167 166

SPIMOSI
(Output) msb Data lsb msb

Figure 60. SPI Master (CP = 1) Timing Diagram

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CPM Electrical Characteristics

13.10SPI Slave AC Electrical Specifications

Table 27 provides the SPI slave timings as shown in Figure 61 and Figure 62.
Table 27. SPI Slave Timing

All
Frequencies
Num Characteristic Unit
Min Max

170 Slave cycle time 2 — tcyc

171 Slave enable lead time 15 — ns

172 Slave enable lag time 15 — ns

173 Slave clock (SPICLK) high or low time 1 — tcyc

174 Slave sequential transfer delay (does not require deselect) 1 — tcyc

175 Slave data setup time (inputs) 20 — ns

176 Slave data hold time (inputs) 20 — ns

177 Slave access time — 50 ns

SPISEL
(Input)

172 171
174
SPICLK
(CI=0)
(Input)
173 182 181
173 170
SPICLK
(CI=1)
(Input)
177 181 182
180 178

SPIMISO
(Output) msb Data lsb Undef msb

175 179
176 181 182

SPIMOSI
(Input) msb Data lsb msb

Figure 61. SPI Slave (CP = 0) Timing Diagram

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CPM Electrical Characteristics

SPISEL
(Input)

172
171 170 174
SPICLK
(CI=0)
(Input)
173 182 181
173 181
SPICLK
(CI=1)
(Input)
177 182
180 178

SPIMISO msb
(Output) Undef msb Data lsb

175 179
176 181 182

SPIMOSI msb
(Input) msb Data lsb

Figure 62. SPI Slave (CP = 1) Timing Diagram

13.11I2C AC Electrical Specifications

Table 28 provides the I2C (SCL < 100 KHz) timings.
Table 28. I2C Timing (SCL < 100 KHZ)

All
Frequencies
Num Characteristic Unit
Min Max

200 SCL clock frequency (slave) 0 100 KHz

1
200 SCL clock frequency (master) 1.5 100 KHz

202 Bus free time between transmissions 4.7 — µs

203 Low period of SCL 4.7 — µs

204 High period of SCL 4.0 — µs

205 Start condition setup time 4.7 — µs

206 Start condition hold time 4.0 — µs

207 Data hold time 0 — µs

208 Data setup time 250 — ns

209 SDL/SCL rise time — 1 µs

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CPM Electrical Characteristics

Table 28. I2C Timing (SCL < 100 KHZ) (continued)

All
Frequencies
Num Characteristic Unit
Min Max

210 SDL/SCL fall time — 300 ns

211 Stop condition setup time 4.7 — µs

1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scalar × 2).
The ratio SyncClk/(BRGCLK/pre_scalar) must be greater than or equal to 4/1.

Table 29 provides the I2C (SCL > 100 KHz) timings.

Table 29. I2C Timing (SCL > 100 KHZ)

All Frequencies
Num Characteristic Expression Unit
Min Max

200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz

200 SCL clock frequency (master) 1 fSCL BRGCLK/16512 BRGCLK/48 Hz

202 Bus free time between transmissions — 1/(2.2 × fSCL) — s

203 Low period of SCL — 1/(2.2 × fSCL) — s

204 High period of SCL — 1/(2.2 × fSCL) — s

205 Start condition setup time — 1/(2.2 × fSCL) — s

206 Start condition hold time — 1/(2.2 × fSCL) — s

207 Data hold time — 0 — s

208 Data setup time — 1/(40 × fSCL) — s

209 SDL/SCL rise time — — 1/(10 × fSCL) s

210 SDL/SCL fall time — — 1/(33 × fSCL) s

211 Stop condition setup time — 1/2(2.2 × fSCL) — s

1 SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) × pre_scalar × 2).
The ratio SyncClk/(Brg_Clk/pre_scalar) must be greater than or equal to 4/1.

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USB Electrical Characteristics

Figure 63 shows the I2C bus timing.

SDA

202 203 204

205 207 208

SCL

206 209 210 211

Figure 63. I2C Bus Timing Diagram

14 USB Electrical Characteristics

This section provides the AC timings for the USB interface.

14.1 USB Interface AC Timing Specifications

The USB Port uses the transmit clock on SCC1. Table 30 lists the USB interface timings.
Table 30. USB Interface AC Timing Specifications

All Frequencies
Name Characteristic Unit
Min Max

US1 USBCLK frequency of operation 1 MHz

Low speed 6 MHz
Full speed 48

US4 USBCLK duty cycle (measured at 1.5 V) 45 55 %

1 USBCLK accuracy should be ± 500 ppm or better. USBCLK may be stopped to conserve power.

15 FEC Electrical Characteristics

This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing
specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII
signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

15.1 MII and Reduced MII Receive Signal Timing

The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz +1%. The reduced MII
(RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK
frequency – 1%.

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67 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
FEC Electrical Characteristics

Table 31 provides information on the MII receive signal timing.

Table 31. MII Receive Signal Timing

Num Characteristic Min Max Unit

M1 MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup 5 — ns

M2 MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 — ns

M3 MII_RX_CLK pulse width high 35% 65% MII_RX_CLK period

M4 MII_RX_CLK pulse width low 35% 65% MII_RX_CLK period

M1_R RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK 4 — ns

MII setup

M2_R RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR 2 — ns

MII hold

Figure 64 shows MII receive signal timing.

M3

MII_RX_CLK (input)

M4

MII_RXD[3:0] (inputs)
MII_RX_DV
MII_RX_ER

M1
M2
Figure 64. MII Receive Signal Timing Diagram

15.2 MII and Reduced MII Transmit Signal Timing

The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK
frequency – 1%.
Table 32 provides information on the MII transmit signal timing.
Table 32. MII Transmit Signal Timing

Num Characteristic Min Max Unit

M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid 5 — ns

M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid — 25 ns

M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period

M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period

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FEC Electrical Characteristics

Table 32. MII Transmit Signal Timing (continued)

Num Characteristic Min Max Unit

M20_R RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup 4 — ns

MII

M21_R RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising 2 — ns

MII edge

Figure 65 shows the MII transmit signal timing diagram.

M7

MII_TX_CLK (input)

M5
M8

MII_TXD[3:0] (outputs)
MII_TX_EN
MII_TX_ER

M6
Figure 65. MII Transmit Signal Timing Diagram

15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 33 provides information on the MII async inputs signal timing.
Table 33. MII Async Inputs Signal Timing

Num Characteristic Min Max Unit

M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK period

Figure 66 shows the MII asynchronous inputs signal timing diagram.

MII_CRS, MII_COL

M9
Figure 66. MII Async Inputs Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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FEC Electrical Characteristics

15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 34 provides information on the MII serial management channel signal timing. The FEC functions correctly
with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.
Table 34. MII Serial Management Channel Timing

Num Characteristic Min Max Unit

M10 MII_MDC falling edge to MII_MDIO output invalid (minimum 0 — ns

propagation delay)

M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) — 25 ns

M12 MII_MDIO (input) to MII_MDC rising edge setup 10 — ns

M13 MII_MDIO (input) to MII_MDC rising edge hold 0 — ns

M14 MII_MDC pulse width high 40% 60% MII_MDC period

M15 MII_MDC pulse width low 40% 60% MII_MDC period

Figure 67 shows the MII serial management channel timing diagram.

M14

MM15
MII_MDC (output)

M10

MII_MDIO (output)

M11

MII_MDIO (input)

M12
M13
Figure 67. MII Serial Management Channel Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Mechanical Data and Ordering Information

16 Mechanical Data and Ordering Information

Table 35 identifies the packages and operating frequencies available for the MPC875/870.
Table 35. Available MPC875/870 Packages/Frequencies

Package Type Temperature (Tj) Frequency (MHz) Order Number

Plastic ball grid array 0°C to 95°C 66 KMPC875ZT66

ZT suffix — Leaded KMPC870ZT66
VR suffix — Lead-Free are available as needed MPC875ZT66
MPC870ZT66

80 KMPC875ZT80
KMPC870ZT80
MPC875ZT80
MPC870ZT80

133 KMPC875ZT133
KMPC870ZT133
MPC875ZT133
MPC870ZT133

Plastic ball grid array -40°C to 100°C 66 KMPC875CZT66

CZT suffix — Leaded KMPC870CZT66
CVR suffix — Lead-Free are available as needed MPC875CZT66
MPC870CZT66

133 KMPC875CZT133
KMPC870CZT133
MPC875CZT133
MPC870CZT133

16.1 Pin Assignments

Figure 68 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional
information, see the MPC885 PowerQUICC Family User’s Manual.
NOTE
The pin numbering starts with B2 in order to conform to the JEDEC standard for
23-mm body size using a 16 × 16 array.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

71 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
Mechanical Data and Ordering Information

NOTE: This is the top view of the device.

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

B
MODCK2 TEXP EXTCLK MODCK1 OP0 ALEA IPB0 BURST IRQ6 BR TEA BI CS0 CS3 CS5 N/C

C
IPA7 RSTCONFSRESET BADDR29 OP1 AS ALEB IRQ2 BB TS TA BDIP CS2 CE1A GPLAB3 GPLA0

D
IPA4 IPA2 WAITA PORESET XTAL EXTAL BADDR30 IPB1 BG GPLA4 GPLA5 WR CE2A CS7 WE2 WE1

E
D31 IPA5 IPA3 VSSSYN VDDSYN HRESET BADDR28 IRQ4 IRQ3 CS1 GPLB4 CS4 GPLAB2 WE0 BSA1 BSA2

F
D29 D30 IPA6 IPA1 VSSSYN1 VDDL VDDL CS6 OE BSA0 BSA3 TSIZ0 A31

G
D7 D28 CLKOUT D26 IPA0 VDDH VDDH WE3 TSIZ1 A26 A22 A18

H
D22 D6 D24 D25 VDDL VDDH GND VDDH VDDL A28 A30 A25 A24

J
D18 D19 D20 D21 GND A23 A21 A20 A29

K
D5 D15 D16 D14 VDDL GND VDDL A14 A19 A27 A17

L
D3 D2 D27 D0 VDDH GND VDDH A10 A12 A15 A16
VDDH

M
VDDH VDDH
D11 D9 D12 PE18 IRQ0 MII_MDIO A2 A8 A11 A13

N
D10 D1 D13 IRQ7 PA2 VDDL VDDL PB26 PB27 A1 A6 A7 A9

P
D23 D17 PE22 IRQ1 PA0 PA4 PE14 PE31 PC6 PA6 PC11 TDO PA15 A3 A5 A4

R
D4 D8 PE25 PA3 PE19 PE28 PE30 PA11 MII_COL PA7 PA10 TCK PB28 PC15 A0 PB29

T
PE26 PD8 PA1 PB31 PE27 PE15 PE17 PE21 PC7 PB19 PB24 TDI TMS PC12 N/C PB30

U
N/C PE20 PE23 MII-TX-EN PE16 PE29 PE24 PC13 MII-CRS PC10 PB23 PB25 TRST GND PA14 N/C

Figure 68. Pinout of the PBGA Package—JEDEC Standard

Table 36 contains a list of the MPC875/870 input and output signals and shows multiplexing and pin assignments.
Table 36. Pin Assignments—JEDEC Standard

Name Pin Number Type

A[0:31] R16, N14, M14, P15, P17, P16, N15, N16, M15, N17, L14, M16, Bidirectional
L15, M17, K14, L16, L17, K17, G17, K15, J16, J15, G16, J14, H17, Three-state (3.3 V only)
H16, G15, K16, H14, J17, H15, F17

TSIZ0 F16 Bidirectional

REG Three-state (3.3 V only)

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

TSIZ1 G14 Bidirectional

Three-state (3.3 V only)

RD/WR D13 Bidirectional

Three-state (3.3 V only)

BURST B9 Bidirectional
Three-state (3.3 V only)

BDIP C13 Output

GPL_B5

TS C11 Bidirectional
Active pull-up (3.3 V only)

TA C12 Bidirectional
Active pull-up (3.3 V only)
TEA B12 Open-drain

BI B13 Bidirectional
Active pull-up (3.3 V only)

IRQ2 C9 Bidirectional
RSV Three-state (3.3 V only)

IRQ4 E9 Bidirectional
KR Three-state (3.3 V only)
RETRY
SPKROUT
D[0:31] L5, N3, L3, L2, R2, K2, H3, G2, R3, M3, N2, M2, M4, N4, K5, K3, K4, Bidirectional
P3, J2, J3, J4, J5, H2, P2, H4, H5, G5, L4, G3, F2, F3, E2 Three-state (3.3 V only)

CR E10 Input
IRQ3

FRZ B10 Bidirectional

IRQ6 Three-state (3.3 V only)

BR B11 Bidirectional (3.3 V only)

BG D10 Bidirectional (3.3 V only)

BB C10 Bidirectional
Active pull-up (3.3 V only)

IRQ0 M6 Input (3.3 V only)

IRQ1 P5 Input (3.3 V only)

IRQ7 N5 Input (3.3 V only)

CS[0:5] B14, E11, C14, B15, E13, B16 Output

CS6 F12 Output

CE1_B

CS7 D15 Output

CE2_B

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Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

WE0 E15 Output

BS_B0
IORD
WE1 D17 Output
BS_B1
IOWR

WE2 D16 Output

BS_B2
PCOE

WE3 G13 Output

BS_B3
PCWE
BS_A[0:3] F14, E16, E17, F15 Output

GPL_A0 C17 Output

GPL_B0
OE F13 Output
GPL_A1
GPL_B1
GPL_A[2:3] E14, C16 Output
GPL_B[2:3]
CS[2–3]
UPWAITA D11 Bidirectional (3.3 V only)
GPL_A4

UPWAITB E12 Bidirectional

GPL_B4
GPL_A5 D12 Output

PORESET D5 Input (3.3 V only)

RSTCONF C3 Input (3.3 V only)

HRESET E7 Open-drain

SRESET C4 Open-drain

XTAL D6 Analog output

EXTAL D7 Analog input (3.3 V only)

CLKOUT G4 Output

EXTCLK B4 Input (3.3 V only)

TEXP B3 Output

ALE_A B7 Output

CE1_A C15 Output

CE2_A D14 Output

WAIT_A D4 Input (3.3 V only)

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

IP_A0 G6 Input (3.3 V only)

IP_A1 F5 Input (3.3 V only)

IP_A2 D3 Input (3.3 V only)

IOIS16_A

IP_A3 E4 Input (3.3 V only)

IP_A4 D2 Input (3.3 V only)

IP_A5 E3 Input (3.3 V only)

IP_A6 F4 Input (3.3 V only)

IP_A7 C2 Input (3.3 V only)

ALE_B C8 Bidirectional
DSCK Three-state (3.3 V only)

IP_B[0:1] B8, D9 Bidirectional (3.3 V only)

IWP[0:1]
VFLS[0:1]

OP0 B6 Bidirectional (3.3 V only)

OP1 C6 Output

OP2 B5 Bidirectional (3.3 V only)

MODCK1
STS
OP3 B2 Bidirectional (3.3 V only)
MODCK2
DSDO

BADDR[28:29] E8, C5 Output

BADDR30 D8 Output
REG
AS C7 Input (3.3 V only)

PA15 P14 Bidirectional

USBRXD

PA14 U16 Bidirectional

USBOE (Optional: open-drain)

PA11 R9 Bidirectional
RXD4 (Optional: open-drain)
MII1-TXD0 (5-V tolerant)
RMII1-TXD0

PA10 R12 Bidirectional

MII1-TXERR (Optional: open-drain)
TIN4 (5-V tolerant)
CLK7

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

PA7 R11 Bidirectional

CLK1
BRGO1
TIN1

PA6 P11 Bidirectional

CLK2
TOUT1
PA4 P7 Bidirectional
CTS4
MII1-TXD1
RMII-TXD1

PA3 R5 Bidirectional
MII1-RXER (5-V tolerant)
RMII1-RXER
BRGO3
PA2 N6 Bidirectional
MII1-RXDV (5-V tolerant)
RMII1-CRS_DV
TXD4
PA1 T4 Bidirectional
MII1-RXD0 (5-V tolerant)
RMII1-RXD0
BRGO4
PA0 P6 Bidirectional
MII1-RXD1 (5-V tolerant)
RMII1-RXD1
TOUT4

PB31 T5 Bidirectional
SPISEL (Optional: open-drain)
MII1 - TXCLK (5-V tolerant)
RMII1-REFCLK

PB30 T17 Bidirectional

SPICLK (Optional: open-drain)
(5-V tolerant)

PB29 R17 Bidirectional

SPIMOSI (Optional: open-drain)
(5-V tolerant)

PB28 R14 Bidirectional

SPIMISO (Optional: open-drain)
BRGO4 (5-V tolerant)

PB27 N13 Bidirectional

I2CSDA (Optional: open-drain)
BRGO1

PB26 N12 Bidirectional

I2CSCL (Optional: open-drain)
BRGO2

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 Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

PB25 U13 Bidirectional

SMTXD1 (Optional: open-drain)
(5-V tolerant)

PB24 T12 Bidirectional

SMRXD1 (Optional: open-drain)
(5-V tolerant)

PB23 U12 Bidirectional

SDACK1 (Optional: open-drain)
SMSYN1

PB19 T11 Bidirectional

MII1-RXD3 (Optional: open-drain)
RTS4
PC15 R15 Bidirectional
DREQ0 (5-V tolerant)
L1ST1

PC13 U9 Bidirectional
MII1-TXD3 (5-V tolerant)
SDACK1

PC12 T15 Bidirectional

MII1-TXD2 (5-V tolerant)
TOUT1

PC11 P12 Bidirectional

USBRXP

PC10 U11 Bidirectional

USBRXN
TGATE1
PC7 T10 Bidirectional
CTS4 (5-V tolerant)
L1TSYNCB
USBTXP
PC6 P10 Bidirectional
CD4 (5-V tolerant)
L1RSYNCB
USBTXN
PD8 T3 Bidirectional
RXD4 (5-V tolerant)
MII-MDC
RMII-MDC
PE31 P9 Bidirectional
CLK8 (Optional: open-drain)
L1TCLKB
MII1-RXCLK
PE30 R8 Bidirectional
L1RXDB (Optional: open-drain)
MII1-RXD2

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

PE29 U7 Bidirectional
MII2-CRS (Optional: open-drain)

PE28 R7 Bidirectional
TOUT3 (Optional: open-drain)
MII2-COL

PE27 T6 Bidirectional
L1RQB (Optional: open-drain)
MII2-RXERR
RMII2-RXERR

PE26 T2 Bidirectional
L1CLKOB (Optional: open-drain)
MII2-RXDV
RMII2-CRS_DV

PE25 R4 Bidirectional
RXD4 (Optional: open-drain)
MII2-RXD3
L1ST2

PE24 U8 Bidirectional
SMRXD1 (Optional: open-drain)
BRGO1
MII2-RXD2

PE23 U4 Bidirectional
TXD4 (Optional: open-drain)
MII2-RXCLK
L1ST1

PE22 P4 Bidirectional
TOUT2 (Optional: open-drain)
MII2-RXD1
RMII2-RXD1
SDACK1

PE21 T9 Bidirectional
TOUT1 (Optional: open-drain)
MII2-RXD0
RMII2-RXD0

PE20 U3 Bidirectional
MII2-TXER (Optional: open-drain)

PE19 R6 Bidirectional
L1TXDB (Optional: open-drain)
MII2-TXEN
RMII2-TXEN
PE18 M5 Bidirectional
SMTXD1 (Optional: open-drain)
MII2-TXD3

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

PE17 T8 Bidirectional
TIN3 (Optional: open-drain)
CLK5
BRGO3
SMSYN1
MII2-TXD2

PE16 U6 Bidirectional
L1RCLKB (Optional: open-drain)
CLK6
MII2-TXCLK
RMII2-REFCLK
PE15 T7 Bidirectional
TGATE1
MII2-TXD1
RMII2-TXD1

PE14 P8 Bidirectional
MII2-TXD0
RMII2-TXD0

TMS T14 Input

(5-V tolerant)

TDI T13 Input

DSDI (5-V tolerant)

TCK R13 Input

DSCK (5-V tolerant)

TRST U14 Input

(5-V tolerant)

TDO P13 Output

DSDO (5-V tolerant)

MII1_CRS U10 Input

MII_MDIO M13 Bidirectional

(5-V tolerant)

MII1_TX_EN U5 Output
RMII1_TX_EN (5-V tolerant)

MII1_COL R10 Input

VSSSYN E5 PLL analog GND

VSSSYN1 F6 PLL analog GND

VDDSYN E6 PLL analog VDD

GND H8, H9, H10, H11, J8, J9, J10, J11, K8, K9, K10, K11, L8, L9, L10, Power
L11, U15

VDDL F7, F8, F9, F10, F11, H6, H13, J6, J13, K6, K13, L6, L13, N7, N8, Power
N9, N10, N11

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Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

VDDH G7, G8, G9, G10, G11, G12, H7, H12, J7, J12, K7, K12, L7, L12, M7, Power
M8, M9, M10, M11, M12

N/C B17, T16, U2, U17 No-connect

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 Mechanical Data and Ordering Information

16.2 Mechanical Dimensions of the PBGA Package

Figure 69 shows the mechanical dimensions of the PBGA package.

NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.

Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC875/870VRXXX.

Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC875/870ZTXXX.

Figure 69. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 81
Document Revision History

17 Document Revision History

Table 37 lists significant changes between revisions of this hardware specification.
Table 37. Document Revision History

Revision
Date Changes
Number

0 2/2003 Initial release.

0.1 3/2003 Took out the time-slot assigner and changed the SCC for SCC3 to SCC4.

0.2 5/2003 Changed the package drawing, removed all references to Data Parity. Changed the SPI
Master Timing Specs. 162 and 164. Added the RMII and USB timing. Added the 80-MHz
timing.

0.3 5/2003 Made sure the pin types were correct. Changed the Features list to agree with the
MPC885.

0.4 5/2003 Corrected the signals that had overlines on them. Made corrections on two pins that were
typos.

0.5 5/2003 Changed the pin descriptions for PD8 and PD9.

0.6 5/2003 Changed a few typos. Put back the I2C. Put in the new reset configuration, corrected the
USB timing.

0.7 6/2003 Changed the pin descriptions per the June 22 spec, removed Utopia from the pin
descriptions, changed PADIR, PBDIR, PCDIR and PDDIR to be 0 in the Mandatory
Reset Config.

0.8 8/2003 Added the reference to USB 2.0 to the Features list and removed 1.1 from USB on the
block diagrams.

0.9 8/2003 Changed the USB description to full-/low-speed compatible.

1.0 9/2003 Added the DSP information in the Features list.

Put a new sentence under Mechanical Dimensions.
Fixed table formatting.
Nontechnical edits.
Released to the external web.

1.1 10/2003 Added TDMb to the MPC875 Features list, the MPC875 Block Diagram, added 13.5
Serial Interface AC Electrical Specifications, and removed TDMa from the pin
descriptions.

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 Document Revision History

Table 37. Document Revision History (continued)

Revision
Date Changes
Number

2.0 12/2003 Changed DBGC in the Mandatory Reset Configuration to X1.

Changed the maximum operating frequency to 133 MHz.
Put the timing in the 80 MHz column.
Put in the orderable part numbers.
Rounded the timings to hundredths in the 80 MHz column.
Put the pin numbers in footnotes by the maximum currents in Table 6.
Changed 22 and 41 in the Timing.
Put TBD in the Thermal table.

3.0 1/07/2004 • Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for
7/19/2004 Integer Values
• Added a footnote to Spec 41 specifying that EDM = 1
• Added the thermal numbers to Table 4.
• Added RMII1_EN under M1II_EN in Table 36 Pin Assignments
• Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL
Max of the I2C Standard
• Put the new part numbers in the Ordering Information Section

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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MPC875EC
Rev. 3.0
07/2004

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE