ANJANEYA PRASAD K
MTech in NIT Karnataka, Surathkal anjaneyaprasadkacharla3730@gmail.com
8555068436
anjaneya-prasad-kacharla-a581b0179
OBJECTIVE
Seeking a challenging opportunity in the VLSI domain, leveraging over 2 years of experience in system-level
validation and skills in digital design, and Verilog. I bring a proactive attitude, strong motivation to learn, and a
commitment to continuous improvement. My goal is to contribute to an innovative and growth-driven
semiconductor organization.
WORK EXPERIENCE
Mavenir Systems Pvt Ltd, Bengaluru
Member of Technical Staff 1-R&D, RTL Design and Validation July,2023 - Jan,2025
• 5G NR, 4G LTE Radio Development using Xilinx Zynq UltraScale + XCZU67DR RFSoC FPGA.
• Performed thorough Radio unit data path validation ensuring optimal performance of downlink, uplink, and
PRACH RF data paths across 3+ FPGA based Radio units.
• Involved in Integrating RTL blocks, debugging, and validating various features within radio units. Collaborated
closely with software team to integrate and test these features within the board-level test software.
• Expertise in system-level validation, board bring-up and debugging validation issues using Xilinx’s ILAs for
identifying functional discrepancies in RTL Code, optimized data path flow by implementing MATLAB based
verification, leveraged Wireshark based fronthaul captures for signal analysis and validation.
• Proficient in using RF test equipment including signal analyzers and signal generators, to capture, analyze, and
validate RF data.
Graduate Intern: Mavenir Systems Pvt Ltd, Bengaluru Jan,2023 - June,2023
• Acquired in-depth experience with the Xilinx Zynq UltraScale + RFSoC DFE ZCU670 Evaluation Kit, from
RTL Coding to Bitstream Generation. Post-implementation programming FPGA boards using JTAG
interface. Conducted rigorous testing and verification using signal analyzers to ensure design met all
specifications for signal integrity and functionality.
• Conducted Spyglass linting analysis to ensure the integrity of Verilog designs, identifying and
addressing syntax errors, uninitialized variables, and coding style violations.
EDUCATION
National Institute of Technology Karnataka, Surathkal
MTech in Communication Engineering & Networks, 2021-2023 CGPA-8.28/10
Chaitanya Bharathi Institute of Technology, Hyderabad (CBIT)
BTech in Electronics and Communication Engineering, 2016-2020 CPGA-7.69/10
SKILLS
• Programming: Verilog, C, TCL, Shell, Python
• Tools & Software: Xilinx Vivado, Cadence Virtuoso, Spyglass Lint, MATLAB, Wireshark, ADS, HFSS
• Technologies:5G NR, 4G LTE, ORAN, PTP, FPGA Prototyping
• Interfaces/Protocols: JTAG, Ethernet, UART, AXI
• RF Equipment: Mixed Signal Analyzers, Signal Generators (Keysight, R&S)
• Development Tools: Jira, Git
Paper(s) published
• N. Puli, A. Prasad, M. Goud and K. Kandasamy, "Compact Sized High Gain and Ultra-Wideband HMSIW
cavity backed Slot Antenna for Ku-band Applications," 2022 IEEE 7th International Conference on Recent
Advances and Innovations in Engineering (ICRAIE), MANGALORE, India, 2022, pp. 373-376, doi:
10.1109/ICRAIE56454.2022.10054254.
PROJECTS
• Comparison of efficiencies of different adders: Evaluated and compared the efficiencies of 32 bit Carry
Look-Ahead, Ripple Carry, and Carry Select Adders at the transistor level (using NMOS and PMOS) with
Cadence Virtuoso in 180nm technology.
• Power measurement logic improvement in RRH FPGA: Improved the existing logic of antenna power
measurement to solve issues in corner testcases in 4T4R and 8T8R (RRH projects). Carried out rigorous
validation of updated power measurement logic using diverse test vectors generated via custom MATLAB
scripts.
• Design of Asynchronous FIFO: Designed FIFO in Verilog for real-time data transmission across different
clock domains, implemented on a Xilinx Zynq UltraScale+ RFSoC DFE ZCU670 Evaluation Kit.
• FSM Design in Verilog: Designed Finite state machine in Verilog for different applications such as Traffic
light Control, Vending Machine.
AREAS OF INTEREST
• Digital Electronics and ASIC/FPGA development
• RTL Coding and Static Timing Analysis
• CMOS VLSI Design
• Semiconductor Device Technology
• Communication Systems
ACHIEVEMENTS
• Received Spotlight award for 2023-24 at Mavenir Systems Pvt ltd in recognition of my performance on the
4T4R project.
• Participated in TCS world 10K Bengaluru, 2024.
• Volunteered and Co-ordinated tech events.
